PIC24FXXKA1XX/FVXXKA3XX PIC24FXXKA1XX/FVXXKA3XX Family Flash Programming Specifications 1.0 DEVICE OVERVIEW This document defines the programming specifications for the PIC24FXXKA1XX/FVXXKA3XX family of 16-bit microcontroller devices. This is required only for developing programming support for the PIC24FXXKA1XX/FVXXKA3XX family. Users of any one of these devices should use the development tools that are already supporting the device programming. The programming specifications are specific to the following devices: • PIC24F08KA101 • PIC24FV32KA301(1) • PIC24F16KA101 • PIC24FV16KA302(1) • PIC24F08KA102 • PIC24FV32KA302(1) • PIC24F16KA102 • PIC24FV16KA304(1) • PIC24FV16KA301(1) • PIC24FV32KA304(1) Note 1: 2.0 The Enhanced ICSP method is a faster method, which takes advantage of the Programming Executive (PE), as illustrated in Figure 2-1. The Programming Executive provides the necessary functionality to erase, program and verify the device through a command set. The command set allows the programmer to program the PIC24FXXKA1XX/FVXXKA3XX devices without having to deal with the low-level programming protocols of the device. Section 4.0 “Device Programming – Enhanced ICSP” describes the ICSP method using the Programming Executive. FIGURE 2-1: PIC24FXXKAXXX Programmer This includes corresponding PIC24FXXKA30X devices. PROGRAMMING OVERVIEW OF THE PIC24FXXKA1XX/FVXXKA3XX FAMILY This section describes the two methods of programming the PIC24FXXKA1XX/FVXXKA3XX family of devices: • In-Circuit Serial Programming™ (ICSP™) • Enhanced In-Circuit Serial Programming (Enhanced ICSP) The ICSP programming method is the most direct method for programming the device. However, it is also the slower of the two methods. It provides a native, low-level programming capability to erase, program and verify the device. Section 3.0 “Device Programming – ICSP” describes the ICSP method. 2008-2012 Microchip Technology Inc. PROGRAMMING SYSTEM OVERVIEW FOR ENHANCED ICSP™ METHOD Programming Executive On-Chip Memory 2.1 Power Requirements Devices in the PIC24FXXKA1XX and PIC24FXXKA3XX families are 3.3V supply designs. The core, the peripherals and the I/O pins operate at 3.3V. The device can operate from 1.8V to 3.6V. Devices in the PIC24FVXXKA3XX families are 5.0V supply designs. The core, the peripherals and the I/O pins operate at 3.3V. The device can operate from 2.0V to 5.5V; an internal regulator operates the core logic at 3.25V. Table 2-1 provides the pins that are required for programming, which are indicated in Figure 2-3. Refer to the appropriate device data sheet for complete pin descriptions. Note that all power supply and ground pins must be connected appropriately for programming. DS39919C-page 1 PIC24FXXKA1XX/FVXXKA3XX TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING) During Programming Pin Name Pin Name Pin Type MCLR/VPP P Programming Enable VDD VDD P Power Supply VSS VSS P Ground VCAP VCAP P Stabilizing Capacitor for Voltage Regulator(1) PGECx PGC I Programming Pin Pair: Serial Clock PGEDx PGD I/O Programming Pin Pair: Serial Data MCLR/VPP Pin Description Legend: I = Input, O = Output, P = Power Note 1: PIC24FVXXKA3XX devices only. 2.1.1 ON-CHIP VOLTAGE REGULATOR CONNECTIONS For PIC24FVXXKA3XX devices, an on-chip regulator provides power to the core from the other VDD pins. A low-ESR capacitor (such as high-quality, ceramic or tantalum) must be connected to the VDDCORE pin (Figure 2-2). This helps to maintain the stability of the regulator. The specifications for core voltage and capacitance are listed in Section 7.0 “AC/DC Characteristics and Timing Requirements”. PIC24FXXKA1XX and PIC24FXXKA3XX devices do not use an on-chip regulator. FIGURE 2-2: CONNECTIONS FOR THE ON-CHIP REGULATOR 5.0V PIC24FVXXKA3XX VDD VCAP CEFC (10 F typ) VSS Note 1: These are typical operating voltages. Refer to Section 7.0 “AC/DC Characteristics and Timing Requirements” for the full operating ranges of VDD and VDDCORE. DS39919C-page 2 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX PIN DIAGRAMS 28-Pin PDIP, SOIC, SSOP MCLR/VPP PGEC2 PGED2 PGED1 PGEC1 PGED3 PGEC3 1 2 3 4 5 6 7 8 9 10 PIC24F(V)XXKAX01 20-Pin SPDIP, SOIC, SSOP 20 19 18 17 16 15 14 13 12 11 VDD VSS MCLR/VPP PGED1 PGEC1 VCAP(1) VSS VDD PGED3 28-Pin QFN PGEC2 PGED2 VCAP(1) PGEC3 PGEC3 PGED3 VDD VSS 44 43 42 41 40 39 38 37 36 35 34 PGEC2 PGED2 VCAP(1) 1 2 3 4 5 6 (1) VCAP 7 PGED2 8 PGEC2 9 10 11 47 47 46 44 43 42 41 40 39 38 37 PGEC3 PGED3 VDD VSS 48-Pin UQFN PIC24FV32KA304 13 14 15 16 VSS 17 VDD 18 MCLR/VPP 19 20 22 PGED1 23 PGEC1 24 1 2 3 4 5 6 (1) 7 VCAP PGED2 8 PGEC2 9 10 11 12 Note 1: VDD VSS PIC24F(V)XXKA304 33 32 31 30 29 VSS 28 VDD 27 26 25 24 23 12 13 14 15 VSS 16 VDD 17 MCLR/VPP 18 19 20 PGED1 21 PGEC1 22 28 27 26 25 24 23 22 1 21 2 20 3 19 4 PIC24F(V)XXKAX02 18 5 17 6 16 7 15 8 9 10 11 12 13 14 VDD PGED3 PGEC3 VSS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 44-Pin QFN, TQFP MCLR/VPP VDD Vss PGED1 PGEC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC24F(V)XXKAX02 FIGURE 2-3: 36 35 34 33 32 31 VSS 30 VDD 29 28 27 26 25 PIC24FVXXKA3XX devices only. PIC24FXXKA3XX devices do not use VCAP. 2008-2012 Microchip Technology Inc. DS39919C-page 3 PIC24FXXKA1XX/FVXXKA3XX 2.2 Memory Map The program memory map for PIC24FXXKA1XX/FVXXKA3XX devices extends from 000000h to FFFFFEh. Code storage is located at the base of the memory map and supports up to 11K instruction words (about 32 Kbytes). Table 2-2 provides the program memory and data EEPROM size, and the number of memory rows present in each device variant. The erase operation can be done on one word, half of a row or one row at a time. The program operation can be done only one word at a time. Additionally, PIC24FXXKA1XX/FVXXKA3XX family devices have an on-chip data EEPROM. This data EEPROM is mapped to the program memory area from location, 7FFE00h to 7FFFFEh. TABLE 2-2: MEMORY SIZES FOR PIC24FXXKA1XX/FVXXKA3XX DEVICES Device Program Memory Upper Address (Instruction Words) Rows Data EEPROM Size (Words) Rows PIC24F08KA10X 15FEh (2.75K) 88 256 32 PIC24F16KA10X 2BFEh (5.5K) 176 256 32 PIC24FV08KA30X(1) 15FEh (2.75K) 88 256 32 PIC24FV16KA30X(1) 2BFEh (5.5K) 176 256 32 PIC24FV32KA30X(1) 57FEh (11K) 352 256 32 Note 1: This includes corresponding PIC24FXXKA3XX devices. Locations, 800000h through 8007FEh, are reserved for executive code memory. This region stores the Programming Executive, the debugging executive and the Diagnostic Words. The Programming Executive is used for device programming and the debug executive is used for in-circuit debugging. This region of memory cannot be used to store user code. The device Configuration registers are implemented from location, F80000h to F80010h, and can be erased or programmed one register at a time. Table 2-3 provides the implemented Configuration registers and their locations. Locations, FF0000h and FF0002h, are reserved for the Device ID registers. These bits can be used by the programmer to identify the device type that is being programmed. See Section 6.0 “Device ID” for more information. The Device ID registers read out normally, even after code protection is applied. Figure 2-4 depicts the memory map for PIC24FXXKA1XX/FVXXKA3XX family variants. DS39919C-page 4 TABLE 2-3: CONFIGURATION REGISTER LOCATIONS Configuration Register Address FBS F80000 FGS F80004 FOSCSEL F80006 FOSC F80008 FWDT F8000A FPOR F8000C FICD F8000E FDS F80010 the 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX FIGURE 2-4: PROGRAM MEMORY MAP 000000h User Flash Code Memory (5632 x 24-bit) User Memory Space 0015FEh/002BFEh/0057FEh (1) Reserved 7FFE00h Data EEPROM Programming Executive Code Memory (1016 x 24-bit) Configuration Memory Space Diagnostic Words 800000h 8007F2h 8007F4h 8007FEh 800800h Reserved F80000h Configuration Registers F80010h Device ID (2 x 16-bit) Reserved Note 1: FEFFFEh FF0000h FF0002h FF0004h FFFFFEh The upper address boundaries for user program memory are device-specific. See Table 2-2 for details. 2008-2012 Microchip Technology Inc. DS39919C-page 5 PIC24FXXKA1XX/FVXXKA3XX 3.0 DEVICE PROGRAMMING – ICSP FIGURE 3-1: The ICSP method is a special programming protocol that allows reading and writing to the PIC24FXXKA1XX/FVXXKA3XX device family memory. ICSP is the most direct method used to program a device; however, Enhanced ICSP is faster. The ICSP mode also reads the contents of the executive memory to determine if the Programming Executive is present. This is accomplished by applying control codes and instructions, serially to the device, using PGCx and PGDx pins. Start Enter ICSP™ Mode Perform Bulk Erase Program Memory In ICSP mode, the system clock is taken from the PGCx pin, regardless of the device‘s Oscillator Configuration bits. All of the instructions are shifted serially to an internal buffer, loaded into the Instruction Register (IR), and then executed. No program is fetched from the internal memory. Instructions are fed in 24 bits at a time. PGDx is used to shift data in, and PGCx is used as both the serial shift clock and the CPU execution clock. Note: 3.1 HIGH–LEVEL ICSP™ PROGRAMMING FLOW Verify Program Program Data EEPROM Memory Verify Data EEPROM Memory During ICSP operation, the operating frequency of PGCx should not exceed 8 MHz. Program Configuration Bits Overview of the Programming Process Verify Configuration Bits Figure 3-1 illustrates the high-level overview of the programming process. Exit ICSP Mode After entering the ICSP mode, perform the following: 1. 2. 3. 4. 5. 3.2 Bulk Erase the device. Program and verify the code memory. Program and verify the data EEPROM memory. Program and verify the device configuration. Program the code-protect Configuration bits, if required. ICSP Operation Upon entry into ICSP mode, the CPU is Idle. An internal state machine governs the execution of the CPU. A 4-bit control code is clocked in, using PGCx and PGDx, and this control code is used to command the CPU (see Table 3-1). End TABLE 3-1: CPU CONTROL CODES IN ICSP™ MODE 4-Bit Mnemonic Control Code Description 0000b SIX Shift in 24-bit instruction and execute. 0001b REGOUT Shift out the VISI (0784h) register. 0010b-1111b N/A This is reserved. The SIX control code is used to send instructions to the CPU for execution and the REGOUT control code is used to read data out of the device via the VISI register. DS39919C-page 6 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 3.2.1 SIX SERIAL INSTRUCTION EXECUTION For example, MOV #0x0,W0 followed by MOV [W0],W1, must have a NOP inserted in between. The SIX control code allows execution of PIC24FXXKA1XX/FVXXKA3XX family assembly instructions. When the SIX code is received, the CPU is suspended for 24 clock cycles, as the instruction is then clocked into the internal buffer. Once the instruction is shifted in, the state machine allows it to be executed over the next four PGC clock cycles. While the received instruction is executed, the state machine simultaneously shifts in the next 4-bit command (see Figure 3-2). If a two-cycle instruction modifies a register, which is used indirectly, it requires two following NOPs; one to execute the second half of the instruction and the other to stall the CPU to correct the pipeline. Coming out of Reset, the first 4-bit control code is always forced to SIX and a forced NOP instruction is executed by the CPU. Five additional PGCx clocks are needed on start-up; thereby, resulting in a 9-bit SIX command, instead of the normal 4-bit SIX command. After the forced SIX is clocked in, the ICSP operation resumes to normal. That is, the next 24 clock cycles load the first instruction word to the CPU. Note: To account for this forced NOP, all example codes in this specification begin with a NOP to ensure that no data is lost. 3.2.1.1 Differences Between SIX Instruction Execution and Normal Instruction Execution There are some differences between executing instructions using the SIX ICSP command and normal device instruction execution. As a result, the code examples in this specification might not match those required to perform the same operations during normal device operation. The differences are: • Two-word instructions require 2 SIX operations to clock in all the necessary data. Examples of two-word instructions are GOTO and CALL. • Two-cycle instructions require 2 SIX operations to complete. The first SIX operation shifts in the instruction and begins to execute it. A second SIX operation, which should shift in a NOP to avoid losing data, allows the CPU clocks required to finish executing the instruction. Examples of two-cycle instructions are Table Read (TBLRD) and Table Write (TBLWT) instructions. • The CPU does not automatically stall to account for pipeline changes. A CPU stall occurs when an instruction modifies a register, which is used by the instruction immediately following the CPU stall for Indirect Addressing. During normal operation, the CPU forces a NOP while the new data is read. To account for this, while using ICSP, any indirect references to a recently modified register should be proceeded with a NOP. 2008-2012 Microchip Technology Inc. For example, TBLWTL [W0++],[W1], should be followed by 2 NOPs. • The device Program Counter (PC) continues to automatically increment during the ICSP instruction execution, even though the Flash memory is not being used. As a result, it is possible for the PC to be incremented so that it points to invalid memory locations. Examples of invalid memory spaces are unimplemented Flash addresses or the vector space (location, 0x0 to 0x1FF). If the PC ever points to these locations, it causes the device to reset, possibly interrupting the ICSP operation. To prevent this, instructions should be periodically executed to reset the PC to a safe space. The optimal method of achieving this is to perform a “GOTO 0x200”. 3.2.2 REGOUT SERIAL INSTRUCTION EXECUTION The REGOUT control code allows for the data to be extracted from the device in the ICSP mode. It is used to clock the contents of the VISI register out of the device over the PGDx pin. After the REGOUT control code is received, the CPU is held Idle for 8 cycles. After this, an additional 16 cycles are required to clock the data out (see Figure 3-3). The REGOUT code is unique, as the PGDx pin is an input when the control code is transmitted to the device. However, after the control code is processed, the PGDx pin becomes an output as the VISI register is shifted out. Note 1: After the contents of VISI are shifted out, the PIC24FXXKA1XX/FVXXKA3XX devices maintain PGDx as an output until the first rising edge of the next clock is received. 2: Data changes on the falling edge and latches on the rising edge of PGCx. For all data transmissions, the Least Significant bit (LSb) is transmitted first. DS39919C-page 7 PIC24FXXKA1XX/FVXXKA3XX FIGURE 3-2: SIX SERIAL EXECUTION P1 1 2 4 3 5 6 7 8 9 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 1 2 3 4 PGCx P4 P3 P4A P1A P1B P2 PGDx 0 0 0 0 0 0 Execute PC – 1, Fetch SIX Control Code 0 0 LSB X 0 X X X X X X X X X X X X X MSB 0 0 0 0 Execute 24-Bit Instruction, Fetch Next Control Code 24-Bit Instruction Fetch Only for Program Memory Entry PGDx = Input FIGURE 3-3: 1 REGOUT SERIAL EXECUTION 2 3 4 1 2 7 8 1 2 3 4 5 6 11 12 13 14 15 16 1 2 3 4 PGCx P4 PGDx 1 0 0 0 Execute Previous Instruction, CPU Held in Idle Fetch REGOUT Control Code PGDx = Input DS39919C-page 8 P4A P5 LSb 1 2 3 4 ... 10 11 12 13 14 MSb Shift Out VISI Register<15:0> PGDx = Output 0 0 0 0 No Execution Takes Place, Fetch Next Control Code PGDx = Input 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 3.3 3.3.2 Entering ICSP Mode 3.3.1 Entering the ICSP Program/Verify mode, using the VPP pin, is the same as entering the mode using MCLR. The only difference is the programming voltage applied to VPP is VIHH, and before presenting the key sequence on PGDx, an interval of at least P18 should elapse (see Figure 3-5). LOW-VOLTAGE ICSP ENTRY As illustrated in Figure 3-4, the following processes are involved in entering ICSP Program/Verify mode using MCLR: 1. 2. 3. MCLR is briefly driven high, then low. A 32-bit key sequence is clocked into PGDx. MCLR is then driven high within a specified period of time and held. Once the key sequence is complete, an interval of at least P7 should elapse, and the voltage should remain at VIHH. The voltage, VIHH, must be held at that level for as long as the Program/Verify mode is to be maintained. An interval of at least P7 must elapse before presenting the data on PGDx. The programming voltage, VIH, is applied to MCLR; this is VDD in the case of PIC24FXXKA1XX/FVXXKA3XX devices. There is no minimum time requirement for holding at VIH. After VIH is removed, an interval of at least P18 must elapse before presenting the key sequence on PGDx. Signals appearing on PGDx before P7 has elapsed will not be interpreted as valid. Upon a successful entry, the program memory can be accessed and programmed in serial fashion. While in ICSP mode, all unused I/Os are placed in a high-impedance state. The key sequence is a specific 32-bit pattern: ‘0100 1101 0100 0011 0100 1000 0101 0001‘ (more easily remembered as 4D434851h in hexadecimal). The device will enter Program/Verify mode only if the sequence is valid. The Most Significant bit (MSb) of the most significant nibble must be shifted in first. 3.3.3 CODE-PROTECT ICSP ENTRY When code protection is employed on the PIC24FXXKA3XX devices (BWRP, GSS0 or GWRP = 0), then the voltage on VDD must be above VBULK in order to erase, and then program the device. Care must be taken in the design and layout of a board so that any parts connected to VDD can withstand what may be an increase in voltage if the device is running below VBULK. Once the key sequence is complete, VIH must be applied to MCLR and held at that level for as long as the Program/Verify mode is to be maintained. An interval of at least P19 and P7 must elapse before presenting data on PGDx. Signals appearing on PGCx before P7 has elapsed would not be interpreted as valid. FIGURE 3-4: HIGH-VOLTAGE ICSP ENTRY ENTERING ICSP™ MODE USING LOW-VOLTAGE ENTRY P6 P19 P14 MCLR P7 VIH VIH VDD Program/Verify Entry Code = 4D434851h 0 b31 PGDx 1 b30 0 b29 0 b28 1 b27 ... 0 b3 0 b2 0 b1 1 b0 PGCx P1A P1B P18 FIGURE 3-5: ENTERING ICSP™ MODE USING HIGH-VOLTAGE ENTRY P7 VIHH P6 VIH VPP VDD Program/Verify Entry Code = 4D434851h 0 b31 PGDx 1 b30 0 b29 0 b28 1 b27 ... 0 b3 0 b2 0 b1 1 b0 PGCx P18 2008-2012 Microchip Technology Inc. P1A P1B DS39919C-page 9 PIC24FXXKA1XX/FVXXKA3XX 3.4 Flash Memory Programming in ICSP Mode 3.4.1 PROGRAMMING OPERATIONS The NVMCON register controls the Flash memory write and erase operations. To program the device, set the NVMCON register to select the type of erase operation (see Table 3-2) or write operation (see Table 3-3). Set the WR control bit (NVMCON<15>) to initiate the program. TABLE 3-2: NVMCON Value NVMCON VALUES FOR ERASE OPERATIONS Erase Operation 4064h Erase the code memory and Configuration registers (does not erase Programming Executive code and Device ID registers). 404Ch Erase the general segment and Configuration bits associated with it. 4068h Erase the boot segment and Configuration bits associated with it. In ICSP mode, all programming operations are self-timed. There is an internal delay between setting and automatic clearing of the WR control bit when the programming operation is complete. Refer to Section 7.0 “AC/DC Characteristics and Timing Requirements” for information on the delays associated with various programming operations. 405Ah(1) Erase four rows of code memory. 4059h(1) Erase two rows of code memory. 3.4.2 STARTING AND STOPPING A PROGRAMMING CYCLE The WR bit (NVMCON<15>) is used to start an erase or write cycle. Initiate the programming cycle by setting the WR bit. All erase and write cycles are self-timed. The WR bit should be polled to determine if the erase or write cycle is complete. Start a programming cycle as follows: BSET NVMCON, #WR 4058h(1) Erase a row of code memory. 4050h Erase the entire data EEPROM memory and Configuration bits associated with it. 405Ah(1) Erase eight words of data EEPROM memory. 4059h(1) Erase four words of data EEPROM memory. 4058h(1) Erase one word of data EEPROM memory. 4054h Erase all the Configuration registers (except the code-protect fuses). 4058h(1) Erase Configuration registers except FBS and FGS. Note 1: The destination address decides the region (code memory, data EEPROM memory or Configuration register) of the erased rows/words. TABLE 3-3: NVMCON Value 4004h(1) 4004h DS39919C-page 10 (1) NVMCON VALUES FOR WRITE OPERATIONS Write Operation Write one Configuration register. Program one row (32 instruction words) of code memory or executive memory. 4004h(1) Program one word of data EEPROM memory. Note 1: The destination address decides the region (code memory, data EEPROM memory or Configuration register) of the erased rows/words. 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 3.5 FIGURE 3-6: Erasing Program Memory To erase the program memory (all of code memory, data memory and Configuration bits, including the code-protect bits), set the NVMCON to 4064h and then execute the programming cycle. BULK ERASE FLOW Start Write 4064h to NVMCON SFR Figure 3-6 illustrates the ICSP programming process for Bulk Erase. This process includes the ICSP command code, which must be transmitted (for each instruction), LSB first, using the PGCx and PGDx pins (see Figure 3-2). Set the WR bit to Initiate Erase Delay P11 + P10 Time Table 3-4 provides the steps for executing serial instruction for the Bulk Erase mode. Note: End Program memory must be erased before writing any data to program memory. TABLE 3-4: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR CHIP ERASE Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Set the NVMCON to erase the entire program memory. 0000 0000 24064A 883B0A MOV MOV #0x4064, W10 W10, NVMCON Step 3: Set the TBLPAG and perform dummy table write to select the erased memory. 0000 0000 0000 0000 0000 0000 200000 880190 200000 BB0800 000000 000000 MOV MOV MOV TBLWTL NOP NOP #<PAGEVAL>, W0 W0, TBLPAG #0x0000, W0 W0, [W0] BSET NOP NOP NVMCON, #WR Step 4: Initiate the erase cycle. 0000 0000 0000 A8E761 000000 000000 Step 5: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. 0000 0000 0000 0000 0000 0000 0001 0000 000000 040200 000000 803B02 883C22 000000 <VISI> 000000 2008-2012 Microchip Technology Inc. NOP GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out the contents of the VISI register. NOP DS39919C-page 11 PIC24FXXKA1XX/FVXXKA3XX 3.6 Writing Code Memory The procedure for writing code memory is the same as writing the Configuration registers. The difference is that the 32 instruction words are programmed one at a time. To facilitate this operation, working registers, W0:W5, are used as temporary holding registers for the data to be programmed. Figure 3-8 illustrates the code memory writing flow. Table 3-5 provides the ICSP programming details, including the serial pattern with the ICSP command code, which must be transmitted, LSB first, using the PGCx and PGDx pins (see Figure 3-2). In Step 1 of Table 3-5, the Reset vector is exited; in Step 2, the NVMCON register is initialized for programming a full row of code memory, and in Step 3, the 24-bit starting destination address for programming is loaded into the TBLPAG register and W7 register. The upper byte of the starting destination address is stored in TBLPAG and the lower 16 bits of the destination address are stored in W7. After the write latches are loaded, initiate programming by writing to the NVMCON register in Steps 7 and 8. In Step 9, the internal PC is reset to 200h. This is a precautionary measure to prevent the PC from incrementing to unimplemented memory when large devices are being programmed. Finally, in Step 10, repeat Steps 3 through 9 until all of the code memory is programmed. FIGURE 3-7: PACKED INSTRUCTION WORDS IN W0:W5 15 8 7 W0 0 LSW0 W1 MSB1 W2 MSB0 LSW1 W3 LSW2 W4 MSB3 W5 MSB2 LSW3 To minimize the programming time, a packed instruction format is used (see Figure 3-7). In Step 4 of Table 3-5, four packed instruction words are stored in working registers, W0:W5, using the MOV instruction. The Read Pointer, W6, is initialized. Figure 3-7 illustrates the contents of W0:W5 holding the packed instruction word data. In Step 5, eight TBLWT instructions are used to copy the data from W0:W5 to the write latches of the code memory. Since code memory is programmed, 32 instruction words at a time, Steps 3 to 5 are repeated eight times to load all the write latches (see Step 6). TABLE 3-5: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Set the NVMCON to program 32 instruction words. 0000 0000 24004A 883B0A MOV MOV #0x4004, W10 W10, NVMCON Step 3: Initialize the Write Pointer (W7) for TBLWT instruction. 0000 0000 0000 200xx0 880190 2xxxx7 MOV MOV MOV #<DestinationAddress23:16>, W0 W0, TBLPAG #<DestinationAddress15:0>, W7 Step 4: Load W0:W5 with the next 4 instruction words to program. 0000 0000 0000 0000 0000 0000 DS39919C-page 12 2xxxx0 2xxxx1 2xxxx2 2xxxx3 2xxxx4 2xxxx5 MOV MOV MOV MOV MOV MOV #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 #<LSW2>, W3 #<MSB3:MSB2>, W4 #<LSW3>, W5 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX TABLE 3-5: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY (CONTINUED) Data (Hex) Description Step 5: Set the Read Pointer (W6) and load the (next set of) write latches. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 EB0300 000000 BB0BB6 000000 000000 BBDBB6 000000 000000 BBEBB6 000000 000000 BB1BB6 000000 000000 BB0BB6 000000 000000 BBDBB6 000000 000000 BBEBB6 000000 000000 BB1BB6 000000 000000 CLR NOP TBLWTL NOP NOP TBLWTH.B NOP NOP TBLWTH.B NOP NOP TBLWTL NOP NOP TBLWTL NOP NOP TBLWTH.B NOP NOP TBLWTH.B NOP NOP TBLWTL NOP NOP W6 [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] Step 6: Repeat Steps 3 though 5, eight times, to load the write latches for 32 instructions. Step 7: Initiate the write cycle. 0000 0000 0000 A8E761 000000 000000 BSET NOP NOP NVMCON, #WR Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. 0000 0000 0000 0000 0000 0001 0000 040200 000000 803B02 883C22 000000 <VISI> 000000 GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out contents of the VISI register. NOP Step 9: Reset device internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 Step 10: Repeat Steps 3 through 9 until the entire code memory is programmed. 2008-2012 Microchip Technology Inc. DS39919C-page 13 PIC24FXXKA1XX/FVXXKA3XX FIGURE 3-8: PROGRAM CODE MEMORY FLOW Start N=1 LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> N=N+1 No All bytes written? Yes N=1 LoopCount = LoopCount + 1 Start Write Sequence and Poll for WR bit to be Cleared No All locations done? Yes End DS39919C-page 14 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 3.7 Writing Data EEPROM Figure 3-9 illustrates the flow of programming the data EEPROM memory. The procedure is the same as writing code memory. The only difference is that only one word is programmed in each operation. When writing data EEPROM, one word is programmed during each operation. Working register, W0, is used as a temporary holding register for the data to be programmed. TABLE 3-6: Command (Binary) Table 3-6 provides the ICSP programming details for writing data EEPROM. Note: When writing to EEPROM, always set the TBLPAG register to 7Fh. This is the upper byte address of all locations of data EEPROM. INSTRUCTION EXECUTION FOR WRITING DATA EEPROM Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Set the NVMCON to program one data word. 0000 0000 24004A 883B0A MOV MOV #0x4004, W10 W10, NVMCON Step 3: Initialize the Write Pointer (W7) for TBLWT instruction. 0000 0000 0000 2007F0 880190 2xxxx7 MOV MOV MOV #0x7F, W0 W0, TBLPAG #<DestinationAddress15:0>, W7 Step 4: Load W0 with the data word to program and load the write latch. 0000 0000 0000 0000 2xxxx0 BB1B80 000000 000000 MOV TBLWTL NOP NOP #<Data_Word_Value>, W0 W0, [W7++] BSET NOP NOP NVMCON, #WR Step 5: Initiate the write cycle. 0000 0000 0000 A8E761 000000 000000 Step 6: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. 0000 0000 0000 0000 0000 00001 0000 040200 000000 803B02 883C22 000000 <VISI> 000000 GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out contents of the VISI register. NOP Step 7: Reset device internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 Step 8: Repeat Steps 4 through 7 until the entire data EEPROM memory is programmed. 2008-2012 Microchip Technology Inc. DS39919C-page 15 PIC24FXXKA1XX/FVXXKA3XX FIGURE 3-9: PROGRAM DATA EEPROM MEMORY FLOW Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> LoopCount = LoopCount + 1 Start Write Sequence and Poll for WR bit to be Cleared No All locations done? Yes End DS39919C-page 16 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 3.8 Writing Configuration Registers TABLE 3-7: The procedure for writing the Configuration registers is the same as for writing code memory. The only difference is that only one word is programmed in each operation. When writing Configuration registers, one word is programmed during each operation; only working register, W0, is used as a temporary holding register for the data to be programmed. Table 3-7 provides the Configuration registers. Note: default values of the When writing to the Configuration registers, always set the TBLPAG register to F8h. This is the upper byte address of all locations of the Configuration registers. Table 3-7 provides the ICSP programming details for programming the Configuration registers, including the serial pattern with the ICSP command code, which must be transmitted, LSB first, using the PGCx and PGDx pins (see Figure 3-2). In Step 1 of Table 3-8, the Reset vector is exited. In Step 2, the NVMCON register is initialized for programming code memory. In Step 3, the 24-bit starting destination address for programming is loaded into the TBLPAG register and W7 register. 2008-2012 Microchip Technology Inc. Configuration Registers DEFAULT VALUES FOR CONFIGURATION REGISTER SERIAL INSTRUCTION Value FBS 0Fh FGS 03h FOSCSEL 87h FOSC FFh FWDT DFh FPOR(1) FBh FICD(2) C3h FDS FFh Note 1: 2: The I2C2SEL bit (FPOR<4>) is not implemented on PIC24FXXKAX01 devices and should be programmed as ‘1’. The FICD<6> bit is a reserved bit and should be programmed as ‘1’. DS39919C-page 17 PIC24FXXKA1XX/FVXXKA3XX TABLE 3-8: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERS Data (Hex) Command (Binary) Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize the Write Pointer (W7) for the TBLWT instruction. 0000 200007 MOV #0x0000, W7 Step 3: Set the NVMCON register to program Configuration registers. 0000 0000 24004A 883B0A MOV MOV #0x4004, W10 W10, NVMCON Step 4: Initialize the TBLPAG register. 0000 0000 200F86 880190 MOV MOV #0xF8, W6 W0, TBLPAG Step 5: Load the Configuration register data to W6. 0000 2xxxx6 MOV #<FBS_VALUE>, W6 Step 6: Write the Configuration register data to the write latch and increment the Write Pointer. 0000 0000 0000 0000 000000 BB1B86 000000 000000 NOP TBLWTL NOP NOP W6, [W7++] Step 7: Initiate the write cycle. 0000 0000 0000 A8E761 000000 000000 BSET NOP NOP NVMCON, #WR Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. 0000 0000 0000 0000 0000 0001 0000 040200 000000 803B02 883C22 000000 <VISI> 000000 GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out contents of the VISI register. NOP Step 9: Reset device internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 Step 10: Repeat Steps 5 through 9 to write other fuses. Load W6 with their respective values and W7 with their respective addresses. DS39919C-page 18 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 3.9 Reading Code Memory To read the code memory, execute a series of TBLRD instructions and clock out the data using the REGOUT command. Table 3-9 provides the ICSP programming details for reading code memory. In Step 1, the Reset vector is exited. In Step 2, the 24-bit starting source address for reading is loaded into the TBLPAG register and the W6 register. The upper byte of the starting source address is stored in TBLPAG, and the lower 16 bits of the source address are stored in W6. TABLE 3-9: Command (Binary) To minimize the reading time, the packed instruction word format, which was used for writing, is also used for reading (see Figure 3-7). In Step 3, the Write Pointer, W7, is initialized. In Step 4, two instruction words are read from code memory, and clocked out of the device through the VISI register, using the REGOUT command. Step 4 is repeated until the required amount of code memory is read. SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY Data (Hex) Description Step 1: Exit Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize TBLPAG and the Read Pointer (W6) for TBLRD instruction. 0000 0000 0000 200xx0 880190 2xxxx6 MOV MOV MOV #<SourceAddress23:16>, W0 W0, TBLPAG #<SourceAddress15:0>, W6 Step 3: Initialize the Write Pointer (W7) to point to the VISI register. 0000 0000 207847 000000 MOV NOP #VISI, W7 Step 4: Read and clock out the contents of the next two locations of code memory through the VISI register using the REGOUT command. 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0001 0000 BA0B96 000000 000000 <VISI> 000000 BA8BB6 000000 000000 BAD3D6 000000 000000 <VISI> 000000 BA0BB6 000000 000000 <VISI> 000000 TBLRDL [W6], [W7] NOP NOP Clock out contents of VISI register. NOP TBLRDH [W6++], [W7] NOP NOP TBLRDH.B [++W6], [W7--] NOP NOP Clock out contents of VISI register. NOP TBLRDL [W6++], [W7] NOP NOP Clock out contents of VISI register. NOP Step 5: Reset device internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 Step 6: Repeat Steps 4 and 5 until the required code memory is read. 2008-2012 Microchip Technology Inc. DS39919C-page 19 PIC24FXXKA1XX/FVXXKA3XX 3.10 Reading Data EEPROM Memory The procedure for reading data EEPROM memory is the same as reading the code memory. The only difference is that the 16-bit data words are read instead of the 24-bit words. TABLE 3-10: Command (Binary) Table 3-10 provides the ICSP programming details for reading data memory. Note: When reading from EEPROM, always set the TBLPAG register to 7Fh. This is the upper byte address of all locations of data EEPROM. SERIAL INSTRUCTION EXECUTION FOR READING DATA EEPROM MEMORY Data (Hex) Description Step 1: Exit Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize TBLPAG and the Read Pointer (W6) for TBLRD instruction. 0000 0000 0000 2007F0 880190 2FExx6 MOV MOV MOV #0x7F, W0 W0, TBLPAG #<SourceAddress15:0>, W6;(FExx) Step 3: Initialize the Write Pointer (W7) to point to the VISI register. 0000 0000 207847 000000 MOV NOP #VISI, W7 Step 4: Read and clock out the contents of the next location of data EEPROM memory through the VISI register using the REGOUT command. 0000 0000 0000 0001 0000 BA0BB6 000000 000000 <VISI> 000000 TBLRDL [W6++], [W7] NOP NOP Clock out contents of VISI register. NOP Step 5: Repeat Step 4 until the required data EEPROM memory is read. Step 6: Reset device internal PC. 0000 0000 DS39919C-page 20 040200 000000 GOTO NOP 0x200 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 3.11 Reading Configuration Memory The procedure for reading a Configuration register is the same as reading the code memory. The only difference is that the 16-bit data words are read (with the upper byte read being all ‘0‘s) instead of the 24-bit words. There are eight Configuration registers and they are read, one register at a time. TABLE 3-11: Command (Binary) Table 3-11 provides the ICSP programming details for reading all of the Configuration registers. Note: When reading from the Configuration registers, always set the TBLPAG register to F8h. This is the upper byte address of all locations of the Configuration registers. The Read Pointer, W6, should be initialized to 00h. SERIAL INSTRUCTION EXECUTION FOR READING ALL THE CONFIGURATION REGISTERS Data (Hex) Description Step 1: Exit Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize TBLPAG, the Read Pointer (W6) and the Write Pointer (W7) for TBLRD instruction. 0000 0000 0000 0000 0000 200F80 880190 200006 207847 000000 MOV MOV MOV MOV NOP #0xF8, W0 W0, TBLPAG #0x0000, W6 #VISI, W7 Step 3: Read the Configuration register and write it to the VISI register (located at 784h), and clock out the VISI register using the REGOUT command. 0000 0000 0000 0001 BA0BB6 000000 000000 <VISI> TBLRDL [W6++], [W7] NOP NOP Clock out contents of VISI register. Step 4: Repeat Step 3 to read other fuses. Load W6 with their respective address. Step 5: Reset device internal PC. 0000 0000 040200 000000 GOTO NOP 2008-2012 Microchip Technology Inc. 0x200 DS39919C-page 21 PIC24FXXKA1XX/FVXXKA3XX 3.12 Verifying Code Memory, Data EEPROM Memory and Configuration Registers FIGURE 3-10: Start To verify the code memory, read the code memory space and compare it with the copy held in the programmer’s buffer. To verify the data EEPROM and Configuration registers, follow the similar procedure. Set TBLPTR = 0 Figure 3-10 illustrates the verify process flowchart. Memory reads occur, 1 byte at a time, hence 2 bytes must be read to compare with the word in the programmer’s buffer. Refer to Section 3.9 “Reading Code Memory” for implementation details of reading code memory. On the same lines, the data EEPROM and Configuration registers can be verified. Note: VERIFY CODE MEMORY FLOW Read Low Byte with Post-Increment Read High Byte with Post-Increment Code memory should be verified immediately after writing if code protection is enabled. Since Configuration registers include the device code protection bit, the device will not be readable or verifiable if a device Reset occurs after the code-protect bits are set (value = 0). Does Word = Expect Data? No Failure Report Error Yes No All code memory verified? Yes End DS39919C-page 22 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 3.13 Reading the Application ID Word The Application ID Word is stored in address, 8007F0h, in the executive code memory. To read this memory location, use the SIX control code to move this program memory location to the VISI register. Then, the REGOUT control code must be used to clock the contents of the VISI register out of the device. Table 3-12 provides the corresponding control and instruction codes that must be serially transmitted to the device to perform this operation. 3.14 Exit the Program/Verify mode by removing VIH from MCLR/VPP, as illustrated in Figure 3-11. The only requirement to exit is that an interval of P16 should elapse between the last clock and program signals on PGCx and PGDx before removing VIH. FIGURE 3-11: After the programmer has clocked out the Application ID Word, it must be inspected. If the Application ID has the value, CBh, the Programming Executive resides in the memory and the device can be programmed using the mechanism described in Section 4.0 “Device Programming – Enhanced ICSP”. However, if the Application ID has any other value, the Programming Executive does not reside in the memory; it must be loaded to memory before the device can be programmed. Section 5.4 “Programming the Programming Executive to Memory” describes the procedure for loading the Programming Executive to memory. TABLE 3-12: Command (Binary) Exiting ICSP Mode EXITING ICSP™ MODE P16 P17 VIH/VIHH MCLR/VPP VDD VIH PGDx PGCx PGD = Input SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORD Data (Hex) Description Step 1: Exit Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize TBLPAG and the Read Pointer (W0) for TBLRD instruction. 0000 0000 0000 0000 0000 0000 0000 0000 200800 880190 207F00 207841 000000 BA0890 000000 000000 MOV MOV MOV MOV NOP TBLRDL NOP NOP #0x80, W0 W0, TBLPAG #0x7F0, W0 #VISI, W1 [W0], [W1] Step 3: Output the VISI register using the REGOUT command. 0001 0000 <VISI> 000000 Clock out contents of the VISI register. NOP 2008-2012 Microchip Technology Inc. DS39919C-page 23 PIC24FXXKA1XX/FVXXKA3XX 4.0 Note: DEVICE PROGRAMMING – ENHANCED ICSP The Programming Executive (PE) can be located in the following folder within your installation of MPLAB® IDE: ...\Microchip\MPLAB IDE\REAL ICE and then selecting the hex PE file, RIPE_01b_xxxxxx.hex. This section describes the programming of the device through Enhanced ICSP and the Programming Executive. The Programming Executive resides in the executive memory (separate from user memory space) and is executed when Enhanced ICSP Programming mode is entered. The Programming Executive provides the mechanism for the programmer (host device) to program and verify the PIC24FXXKA1XX/FVXXKA3XX devices, using a simple command set and communication protocol. The basic functions provided by the Programming Executive are: • • • • Read Memory Program Memory Blank Check Read Executive Firmware Revision The Programming Executive performs the low-level tasks required for erasing, programming and verifying a device. This allows the programmer to program the device by issuing the appropriate commands and data. Table 4-1 provides these commands. For detailed descriptions of each command, see Section 5.2 “Programming Executive Commands”. TABLE 4-1: COMMAND SET SUMMARY Command Description SCHECK Sanity check. READC Read Device ID registers. READD Read data EEPROM memory. READP Read Code register. PROGC Write User ID. PROGD Program and verify one word of data EEPROM memory. PROGP Program and verify one row of code memory or one Configuration register. QBLANK Query if the code memory is blank. QVER Query the software version. The Programming Executive uses the device’s data RAM for variable storage and program execution. After the Programming Executive is run, no assumptions should be made about the contents of the data RAM. 4.1 Overview of the Programming Process Figure 4-1 illustrates the high-level overview of the programming process. Perform the following steps: 1. 2. 3. 4. 5. 6. 7. 8. 9. Enter ICSP mode. Erase the device. Verify the Programming Executive. Exit ICSP mode. Enter Enhanced ICSP mode. Program the code memory. Verify the code memory. Program the Configuration registers. Verify the Configuration registers. Steps 7 and 9 ensure that the programming was successful. After the Programming Executive is verified in memory (or loaded, if not present), the PIC24FXXKA1XX/FVXXKA3XX devices can be programmed using the command set provided in Table 4-1. FIGURE 4-1: HIGH-LEVEL ENHANCED ICSP™ PROGRAMMING FLOW Start Enter ICSP™ Mode Perform Chip Erase Exit ICSP Mode Enter Enhanced ICSP Mode Program and Verify Code Memory Program and Verify Data EEPROM Memory Program and Verify Configuration Bits Exit Enhanced ICSP Mode End DS39919C-page 24 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 4.2 Confirming the Presence of the Programming Executive Before beginning programming, confirm if the Programming Executive is stored in the executive memory and perform the following: 1. 2. Enter In-Circuit Serial Programming mode (ICSP). Read the unique Application ID Word stored in the executive memory. Figure 4-2 illustrates this procedure. If the Programming Executive is resident, the Application ID Word is CBh, which means programming can resume as normal. However, if the Application ID Word is not CBh, the Programming Executive must be programmed to executive code memory, using the method described in Section 5.4 “Programming the Programming Executive to Memory”. Section 3.0 “Device Programming – ICSP” describes the ICSP programming method. Section 3.13 “Reading the Application ID Word” describes the procedure for reading the Application ID Word in ICSP mode. FIGURE 4-2: CONFIRMING PRESENCE OF PROGRAMMING EXECUTIVE Start Enter ICSP™ Mode Read the Application ID from Address 8007F0h Is Application ID CBh? No Yes Prog. Executive is Resident in Memory Prog. Executive must be Programmed Finish 2008-2012 Microchip Technology Inc. DS39919C-page 25 PIC24FXXKA1XX/FVXXKA3XX 4.3 Entering Enhanced ICSP Mode 4.3.1 LOW-VOLTAGE ENTRY Perform the following steps to enter Enhanced ICSP Program/Verify mode using MCLR: 1. 2. 3. Briefly drive the MCLR pin high and then low. Clock a 32-bit key sequence into PGDx. Drive the MCLR high within a specified period and continue to hold high. Figure 4-3 illustrates this procedure. The programming voltage applied to MCLR is VIH, which is essentially VDD in the case of PIC24FXXKA1XX/FVXXKA3XX devices. There is no minimum time requirement for holding at VIH. After VIH is removed, an interval of at least P18 must elapse before presenting the key sequence on PGDx. The key sequence is a specific 32-bit pattern: ‘0100 1101 0100 0011 0100 1000 0101 0000’ (more easily remembered as 4D434850h in hexadecimal format). The device will enter Program/Verify mode only if the key sequence is valid. The MSB of the most significant nibble must be shifted in first. Once the key sequence is complete, VIH must be applied to MCLR and held at that level for as long as the Program/Verify mode is to be maintained. An interval of at least P19 and P7 must elapse before presenting data on PGDx. Signals appearing on PGDx before P7 has elapsed will not be interpreted as valid. DS39919C-page 26 4.3.2 HIGH-VOLTAGE ENTRY The procedure for entering Enhanced ICSP Program/Verify mode, using the VPP pin, is the same as entering the mode using MCLR. The only differences are that the programming voltage applied to VPP is VIHH, and before presenting the key sequence on PGDx, an interval of at least P18 should elapse. Figure 4-4 illustrates this procedure. Once the key sequence is complete, VIHH must be applied to VPP and held at that level for as long as the Program/Verify mode is to be maintained. An interval of at least P19 and P7 should elapse before presenting data on PGDx. Signals appearing on PGDx before P7 has elapsed will not be interpreted as valid. On successful entry, the program memory can be accessed and programmed in serial fashion. While in the Program/Verify mode, all unused I/Os are placed in the high-impedance state. 4.3.3 CODE-PROTECT ICSP ENTRY When code protection is employed on the PIC24FXXKA3XX devices (BWRP, GSS0 or GWRP = 0), then the voltage on VDD must be above VBULK in order to erase, and then program, the device. Care must be taken in the design and layout of a board so that any parts connected to VDD can withstand what may be an increase in voltage if the device is running below VBULK. 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX FIGURE 4-3: ENTERING ENHANCED ICSP™ MODE USING LOW-VOLTAGE ENTRY P6 P19 P14 MCLR P7 VIH VIH VDD Program/Verify Entry Code = 4D434850h PGDx 0 1 0 0 1 b31 b30 b29 b28 b27 ... 0 0 0 0 b3 b2 b1 b0 PGCx P1A P18 P1B FIGURE 4-4: ENTERING ENHANCED ICSP™ MODE USING HIGH-VOLTAGE ENTRY P6 VIHH VPP P7 VDD Program/Verify Entry Code = 4D434850h PGDx 0 1 0 0 1 b31 b30 b29 b28 b27 ... 0 0 0 0 b3 b2 b1 b0 PGCx P18 P1A P1B 2008-2012 Microchip Technology Inc. DS39919C-page 27 PIC24FXXKA1XX/FVXXKA3XX 4.4 Blank Check The term, “Blank Check”, implies verifying if the device has been successfully erased and has no programmed memory locations. A blank or erased memory location is always read as ‘1’. The Device ID registers (FF0002h:FF0000h) can be ignored by the Blank Check, as this region stores device information that cannot be erased. The device Configuration registers are also ignored by the Blank Check. Additionally, all unimplemented memory space should be ignored by the Blank Check. The QBLANK command is used for the Blank Check. It determines if the code memory is erased by testing these memory regions. A ‘BLANK’ or ‘NOT BLANK’ response is returned. If it is determined that the device is not blank, it must be erased before attempting to program the device. 4.5 4.5.1 4.5.2 PROGRAMMING VERIFICATION After the code memory is programmed, the contents of the memory can be verified to ensure that the programming is successful. Verification requires the code memory to be read back and compared with the copy held in the programmer‘s buffer. The READP command can be used to read back all of the programmed code memory. Alternatively, the programmer can perform the verification, after the entire device is programmed, using a checksum computation. FIGURE 4-5: FLOWCHART FOR PROGRAMMING CODE MEMORY Start Code Memory Programming BaseAddress = 00h RemainingCmds = 176 PROGRAMMING METHODOLOGY Code memory is programmed with the PROGP command. PROGP programs one row of code memory, starting from the memory address specified in the command. The number of PROGP commands required to program a device depends on the number of write blocks that must be programmed in the device. Send PROGP Command to Program BaseAddress Is PROGP response PASS? Figure 4-5 illustrates an example flowchart for programming code memory. In this example, all 5.5K instruction words of a PIC24FXXKA1XX/FVXXKA3XX device are programmed. • First, the number of commands to send (titled ‘RemainingCmds’ in the flowchart) is set to 176 and the destination address (called ‘BaseAddress’) is set to ‘0’. • Next, one write block in the device is programmed with a PROGP command. Each PROGP command contains data for one row of code memory of the PIC24FXXKA1XX/FVXXKA3XX device. • After the first command is processed successfully, ‘RemainingCmds’ is decremented by 1 and compared with ‘0’. Since there are more PROGP commands to be sent, ‘BaseAddress’ is incremented by 40h to point to the next row of memory. On the second PROGP command, the second row is programmed. This process is repeated until the entire device is programmed. Special handling should not be performed when a panel boundary is crossed. DS39919C-page 28 No Yes RemainingCmds = RemainingCmds – 1 BaseAddress = BaseAddress + 40h No Are RemainingCmds ‘0’? Yes End Failure Report Error 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 4.6 4.6.1 Data EEPROM Programming FIGURE 4-6: FLOWCHART FOR PROGRAMMING DATA EEPROM PROGRAMMING METHODOLOGY The Programming Executive uses the PROGD command to program the data EEPROM. Figure 4.7 illustrates this process. • First, the number of words to program (RemainingWords) is based on the device size and the destination address (DestAddress) is set to ‘0’. In this example, 256 words of data EEPROM will be programmed. • The first PROGD command programs the first word of data EEPROM. • Once the command completes successfully, ‘RemainingWords’ is decremented by 1 and compared with ‘0’. • Since there are 255 more words to program, ‘BaseAddress’ is incremented by 02h to point to the next word of data EEPROM. • This process is then repeated until all 256 words of data EEPROM are programmed. 4.6.2 PROGRAMMING VERIFICATION Once the data EEPROM is programmed, the contents of the memory can be verified to ensure the programming was successful. Verification requires the data EEPROM to be read back and compared with the copy held in the programmer’s buffer. The READD command reads back the programmed data EEPROM. Alternatively, the programmer can perform the verification, once the entire device is programmed, using a checksum computation, as described in Section 6.1.1 “Checksum Computation”. 2008-2012 Microchip Technology Inc. Start RemainingWords = 256 (100h) BaseAddress = 0 Send PROGD Command to Program BaseAddress Is PROGD response PASS? No Yes RemainingWords = RemainingWords – 1 BaseAddress = BaseAddress + 02h No Are RemainingWords ‘0’? Yes Finish Failure Report Error DS39919C-page 29 PIC24FXXKA1XX/FVXXKA3XX 4.7 Configuration Bits Programming The PIC24FXXKA1XX/FVXXKA3XX family has eight Configuration registers. The bits of these registers can be set or cleared to select various device configurations. There are three types of Configuration bits: Eight PROGP commands are required to program the Configuration bits. Figure 4-7 illustrates the flowchart for Configuration bit programming. Note: • System Operation Bits These bits determine the power-on settings for system-level components, such as the oscillator and Watchdog Timer. • Code-Protect Bits These bits prevent program memory from being read and written. • Device ID Bits These are read-only bits, which are located from FF0000 to FF0003, and are unique to every device. Table 4-2 provides the Configuration registers. 4.7.1 PROGRAMMING METHODOLOGY Configuration bits may be programmed, a single byte at a time, using the PROGP command. This command specifies the configuration data and Configuration register address. When Configuration bits are programmed, any unimplemented or reserved bits must be programmed with a ‘1’. FIGURE 4-7: 4.7.2 If the General Segment Code-Protect bit (GCP) is programmed to ‘0‘, code memory is code-protected and cannot be read. Code memory must be verified before enabling code protection. See Section 4.7.3 “Code-Protect Configuration Bits” for more information on code-protect Configuration bits. PROGRAMMING VERIFICATION After the Configuration bits are programmed, the contents of memory should be verified to ensure that the programming was successful. Verification requires the Configuration bits to be read back and compared against the copy held in the programmer‘s buffer. The READP command reads back the programmed Configuration bits and verifies that the programming was successful. CONFIGURATION BIT PROGRAMMING FLOW Start ConfigAddress = F80000h Send PROGP Command Is PROGP response PASS? No Yes ConfigAddress = ConfigAddress + 2 No Is ConfigAddress F80010h? Yes End DS39919C-page 30 Failure Report Error 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 4.7.3 CODE-PROTECT CONFIGURATION BITS The FBS and FGS Configuration registers are special Configuration registers, which control the code protection for the boot segment and general segment, respectively. For each segment, two forms of code protection are provided. One form prevents code memory from being written (write protection), while the other prevents code memory from being read (read protection). It is imperative that all code protection bits should be ‘1’ while the device is being programmed and verified. Only after the device is programmed and verified, should any of the above bits be programmed to ‘0’ (see Section 4.7 “Configuration Bits Programming”). Note: All bits in the FBS and FGS Configuration registers can only be programmed to a value of ‘0‘.Bulk Erasing the chip is the only way to reprogram code-protect bits from on (‘0’) to off (‘1’). The BWRP and GWRP bits control write protection and the BSS0 and GSS0 bits control read protection. When write protection is enabled, any programming operation to code memory will fail. When read protection is enabled, any read from code memory will cause a 00h to be read, regardless of the actual contents of code memory. Since the Programming Executive always verifies what it programs, attempting to program code memory, with read protection enabled, also results in failure. TABLE 4-2: Bit Field PIC24F(V)XXKAXXX FAMILY CONFIGURATION BITS DESCRIPTION Register Description BOREN<1:0> FPOR<1:0> Brown-out Reset Enable bits 11 = Brown-out Reset is enabled in hardware; SBOREN bit is disabled 10 = Brown-out Reset is enabled only while device is active and disabled in Sleep; SBOREN bit is disabled 01 = Brown-out Reset is controlled with the SBOREN bit setting 00 = Brown-out Reset is disabled in hardware; SBOREN bit is disabled BORV<1:0> FPOR<6:5> Brown-out Reset Voltage bits For PIC24FXXKA1XX and PIC24FXXKA3XX Devices: 11 = VBOR is set to 1.8V min 10 = VBOR is set to 2.7V min 01 = VBOR is set to 3.0V min For PIC24FVXXKA3XX Devices: 11 = VBOR is set to 2.0V min 10 = VBOR is set to 2.7V min 01 = VBOR is set to 3.0V min For All Devices: 00 = Downside protection on POR is enabled – “Zero-Power” is selected BSS0 FBS<3> Boot Segment Program Flash Code Protection bit 1 = Standard security is enabled 0 = High security is enabled BSZ<1:0> FBS<2:1> Boot Segment Program Flash Size Selection bits(1) 11 = No boot program Flash segment 10 = Boot program Flash segment starts at 200h, ends at 000AFEh 01 = Boot program Flash segment starts at 200h, ends at 0015FEh For PIC24FV32KA3XX Devices: 00 = Reserved For All Other Devices: 00 = Reserved Note 1: 2: This applies only to 28-pin devices. The MCLRE fuse can only be changed when using the VPP-Based Test mode entry. This prevents a user from accidentally locking out the device from low-voltage test entry. 2008-2012 Microchip Technology Inc. DS39919C-page 31 PIC24FXXKA1XX/FVXXKA3XX TABLE 4-2: Bit Field PIC24F(V)XXKAXXX FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED) Register Description BWRP FBS<0> Boot Segment Program Flash Write Protection bit 1 = Boot segment may be written 0 = Boot segment is write-protected DEBUG FICD<7> Background Debugger Enable bit 1 = Background debugger is disabled 0 = Background debugger functions are enabled DSWDTEN FDS<7> Deep Sleep Watchdog Timer Enable bit 1 = DSWDT is enabled 0 = DSWDT is disabled DSWCKSEL FDS<4> DSWDT Reference Clock Select bit 1 = DSWDT uses LPRC as the reference clock 0 = DSWDT uses SOSC as the reference clock DSWDTPS<3:0> FDS<3:0> Deep Sleep Watchdog Timer Postscale Select bits The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms. 1111 = 1:2,147,483,648 (25.7 days) 1110 = 1:536,870,912 (6.4 days) 1101 = 1:134,217,728 (38.5 hours) 1100 = 1:33,554,432 (9.6 hours) 1011 = 1:8,388,608 (2.4 hours) 1010 = 1:2,097,152 (36 minutes) 1001 = 1:524,288 (9 minutes) 1000 = 1:131,072 (135 seconds) 0111 = 1:32,768 (34 seconds) 0110 = 1:8,192 (8.5 seconds) 0101 = 1:2,048 (2.1 seconds) 0100 = 1:512 (528 ms) 0011 = 1:128 (132 ms) 0010 = 1:32 (33 ms) 0001 = 1:8 (8.3 ms) 0000 = 1:2 (2.1 ms) DSBOREN FDS<6> Deep Sleep Zero-Power BOR Enable bit 1 = Zero-Power BOR is enabled in Deep Sleep 0 = Zero-Power BOR is disabled in Deep Sleep (does not affect operation in non Deep Sleep modes) FCKSM<1:0> FOSC<7:6> Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled FNOSC<2:0> FOSCSEL<2:0> Oscillator Selection bits 000 = Fast RC Oscillator (FRC) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 010 = Primary Oscillator (XT, HS, EC) 011 = Primary Oscillator with PLL module (HS+PLL, EC+PLL) 100 = Secondary Oscillator (SOSC) 101 = Low-Power RC Oscillator (LPRC) 110 = Reserved; do not use 111 = Fast RC Oscillator with divide-by-N (FRCDIV) Note 1: 2: This applies only to 28-pin devices. The MCLRE fuse can only be changed when using the VPP-Based Test mode entry. This prevents a user from accidentally locking out the device from low-voltage test entry. DS39919C-page 32 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX TABLE 4-2: Bit Field PIC24F(V)XXKAXXX FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED) Register Description FWDTEN FWDT<7> Watchdog Timer Enable bit (PIC24FXXKA1XX devices only) 1 = WDT is enabled 0 = WDT is disabled (control is placed on the SWDTEN bit) FWDTEN<1:0> FWDT<7,5> Watchdog Timer Enable bits (all PIC24FVXXKA3XX devices) 11 = WDT is enabled in hardware 10 = WDT is controlled with the SWDTEN bit 01 = WDT is enabled only while device is active and disabled in Sleep; SWDTEN bit is disabled 00 = WDT is disabled in hardware; SWDTEN bit is disabled GSS0 FGS<1> General Segment Code Flash Code Protection bit 1 = No protection 0 = Standard security is enabled GWRP FGS<0> General Segment Code Flash Write Protection bit 1 = General segment may be written 0 = General segment is write-protected ICS<1:0> FICD<1:0> ICD Pin Placement Select bits 11 = ICD EMUC/EMUD pins are shared with PGEC1/PGED1 10 = ICD EMUC/EMUD pins are shared with PGEC2/PGED2 01 = ICD EMUC/EMUD pins are shared with PGEC3/PGED3 00 = Reserved; do not use IESO FOSCSEL<7> Internal External Switchover bit 1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled) 0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled) I2C1SEL FPOR<4> Alternate I2C1 Pin Mapping bit(1) 1 = Default location for SCL1/SDA1 pins 0 = Alternate location for SCL1/SDA1 pins MCLRE FPOR<7> MCLR Pin Enable bit(2) 1 = MCLR pin is enabled; RA5 input pin is disabled 0 = RA5 input pin is enabled; MCLR is disabled OSCIOFNC FOSC<2> CLKO Enable Configuration bit 1 = CLKO output signal is active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMD<1:0> = 11 or 00) 0 = CLKO output is disabled POSCMD<1:0> FOSC<1:0> Primary Oscillator Configuration bits 11 = Primary oscillator is disabled 10 = HS Oscillator mode is selected (4 MHz-25 MHz) 01 = XT Oscillator mode is selected (100 kHz-4 MHz) 00 = External Clock mode is selected POSCFREQ<1:0> FOSC<4:3> Note 1: 2: Primary Oscillator Frequency Range Configuration bits 11 = Primary oscillator/external clock input frequency is greater than 8 MHz 10 = Primary oscillator/external clock input frequency is between 100 kHz and 8 MHz 01 = Primary oscillator/external clock input frequency is less than 100 kHz 00 = Reserved; do not use This applies only to 28-pin devices. The MCLRE fuse can only be changed when using the VPP-Based Test mode entry. This prevents a user from accidentally locking out the device from low-voltage test entry. 2008-2012 Microchip Technology Inc. DS39919C-page 33 PIC24FXXKA1XX/FVXXKA3XX TABLE 4-2: Bit Field PIC24F(V)XXKAXXX FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED) Register Description PWRTEN FPOR<3> Power-up Timer Enable bit 1 = PWRT is enabled 0 = PWRT is disabled RTCCKSEL FDS<5> RTCC Reference Clock Select bit (PIC24FXXKA1XX devices only) 1 = RTCC uses SOSC as the reference clock 0 = RTCC uses LPRC as the reference clock SOSCSEL FOSC<5> Secondary Oscillator Select bit 1 = Secondary oscillator is configured for high-power operation 0 = Secondary oscillator is configured for low-power operation FWPSA FWDT<4> WDT Prescaler bit 1 = WDT prescaler ratio of 1:128 0 = WDT prescaler ratio of 1:32 WDTPS<3:0> FWDT<3:0> Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 WINDIS FWDT<6> Windowed Watchdog Timer Disable bit 1 = Standard WDT is selected; windowed WDT is disabled 0 = Windowed WDT is enabled Note 1: 2: 4.8 This applies only to 28-pin devices. The MCLRE fuse can only be changed when using the VPP-Based Test mode entry. This prevents a user from accidentally locking out the device from low-voltage test entry. Exiting the Enhanced ICSP Mode To exit the Program/Verify mode, remove VIH from MCLR/VPP, as illustrated in Figure 4-8. For exiting, an interval, P16, should elapse between the last clock, and program signals on PGCx and PGDx, before removing VIH. FIGURE 4-8: EXITING ENHANCED ICSP™ MODE P16 P17 VIH/VIHH MCLR/VPP VDD VIH PGDx PGCx PGDx = Input DS39919C-page 34 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 5.0 THE PROGRAMMING EXECUTIVE This section describes the Programming Executive communication, Programming Executive commands, programming responses, programming the Programming Executive to memory and programming verification. 5.1 Programming Executive Communication The programmer and the Programming Executive have a master-slave relationship, where the programmer is the master programming device and the Programming Executive is the slave. Communication is initiated by the programmer in the form of a command. Only one command at a time can be sent to the Programming Executive. The Programming Executive, in turn, only sends one response to the programmer after receiving and processing a command. The Programming Executive command set is described in Section 5.2 “Programming Executive Commands”. The response set is described in Section 5.3 “Programming Executive Responses”. 5.1.1 COMMUNICATION INTERFACE AND PROTOCOL The Enhanced ICSP interface is a two-wire SPI, implemented using the PGCx and PGDx pins. The PGCx pin is used as a clock input pin; the programmer should provide the clock source. The PGDx pin is used to send the command data to, and receive response data from, the Programming Executive. As a 2-wire SPI is used and data transmissions are half-duplex, a simple protocol is used to control the direction of PGDx. When the programmer completes a command transmission, it releases the PGDx line and allows the Programming Executive to drive this line high. The Programming Executive keeps the PGDx line high to indicate that it is processing the command. After the Programming Executive has processed the command, it brings PGDx low for 15 sec to indicate to the programmer that the response is available to be clocked out. The programmer can begin to clock out the response, 23 sec after PGDx is brought low, and it must provide the necessary amount of clock pulses to receive the entire response from the Programming Executive. After the entire response is clocked out, the programmer should terminate the clock on PGCx until it is time to send another command to the Programming Executive; Figure 5.2 displays this protocol. 5.1.2 SPI RATE In Enhanced ICSP mode, the PIC24FXXKA1XX/FVXXKA3XX family devices operate from the internal Fast RC Oscillator, which has a nominal frequency of 8 MHz. This oscillator frequency yields an effective system clock frequency of 4 MHz. To ensure that the programmer does not clock too fast, it is recommended that a 4 MHz clock be provided by the programmer. FIGURE 5-2: PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA TRANSMITTED TO DEVICE Data transmits to the device should change on the rising edge and hold on the falling edge of PGCx. Data receives from the device change on the falling edge and holds on the rising edge of PGCx. The data transmissions are sent to the MSB first, using 16-bit mode (see Figure 5-1 and Figure 5-2). FIGURE 5-1: PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA RECEIVED FROM DEVICE P1 1 2 3 4 5 6 11 12 13 14 15 16 PGCx P1A P1B PGDx MSb P3 P2 14 13 12 11 ... 5 4 3 2 1 LSb P1 1 2 3 4 5 6 11 12 13 14 15 16 1 LSb PGCx P1A P1B P3 P2 PGDx MSb 14 13 12 11 ... 5 4 2008-2012 Microchip Technology Inc. 3 2 DS39919C-page 35 PIC24FXXKA1XX/FVXXKA3XX 5.1.3 TIME-OUTS does not have a time-out, it is imperative that the programmer correctly follow the described communication protocol. The Programming Executive does not use the Watchdog Timer or time-out for transmitting responses to the programmer. If the programmer does not follow the flow control mechanism using PGCx, as described in Section 5.1.1 “Communication Interface and Protocol”, it is possible that the Programming Executive will behave unexpectedly while trying to send a response to the programmer. Since the Programming Executive FIGURE 5-3: As a safety measure, the programmer should use the command time-outs, identified and listed in Table 5-1. If the command time-out expires, the programmer should reset the Programming Executive and start programming the device again. PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL Host Transmits Last Command Word 1 2 Programming Executive Processes Command Host Clocks Out Response 1 15 16 2 15 16 1 2 15 16 PGCx PGDx MSB X X X LSB 1 P8 PGCx = Input PGDx = Input 5.2 Programming Executive Commands COMMAND FORMAT The Programming Executive commands have a general format, consisting of a 16-bit header and any required data for the command (see Figure 5-4). The 16-bit header consists of a 4-bit opcode field, which is used to identify the command, followed by a 12-bit command length field. DS39919C-page 36 P20 MSB X X X LSB P21 PGCx = Input (Idle) PGDx = Output The Programming Executive command set is listed in Table 5-1. This table contains the opcode, mnemonic, length, time-out and description for each command. Section 5.2.4 “Command Descriptions” provides functional details on each command. 5.2.1 MSB X X X LSB 0 P9 PGCx = Input PGDx = Output FIGURE 5-4: 15 12 COMMAND FORMAT 11 0 Opcode Length Command Data First Word (if required) • • Command Data Last Word (if required) The command opcode must match one of those in the command set. Any command that is received that does not match the list in Table 5-1 returns a “NACK” response (see Section 5.3.1.1 “Opcode Field”). The command length is represented in 16-bit words as the SPI operates in 16-bit mode. The Programming Executive uses the command length field to determine the number of words to read from the SPI port. If the value of this field is incorrect, the command will not be properly received by the Programming Executive. 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 5.2.2 PACKED DATA FORMAT 5.2.3 When 24-bit instruction words are transferred across the 16-bit SPI interface, they are packed to conserve space using the format illustrated in Figure 5-5. This format minimizes the traffic over the SPI and provides the Programming Executive the data that is properly aligned for performing table write operations. FIGURE 5-5: PACKED INSTRUCTION WORD FORMAT 15 8 7 0 LSW1 MSb2 LSWx: Least Significant 16 bits of instruction word MSbx: Most Significant bits of instruction word Note: COMMAND DESCRIPTIONS The commands supported by the Programming Executive are described in Section 5.2.5 “SCHECK Command” through Section 5.2.13 “QVER Command”. When the number of instruction words transferred is odd, MSb2 is zero and LSW2 cannot be transmitted. TABLE 5-1: Opcode The Programming Executive will return a “NACK” response for all unsupported commands. Additionally, due to the memory constraints of the Programming Executive, no checking is performed on the data contained in the programmer command. It is the responsibility of the programmer to command the Programming Executive with valid command arguments; otherwise, the programming operation might fail. Section 5.3.1.3 “QE_Code Field” provides additional information on error handling. 5.2.4 MSb1 LSW2 PROGRAMMING EXECUTIVE ERROR HANDLING PROGRAMMING EXECUTIVE COMMAND SET Mnemonic Length (16-bit words) Time-out Description 0h SCHECK 1 1 ms Sanity check. 1h READC 3 1 ms Read up to (256) 8-bit words, starting from the specified Device ID register. 2h READP 4 1 ms/row 3h RESERVED N/A N/A This command is reserved; it returns a NACK. 4h PROGC 4 5 ms Write an 8-bit word to the specified Device ID registers. 5h PROGP 99 5 ms Program up to 32 instructions (one row) of code memory at the specified address and then verify.(1) 6h RESERVED N/A N/A This command is reserved; it returns a NACK. 7h RESERVED N/A N/A This command is reserved; it returns a NACK. 8h RESERVED N/A N/A This command is reserved; it returns a NACK. Read up to 32K instruction words of code memory, starting from the specified address.(1) 9h RESERVED N/A N/A This command is reserved; it returns a NACK. Ah QBLANK 3 TBD Query if the code memory is blank.(1) Bh QVER 1 1 ms Query the Programming Executive software version. Ch RESERVED N/A N/A This command is reserved; it returns a NACK. Dh RESERVED N/A N/A Eh READD 4 1 ms/word Fh PROGD 19 5 ms Note 1: This command is reserved. it returns a NACK. Read up to (256) 16-bit words, starting from the specified address. Program one word of data EEPROM memory at the specified address and then verify. One row of code memory consists of (32) 24-bit words. Refer to Table 2-2 for device-specific information. 2008-2012 Microchip Technology Inc. DS39919C-page 37 PIC24FXXKA1XX/FVXXKA3XX 5.2.5 SCHECK COMMAND 15 12 11 5.2.6 0 Opcode 15 READC COMMAND 12 11 Opcode Length 8 7 0 Length N Field Opcode Description 0h Length 1h The SCHECK command instructs the Programming Executive to merely generate a response. This command is used as a “Sanity Check” to verify if the Programming Executive is operational. Expected Response (2 words): 1000h Field This instruction is provided for development purposes only; this is not required for programming. Description Opcode 1h Length 3h N Number of 8-bit Device ID registers to read (max. of 256). Addr_MSB MSb of 24-bit source address. Addr_LS Least Significant 16 bits of 24-bit source address. 0002h Note: Addr_MSB Addr_LS The READC command instructs the Programming Executive to read N or Device ID registers, starting from the 24-bit address specified by Addr_MSB and Addr_LS. Note: The READC command can only be used to read 8-bit or 16-bit data. When this command is used to read the Device ID registers, the upper byte in every data word returned by the Programming Executive is 00h and the lower byte contains the Device ID register value. Expected Response (4 + 3 * (N – 1)/2 words for N odd): 1100h 2+N Device ID Register 1 ... Device Register N Note: DS39919C-page 38 Reading unimplemented memory will cause the Programming Executive to reset. Ensure that only memory locations present on a particular device are accessed. 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 5.2.7 READD COMMAND 15 12 11 Opcode 5.2.8 8 7 0 READP COMMAND 15 12 11 Reserved0 N Reserved1 Addr_MSB 0 Length N Reserved Addr_MSB Addr_LS Addr_LS Field 8 7 Opcode Length Field Description Description Opcode Eh Opcode 2h Length 4h Length 4h Reserved0 0h N N Number of 16-bit words to read (max. of 256). Number of 24-bit instructions to read (max. of 32768). Reserved 0h Reserved1 0h Addr_MSB MSb of 24-bit source address. Addr_MSB MSb of 24-bit source address. Addr_LS Addr_LS Least Significant 16 bits of 24-bit source address. Least Significant 16 bits of 24-bit source address. The READD command instructs the Programming Executive to read N 16-bit words from data EEPROM memory, starting from the 24-bit address specified by Addr_MSB and Addr_LS. Note: This command can only be used to read 16-bit data. Expected Response (N + 2 words): 1E00h 2+N Data word 1 ... Data word N The READP command instructs the Programming Executive to read N 24-bit words of code memory, including Configuration registers, starting from the 24-bit address specified by Addr_MSB and Addr_LS. Note: This command can only be used to read 24-bit data. The entire data returned in response to this command uses the packed data format described in Section 5.2.2 “Packed Data Format”. Expected Response (2 + 3 * N/2 words for N even): 1200h 2 + 3 * N/2 LSB program memory word 1 ... LSB data word N Expected Response (4 + 3 * (N – 1)/2 words for N odd): 1200h 4 + 3 * (N – 1)/2 LSB program memory word 1 ... MSB of program memory word N (zero-padded) Note: 2008-2012 Microchip Technology Inc. Reading unimplemented memory will cause the Programming Executive to reset. Ensure that only memory locations present on a particular device are accessed. DS39919C-page 39 PIC24FXXKA1XX/FVXXKA3XX 5.2.9 PROGC COMMAND 15 12 11 5.2.10 8 7 Opcode 0 Length Reserved Field PROGD COMMAND 15 12 11 8 7 Opcode 0 Length Reserved Addr_MSB Addr_MSB Addr_LS Addr_LS Data D_1 Description Field Description Opcode 4h Opcode Fh Length 4h Length 4h Reserved 0h Reserved 0h Addr_MSB MSb of 24-bit destination address. Addr_MSB MSB of 24-bit source address. Addr_LS Least Significant 16 bits of 24-bit destination address. Addr_LS Least Significant 16 bits of 24-bit source address. Data 8-bit data word. D_1 16-bit data word. The PROGC command instructs the Programming Executive to program a single User ID register, located at the specified memory address. After the specified data word has been programmed to code memory, the Programming Executive verifies the programmed data against the data in the command. Expected Response (2 words): 1400h 0002h The PROGD command instructs the Programming Executive to program one word (16-bit) of data EEPROM memory, starting from the 24-bit address specified by Addr_MSB and Addr_LS. Once one word of data EEPROM has been programmed, the Programming Executive verifies the programmed data against the data in the command. Expected Response (2 words): 1F00h 0002h Note: DS39919C-page 40 Refer to Table 2-2 for data EEPROM memory size information. 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 5.2.11 PROGP COMMAND 15 12 11 5.2.12 8 7 Opcode 0 Length Reserved 15 QBLANK COMMAND 12 11 Length Addr_MSB Addr_LS 0 Opcode PSize Reserved DSize Field Description D_1 D_2 ... Opcode Ah D_48 Length 3h PSize Length of program memory to check in 24-bit words (max. of 49152). 5h Reserved 0h Length 33h DSize Reserved 0h Length of data memory to check in 16-bit words (max. of 2048). Addr_MSB MSb of 24-bit destination address. Addr_LS Least Significant 16 bits of 24-bit destination address. D_1 16-bit data word 1. D_2 16-bit data word 2. ... 16-bit data word 3 through 47. D_48 16-bit data word 48. Field Opcode Description The PROGP command instructs the Programming Executive to program one row of code memory to the specified memory address. Programming begins with the row address specified in the command. The destination address should be a multiple of 40h. The data to program to memory, located in command words, D_1 through D_48, should be arranged using the packed instruction word format depicted in Figure 5-5. After the entire data is programmed to code memory, the Programming Executive verifies the programmed data against the data in the command. The PROGP command is also used to program Configuration Words. While PROGP is used to program Configuration Words, the length in the command should be four. Only one Configuration Word at a time can be programed. The unimplemented bits of the Configuration Word should be stuffed with ‘1’s. The QBLANK command queries the Programming Executive to determine if the contents of code memory and code-protect Configuration bits (GCP and GWRP) are blank (contain all ‘1’s). The size of the code memory to check should be specified in the command. The Blank Check for code memory begins at 0h and advances toward larger addresses for the specified number of instruction words. QBLANK returns a QE_Code of F0h if the specified code memory and code-protect bits are blank; otherwise, it returns a QE_Code of 0Fh. Expected Response (2 words for blank device): 1AF0h 0002h Expected Response (2 words for non-blank device): 1A0Fh 0002h Note: QBLANK does not check the system operation Configuration bits as these bits are not set to ‘1’ when a Chip Erase is performed. Expected Response (2 words): 1500h 0002h Note: Refer to Table 2-2 for program memory size information. 2008-2012 Microchip Technology Inc. DS39919C-page 41 PIC24FXXKA1XX/FVXXKA3XX 5.2.13 15 QVER COMMAND 12 11 Length Field Description Bh Length 1h Programming Executive Responses 0 Opcode Opcode 5.3 The QVER command queries the version of the Programming Executive software stored in the test memory. The “version.revision” information is returned in the response‘s QE_Code using a single byte in the following format: The main version is in the upper nibble and the revision is in the lower nibble (i.e., 23h stands for Version 2.3 of the Programming Executive software). Expected Response (2 words): 1BMNh (“MN” stands for version M.N) 0002h The Programming Executive sends a response to the programmer for each command that it receives. The response indicates if the command was processed correctly. It includes any required response data or error data. The Programming Executive response set is provided in Table 5-2. This table contains the opcode, mnemonic and description for each response. The response format is described in Section 5.3.1 “Response Format”. TABLE 5-2: Opcode PROGRAMMING EXECUTIVE RESPONSE OPCODES Mnemonic Description 1h PASS Command successfully processed. 2h FAIL Command unsuccessfully processed. 3h NACK Command not known. 5.3.1 RESPONSE FORMAT All Programming Executive responses have a general format, consisting of a two-word header and any required data for the command. 15 12 11 Opcode 8 7 Last_Cmd 0 QE_Code Length D_1 (if applicable) ... D_N (if applicable) Field DS39919C-page 42 Description Opcode Response opcode. Last_Cmd Programmer command that generated the response. QE_Code Query code or error code. Length Response length in 16-bit words (includes 2 header words). D_1 First 16-bit data word (if applicable). D_N Last 16-bit data word (if applicable). 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 5.3.1.1 Opcode Field The opcode is a 4-bit field in the first word of the response. The opcode indicates how the command was processed (see Table 5-2). If the command was processed successfully, the response opcode is PASS. If there was an error in processing the command, the response opcode is FAIL and the QE_Code indicates the reason for the failure. If the command sent to the Programming Executive is not identified, the Programming Executive returns a NACK response. 5.3.1.2 Last_Cmd Field The Last_Cmd is a 4-bit field in the first word of the response and it indicates the command that the Programming Executive processed. As the Programming Executive can process only one command at a time, this field is technically not required. However, it can be used to verify that the Programming Executive correctly received the command that the programmer transmitted. 5.3.1.3 QE_Code Field The QE_Code is a byte in the first word of the response. This byte is used to return data for query commands and error codes for all of the other commands. When the Programming Executive processes one of the two query commands (QBLANK or QVER), the returned opcode is always PASS and the QE_Code holds the query response data. If a command is successfully processed, the returned QE_Code is set to 0h, which indicates that there was no error in the command processing. If the verify of the programming for the PROGP or PROGC command fails, the QE_Code is set to 1h. For all other Programming Executive errors, the QE_Code is 2h. TABLE 5-4: QE_Code FOR NON-QUERY COMMANDS QE_Code 0h Description No error. 1h Verify failed. 2h Other error. 5.3.1.4 Response Length The response length indicates the length of the Programming Executive’s response in 16-bit words. This field includes the two words of the response header. With the exception of the response for the READP command, the length of each response is only two words. The response to the READP command uses the packed instruction word format, described in Section 5.2.2 “Packed Data Format”. When reading an odd number of program memory words (N odd), the response to the READP command is (3 * (N + 1)/2 + 2) words. When reading an even number of program memory words (N even), the response to the READP command is (3 * N/2 + 2) words. Table 5-3 provides the format of the QE_Code for both queries. TABLE 5-3: Query QE_Code FOR QUERIES QE_Code QBLANK 0Fh = Code memory is NOT blank F0h = Code memory is blank QVER 0xMN, where Programming Executive Software Version = M.N (i.e., 32h stands for Version 3.2 of the Programming Executive software) When the Programming Executive processes any command other than a query, the QE_Code represents an error code. Table 5-4 provides the supported error codes. 2008-2012 Microchip Technology Inc. DS39919C-page 43 PIC24FXXKA1XX/FVXXKA3XX 5.4 Programming the Programming Executive to Memory This section describes the programming of the Programming Executive to memory and also provides the procedure to perform this. 5.4.1 OVERVIEW If it is determined that the Programming Executive is not present in the executive memory (as described in Section 4.2 “Confirming the Presence of the Programming Executive”), it must be programmed into the executive memory using ICSP, as described in Section 3.0 “Device Programming – ICSP”. TABLE 5-5: Command (Binary) Storing the Programming Executive to executive memory is the same as normal programming of code memory. The executive memory should be erased and then the Programming Executive must be programmed, 32 words at a time. Erasing the last page of executive memory causes the device diagnostic data in the Diagnostic addresses, 8007F4h to 8007FEh, to be erased. To retain this data, the memory locations should be read and stored prior to erasing the executive memory, and then be reprogrammed in the last words of program memory. Table 5-5 provides this control flow. PROGRAMMING THE PROGRAMMING EXECUTIVE Data (Hex) Description Step 1: Exit Reset vector and erase the executive memory. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize pointers to read Diagnostic Words for storage in data RAM. 0000 0000 0000 0000 0000 200800 880190 207F41 208002 000000 MOV MOV MOV MOV NOP #0x80, W0 W0, TBLPAG #0x07F4, W1 #0x0800, W2 Step 3: Repeat this step, six times, to read Diagnostic Words, storing them in data RAM starting at 0x800. 0000 0000 0000 BA0191 000000 000000 BA8231 000000 000000 781903 000000 781904 000000 TBLRDL NOP NOP TBLRDH NOP NOP MOV NOP MOV NOP [W1], W3 [W1++], W4 W3, [W2++] W4, [W2++] Step 4: Initialize the NVMCON to erase the executive memory. 0000 0000 2405A0 883B00 MOV MOV #0x405A, W0 W0, NVMCON MOV MOV MOV NOP TBLWTL NOP NOP BSET NOP NOP #0x80, W0 W0, TBLPAG #0x00, W1 Step 5: Initiate the erase cycle. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 DS39919C-page 44 200800 880190 200001 000000 BB0881 000000 000000 A8E761 000000 000000 W1, [W1] NVMCON, #15 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX TABLE 5-5: Command (Binary) PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED) Data (Hex) Description Step 6: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. 0000 0000 0000 0000 0000 0000 0001 0000 040200 000000 803B02 883C22 000000 000000 <VISI> 000000 GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP NOP Clock out contents of the VISI register NOP Step 7: Repeat Steps 5 and 6 to erase the rest of the executive memory. W1 should be incremented by 100h each time to point to the next four rows. Step 8: Initialize the NVMCON registers. 0000 0000 240041 883B01 MOV MOV #0x4004, W1 W1, NVMCON Step 9: Initialize TBLPAG and the Write Pointer (W2). 0000 0000 0000 0000 200800 880190 EB0280 000000 MOV MOV CLR NOP #0x80, W0 W0, TBLPAG W5 Step 10: Load W0:W2 with the next two words of packed Programming Executive code. 0000 0000 0000 2<LSW0>0 MOV 2<MSB1:MSB0>1 MOV 2<LSW1>2 MOV #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 Step 11: Set the Read Pointer (W6) and load the (next four write) latches. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 EB0200 000000 BB0AB4 000000 000000 BBDAB4 000000 000000 BBEAB4 000000 000000 BB1AB4 000000 000000 CLR NOP TBLWTL NOP NOP TBLWTH.B NOP NOP TBLWTH.B NOP NOP TBLWTL NOP NOP W4 [W4++], [W5] [W4++], [W5++] [W4++], [++W5] [W4++], [W5++] Step 12: Repeat Steps 10 and 11, sixteen times, to load the write latches for the 32 instructions. Step 13: Initiate the programming cycle. 0000 0000 0000 A8E761 000000 000000 BSET NOP NOP 2008-2012 Microchip Technology Inc. NVMCON, #15 DS39919C-page 45 PIC24FXXKA1XX/FVXXKA3XX TABLE 5-5: Command (Binary) PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED) Data (Hex) Description Step 14: Repeatedly read the NVMCON register and poll for WR bit to get cleared. 0000 0000 0000 0000 0000 0000 0001 0000 040200 000000 803B02 883C22 000000 000000 <VISI> 000000 GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP NOP Clock out contents of the VISI register NOP Step 15: Reset the device internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 Step 16: Repeat Steps 8 through 15 until the executive has been programmed. Step 17: Pre-fill the table write latches with 0xFFFF 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 200800 880190 207FC0 2FFFF5 BB0A05 000000 000000 BB9A05 000000 000000 MOV MOV MOV MOV TBLWTL NOP NOP TBLWTH NOP NOP #0x80, W0 W0, TBLPAG #0x07C0, W4 #0xFFFF, W5 w5,[w4] w5,[w4++] Step 18: Repeat 32 times to fill each latch. Step 19: Load the data RAM address into W4. 0000 0000 208004 000000 MOV NOP #0x0800, W4 Step 20: Load the saved Diagnostic Words in the write latch. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 207F45 780134 000000 7801B4 000000 BB0A82 000000 000000 BB9A83 000000 000000 MOV MOV NOP MOV NOP TBLWTL NOP NOP TBLWTH NOP NOP 0x07F4, W5 [W4++], W2 [W4++], W3 W2, [W5] W3, [W5++] Step 21: Repeat Step 20 for each of the six saved Diagnostic Words. Step 22: Execute code from Step 13 to initiate the programming cycle. Step 23: Execute code from Step 14 to poll the WR bit. DS39919C-page 46 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 5.5 Programming Verification After the Programming Executive is programmed to the executive memory, using ICSP, it must be verified. Verify by reading out the contents of the executive memory and comparing it with the image of the Programming Executive stored in the programmer. Table 5-6 provides the procedure for reading the executive memory. Note: In Step 2 of Table 5-6, the TBLPAG register must be set to 80h in order to read the executive memory. Read the contents of the executive memory using the same method described in Section 3.9 “Reading Code Memory”. TABLE 5-6: Command (Binary) READING EXECUTIVE MEMORY Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize TBLPAG and the Read Pointer (W6) for TBLRD instruction. 0000 0000 0000 200800 880190 EB0300 MOV MOV CLR #0x80, W0 W0, TBLPAG W6 Step 3: Initialize the Write Pointer (W7) to point to the VISI register. 0000 0000 207847 000000 MOV NOP #VISI, W7 Step 4: Read and clock out the contents of the next two locations of the executive memory through the VISI register, using the REGOUT command. 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0001 0000 BA0B96 000000 000000 <VISI> 000000 BA8BB6 000000 000000 BAD3D6 000000 000000 <VISI> 000000 BA0BB6 000000 000000 <VISI> 000000 TBLRDL [W6], [W7] NOP NOP Clock out contents of VISI register NOP TBLRDH [W6++], [W7] NOP NOP TBLRDH.B [++W6], [W7--] NOP NOP Clock out contents of VISI register NOP TBLRDL [W6++], [W7] NOP NOP Clock out contents of VISI register NOP Step 5: Reset the device internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 Step 6: Repeat Steps 4 and 5 until the entire executive memory is read. 2008-2012 Microchip Technology Inc. DS39919C-page 47 PIC24FXXKA1XX/FVXXKA3XX 6.0 DEVICE ID TABLE 6-1: Device ID The Device ID region of memory can be used to determine the mask, variant and manufacturing information about the device. The Device ID region is 2 x 16 bits and it can be read using the READC command. This region of memory is read-only and can also be read when code protection is enabled. Table 6-1 provides the Device ID for each device and Table 6-2 provides the Device ID registers. Table 6-3 describes the bit field of each register. TABLE 6-2: DEVICE IDs DEVID PIC24F08KA101 0D08h PIC24F16KA101 0D01h PIC24F08KA102 0D0Ah PIC24F16KA102 0D03h PIC24FV16KA301 4509h PIC24F16KA301 4508h PIC24FV16KA302 4503h PIC24F16KA302 4502h PIC24FV16KA304 4507h PIC24F16KA304 4506h PIC24FV32KA301 4519h PIC24F32KA301 4518h PIC24FV32KA302 4513h PIC24F32KA302 4512h PIC24FV32KA304 4517h PIC24F32KA304 4516h PIC24FXXKA1XX/FVXXKA3XX DEVICE ID REGISTERS Bit Address Name 15 FF0000h DEVID FF0002h DEVREV TABLE 6-3: Bit Field 14 13 12 11 10 9 8 7 6 FAMID<7:0> 4 3 2 1 0 DEV<7:0> — REV<3:0> DEVICE ID BITS DESCRIPTION Register Description FAMID<7:0> DEVID Encodes the family ID of the device. DEV<7:0> DEVID Encodes the individual ID of the device. REV<3:0> DEVREV DS39919C-page 48 5 Encodes the revision number of the device. 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX 6.1 6.1.1 Checksums Table 6-4 describes how to calculate the checksum for each device. CHECKSUM COMPUTATION Checksums for the PIC24FXXKA1XX/FVXXKA3XX family are 16 bits. The checksum is calculated by summing the following: • Contents of the code memory locations • Contents of the Configuration registers TABLE 6-4: All memory locations are summed, one byte at a time, using only their native data size. More specifically, Configuration registers are summed by adding the lower two bytes of these locations (the upper byte is ignored) while the code memory is summed by adding all three bytes of the code memory. CHECKSUM COMPUTATION Chip Checksum with 0xAAAAAA at 0x00 Location and at Last Location 0x7F5A Device Read Code Protection Checksum Computation Erased Checksum Value PIC24FV32KA30X(1) Disabled CFGB + SUM (0:0057FE) 0x8158 Enabled 0 0x0000 0x0000 PIC24FV16KA30X(1) Disabled CFGB + SUM (0:002BFE) 0xC358 0xC15A Enabled 0 0x0000 0x0000 PIC24F16KA1XX Disabled CFGB + SUM (0:002BFE) 0xC334 0xC136 Enabled 0 0x0000 0x0000 PIC24F08KA1XX Disabled CFGB + SUM (0:0015FE) 0xE434 0xE236 Enabled 0 0x0000 0x0000 Description Legend: Item SUM[a:b] = Byte sum of locations, a to b inclusive (all 3 bytes of code memory) CFGB = Configuration Block (masked): For PIC24FXXKA1 devices: Byte sum of (FBS & 0x000F + FGS & 0x0003 + FOSCSEL & 0x0087 + FOSC & 0x00FF + FWDT & 0x00DF + FPOR & 0x00FB + FICD & 0x00C3 + FDS & 0x00FF) For PIC24FVXXKA3 devices: Byte sum of (FBS & 0x000F + FGS & 0x0003 + FOSCSEL & 0x00E7 + FOSC & 0x00FF + FWDT & 0x00FF + FPOR & 0x00FF + FICD & 0x0083 + FDS & 0x00DF) Note 1: This includes PIC24FVXXKA3XX devices. 2008-2012 Microchip Technology Inc. DS39919C-page 49 PIC24FXXKA1XX/FVXXKA3XX 7.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS TABLE 7-1: STANDARD OPERATING CONDITIONS Standard Operating Conditions Operating Temperature: 0C to +70C and programming: +25C is recommended. Param Symbol No. D111 VDD Characteristic Supply Voltage During Programming Min Max Units 2.0 3.60 V Normal programming, PIC24FXXKA1XX and PIC24FXXKA3XX VDDCORE 5.00 V Normal programming, PIC24FVXXKA3XX — 50 A D112 IPP Programming Current on MCLR D113 IDDP Supply Current During Programming — 2 mA D031 VIL Input Low Voltage VSS 0.2 VDD V D041 VIH Input High Voltage 0.8 VDD VDD V D042 VIHH Programing Voltage on VPP VDD + 1.5 9 V D080 VOL Output Low Voltage — 0.4 V Conditions IOL = 8.5 mA @ 3.6V D090 VOH Output High Voltage 1.4 — V IOH = -3.0 mA @ 3.6V D012 CIO Capacitive Loading on I/O pin (PGDx) — 50 pF To meet AC specifications D100 VBULK Bulk Erase Voltage 2.7 — V PIC24F(V)XXKA3XX 2.0 — V PIC24FXXKA1XX D110 VCAP Regulator Output Voltage 3.1 3.6 V D120 CEFC 4.7 — µF P1 TPGC P1A P1B P2 TPGCL TPGCH TSET1 Serial Clock (PGCx) Period Serial Clock (PGCx) Low Time Serial Clock (PGCx) High Time 125 — ns ICSP™ mode 250 — ns Enhanced ICSP mode 50 — ns ICSP mode 100 — ns Enhanced ICSP mode 50 — ns ICSP mode 100 — ns Enhanced ICSP mode Input Data Setup Time to Serial Clock 15 — ns P3 THLD1 Input Data Hold Time from PGCx 15 — ns P4 TDLY1 Delay Between 4-Bit Command and Command Operand 40 — ns P4A TDLY1A Delay Between 4-Bit Command Operand and the Next 4-Bit Command 40 — ns P5 TDLY2 Delay Between Last PGCx of Command Byte and First PGCx of Read of Data Word 20 — ns P6 TSET2 VDD Setup Time to MCLR 100 — ns P7 THLD2 Input Data Hold Time from MCLR VPP (from VIHH to VIH) 25 — ms P8 TDLY3 Delay Between Last PGCx of Command Byte and PGDx by Programming Executive 12 — s P9 TDLY4 Programming Executive Command Processing Time 40 — s P10 TDLY6 PGCx Low Time After Programming 400 — ns P11 TDLY7 Chip Erase Time 2.5 — ms P12 TDLY10 Page (4 rows) Erase Time 2.5 — ms P13 TDLY9 Row Programming Time 1.25 — ms DS39919C-page 50 Series resistance < 3 Ohm recommended; < 5 Ohm required. 2008-2012 Microchip Technology Inc. PIC24FXXKA1XX/FVXXKA3XX TABLE 7-1: STANDARD OPERATING CONDITIONS (CONTINUED) Standard Operating Conditions Operating Temperature: 0C to +70C and programming: +25C is recommended. Param Symbol No. P14 TR Characteristic Min Max Units MCLR Rise Time to Enter ICSP™ mode — 1.0 s P15 TVALID Data Out Valid from PGCx 10 — ns P16 TDLY10 Delay Between Last PGCx and MCLR 0 — s P17 THLD3 MCLR to VDD — 100 ns P18 TKEY1 Delay Between First MCLR and First PGCx for Key Sequence on PGDx 1 — ms P19 TKEY2 Delay Between Last PGCx for Key Sequence on PGDx and Second MCLR 1 — ms P20 TDLY11 Delay Between PGDx by Programming Executive and First PGCx of Reception of Response 23 — s P21 TDLY12 Delay Between Programming Executive Command Response Words 8 — ns 2008-2012 Microchip Technology Inc. Conditions DS39919C-page 51 PIC24FXXKA1XX/FVXXKA3XX APPENDIX A: REVISION HISTORY Rev A Document (6/2008) Original version of this document, covering PIC24FXXKA1XX and PIC24XXKA20X family devices. Rev B Document (4/2011) Adds PIC24FVXXKA3XX family devices; removes PIC24FXXKA20X devices for inclusion in their own programming specification (DS399XX). These changes occur throughout the entire document, except as otherwise noted; programming algorithms remain unchanged. Updated Figure 2-3 to reflect the deletion of 14-pin packaging specific to PIC24FXXKA20X devices and the addition of 44-pin packaging for PIC24FVXXKA3XX devices. Revised Section 2.0 “Programming Overview of the PIC24FXXKA1XX/FVXXKA3XX Family” to include new information on voltage regulators for PIC24FVXXKA3XX devices. Reorganized Table 2-3 to combine information. Corrects Section 4.2 “Confirming the Presence of the Programming Executive” and Section 5.4 “Programming the Programming Executive to Memory” regarding verifying and programming the Programming Executive code. Revised Table 4-2 with new Configuration bit descriptions specific to PIC24FVXXKA3XX devices and removing descriptions specific to PIC24FXXKA20X devices. Updated Section 6.0 “Device ID” with new device ID and checksum information. Corrected existing checksum information for PIC24FXXKA1XX devices. Updated Section 7.0 “AC/DC Characteristics and Timing Requirements” for new specifications related to programming voltage for PIC24FVXXKA3XX devices (D111) and Enhanced ICSP timing specification (P1, P1A and P1B). Modified erase and programming times (P11, P12 and P13), and initial key delay for entering programming modes (P18). Other minor typographic corrections throughout. Rev C 6/2012 Added the 48-pin PIC24F(V)32KA304 to Figure 2-3: Pin Diagrams, added new checksum information regarding KM devices and added 44-pin and 48-pin devices. DS39919C-page 52 2008-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62076-337-7 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2008-2012 Microchip Technology Inc. DS39919C-page 53 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Osaka Tel: 81-66-152-7160 Fax: 81-66-152-9310 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 China - Hangzhou Tel: 86-571-2819-3187 Fax: 86-571-2819-3189 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-330-9305 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 DS39919C-page 54 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 11/29/11 2008-2012 Microchip Technology Inc.