PIC24FJ256GA412/GB412 Family Flash Programming Specification

PIC24FJ256GA412/GB412 FAMILY
PIC24FJ256GA412/GB412 Family
Flash Programming Specification
1.0
DEVICE OVERVIEW
This document defines the programming specification
for the PIC24FJ256GA412/GB412 family of 16-bit
microcontrollers with Dual Partition Flash mode functionality. This programming specification is required
only for those developing programming support for the
following devices:
• PIC24FJ256GB412
• PIC24FJ256GA412
• PIC24FJ128GB412
• PIC24FJ128GA412
• PIC24FJ64GB412
• PIC24FJ64GA412
• PIC24FJ256GB410
• PIC24FJ256GA410
• PIC24FJ128GB410
• PIC24FJ128GA410
• PIC24FJ64GB410
• PIC24FJ64GA410
• PIC24FJ256GB406
• PIC24FJ256GA406
• PIC24FJ128GB406
• PIC24FJ128GA406
• PIC24FJ64GB406
• PIC24FJ64GA406
Topics covered include:
•
•
•
•
•
•
•
•
•
Section 1.0 “Device Overview”
Section 2.0 “Programming Overview”
Section 3.0 “Device Programming – ICSP”
Section 4.0 “Device Programming – Enhanced
ICSP”
Section 5.0 “Programming the Programming
Executive to Memory”
Section 6.0 “The Programming Executive”
Section 7.0 “Dual Partition Flash
Programming Considerations”
Section 9.0 “Checksum Computation”
Section 10.0 “AC/DC Characteristics and
Timing Requirements”
Customers using only one of these devices should use
the development tools that already provide support for
device programming.
 2015 Microchip Technology Inc.
DS30010073A-page 1
PIC24FJ256GA412/GB412 FAMILY
2.0
PROGRAMMING OVERVIEW
2.1
These devices require specific connections for
programming to take place. These connections include
power, VCAP, MCLR and one programming pair (PGEDx/
PGECx). Table 2-1 describes these connections (refer to
the specific device data sheet for pin descriptions and
power connection requirements).
There are two methods of programming that are
discussed in this programming specification:
• In-Circuit Serial Programming™ (ICSP™)
• Enhanced In-Circuit Serial Programming
The ICSP programming method is the most direct
method to program the device; however, it is also the
slower of the two methods. It provides native, low-level
programming capability to erase, program and verify
the device.
2.2
Power Requirements
All PIC24FJ256GA412/GB412 family devices power
their core digital logic at a nominal 1.8V. To simplify system design, all devices in the PIC24FJ256GA412/
GB412 family incorporate an on-chip regulator that
allows the device to run its core logic from VDD.
The Enhanced ICSP protocol uses a faster method that
takes advantage of the Programming Executive (PE), as
illustrated in Figure 2-1. The PE provides all the
necessary functionality to erase, program and verify the
chip through a small command set. The command set
allows the programmer to program a PIC24FJ256GA412/
GB412 family device without dealing with the low-level
programming protocols.
FIGURE 2-1:
Required Connections
The regulator provides power to the core from the other
VDD pins. A low-ESR capacitor (such as ceramic or
tantalum) must be connected to the VCAP pin (see
Table 2-1 and Figure 2-2). This helps to maintain the
stability of the regulator. The specifications for core
voltage and capacitance are listed in Section 10.0 “AC/
DC Characteristics and Timing Requirements”.
PROGRAMMING SYSTEM
OVERVIEW FOR
ENHANCED ICSP™
FIGURE 2-2:
PIC24FJ256GA412/GB412
Programming
Executive
Programmer
CONNECTIONS FOR THE
ON-CHIP REGULATOR
3.3V
PIC24FJ256GA412/GB412
VDD
On-Chip Memory
VCAP
CEFC
(10 µF typ)
VSS
This programming specification is divided into two
major sections that describe the programming methods
independently. Section 3.0 “Device Programming –
ICSP” describes the ICSP method. Section 4.0
“Device Programming – Enhanced ICSP” describes
the Enhanced ICSP method.
TABLE 2-1:
PINS USED DURING PROGRAMMING
Pin Name
Pin Type
Pin Description
MCLR
I
Programming Enable
VDD and AVDD(1)
P
Power Supply(1)
VSS and AVSS(1)
P
Ground(1)
VCAP
P
On-Chip Voltage Regulator Filter Capacitor
PGECx
I
Programming Pin Pair: Serial Clock
PGEDx
I/O
Programming Pin Pair: Serial Data
Legend: I = Input
O = Output
P = Power
Note 1: All power supply and ground pins must be connected, including AVDD and AVSS. It is also recommended
to connect the VBAT pin to the battery or VDD during programming.
DS30010073A-page 2
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
2.3
Pin Diagrams
2.3.1
All devices in the PIC24FJ256GA412/GB412 family
have three separate pairs of programming pins, labeled
as PGEC1/PGED1, PGEC2/PGED2 and PGEC3/
PGED3. Any one of these pin pairs may be used for
device programming by either ICSP or Enhanced ICSP.
Unlike voltage supply and ground pins, it is not
necessary to connect all three pin pairs to program the
device. However, the programming method must use
both pins of the same pair.
Figure 2-3 through Figure 2-5 show the pin diagrams
for the PIC24FJ256GA412/GB412 family. The pins that
are required for programming are listed in Table 2-1
and are indicated in bold text in the figures. Refer to the
appropriate device data sheet for complete pin
descriptions.
FIGURE 2-3:
PGECx AND PGEDx PIN PAIRS
PIN DIAGRAMS (64-PIN PACKAGES)
49
50
51
52
53
54
55
56
57
59
58
60
61
62
64
64-Pin QFN(1)
63
RE4
RE3
RE2
RE1
RE0
RF1
RF0
VBAT
VCAP
RD7
RD6
RD5
RD4
RD3
RD2
RD1
64-Pin TQFP
1
RE5
RE6
RE7
RG6
RG7
RG8
MCLR
RG9
VSS
VDD
PGEC3
PGED3
RB3
RB2
PGEC1
PGED1
2
3
48
RC14
47
RC13
46
RD0
RD11
RD10
RD9
4
45
5
44
6
43
7
42
PIC24FJXXXXGA406
8
41
RD8
VSS
40
OSCO/RC15
10
39
OSCI/RC12
11
38
12
37
VDD
D+/RG2
13
36
14
35
15
34
16
33
VBUS/RF7
RF3
32
31
30
29
28
27
26
25
24
23
21
22
19
18
17
D-/RG3
VUSB3V3(2)
PGEC2
PGED2
AVDD
AVSS
RB8
RB9
RB10
RB11
VSS
VDD
RB12
RB13
RB14
RB15
RF4
RF5
20
PIC24FJXXXXGB406
9
Pin
Legend:
Note
1:
2:
Complete Programming Pin Functions
11
PGEC3/SEG2/AN5/C1INA/RP18/RB5
12
PGED3/SEG3/AN4/C1INB/RP28/USBOEN/RB4
15
PGEC1/SEG6/VREF-/CVREF-/AN1/AN1-/RP1/CTED12/RB1
16
PGED1/SEG7/VREF+/CVREF+/DVREF+/AN0/RP0/RB0
17
PGEC2/LCDBIAS3/AN6/RP6/RB6
18
PGED2/SEG63/AN7/RP7/U6TX/RB7
Red indicates pin functions present on PIC24FJXXXXGBXX6 devices only. Bold indicates pins used in device programming;
the complete list of functions associated with programming/emulation pins is shown in the accompanying table.
It is recommended to connect the metal pad on the bottom of the 64-pin QFN package to VSS.
RF6 on PIC24FJXXXXGA406 devices.
 2015 Microchip Technology Inc.
DS30010073A-page 3
PIC24FJ256GA412/GB412 FAMILY
FIGURE 2-4:
PIN DIAGRAMS (100-PIN PACKAGE)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
RE4
RE3
RE2
RG13
RG12
RG14
RE1
RE0
RA7
RA6
RG0
RG1
RF1
RF0
VBAT
VCAP
RD7
RD6
RD5
RD4
RD13
RD12
RD3
RD2
RD1
100-Pin TQFP
RG15
1
75
VSS
VDD
2
74
RC14
RE5
3
73
RC13
RE6
4
72
RE7
5
71
RD0
RD11
RC1
6
70
RD10
RC2
7
69
RD9
RC3
8
68
RD8
RC4
9
67
RG6
10
66
RA15
RA14
RG7
11
RG8
12
MCLR
13
RG9
14
VSS
64
VSS
OSCO/RC15
63
OSCI/RC12
62
VDD
15
61
RA5
VDD
16
60
RA4
RA0
17
59
RA3
RE8
18
58
RA2
RE9
19
57
D+/RG2
PGEC3
20
56
D-/RG3
PGED3
21
55
VUSB3V3(1)
RB3
22
54
VBUS/RF7
RB2
23
RF8
PGEC1
53
24
RF2
PGED1
52
25
51
RF3
65
Pin
Legend:
Note
1:
VSS
VDD
RD14
RD15
RF4
RF5
PGEC2
PGED2
RA9
RA10
AVDD
AVSS
RB8
RB9
RB10
RB11
VSS
VDD
RA1
RF13
RF12
RB12
RB13
RB14
RB15
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PIC24FJXXXXGA410
PIC24FJXXXXGB410
Complete Programming Pin Functions
20
PGEC3/SEG2/AN5/C1INA/RP18/RB5
21
PGED3/SEG3/AN4/C1INB/RP28/USBOEN/RB4
24
PGEC1/SEG6/VREF-/CVREF-/AN1/AN1-/RP1/CTED12/RB1
25
PGED1/SEG7/VREF+/CVREF+/DVREF+/AN0/RP0/RB0
26
PGEC2/LCDBIAS3/AN6/RP6/RB6
27
PGED2/SEG63/AN7/RP7/U6TX/RB7
Red indicates pin functions present on PIC24FJXXXXGB610 devices only. Bold indicates pins used in device programming;
the complete list of functions associated with programming/emulation pins is shown in the accompanying table.
RF6 on PIC24FJXXXXGA410devices.
DS30010073A-page 4
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
FIGURE 2-5:
PIN DIAGRAMS (PIC24FJXXXGA412/GB412 121-PIN PACKAGE)
121-Pin BGA
1
2
3
4
5
6
9
10
11
A
RE4
RE3
RG13
RE0
RG0
RF1
RD12
RD2
RD1
B
RH1
RG15
RE2
RE1
RA7
RF0
VCAP
RD5
RD3
VSS
RC14
C
RE6
VDD
RG12
RG14
RA6
VSS
RD7
RD4
RH13
RC13
RD11
D
RC1
RE7
RE5
RH2
RJ0
VDD
RD6
RD13
RD0
VSS
RD10
E
RC4
RC3
RG6
RC2
RJ1
RG1
VDD
RA15
RD8
RD9
RA14
F
MCLR
RG8
RG9
RG7
VSS
RH15
RH12
VDD
RC12
VSS
RC15
G
RE8
RE9
RA0
RH3
VDD
VSS
VSS
RH11
RA5
RA3
RA4
H
PGEC3
PGED3
RH4
RH5
RB10
VDD
RH8
J
RB3
RB2
PGED2
AVDD
RA1
RB12
RH9
K
PGEC1
PGED1
RA10
RB8
RF12
RB14
VDD
L
PGEC2
RA9
AVSS
RB9
RF13
RB13
RB15
Pin
H1
Legend:
Note
1:
RH7
RB11
RH6
7
8
VBAT
RH14
VBUS/RF7 VUSB3V3(1) D+/RG2
RH10
RA2
RF8
D-/RG3
RD15
RF3
RF2
RD14
RF4
RF5
Complete Programming Pin Functions
PGEC3/SEG2/AN5/C1INA/RP18/RB5
H2
PGED3/SEG3/AN4/C1INB/RP28/USBOEN/RB4
K1
PGEC1/SEG6/VREF-/CVREF-/AN1/AN1-/RP1/CTED12/RB1
K2
PGED1/SEG7/VREF+/CVREF+/DVREF+/AN0/RP0/RB0
L1
PGEC2/LCDBIAS3/AN6/RP6/RB6
J3
PGED2/SEG63/AN7/RP7/U6TX/RB7
Red indicates pin functions present on PIC24FJXXXXGB610 (BGA) devices only. Bold indicates pins used in device programming;
the complete list of functions associated with programming/emulation pins is shown in the accompanying table.
RF6 on PIC24FJXXXXGA412 devices.
 2015 Microchip Technology Inc.
DS30010073A-page 5
PIC24FJ256GA412/GB412 FAMILY
2.4
Program Memory Write/Erase
Requirements
The program Flash memory has a specific write/erase
requirement that must be adhered to for proper device
operation. The rule is that any given word in memory
must not be written without first erasing the page in
which it is located. Thus, the easiest way to conform
to this rule is to write all the data in a programming
block within one write cycle. The programming methods specified in this document comply with this
requirement.
2.5
Memory Map
The program memory map extends from 000000h to
FFFFFEh. Code storage is located at the base of the
memory map. The last locations of implemented
program memory are reserved for the device
Configuration bits.
Table 2-2 lists the code memory size, the size of the
erase blocks and the number of erase blocks present
in each device variant.
TABLE 2-2:
Locations, 800100h through 800BFEh, are reserved
for executive code memory. This region stores the PE
and the debugging executive, which is used for device
programming. This region of memory cannot be
used to store user code. See Section 6.0 “The
Programming Executive” for more information.
Locations, 801380h through 8013FEh, are reserved for
the customer OTP data. This area can be used for
storing product information, such as serial numbers,
system manufacturing dates, manufacturing lot numbers
and other application-specific information; it is described
in Section 2.6.3 “One-Time-Programmable (OTP)
Memory”.
Locations, FF0000h and FF0002h, are reserved for the
Device ID Word registers. These bits can be used by
the programmer to identify which device type is being
programmed. They are described in Section 8.0
“Device ID”. The Device ID registers read out
normally, even after code protection is applied.
Figure 2-6 and Figure 2-7 show the generic memory
maps for the devices described in this specification.
See the “Memory Organization” chapter in the
specific device data sheet for exact memory
addresses.
PROGRAM MEMORY SIZES AND BOUNDARIES
Program Memory Upper Boundary (Instruction Words)
Device
Write
Blocks(1)
Erase
Blocks(1)
0157FEh(44K)
1376
172
00ABFEh (22K)
00ABFEh (22K)
688
86
0057FEh (11K)
0057FEh (11K)
352
44
Dual Partition Flash Mode
Single Partition
Flash Mode
Active Partition
Inactive Partition
02AFFEh (88K)
0157FEh(44K)
PIC24FJ128GX4XX
0157FEh(44K)
PIC24FJ64GX4XX
00AFFEh (22K)
PIC24FJ256GX4XX
Note 1:
1 Write Block = 64 Instruction Words; 1 Erase Block = 512 Instruction Words.
DS30010073A-page 6
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
FIGURE 2-6:
PROGRAM MEMORY MAP FOR SINGLE PARTITION FLASH MODE
000000h
User Memory Space
User Flash Program Memory
Flash Config Words
0xxxFEh(1)
0xxx00h(1)
Unimplemented
Read ‘0’
Reserved
Executive Code Memory
Reserved
Customer OTP Memory
Configuration Memory Space
Reserved
FBOOT
7FFFFFh
800000h
800100h
800BFEh
800C00h
80137Eh
801380h
8013FEh
801400h
8017FEh
801800h
801802h
801804h
Reserved
Device Config Registers
Reserved
Flash Write Latches
F7FFFEh
F80000h
F80026h
F80028h
F9FFFEh
FA0000h
FA007Eh
FA0080h
Reserved
DEVID (2)
Reserved
FEFFFEh
FF0000h
FF0004h
FFFFFFh
Legend:
Memory areas are not shown to scale.
Note 1:
Exact boundary addresses are determined by the size of the implemented program memory. See Table 2-2
for details.
 2015 Microchip Technology Inc.
DS30010073A-page 7
PIC24FJ256GA412/GB412 FAMILY
FIGURE 2-7:
PROGRAM MEMORY MAP FOR DUAL PARTITION FLASH MODES
000000h
User Flash Program Memory
Active Partition
User Memory Space
Flash Config Words
0xxxFEh(1)
0xxx00h(1)
Unimplemented
Read ‘0’
400000h
User Flash Program Memory
Inactive Partition
Flash Config Words
4xxxFEh(1)
4xxx00h(1)
Unimplemented
Read ‘0’
Reserved
Executive Code Memory
Reserved
Customer OTP Memory
Configuration Memory Space
Reserved
FBOOT
7FFFFFh
800000h
800100h
800BFEh
800C00h
80137Eh
801380h
8013FEh
801400h
8017FEh
801800h
801802h
801804h
Reserved
Device Config Registers
Reserved
Flash Write Latches
F7FFFEh
F80000h
F80026h
F80028h
F9FFFEh
FA0000h
FA007Eh
FA0080h
Reserved
DEVID (2)
Reserved
FEFFFEh
FF0000h
FF0004h
FFFFFFh
Legend:
Memory areas are not shown to scale.
Note 1:
Exact boundary addresses are determined by the size of the implemented program memory. See Table 2-2
for details.
DS30010073A-page 8
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
2.6
Configuration Bits
2.6.1
2.6.2
OVERVIEW
The Configuration bits are stored in the last page location of implemented program memory. These bits can be
set or cleared to select various device configurations.
There are two types of Configuration bits: system operation bits and code-protect bits. The system operation
bits determine the power-on settings for system-level
components, such as the oscillator and the Watchdog
Timer. The code-protect bits prevent program memory
from being read and written.
Table 2-3 lists the Configuration register address range
for each device in Single and Dual Partition modes.
Table 2-4 lists all of the Configuration bits found in the
PIC24FJ256GA412/GB412 family devices, as well as
their Configuration register locations. Refer to the
“Special Features” chapter in the specific device data
sheet for the full Configuration register description for a
specific device.
TABLE 2-3:
Configuration
Register
CODE-PROTECT CONFIGURATION
BITS
The device implements an intermediate security feature
defined by the FSEC register. The Boot Segment (BS) is
the higher privilege segment and the General Segment
(GS) is the lower privilege segment. The total user code
memory can be split into BS or GS. The size of the
segments is determined by the BSLIM<12:0> bits. The
relative location of the segments within user space does
not change, such that BS (if present) occupies the
memory area just after the Interrupt Vector Table (IVT)
and the GS occupies the space just after the BS (or if the
Alternate IVT is enabled, just after it).
The Configuration Segment (or CS) is a small segment
(less than a page, typically just one row) within user
Flash address space. It contains all user configuration
data that is loaded by the NVM Controller during the
Reset sequence.
CONFIGURATION WORD ADDRESSES
Single Partition Flash Mode
PIC24FJ256GX4XX
PIC24FJ128GX4XX
PIC24FJ64GX4XX
FSEC
02AF80h
015780h
00AF80h
FBSLIM
02AF90h
015790h
00AF90h
FSIGN
02AF94h
015794h
00AF94h
FOSCSEL
02AF98h
015798h
00AF98h
FOSC
02AF9Ch
01579Ch
00AF9Ch
FWDT
02AFA0h
0157A0h
00AFA0h
FPOR
02AFA4h
0157A4h
00AFA4h
FICD
02AFA8h
0157A8h
00AFA8h
FDS
02AFACh
0157ACh
00AFACh
FDEVOPT1
02AFB0h
0157B0h
00AFB0h
FBOOT
801800h
Dual Partition Flash Modes(1)
FSEC(2)
015780/415780h
00AB80/40AB80h
005580/405580h
FBSLIM(2)
015790/415790h
00AB90/40AB90h
005590/405590h
FSIGN(2)
015794/415794h
00AB94/40AB94h
005594/405594h
FOSCSEL
015798/415798h
00AB98/40AB98h
005598/405598h
FOSC
01579C/41579Ch
00AB9C/40AB9Ch
00559C/40559Ch
FWDT
0157A0/4157A0h
00ABA0/40ABA0h
0055A0/4055A0h
FPOR
0157A4/4157A4h
00ABA4/40ABA4h
0055A4/4055A4h
FICD
0157A8/4157A8h
00ABA8/40ABA8h
0055A8/4055A8h
FDS
0157AC/4157ACh
00ABAC/40ABACh
0055AC/4055ACh
FDEVOPT1
0157B0/4157B0h
00ABB0/40ABB0h
0055B0/4055B0h
FBTSEQ
0157FC/4157FCh
00ABFC/40ABFCh
0055FC/4055FCh
FBOOT
Note 1:
2:
801800h
Addresses shown for Dual Partition Flash modes are for the Active/Inactive Partitions, respectively.
Changes to these Inactive Partition Configuration Words affect how the Active Partition accesses the Inactive Partition.
 2015 Microchip Technology Inc.
DS30010073A-page 9
PIC24FJ256GA412/GB412 FAMILY
TABLE 2-4: CONFIGURATION BITS FOR PIC24FJ256GA412/GB412 FAMILY DEVICES
Bit Field
Register
AIVTDIS
FSEC<15>
ALTCMPI
FDEVOPT1<1>
Description
Alternate Interrupt Vector Table bit
1 = Disables AIVT; AIVTEN (INTCON2<8>) bit is not available
0 = Enables AIVT; AIVTEN (INTCON2<8> bit is available
Alternate Comparator Location Enable bit
1 = C1INC, C2INC and C3INC are on their standard pin locations
0 = C1INC, C2INC and C3INC are on RG9
BOREN<1:0>
FPOR<1:0>
Brown-out Reset Enable bits
11 = Brown-out Reset is enabled in hardware; SBOREN bit is disabled
10 = Brown-out Reset is enabled only while device is active and is disabled in
Sleep; SBOREN bit is disabled
01 = Brown-out Reset is controlled with the SBOREN bit setting
00 = Brown-out Reset is disabled in hardware; SBOREN bit is disabled
BSLIM<12:0>
FBSLIM<12:0>
Boot Segment Code Flash Page Address Limit bits
Specifies the last Boot Segment page + 1 (the first page of the General
Segment). As this value is inverted, the default unprogrammed value (1FFFh)
sets the Boot Segment size to 0.
BSS<1:0>
FSEC<2:1>
BSEN
FSEC<3>
BTMODE<1:0>
BSEQ<11:0>
Boot Segment Code Protection Level bits
11 = No protection (other than the BWRP bit)
10 = Standard security
0x = High security
Boot Segment Control bit
1 = No Boot Segment is enabled
0 = Boot Segment size is determined by BSLIM<12:0>
FBOOT<1:0>
Device Partition Flash Mode Configuration bits
11 = Single Partition Flash mode
10 = Dual Partition Flash mode
01 = Protected Dual Partition Flash mode (Partition 1 is write-protected when
inactive)
00 = Reserved; do not use
FBTSEQ<11:0>
Boot Sequence Number bits (Dual Partition Flash modes only)
Relative value defining which partition will be active after a device Reset; the
partition containing a lower boot number will be active.
BTSWP
FICD<15>
BOOTSWP Instruction Disable bit
1 = BOOTSWP instruction is disabled
0 = BOOTSWP instruction is enabled
BWRP
FSEC<0>
Boot Segment Program Write Protection bit
1 = Boot Segment can be written
0 = Boot Segment is write-protected
CSS<2:0>
FSEC<11:9>
Configuration Segment Code Protection Level bits
111 = No protection (other than the CWRP bit)
110 = Standard security
10x = Enhanced security
0xx = High security
CWRP
FSEC<8>
Configuration Segment Program Write Protection bit
1 = Configuration Segment is not write-protected
0 = Configuration Segment is write-protected
DEBUG
FIDC<7>
Background Debugger Enable bit
1 = Background debugger is disabled
0 = Background debugger is enabled
DS30010073A-page 10
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
TABLE 2-4: CONFIGURATION BITS FOR PIC24FJ256GA412/GB412 FAMILY DEVICES (CONTINUED)
Bit Field
Register
Description
DSBOREN
FDS<6>
Deep Sleep Brown-out Reset Enable bit
1 = Deep Sleep BOR is enabled in Deep Sleep mode
0 = Deep Sleep BOR is disabled in Deep Sleep mode (remains active in
other Sleep modes)
DSSWEN
FDS<15>
Deep Sleep Software Control Select bit
1 = Deep Sleep operation is enabled and controlled by the DSEN bit
0 = Deep Sleep operation is disabled
DSWDTEN
FDS<7>
Deep Sleep Watchdog Timer Enable bit
1 = Deep Sleep WDT is enabled
0 = Deep Sleep WDT is disabled
DSWDTPS<4:0> FDS<4:0>
Deep Sleep Watchdog Timer Postscale Select bits
11111 = 1:68,719,476736 (25.7 days)
11110 = 1:34,359,738368(12.8 days)
11101 = 1:17,179,869184 (6.4 days)
11100 = 1:8,589,934592 (77.0 hours)
11011 = 1:4,294,967296 (38.5 hours)
11010 = 1:2,147,483648 (19.2 hours)
11001 = 1:1,073,741824 (9.6 hours)
11000 = 1:536,870912 (4.8 hours)
10111 = 1:268,435456 (2.4 hours)
10110 = 1:134,217728 (72.2 minutes)
10101 = 1:67,108864 (36.1 minutes)
10100 = 1:33,554432 (18.0 minutes)
10011 = 1:16,777216 (9.0 minutes)
10010 = 1:8,388608 (4.5 minutes)
10001 = 1:4,194304 (135.3s)
10000 = 1:2,097152 (67.7s)
01111 = 1:1,048576 (33.825s)
01110 = 1:524288 (16.912s)
01101 = 1:262114 (8.456s)
01100 = 1:131072 (4.228s)
01011 = 1:65536 (2.114s)
01010 = 1:32768 (1.057s)
01001 = 1:16384 (528.5 ms)
01000 = 1:8192 (264.3 ms)
00111 = 1:4096 (132.1 ms)
00110 = 1:2048 (66.1 ms)
00101 = 1:1024 (33 ms)
00100 = 1:512 (16.5 ms)
00011 = 1:256 (8.3 ms)
00010 = 1:128 (4.1 ms)
00001 = 1:64 (2.1 ms)
00000 = 1:32 (1 ms)
DSWDTOSC
FDS<5>
Deep Sleep Watchdog Timer Clock Select bit
1 = Clock source is LPRC
0 = Clock source is SOSC
FCKSM<1:0>
FOSC<7:6>
Clock Switching Mode bits
1x = Clock switching and Fail-Safe Clock Monitor are disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching and Fail-Safe Clock Monitor are enabled
 2015 Microchip Technology Inc.
DS30010073A-page 11
PIC24FJ256GA412/GB412 FAMILY
TABLE 2-4: CONFIGURATION BITS FOR PIC24FJ256GA412/GB412 FAMILY DEVICES (CONTINUED)
Bit Field
Register
Description
FNOSC<2:0>
FOSCSEL<2:0>
Oscillator Selection bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved, do not use
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Divide-by-N with PLL (FRCPLL)
000 = Fast RC Oscillator (FRC)
FWDTEN<1:0>
FWDT<6:5>
Watchdog Timer Enable bits
11 = WDT is enabled
10 = WDT is disabled (control is placed on the SWDTEN bit)
01 = WDT is enabled only while device is active and is disabled in Sleep;
SWDTEN bit is disabled
00 = WDT and SWDTEN are disabled
FWPSA
FWDT<4>
Watchdog Timer Prescaler
1 = WDT prescaler ratio of 1:128
0 = WDT prescaler ratio of 1:32
GSS<1:0>
FSEC<7:6>
General Segment Code Protection Level bits
11 = No protection (other than the GWRP bit)
10 = Standard security
0x = High security
GWRP
FSEC<5>
General Segment Program Write Protection bit
1 = General Segment is not write-protected
0 = General Segment is write-protected
IBSEQ<11:0>
FBTSEQ<23:12> Inverse Boot Sequence Number bits (Dual Partition Flash modes only)
The one’s complement of BSEQ<11:0>; must be calculated by
the user.
ICS<1:0>
FICD<1:0>
ICD Communication Channel Select bits
11 = Communicates on PGEC1/PGED1
10 = Communicates on PGEC2/PGED2
01 = Communicates on PGEC3/PGED3
00 = Reserved; do not use
IESO
FOSCSEL<7>
Two-Speed Oscillator Start-up Enable bit
1 = Starts up the device with FRC, then automatically switches to the
user-selected oscillator when ready
0 = Starts up the device with the user-selected oscillator source
IOL1WAY
FOSC<5>
Peripheral Pin Select Configuration bit
1 = The IOLOCK bit can be set only once (with unlock sequence).
0 = The IOLOCK bit can be set and cleared as needed (with unlock sequence)
JTAGEN
FICD<5>
JTAG Enable bit
1 = JTAG port is enabled
0 = JTAG port is disabled
LPCFG
FPOR<2>
Retention Voltage Regulator Control Enable bit
1 = Retention feature is not available
0 = Retention feature is available and controlled by RETEN during Sleep
OSCIOFNC
FOSC<2>
CLKO Enable Configuration bit
1 = CLKO output signal is active on the OSCO pin (when primary oscillator is
disabled or configured for EC mode)
0 = CLKO output is disabled
DS30010073A-page 12
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
TABLE 2-4: CONFIGURATION BITS FOR PIC24FJ256GA412/GB412 FAMILY DEVICES (CONTINUED)
Bit Field
Register
Description
PLLMODE<3:0>
FOSCSEL<6:3>
PLL Frequency Multiplier Select bits
1111 = No PLL is used (PLLEN bit is unavailable)
1110 = 8x PLL is selected
1101 = 6x PLL is selected
1100 = 4x PLL is selected
0111 = 96 MHz USB PLL is selected (input frequency = 48 MHz)
0110 = 96 MHz USB PLL is selected (input frequency = 32 MHz)
0101 = 96 MHz USB PLL is selected (input frequency = 24 MHz)
0100 = 96 MHz USB PLL is selected (input frequency = 20 MHz)
0011 = 96 MHz USB PLL is selected (input frequency = 16 MHz)
0010 = 96 MHz USB PLL is selected (input frequency = 12 MHz)
0001 = 96 MHz USB PLL is selected (input frequency = 8 MHz)
0000 = 96 MHz USB PLL is selected (input frequency = 4 MHz)
PLLSS
FOSC<4>
PLL Secondary Selection Configuration bit
This Configuration bit only takes effect when PLL is NOT being used by the
system (i.e., selected as the system clock source).
1 = PLL is driven by the primary oscillator
0 = PLL is driven by the FRC oscillator
POSCMOD<1:0> FOSC<1:0>
Primary Oscillator Configuration bits
11 = Primary oscillator is disabled
10 = HS Oscillator mode is selected (10 MHz-32 MHz)
01 = XT Oscillator mode is selected (3.5 MHz-10 MHz)
00 = EC Oscillator mode is selected
RTCBAT
FDS<14>
VBAT RTCC Operation Select bit
1 = RTCC operation continues when the device is in VBAT mode
0 = RTCC operation stops when the device is in VBAT mode
(Reserved)
FSIGN<15>
Reserved; always maintain as ‘0’
SOSCSEL
FOSC<3>
SOSC Selection Configuration bit
1 = Crystal (SOSCI/SOSCO) mode
0 = Digital (SCLKI) mode
TMPRPIN
FDEVOPT1<2>
Tamper Pin Disable bit
1 = TMPRN pin function is disabled
0 = TMPRN pin function is enabled
WDTCLK<1:0>
FWDT<14:13>
Watchdog Timer Clock Select bits
11 = Always uses INTOSC/LPRC
10 = Uses FRC when WINDIS = 0, system clock is not INTOSC/LPRC and
device is not in Sleep; otherwise, uses INTOSC/LPRC
01 = Uses peripheral clock when system clock is not INTOSC/LPRC and device
is not in Sleep; otherwise, uses INTOSC/LPRC
00 = Always use SOSC
WDTCMX
FWDT<11>
WDT Clock MUX Control bit
1 = Enables WDT clock MUX
0 = WDT clock MUX is disabled
 2015 Microchip Technology Inc.
DS30010073A-page 13
PIC24FJ256GA412/GB412 FAMILY
TABLE 2-4: CONFIGURATION BITS FOR PIC24FJ256GA412/GB412 FAMILY DEVICES (CONTINUED)
Bit Field
Register
Description
WDTPS<3:0>
FWDT<3:0>
Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
WDTWIN<1:0>
FWDT<9:8>
Watchdog Timer Window Width bits
11 = WDT window is 25% of the WDT period
10 = WDT window is 37.5% of the WDT period
01 = WDT window is 50% of the WDT period
00 = WDT window is 75% of the WDT period
WINDIS
2.6.3
FWDT<7>
Windowed Watchdog Timer Disable bit
1 = Windowed WDT is disabled
0 = Windowed WDT is enabled
ONE-TIME-PROGRAMMABLE (OTP)
MEMORY
PIC24FJ256GA412/GB412 family devices provide
384 bytes of One-Time Programmable (OTP) memory, located at addresses, 801700h through 8017FEh.
This memory can be used for persistent storage of
application-specific information that will not be erased
by reprogramming the device. This includes many
types of information, such as (but not limited to):
•
•
•
•
•
•
Application checksums
Code revision information
Product information
Serial numbers
System manufacturing dates
Manufacturing lot numbers
Customer OTP memory may be programmed in any
mode, including user RTSP mode, but it cannot be
erased. Data is not cleared by a Chip Erase.
Do not perform repeated writes on the OTP memory.
DS30010073A-page 14
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
3.0
DEVICE PROGRAMMING – ICSP
ICSP mode is a special programming protocol that
allows you to read and write to device memory. The
ICSP mode is the most direct method used to program
the device, which is accomplished by applying control
codes and instructions serially to the device, using the
PGECx and PGEDx pins. ICSP mode also has the
ability to read executive memory to determine if the
Programming Executive (PE) is present and to write
the PE to executive memory if Enhanced ICSP mode
will be used.
In ICSP mode, the system clock is taken from the
PGECx pin, regardless of the device’s Oscillator
Configuration bits. All instructions are shifted serially
into an internal buffer, then loaded into the Instruction
Register (IR) and executed. No program fetching
occurs from internal memory. Instructions are fed in
24 bits at a time. PGEDx is used to shift data in, and
PGECx is used as both the serial shift clock and the
CPU execution clock.
Note 1: During ICSP operation, the operating
frequency of PGECx must not exceed
5 MHz.
2: ICSP mode is slower than Enhanced
ICSP mode for programming.
3.1
Overview of the Programming
Process
Figure 3-1 illustrates the high-level overview of the
programming process. After entering ICSP mode, the
first action is to Chip Erase program memory. Next, the
code memory is programmed, followed by the device
Configuration bits. Code memory (including the Configuration bits) is then verified to ensure that programming
was successful. Then, the code-protect Configuration
bits are programmed, if required.
FIGURE 3-1:
HIGH-LEVEL ICSP™
PROGRAMMING FLOW
Start
Enter ICSP™
Perform Chip
Erase
Program Memory,
Configuration Words
and User ID Words
Verify Program Memory,
Configuration Words
and User ID Words
Program Code-Protect
Configuration bits
Exit ICSP
End
 2015 Microchip Technology Inc.
DS30010073A-page 15
PIC24FJ256GA412/GB412 FAMILY
3.2
Entering ICSP Mode
The key sequence is a specific 32-bit pattern,
‘0100 1101 0100 0011 0100 1000 0101 0001’
(more easily remembered as 4D434851h in
hexadecimal). The device will enter Program/Verify
mode only if the sequence is valid. The Most Significant
bit (MSb) of the most significant nibble must be shifted in
first.
As illustrated in Figure 3-2, entering ICSP Program/
Verify mode requires three steps:
1.
2.
3.
MCLR is briefly driven high and then low
(P21).(1)
A 32-bit key sequence is clocked into PGEDx.
MCLR is then driven high within a specified
period of time, ‘P19’, and held.
Once the key sequence is complete, VIH must be
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval
time of at least P19, P7 and P1 * 5 must elapse before
presenting data on PGEDx. Signals appearing on
PGEDx before P7 has elapsed will not be interpreted
as valid.
Note 1: If a capacitor is present on the MCLR pin,
the high time for entering ICSP mode can
vary.
The programming voltage applied to MCLR is
VIH, which is essentially V DD in the case of
PIC24FJ256GA412/GB412 family devices. There is no
minimum time requirement for holding at VIH. After VIH
is removed, an interval of at least P18 must elapse
before presenting the key sequence on PGEDx.
FIGURE 3-2:
P6
P14
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
ICSP mode, all unused I/Os are placed in a
high-impedance state.
ENTERING ICSP™ MODE
P21
P19
MCLR
VDD
PGEDx
P7
P1 * 5
VIH
VIH
Program/Verify Entry Code = 4D434851h
0
b31
1
b30
0
b29
0
b28
1
b27
...
0
b3
0
b2
0
b1
1
b0
PGECx
P18
P1A
P1B
DS30010073A-page 16
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
3.3
ICSP Operation
3.3.1
After entering into ICSP mode, the CPU is Idle.
Execution of the CPU is governed by an internal state
machine. A 4-bit control code is clocked in using
PGECx and PGEDx, and this control code is used to
command the CPU (see Table 3-1).
The SIX control code allows execution of assembly
instructions. When the SIX code is received, the CPU is
suspended for 24 clock cycles as the instruction is then
clocked into the internal buffer. Once the instruction is
shifted in, the state machine allows it to be executed over
the next four clock cycles. While the received instruction
is executed, the state machine simultaneously shifts in
the next 4-bit command (see Figure 3-3).
The SIX control code is used to send instructions to the
CPU for execution and the REGOUT control code is
used to read data out of the device through the VISI
register.
TABLE 3-1:
Note 1: Coming out of the ICSP entry sequence,
the first 4-bit control code is always
forced to SIX and a forced NOP
instruction is executed by the CPU. Five
additional PGECx clocks are needed on
start-up, thereby resulting in a 9-bit SIX
command instead of the normal 4-bit SIX
command. After the forced SIX is
clocked in, ICSP operation resumes as
normal (the next 24 clock cycles load the
first instruction word to the CPU). See
Figure 3-4 for details.
CPU CONTROL CODES IN
ICSP™ MODE
4-Bit
Control Code
Mnemonic
Description
0000
SIX
Shift in 24-bit instruction
and execute.
0001
REGOUT
Shift out the VISI
register.
N/A
0010-1111
SIX SERIAL INSTRUCTION
EXECUTION
Reserved.
2: TBLRDH, TBLRDL, TBLWTH and TBLWTL
instructions must be followed by a NOP
instruction.
FIGURE 3-3:
SIX SERIAL EXECUTION
P1
1
2
3
4
1
2
3
4
5
6
7
8
1
17 18 19 20 21 22 23 24
2
3
4
PGECx
P4
P3
P4a
P1A
P1B
P2
PGEDx
0
0
0
0
LSB X
X
X
X
X
Execute PC – 1,
Fetch SIX Control Code
X
X
X
X
X
X
X
X
X MSB
0
24-Bit Instruction Fetch
0
0
0
Execute 24-Bit Instruction,
Fetch Next Control Code
PGEDx = Input
FIGURE 3-4:
PROGRAM ENTRY AFTER RESET
P1
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
17 18 19 20 21 22 23 24
1
2
3
4
PGECx
P4
P3
P4a
P1A
P1B
P2
PGEDx 0
0
0
0
0
0
0
Execute PC – 1,
Fetch SIX Control Code
0
0
LSB X
X
X
X
X
X
X
X
X
X
24-Bit Instruction Fetch
X
X
X
X MSB
0
0
0
0
Execute 24-bit Instruction,
Fetch Next Control Code
PGEDx = Input
 2015 Microchip Technology Inc.
DS30010073A-page 17
PIC24FJ256GA412/GB412 FAMILY
3.3.2
REGOUT SERIAL INSTRUCTION
EXECUTION
The REGOUT code is unique because the PGEDx pin is
an input when the control code is transmitted to the
device. However, after the control code is processed,
the PGEDx pin becomes an output as the VISI register
is shifted out.
The REGOUT control code allows for data to be
extracted from the device in ICSP mode. It is used to
clock the contents of the VISI register out of the device
over the PGEDx pin. After the REGOUT control code is
received, the CPU is held Idle for eight cycles. After
these eight cycles, an additional 16 cycles are required
to clock the data out (see Figure 3-5).
FIGURE 3-5:
Note:
The device will latch input PGEDx data on
the rising edge of PGECx and will output
data on the PGEDx line on the rising edge
of PGECx. For all data transmissions, the
Least Significant bit (LSb) is transmitted
first.
REGOUT SERIAL EXECUTION
1
2
3
4
1
2
7
8
1
2
3
4
6
5
11
12 13 14 15 16
1
2
3
4
PGECx
P4
PGEDx
1
0
0
0
Execute Previous Instruction, CPU Held in Idle
Fetch REGOUT Control Code
PGEDx = Input
DS30010073A-page 18
P4a
P5
LSb
1
2
3
4
...
10 11 12 13 14 MSb
0
0
0
0
Shift Out VISI Register<15:0>
No Execution Takes Place,
Fetch Next Control Code
PGEDx = Output
PGEDx = Input
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
3.4
Flash Memory Programming in
ICSP Mode
3.4.1
PROGRAMMING OPERATIONS
Flash memory write/erase operations are controlled by
the NVMCON register. Programming is performed by
setting NVMCON to select the type of erase operation
(Table 3-2) or write operation (Table 3-3) and initiating
the programming by setting the WR control bit
(NVMCON<15>).
In ICSP mode, all programming operations are
self-timed. There is an internal delay between the user
setting the WR control bit and the automatic clearing
of the WR control bit when the programming
operation is complete. Refer to Section 10.0 “AC/DC
Characteristics and Timing Requirements” for
detailed information about the delays associated with
various programming operations.
TABLE 3-2:
NVMCON
Value
STARTING AND STOPPING A
PROGRAMMING CYCLE
For protection against accidental operations, the erase/
write initiate sequence must be written to the NVMKEY
register to allow any erase or program operation to
proceed. The two instructions following the start of the
programming sequence should be NOPs. To start an
erase or write sequence, the following steps must be
completed:
1.
2.
3.
4.
Write 55h to the NVMKEY register.
Write AAh to the NVMKEY register.
Set the WR bit in the NVMCON register.
Execute three NOP instructions.
All erase and write cycles are self-timed. The WR bit
should be polled to determine if the erase or write cycle
has been completed.
NVMCON ERASE OPERATIONS
Erase Operation
400Eh
Chip Erase user memory (does not erase
Device ID, customer OTP or Program
Executive memory).
4003h
Erase a page of program or executive
memory.
4004h
Erase user memory and Configuration
Words in the Inactive Partition
(Dual Partition modes only).
TABLE 3-3:
NVMCON
Value
3.4.2
NVMCON WRITE OPERATIONS
Write Operation
4001h
Double-word program operation.
4002h
Row programming operation.
 2015 Microchip Technology Inc.
DS30010073A-page 19
PIC24FJ256GA412/GB412 FAMILY
3.5
Erasing Program Memory
FIGURE 3-6:
The general procedure for erasing user memory is
shown in Figure 3-6. The process for Chip Erase, Page
Erase and Inactive Partition Erase are all substantially
similar, and are described in Table 3-4 through
Table 3-6.
The last row of the last page of program memory contains the Flash Configuration Words. Before programming these Words, they must be erased. If they are
erased with a Page Erase operation, all other rows in
the page will also be erased. Users may want to either
avoid using the rest of this page for application code, or
ensure that the non-configuration data in the CS page is
copied before the erase and reprogrammed afterwards.
ERASE FLOW
Start
Set the WREN bit
Write Appropriate Value to NVMCON<3:0>
Set the WR bit to Initiate Erase
The Configuration Read registers can only be loaded
as part of the Reset sequence and cannot be modified
at any other time.
Delay P11 + P10 Time
Note 1: Program memory must be erased before
writing any data to program memory.
End
2: For Page Erase operations, the
NVMADRL/H registers must also be
loaded with the address of the page to be
erased.
TABLE 3-4:
SERIAL EXECUTION FOR CHIP ERASE
Command
(Binary)
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Configure the NVMCON register to perform a Chip Erase.
0000
0000
2400E0
883B00
MOV
MOV
#0x400E, W0
W0, NVMCON
MOV
MOV
MOV
MOV
BSET
NOP
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W0
W0, NVMKEY
NVMCON, #WR
Step 3: Set the WR bit.
0000
0000
0000
0000
0000
0000
0000
0000
200550
883B30
200AA0
883B30
A8E761
000000
000000
000000
Step 4: Repeat this step to poll the WR bit until it is cleared by hardware.
0000
0000
0000
0000
0000
0001
0000
0000
DS30010073A-page 20
040200
00000
803B02
883C22
000000
<VISI>
000000
060000
GOTO
0x200
NOP
MOV
NVMCON, W2
MOV
W2, VISI
NOP
Clock out the contents of the VISI register.
NOP
RETURN
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
TABLE 3-5:
SERIAL EXECUTION FOR PAGE ERASE
Command
(Binary)
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Set the NVMCON register to erase a page.
0000
0000
240030
883B00
MOV
MOV
#0x4003, W0
W0, NVMCON
Step 3: Load the address of the page to be erased into the NVMADR register pair.
0000
0000
0000
0000
200000
883B10
200000
883B20
MOV
MOV
MOV
MOV
#PageAddress<15:0>, W0
W0, NVMADR
#PageAddress<24:16>, W0
W0, NVMADRU
200550
883B30
200AA0
883B30
A8E761
000000
000000
000000
MOV
MOV
MOV
MOV
BSET
NOP
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W0
W0, NVMKEY
NVMCON, #WR
Step 4: Set the WR bit.
0000
0000
0000
0000
0000
0000
0000
0000
Step 5: Repeat this step to poll the WR bit until it is cleared by hardware.
0000
0000
0000
0000
0000
0001
0000
040200
000000
803B02
883C22
000000
<VISI>
000000
GOTO
0x200
NOP
MOV
NVMCON, W2
MOV
W2, VISI
NOP
Clock out the contents of the VISI register.
NOP
Step 6: Clear the WREN bit.
0000
0000
200000
883B00
 2015 Microchip Technology Inc.
MOV
MOV
NVMCON, W2
W0, NVMCON
DS30010073A-page 21
PIC24FJ256GA412/GB412 FAMILY
TABLE 3-6:
SERIAL EXECUTION FOR INACTIVE PARTITION ERASE
Command
(Binary)
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Set the NVMCON register to erase a page.
0000
0000
240040
883B00
MOV
MOV
#0x4004, W0
W0, NVMCON
200550
883B30
200AA0
883B30
A8E761
000000
000000
000000
MOV
MOV
MOV
MOV
BSET
NOP
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W0
W0, NVMKEY
NVMCON, #WR
Step 3: Set the WR bit.
0000
0000
0000
0000
0000
0000
0000
0000
Step 4: Repeat this step to poll the WR bit until it is cleared by hardware.
0000
0000
0000
0000
0000
0001
0000
040200
000000
803B02
883C22
000000
<VISI>
000000
GOTO
0x200
NOP
MOV
NVMCON, W2
MOV
W2, VISI
NOP
Clock out the contents of the VISI register.
NOP
Step 5: Clear the WREN bit.
0000
0000
DS30010073A-page 22
200000
883B00
MOV
MOV
NVMCON, W2
W0, NVMCON
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
3.6
Writing Code Memory
Two-word writes program code memory with two
instruction words at a time. Two words are loaded into
the write latches and the Write Pointer is incremented.
Next, the write sequence is initiated, and finally, the WR
bit is checked for the sequence to be complete. This
process continues for all the data to be programmed.
For PIC24FJ256GA412/GB412 devices, there are two
methods available for writing to code memory:
two-word writes using the write latches or 64-word row
writes. Figure 3-7 provides a high-level description of
the two methods.
FIGURE 3-7:
Table 3-7 provides an example of ICSP programming
for a two-word write operation.
PROGRAM CODE MEMORY FLOW
Start
Configure Device
for Writes
Using RAM Row
Programming
Using Two-Word
Programming
Load 64 Words
into Write Latches
Load Two Words into
Write Latches
Initialize Write Pointer
with Row Address
(DestinationAddress)
Increment
Write Pointer
Initiate Write
Sequence and Poll
WR bit to be Cleared
No
All Data
Written?
No
Yes
End
 2015 Microchip Technology Inc.
DS30010073A-page 23
PIC24FJ256GA412/GB412 FAMILY
TABLE 3-7:
Command
(Binary)
SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CODE MEMORY:
TWO-WORD LATCH WRITES
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Initialize the TBLPAG register for writing to the latches.
0000
0000
200FAC
8802AC
MOV
MOV
#0xFA, W12
W12, TBLPAG
Step 3: Load W0:W2 with the next two packed instruction words to program.
0000
0000
0000
2xxxx0
2xxxx1
2xxxx2
MOV
MOV
MOV
#<LSW0>, W0
#<MSB1:MSB0>, W1
#<LSW1>, W2
Step 4: Set the Read Pointer (W6) and Write Pointer (W7), and load the (next set of) write latches.
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
EB0300
000000
EB0380
000000
BB0BB6
000000
000000
BBDBB6
000000
000000
BBEBB6
000000
000000
BB1BB6
000000
000000
CLR
NOP
CLR
NOP
TBLWTL
NOP
NOP
TBLWTH.B
NOP
NOP
TBLWTH.B
NOP
NOP
TBLWTL.W
NOP
NOP
W6
W7
[W6++], [W7]
[W6++], [W7++]
[W6++], [++W7]
[W6++], [W7++]
Step 5: Set the NVMADRU/NVMADR register pair to point to the correct address.
0000
0000
0000
0000
2xxxx3
2xxxx4
883B13
883B24
MOV
MOV
MOV
MOV
#DestinationAddress<15:0>, W3
#DestinationAddress<23:16>, W4
W3, NVMADR
W4, NVMADRU
Step 6: Set the NVMCON register to program two instruction words.
0000
0000
0000
24001A
883B0A
000000
MOV
MOV
NOP
#0x4001, W10
W10, NVMCON
MOV
MOV
MOV
MOV
BSET
NOP
NOP
NOP
#0x55, W1
W1, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
Step 7: Initiate the write cycle.
0000
0000
0000
0000
0000
0000
0000
0000
200551
883B31
200AA1
883B31
A8E761
000000
000000
000000
DS30010073A-page 24
 2015 Microchip Technology Inc.
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TABLE 3-7:
Command
(Binary)
SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CODE MEMORY:
TWO-WORD LATCH WRITES (CONTINUED)
Data
(Hex)
Description
Step 8: Wait for program operation to complete and make sure the WR bit is clear.
0000
0000
0000
0001
0000
0000
0000
—
803B00
883C20
000000
<VISI>
000000
040200
000000
—
MOV
NVMCON, W0
MOV
W0, VISI
NOP
Clock out the contents of the VISI register.
NOP
GOTO
0x200
NOP
Repeat until the WR bit is clear.
Step 9: Repeat Steps 3-8 until all code memory is programmed.
Step 10: Clear the WREN bit.
0000
0000
803B02
883B00
 2015 Microchip Technology Inc.
MOV
MOV
NVMCON, W2
W0, NVMCON
DS30010073A-page 25
PIC24FJ256GA412/GB412 FAMILY
Row writes program one row (64 instruction words) at
a time. First, the Table Pointer is initialized to point to
the program latches and data is written into them with
Table Writes. Next, the Write Pointer is initialized
(NVMADRU and NVMADR register pair) with the
row address (DestinationAddress). Finally, the write
sequence is initiated and the WR bit is checked for the
row programming to be complete. This process is
repeated for all data to be programmed. Table 3-8
shows the ICSP programming details for row writes.
FIGURE 3-8:
To minimize programming time, the data to be programmed is stored in the W0:W5 registers in a packed
data format (Figure 3-8). This is the same packed
format used by the PE. See Section 6.2.2 “Packed
Data Format” for additional information.
TABLE 3-8:
PACKED INSTRUCTION
WORD STORAGE IN
W0:W5
15
7
LSW0
W0
W1
MSB1
MSB0
W2
LSW1
W3
LSW2
W4
0
MSB3
W5
MSB2
LSW3
SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CODE MEMORY:
ROW WRITES
Command
(Binary)
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Set the NVMCON register to program 64 instruction words.
0000
0000
240020
883B00
MOV
MOV
#0X4002, W0
W0, NVMCON
Step 3: Initialize the TBLPAG register for writing to the latches.
0000
0000
200FAC
8802AC
MOV
MOV
#0xFA, W12
W12, TBLPAG
Step 4: Load W0:W5 with the next 4 instruction words to program.
0000
0000
0000
0000
0000
0000
DS30010073A-page 26
2xxxx0
2xxxx1
2xxxx2
2xxxx3
2xxxx4
2xxxx5
MOV
MOV
MOV
MOV
MOV
MOV
#<LSW0>, W0
#<MSB1:MSB0>, W1
#<LSW1>, W2
#<LSW2>, W3
#<MSB3:MSB2>, W4
#<LSW3>, W5
 2015 Microchip Technology Inc.
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TABLE 3-8:
Command
(Binary)
SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CODE MEMORY:
ROW WRITES (CONTINUED)
Data
(Hex)
Description
Step 5: Set the Read Pointer (W6) and load the (next set of) write latches.
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
EB0300
000000
EB0380
000000
BB0BB6
000000
000000
BBDBB6
000000
000000
BBEBB6
000000
000000
BB1BB6
000000
000000
BB0BB6
000000
000000
BBDBB6
000000
000000
BBEBB6
000000
000000
BB1BB6
000000
000000
CLR
NOP
CLR
NOP
TBLWTL
NOP
NOP
TBLWTH.B
NOP
NOP
TBLWTH.B
NOP
NOP
TBLWTL
NOP
NOP
TBLWTL
NOP
NOP
TBLWTH.B
NOP
NOP
TBLWTH.B
NOP
NOP
TBLWTL
NOP
NOP
W6
W7
[W6++], [W7]
[W6++], [W7++]
[W6++], [++W7]
[W6++], [W7++]
[W6++], [W7]
[W6++], [W7++]
[W6++], [++W7]
[W6++], [W7++]
Step 6: Repeat Steps 4 and 5, for a total of 16 times, to load the write latches with 64 instructions.
Step 7: Set the NVMADRU/NVMADR register pair to point to the correct address.
0000
0000
0000
0000
2xxxx3
2xxxx4
883B13
883B24
MOV
MOV
MOV
MOV
#DestinationAddress<15:0>, W3
#DestinationAddress<23:16>, W4
W3, NVMADR
W4, NVMADRU
Step 8: Execute the WR bit unlock sequence and initiate the write cycle.
0000
0000
0000
0000
0000
0000
0000
0000
200550
883B30
200AA0
883B30
A8E761
000000
000000
000000
MOV
MOV
MOV
MOV
BSET
NOP
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W0
W0, NVMKEY
NVMCON, #WR
Step 9: Repeat this step to poll the WR bit until it is cleared by hardware.
0000
0000
0000
0000
0000
0001
0000
040200
000000
803B02
883C22
000000
<VISI>
000000
 2015 Microchip Technology Inc.
GOTO
0x200
NOP
MOV
NVMCON, W2
MOV
W2, VISI
NOP
Clock out the contents of the VISI register.
NOP
DS30010073A-page 27
PIC24FJ256GA412/GB412 FAMILY
TABLE 3-8:
SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CODE MEMORY:
ROW WRITES (CONTINUED)
Command
(Binary)
Data
(Hex)
Description
Step 10: Reset the device’s internal Program Counter.
0000
0000
040200
000000
GOTO
NOP
0x200
Step 11: Repeat Steps 3 through 9 until all code memory is programmed.
Step 12: Clear the WREN bit.
0000
0000
DS30010073A-page 28
803B02
883B00
MOV
MOV
NVMCON, W2
W0, NVMCON
 2015 Microchip Technology Inc.
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3.7
Writing Configuration Bits
The procedure for writing Configuration bits is similar to
the procedure for writing code memory. Table 3-9
shows the ICSP programming details for writing the
Configuration bits.
For all Configuration Words, except FBTSEQ, only the
lower two bytes of the Word contain configuration data;
the upper byte is unused. It is recommended that the
upper byte be programmed with FFFFh, as indicated in
Step 3 (see Table 3-9). FBTSEQ (implemented only in
Dual Partition modes) uses all 24 bits of the program
memory’s width to store the Boot Sequence Number
bits, BSEQ<11:0> (FBTSEQ<11:0>), and their one’s
complement, IBSEQ<11:0> (FBTSEQ<23:12>).
To change the values of the Configuration bits once
they have been programmed, the device must be
erased, as described in Section 3.5 “Erasing
Program Memory”, and reprogrammed to the desired
value. Note that it is only possible to program a
Configuration bit from ‘1’ to ‘0’ to enable code
protection; it is not possible to program it from ‘0’ to ‘1’.
The Flash page on which the Configuration Segment
resides is shared with the General Segment. To erase and
rewrite the Configuration bits, the entire page must be
erased. To avoid losing data held in the General Segment:
1.
2.
3.
Copy the page to RAM.
Update the RAM copy with the
Configuration bit values.
Write back the data to the Flash page.
new
Alternatively, avoid use of the portion of this Flash page
used by the General Segment.
TABLE 3-9:
Command
(Binary)
SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CONFIGURATION WORDS:
TWO-WORD LATCH WRITES
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Initialize the TBLPAG register for writing to the latches.
0000
0000
200FAC
8802AC
MOV
MOV
#0xFA, W12
W12, TBLPAG
Step 3: Load W0:W1 with the next two Configuration Words to program.
0000
—
0000
0000
2xxxx0
—
2xxxx1
2FFFF2
MOV
#<LSW0>, W0
Upper word is 0xFFFF for all Configuration Words except FBTSEQ.
MOV
#<MSB1:MSB0>, W1
MOV
#<LSW1>, W2
Step 4: Set the Read Pointer (W6) and Write Pointer (W7), and load the (next set of) write latches.
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
EB0300
000000
EB0380
000000
BB0BB6
000000
000000
BBDBB6
000000
000000
BBEBB6
000000
000000
BB1BB6
000000
000000
 2015 Microchip Technology Inc.
CLR
NOP
CLR
NOP
TBLWTL
NOP
NOP
TBLWTH.B
NOP
NOP
TBLWTH.B
NOP
NOP
TBLWTL.W
NOP
NOP
W6
W7
[W6++], [W7]
[W6++], [W7++]
[W6++], [++W7]
[W6++], [W7++]
DS30010073A-page 29
PIC24FJ256GA412/GB412 FAMILY
TABLE 3-9:
Command
(Binary)
SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CONFIGURATION WORDS:
TWO-WORD LATCH WRITES (CONTINUED)
Data
(Hex)
Description
Step 5: Set the NVMADRU/NVMADR register pair to point to the correct address.
0000
0000
0000
0000
2xxxx3
2xxxx4
883B13
883B24
MOV
MOV
MOV
MOV
#DestinationAddress<15:0>, W3
#DestinationAddress<23:16>, W4
W3, NVMADR
W4, NVMADRU
Step 6: Set the NVMCON register to program two instruction words.
0000
0000
0000
24001A
883B0A
000000
MOV
MOV
NOP
#0x4001, W10
W10, NVMCON
MOV
MOV
MOV
MOV
BSET
NOP
NOP
NOP
#0x55, W1
W1, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
Step 7: Initiate the write cycle.
0000
0000
0000
0000
0000
0000
0000
0000
200551
883B31
200AA1
883B31
A8E761
000000
000000
000000
Step 8: Wait for program operation to complete and make sure the WR bit is clear.
0000
0000
0000
0001
0000
0000
0000
—
803B00
883C20
000000
<VISI>
000000
040200
000000
—
MOV
NVMCON, W0
MOV
W0, VISI
NOP
Clock out the contents of the VISI register.
NOP
GOTO
0x200
NOP
Repeat until the WR bit is clear.
Step 9: Repeat Steps 3-8 until all code memory is programmed.
Step 10: Clear the WREN bit.
0000
0000
803B02
883B00
DS30010073A-page 30
MOV
MOV
NVMCON, W2
W0, NVMCON
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3.8
Reading Code Memory
3.9
Reading from code memory is performed by executing
a series of TBLRD instructions and clocking out the data
using the REGOUT command.
Table 3-10 shows the ICSP programming details for
reading code memory.
Reading Configuration Words
The procedure for reading Configuration Words is
identical to the procedure for reading code memory,
shown in Table 3-10. Since there are multiple
Configuration Words, they are read one at a time.
To minimize reading time, the same packed data
format that the PE uses is utilized. See Section 6.2
“Programming Executive Commands” for more
details on the packed data format.
TABLE 3-10:
Command
(Binary)
SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Initialize the Write Pointer (W7) to point to the VISI register.
0000
0000
207847
000000
MOV
NOP
#VISI, W7
Step 3: Initialize the TBLPAG register and the Read Pointer (W6) for the TBLRD instruction.
0000
0000
0000
200xx0
8802A0
2xxxx6
MOV
MOV
MOV
#<SourceAddress23:16>, W0
W0, TBLPAG
#<SourceAddress15:0>, W6
Step 4: Read and clock out the contents of the next two locations of code memory, through the VISI register, using
the REGOUT command.
0000
0000
0000
0001
0000
0000
0000
0000
0000
0000
0000
0001
0000
0000
0000
0000
0001
0000
BA0B96
000000
000000
<VISI>
000000
BADBB6
000000
000000
BAD3D6
000000
000000
<VISI>
000000
BA0BB6
000000
000000
<VISI>
000000
TBLRDL
[W6], [W7]
NOP
NOP
Clock out the contents of the VISI register.
NOP
TBLRDH.B [W6++], [W7++]
NOP
NOP
TBLRDH.B [++W6], [W7--]
NOP
NOP
Clock out the contents of the VISI register.
NOP
TBLRDL
[W6++], [W7]
NOP
NOP
Clock out the contents of the VISI register.
NOP
Step 5: Reset the device’s internal Program Counter.
0000
0000
040200
000000
GOTO
NOP
0x200
Step 6: Repeat Steps 3 through 5 until all desired code memory is read (note that “Reset the device’s internal
Program Counter” will be Step 5).
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DS30010073A-page 31
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3.10
Verify Code Memory and
Configuration Bits
The verify step involves reading back the code memory
space and comparing it against the copy held in the
programmer’s buffer. The Configuration Words are
verified with the rest of the code.
The verify process is illustrated in Figure 3-9. The lower
word of the instruction is read, and then the lower byte
of the upper word is read and compared against the
instruction stored in the programmer’s buffer. Refer
to Section 3.8 “Reading Code Memory” for
implementation details of reading code memory.
Note:
Because the Configuration bytes include
the device code protection bit, code memory should be verified immediately after
writing if the code protection is to be
enabled. This is because the device will
not be readable or verifiable if a device
Reset occurs after the code-protect bit
has been cleared.
3.11
Exiting ICSP Mode
Exiting Program/Verify mode is done by removing VIH
from MCLR, as illustrated in Figure 3-10. The only
requirement for exit is that an interval, P16, should
elapse between the last clock, and program signals on
PGECx and PGEDx, before removing VIH.
FIGURE 3-10:
EXITING ICSP™ MODE
P16
P17
VIH
MCLR
VDD
VIH
PGEDx
PGECx
PGEDx = Input
FIGURE 3-9:
VERIFY CODE
MEMORY FLOW
Start
Set TBLPTR = 0
Read Low Word
with Post-Increment
Read High Byte
with Post-Increment
Does
Instruction Word
= Expected
Data?
No
Yes
No
All
Code Memory
Verified?
Yes
End
DS30010073A-page 32
Failure
Report Error
 2015 Microchip Technology Inc.
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4.0
DEVICE PROGRAMMING –
ENHANCED ICSP
This section discusses programming the device
through Enhanced ICSP and the Programming
Executive (PE). The PE resides in executive memory
(separate from code memory) and is executed when
Enhanced ICSP Programming mode is entered. The
PE provides the mechanism for the programmer (host
device) to program and verify the PIC24FJ256GA412/
GB412 family devices, using a simple command set
and communication protocol. There are several basic
functions provided by the PE:
•
•
•
•
Read Memory
Erase Memory
Program Memory
Blank Check
The PE performs the low-level tasks required for
erasing, programming and verifying a device. This
allows the programmer to program the device by
issuing the appropriate commands and data. A detailed
description for each command is provided in
Section 6.2 “Programming Executive Commands”.
Note:
The PE uses the device’s data RAM for
variable storage and program execution.
After running the PE, no assumptions
should be made about the contents of
data RAM.
4.1
Overview of the Programming
Process
Figure 4-1 shows the high-level overview of the
programming process. First, it must be determined if
the PE is present in executive memory, and then,
Enhanced ICSP mode is entered. The program
memory is then erased, and the program memory and
Configuration Words are programmed and verified.
Last, the code-protect Configuration bits are
programmed (if required) and Enhanced ICSP mode is
exited.
FIGURE 4-1:
HIGH-LEVEL ENHANCED
ICSP™ PROGRAMMING
FLOW
Start
Confirm Presence of
Programming Executive
Enter Enhanced
ICSP™ mode
Erase
Program Memory
Program Memory,
Configuration Words
and User ID Words
Verify Program Memory,
Configuration Words
and User ID Words
Program Code-Protect
Configuration bits
Exit Enhanced ICSP
End
 2015 Microchip Technology Inc.
DS30010073A-page 33
PIC24FJ256GA412/GB412 FAMILY
4.2
Confirming the Presence of the
Programming Executive
Before programming, the programmer must confirm
that the PE is stored in executive memory. The
procedure for this task is illustrated in Figure 4-2.
First, ICSP mode is entered. Then, the unique Application
ID Word, stored in executive memory, is read. If the Application ID has the value, E0h, the Programming Executive
is resident in memory and the device can be
programmed. However, if the Application ID Word is not
present, the PE must be programmed to executive code
memory using the method described in Section 5.0
“Programming the Programming Executive to
Memory”.
Section 3.0 “Device Programming – ICSP”
describes the ICSP programming method. Section 4.3
“Reading the Application ID Word” describes the
procedure for reading the Application ID Word in ICSP
mode.
FIGURE 4-2:
CONFIRMING PRESENCE
OF PROGRAMMING
EXECUTIVE
Start
Enter ICSP™ mode
Check the
Application ID
by Reading Address
800BFEh
Is
Content = E0h?
Yes
No
Prog. Executive must
be Programmed
Exit ICSP mode
Enter Enhanced
ICSP mode
Sanity Check
End
DS30010073A-page 34
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4.3
Reading the Application ID Word
The Application ID Word is stored at address,
800FF0h, in executive code memory. To read this
memory location, you must use the SIX control code to
move this program memory location to the VISI
register. Then, the REGOUT control code must be used
to clock the contents of the VISI register out of the
device. The corresponding control and instruction
codes that must be serially transmitted to the device to
perform this operation are shown in Table 4-1.
TABLE 4-1:
Command
(Binary)
If the Application ID has the value, 0Eh, the
Programming Executive is resident in memory and the
device can be programmed using the mechanism
described in this section. However, if the Application
ID has any other value, the PE is not resident in
memory; it must be loaded to memory before the
device can be programmed. The procedure for loading
the PE to memory is described in Section 5.0
“Programming the Programming Executive to
Memory”.
SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORD
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Initialize the TBLPAG register and the Read Pointer (W0) for the TBLRD instruction.
0000
0000
0000
0000
0000
0000
0000
0000
0000
200800
8802A0
20FF00
207841
000000
BA0890
000000
000000
000000
MOV
MOV
MOV
MOV
NOP
TBLRDL
NOP
NOP
NOP
#0x80, W0
W0, TBLPAG
#0xFF0, W0
#VISI, W1
[W0], [W1]
Step 3: Output the VISI register using the REGOUT command.
0001
<VISI>
 2015 Microchip Technology Inc.
Clock out the contents of the VISI register.
DS30010073A-page 35
PIC24FJ256GA412/GB412 FAMILY
4.4
Entering Enhanced ICSP Mode
As illustrated in Figure 4-3, entering Enhanced ICSP
Program/Verify mode requires three steps:
1.
2.
3.
The MCLR pin is briefly driven high and then
low.
A 32-bit key sequence is clocked into PGEDx.
MCLR is then driven high within a specified
period of time and held.
The programming voltage applied to MCLR is VIH,
which is essentially VDD in PIC24FJ256GA412/GB412
family devices. There is no minimum time requirement
for holding at VIH. After VIH is removed, an interval of at
least P18 must elapse before presenting the key
sequence on PGEDx.
The key sequence is a specific 32-bit pattern,
‘0100 1101 0100 0011 0100 1000 0101 0000’
(more easily remembered as 4D434850h in hexadecimal format). The device will enter Program/Verify
mode only if the key sequence is valid. The Most
Significant bit (MSb) of the most significant nibble must
be shifted in first.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
the Program/Verify mode, all unused I/Os are placed in
the high-impedance state.
4.5
Blank Check
The term, “Blank Check”, implies verifying that the
device has been successfully erased and has no
programmed memory locations. A blank or erased
memory location is always read as ‘1’.
The Device ID registers (FF0000h:FF0002h) can be
ignored by the Blank Check, since this region stores
device information that cannot be erased. Additionally,
all unimplemented memory space should be ignored by
the Blank Check.
The QBLANK command is used for the Blank Check. It
determines if the code memory is erased by testing
these memory regions. A ‘BLANK’ or ‘NOT BLANK’
response is returned. If it is determined that the device
is not blank, it must be erased before attempting to
program the chip.
Once the key sequence is complete, VIH must be
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval
time of at least P19, P7 and P1 * 5 must elapse before
presenting data on PGEDx. Signals appearing on
PGEDx before P7 has elapsed will not be interpreted
as valid.
FIGURE 4-3:
P6
P14
ENTERING ENHANCED ICSP™ MODE
P21
P19
MCLR
VDD
PGEDx
P7
P1 * 5
VIH
VIH
Program/Verify Entry Code = 4D434850h
0
b31
1
b30
0
b29
0
b28
1 ...
b27
0
b3
0
b2
0
b1
0
b0
PGECx
P18
DS30010073A-page 36
P1A
P1B
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
4.6
4.6.1
Code Memory Programming
PROGRAMMING METHODOLOGY
There are two commands that can be used for
programming code memory when utilizing the PE. The
PROG2W command programs and verifies two 24-bit
instruction words into the program memory, starting at the
address specified. The second and faster command,
PROGP, allows up to 64 instruction words (each 24 bits) to
be programmed and verified into program memory,
starting at the address specified. See Section 6.0 “The
Programming Executive” for a full description of each of
these commands.
FIGURE 4-4:
Figure 4-4 and Figure 4-5 show the programming
methodology for the PROG2W and PROGP commands. In
both instances, 87552 instruction words of the device
are programmed.
Note:
If a bootloader needs to be programmed,
its code must not be programmed into the
first page of code memory. For example, if
a bootloader located at address, 200h,
attempts to erase the first page, it would
inadvertently erase itself. Instead,
program the bootloader into the second
page (e.g., 400h).
FIGURE 4-5:
FLOWCHART FOR
DOUBLE-WORD
PROGRAMMING
FLOWCHART FOR
MULTIPLE WORD
PROGRAMMING
Start
Start
BaseAddress = 0h
RemainingCmds = 684
BaseAddress = 0h
RemainingCmds = 43776
Send PROGP
Command to Program
BaseAddress
Send PROG2W
Command to Program
BaseAddress
Is
PROG2W Response
PASS?
Is
PROGP response
PASS?
No
Yes
Yes
RemainingCmds =
RemainingCmds – 1
RemainingCmds =
RemainingCmds – 1
BaseAddress =
BaseAddress + 100h
BaseAddress =
BaseAddress + 04h
No
No
No
Is
RemainingCmds
‘0’?
Yes
Yes
End
 2015 Microchip Technology Inc.
Is
RemainingCmds
‘0’?
Failure
Report Error
End
Failure
Report Error
DS30010073A-page 37
PIC24FJ256GA412/GB412 FAMILY
4.7
Configuration Bit Programming
4.8
Programming Verification
Configuration bits are programmed one at a time using
the PROG2W command. This command specifies the
configuration data and address. When Configuration
bits are programmed, any unimplemented bits must be
programmed with a ‘1’.
After code memory is programmed, the contents of
memory can be verified to ensure that programming
was successful. Verification requires code memory to
be read back and compared against the copy held in
the programmer’s buffer.
Multiple PROG2W commands are required to program
all Configuration bits. A flowchart for Configuration bit
programming is shown in Figure 4-6.
The READP command can be used to read back all the
programmed code memory and Configuration Words.
FIGURE 4-6:
CONFIGURATION BIT
PROGRAMMING FLOW
Alternatively, you can have the programmer perform
the verification after the entire device is programmed
using a checksum computation.
See Section 9.0 “Checksum Computation” for more
information on calculating the checksum.
Start
4.9
Exiting Enhanced ICSP Mode
Exiting Program/Verify mode is done by removing VIH
from MCLR, as illustrated in Figure 4-7. The only
requirement for exit is that an interval, P16, should
elapse between the last clock, and program signals on
PGECx and PGEDx before removing VIH.
Send PROG2W
Command
Is
PROG2W Response
PASS?
FIGURE 4-7:
No
EXITING ENHANCED
ICSP™ MODE
P16
P17
VIH
Yes
MCLR
ConfigAddress =
ConfigAddress +
04h
No
Last
Configuration
Byte?
VDD
VIH
PGEDx
Yes
End
Failure
Report Error
PGECx
PGEDx = Input
DS30010073A-page 38
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
5.0
Note:
5.1
PROGRAMMING THE
PROGRAMMING EXECUTIVE
TO MEMORY
The Programming Executive (PE) can be
obtained from each device page on the
Microchip web site: www.microchip.com.
Overview
5.2
Erasing Executive Memory
Executive memory is erased by a series of Page Erase
operations, as shown in Figure 5-2. This consists of
several cycles of setting NVMCON to 400Eh, executing
the programming cycle and repeating these steps for
each page of executive memory.
Table 5-1 illustrates the ICSP programming process for
Chip Erasing memory.
Note:
If it is determined that the PE is not present in executive
memory (as described in Section 4.2 “Confirming the
Presence of the Programming Executive”), the PE
must be programmed to executive memory.
The PE must always be erased before it
is programmed, as shown in Figure 5-1.
FIGURE 5-2:
Figure 5-1 shows the high-level process of programming the PE into executive memory. First, ICSP mode
must be entered, and executive memory and user
memory are erased; then, the PE is programmed and
verified. Finally, ICSP mode is exited.
FIGURE 5-1:
PAGE ERASE FLOW
Start
i=4
Address = 800000h
HIGH-LEVEL
PROGRAMMING
EXECUTIVE PROGRAM
FLOW
Start
Write 4003h
to NVMCON
Set WR bit
to Initiate Erase
Address =
Address + 512
Enter ICSP™ mode
Delay P11 + P10
Erase
Memory
i=i–1
Program the
Programming Executive
Read/Verify the
Programming Executive
N
i = 0?
Y
Exit ICSP mode
End
End
 2015 Microchip Technology Inc.
DS30010073A-page 39
PIC24FJ256GA412/GB412 FAMILY
TABLE 5-1:
SERIAL INSTRUCTION EXECUTION FOR ERASING EXECUTIVE MEMORY
Command
(Binary)
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
0000
000000
040200
000000
000000
NOP
GOTO
NOP
NOP
0x200
Step 2: Set the NVMCON register to erase a page.
0000
0000
240030
883B00
MOV
MOV
#0x4003, W0
W0, NVMCON
Step 3: Load the address of the page to be erased into the NVMADR register pair.
0000
0000
0000
0000
200004
883B14
200800
883B20
MOV
MOV
MOV
MOV
#0000, W4
W4, NVMADR
#0080, W0
W0, NVMADRU
MOV
MOV
MOV
MOV
BSET
NOP
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W0
W0, NVMKEY
NVMCON, #WR
Step 4: Set the WR bit.
0000
0000
0000
0000
0000
0000
0000
0000
200550
883B30
200AA0
883B30
A8E761
000000
000000
000000
Step 5: Repeat this step to poll the WR bit until it is cleared by hardware.
0000
0000
0000
0000
0000
0001
0000
040200
000000
803B02
883C22
000000
<VISI>
000000
GOTO
0x200
NOP
MOV
NVMCON, W2
MOV
W2, VISI
NOP
Clock out the contents of the VISI register.
NOP
Step 6: Increment W4 by 1024 (400h).
0000
0000
0000
204003
418204
883B24
MOV
ADD
MOV
#0x400, W3
W3, W4, W4
W4, NVMADRU
Step 7: Repeat Steps 4-6 until the entire test memory has been erased.
Step 8: Clear the WREN bit.
0000
0000
803B02
883B00
DS30010073A-page 40
MOV
MOV
NVMCON, W2
W0, NVMCON
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
5.3
Program the Programming
Executive
Storing the PE to executive memory is similar to normal
programming of code memory. The executive memory
must first be erased, and then programmed, using
either two-word writes (two instruction words) or row
writes (64 instruction words). The control flow for both
methods is identical to that for programming code
memory, as shown in Figure 3-7.
TABLE 5-2:
Command
(Binary)
Table 5-2 and Table 5-3 illustrate the ICSP programming
processes for PE memory. To minimize programming
time, the same packed data format that the PE uses is
utilized. See Section 6.2 “Programming Executive
Commands” for more details on the packed data
format.
PROGRAMMING THE PROGRAMMING EXECUTIVE
(TWO-WORD LATCH WRITES)
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Initialize the TBLPAG register for writing to the latches.
0000
0000
200FAC
8802AC
MOV
MOV
#0xFA, W12
W12, TBLPAG
Step 3: Load W0:W2 with the next two packed instruction words to program.
0000
0000
0000
2xxxx0
2xxxx1
2xxxx2
MOV
MOV
MOV
#<LSW0>, W0
#<MSB1:MSB0>, W1
#<LSW1>, W2
Step 4: Set the Read Pointer (W6) and the Write Pointer (W7), and load the write latches.
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
EB0300
000000
EB0380
000000
BB0BB6
000000
000000
BBDBB6
000000
000000
BBEBB6
000000
000000
BB1BB6
000000
000000
CLR
NOP
CLR
NOP
TBLWTL
NOP
NOP
TBLWTH.B
NOP
NOP
TBLWTH.B
NOP
NOP
TBLWTL.W
NOP
NOP
W6
W7
[W6++], [W7]
[W6++], [W7++]
[W6++], [++W7]
[W6++], [W7++]
Step 5: Set the NVMADRU/NVMADR register pair to point to the correct row.
0000
0000
0000
0000
2xxxx3
2xxxx4
883B13
883B24
MOV
MOV
MOV
MOV
#DestinationAddress<15:0>, W3
#DestinationAddress<23:16>, W4
W3, NVMADR
W4, NVMADRU
Step 6: Set the NVMCON register to program two instruction words.
0000
0000
0000
0000
0000
24001A
000000
883B0A
000000
000000
 2015 Microchip Technology Inc.
MOV
NOP
MOV
NOP
NOP
#0x4001, W10
W10, NVMCON
DS30010073A-page 41
PIC24FJ256GA412/GB412 FAMILY
TABLE 5-2:
PROGRAMMING THE PROGRAMMING EXECUTIVE
(TWO-WORD LATCH WRITES) (CONTINUED)
Command
(Binary)
Data
(Hex)
Description
Step 7: Initiate the write cycle.
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
200551
883B31
200AA1
883B31
A8E761
000000
000000
000000
000000
000000
MOV
MOV
MOV
MOV
BSET
NOP
NOP
NOP
NOP
NOP
#0x55, W1
W1, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
Step 8: Wait for program operation to complete and make sure the WR bit is clear.
0000
0000
0000
0000
0000
0001
0000
0000
0000
—
000000
803B00
000000
883C20
000000
<VISI>
000000
040200
000000
—
NOP
MOV
NVMCON, W0
NOP
MOV
W0, VISI
NOP
Clock out the contents of the VISI register.
NOP
GOTO
0x200
NOP
Repeat until the WR bit is clear.
Step 9: Repeat Steps 3-8 until all code memory is programmed.
Step 10: Clear the WREN bit.
0000
0000
803B02
883B00
DS30010073A-page 42
MOV
MOV
NVMCON, W2
W0, NVMCON
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
TABLE 5-3:
Command
(Binary)
PROGRAMMING THE PROGRAMMING EXECUTIVE (ROW WRITES)
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Set the NVMCON register to program 64 instruction words.
0000
0000
240020
883B00
MOV
MOV
#0x4002, W0
W0, NVMCON
Step 3: Initialize the TBLPAG register for writing to the latches.
0000
0000
200FAC
8802AC
MOV
MOV
#0xFA, W12
W12, TBLPAG
Step 4: Load W0:W5 with the next 4 instruction words to program.
0000
0000
0000
0000
0000
0000
2xxxx0
2xxxx1
2xxxx2
2xxxx3
2xxxx4
2xxxx5
MOV
MOV
MOV
MOV
MOV
MOV
#<LSW0>, W0
#<MSB1:MSB0>, W1
#<LSW1>, W2
#<LSW2>, W3
#<MSB3:MSB2>, W4
#<LSW3>, W5
Step 5: Set the Read Pointer (W6) and load the (next set of) write latches.
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
EB0300
000000
EB0380
000000
BBDBB6
000000
000000
BBEBB6
000000
000000
BB1BB6
000000
000000
BB0BB6
000000
000000
BBDBB6
000000
000000
BBEBB6
000000
000000
BB1BB6
000000
000000
CLR
NOP
CLR
NOP
TBLWTL
NOP
NOP
TBLWTH.B
NOP
NOP
TBLWTL
NOP
NOP
TBLWTL
NOP
NOP
TBLWTH.B
NOP
NOP
TBLWTH.B
NOP
NOP
TBLWTL
NOP
NOP
W6
W7
[W6++], [W7]
[W6++], [++W7]
[W6++], [W7++]
[W6++], [W7]
[W6++], [W7++]
[W6++], [++W7]
[W6++], [W7++]
Step 6: Repeat Steps 4 and 5, for a total of 16 times, to load the write latches with 64 instructions.
Step 7: Set the NVMADRU/NVMADR register pair to point to the correct address.
0000
0000
0000
0000
2xxxx3
2xxxx4
883B13
883B24
 2015 Microchip Technology Inc.
MOV
MOV
MOV
MOV
#DestinationAddress<15:0>, W3
#DestinationAddress<23:16>, W4
W3, NVMADR
W4, NVMADRU
DS30010073A-page 43
PIC24FJ256GA412/GB412 FAMILY
TABLE 5-3:
PROGRAMMING THE PROGRAMMING EXECUTIVE (ROW WRITES) (CONTINUED)
Command
(Binary)
Data
(Hex)
Description
Step 8: Execute the WR bit unlock sequence and initiate the write cycle.
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
200551
883B31
200AA1
883B31
A8E761
000000
000000
000000
000000
000000
MOV
MOV
MOV
MOV
BSET
NOP
NOP
NOP
NOP
NOP
#0x55, W1
W1, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
Step 9: Repeat this step to poll the WR bit until it is cleared by hardware.
0000
0000
0000
0000
0000
0001
0000
040200
000000
803B00
883C20
000000
<VISI>
000000
GOTO
0x200
NOP
MOV
NVMCON, W0
MOV
W0, VISI
NOP
Clock out the contents of the VISI register.
NOP
Step 10: Reset the device’s internal Program Counter.
0000
0000
040200
000000
GOTO
NOP
0x200
Step 11: Repeat Steps 3 through 9 until all code memory is programmed.
Step 12: Clear the WREN bit.
0000
0000
803B02
883B00
DS30010073A-page 44
MOV
MOV
NVMCON, W2
W0, NVMCON
 2015 Microchip Technology Inc.
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5.4
Reading Executive Memory
To minimize reading time, the same packed data format
that the PE uses is utilized. See Section 6.2
“Programming Executive Commands” for more
details on the packed data format.
Reading from executive memory is performed by
executing a series of TBLRD instructions and clocking
out the data using the REGOUT command.
Table 5-4 shows the ICSP programming details for
reading executive memory.
TABLE 5-4:
Command
(Binary)
SERIAL EXECUTION FOR READING EXECUTIVE MEMORY
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Initialize the TBLPAG register and the Read Pointer (W6) for the TBLRD instruction.
0000
0000
0000
200xx0
8802A0
2xxxx6
MOV
MOV
MOV
#<SourceAddress23:16>, W0
W0, TBLPAG
#<SourceAddress15:0>, W6
Step 3: Initialize the Write Pointer (W7) and store the next four locations of code memory in W0:W5.
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
EB0380
000000
BA1B96
000000
000000
BADBB6
000000
000000
BADBD6
000000
000000
BA1BB6
000000
000000
BA1B96
000000
000000
BADBB6
000000
000000
BADBD6
000000
000000
BA0BB6
000000
000000
 2015 Microchip Technology Inc.
CLR
NOP
TBLRDL
NOP
NOP
TBLRDH.B
NOP
NOP
TBLRDH.B
NOP
NOP
TBLRDL
NOP
NOP
TBLRDL
NOP
NOP
TBLRDH.B
NOP
NOP
TBLRDH.B
NOP
NOP
TBLRDL
NOP
NOP
W7
[W6], [W7++]
[W6++], [W7++]
[++W6], [W7++]
[W6++], [W7++]
[W6], [W7++]
[W6++], [W7++]
[++W6], [W7++]
[W6++], [W7]
DS30010073A-page 45
PIC24FJ256GA412/GB412 FAMILY
TABLE 5-4:
SERIAL EXECUTION FOR READING EXECUTIVE MEMORY (CONTINUED)
Command
(Binary)
Data
(Hex)
Description
Step 4: Output W0:W5 using the VISI register and the REGOUT command.
0000
0000
0001
0000
0000
0000
0001
0000
0000
0000
0001
0000
0000
0000
0001
0000
0000
0000
0001
0000
0000
0000
0001
0000
883C20
000000
<VISI>
000000
883C21
000000
<VISI>
000000
883C22
000000
<VISI>
000000
883C23
000000
<VISI>
000000
883C24
000000
<VISI>
000000
883C25
000000
<VISI>
000000
MOV
W0, VISI
NOP
Clock out the contents of the VISI register.
NOP
MOV
W1, VISI
NOP
Clock out the contents of the VISI register.
NOP
MOV
W2, VISI
NOP
Clock out the contents of the VISI register.
NOP
MOV
W3, VISI
NOP
Clock out the contents of the VISI register.
NOP
MOV
W4, VISI
NOP
Clock out the contents of the VISI register.
NOP
MOV
W5, VISI
NOP
Clock out the contents of the VISI register.
NOP
Step 5: Reset the device’s internal Program Counter.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 6: Repeat Steps 3 through 5 until all desired code memory is read (note that “Reset the device’s internal
Program Counter” will be Step 5).
DS30010073A-page 46
 2015 Microchip Technology Inc.
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5.5
Verify Programming Executive
FIGURE 5-3:
The verify step involves reading back the executive
memory space and comparing it against the copy held
in the programmer’s buffer.
VERIFY PROGRAMMING
EXECUTIVE MEMORY
FLOW
Start
The verify process is illustrated in Figure 5-3. The lower
word of the instruction is read, and then the lower byte
of the upper word is read and compared against the
instruction stored in the programmer’s buffer. Refer to
Section 5.4 “Reading Executive Memory” for
implementation details of reading executive memory.
Set TBLPTR = 0
Read Low Word
with Post-Increment
Read High Byte
with Post-Increment
Does
Instruction Word
= Expected
Data?
No
Yes
No
All
Executive Memory
Verified?
Yes
End
 2015 Microchip Technology Inc.
Failure
Report Error
DS30010073A-page 47
PIC24FJ256GA412/GB412 FAMILY
6.0
THE PROGRAMMING
EXECUTIVE
6.1
Programming Executive
Communication
FIGURE 6-1:
P1
1
The programmer and PE have a master-slave
relationship, where the programmer is the master
programming device and the PE is the slave.
4
5
6
11
12
13
14
15
16
P3
P2
PGEDx
MSb 14 13 12
11
...
5
4
3
2
1
LSb
After the PE has processed the command, it brings
PGEDx low (P9b) to indicate to the programmer that
the response is available to be clocked out. The
programmer can begin to clock out the response after a
maximum wait (P9b) and it must provide the necessary
amount of clock pulses to receive the entire response
from the PE.
After the entire response is clocked out, the
programmer should terminate the clock on PGECx until
it is time to send another command to the PE. This
protocol is illustrated in Figure 6-2.
The ICSP/Enhanced ICSP interface is a 2-wire SPI,
implemented using the PGECx and PGEDx pins. The
PGECx pin is used as a clock input pin and the clock
source must be provided by the programmer. The
PGEDx pin is used for sending command data to and
receiving response data from the PE.
6.1.2
SPI RATE
In Enhanced ICSP mode, PIC24FJ256GA412/GB412
family devices operate from the Fast Internal RC
Oscillator (FRC), which has a nominal frequency of
8 MHz. This oscillator frequency yields an effective
system clock frequency of 4 MHz. To ensure that the
programmer does not clock too fast, it is recommended
that a 2 MHz clock be provided by the programmer.
For Enhanced ICSP, all serial data is
transmitted on the falling edge of PGECx
and latched on the rising edge of PGECx.
All data transmissions are sent to the MSb
first using 16-bit mode (see Figure 6-1).
Since a 2-wire SPI is used, and data transmissions are
bidirectional, a simple protocol is used to control the
direction of PGEDx. When the programmer completes
a command transmission, it releases the PGEDx line
and allows the PE to drive this line high. The PE keeps
the PGEDx line high to indicate that it is processing the
command.
FIGURE 6-2:
3
P1B
COMMUNICATION INTERFACE
AND PROTOCOL
Note:
2
PGECx P1A
All communication is initiated by the programmer in the
form of a command. Only one command at a time can
be sent to the PE. In turn, the PE only sends one
response to the programmer after receiving and
processing a command. The PE command set is
described in Section 6.2 “Programming Executive
Commands”. The response set is described in
Section 6.3 “Programming Executive Responses”.
6.1.1
PROGRAMMING
EXECUTIVE SERIAL
TIMING
PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL
Host Transmits
Last Command Word
1
2
Programming Executive
Processes Command
15 16
Host Clocks Out Response
1
2
15 16
1
2
15 16
PGECx
PGEDx
MSB X X X LSB
P8
PGECx = Input
PGEDx = Input
Note
1:
1
0
P9a
P9b
PGECx = Input (Idle)
PGEDx = Output
MSB X X X LSB
MSB X X X LSB
PGECx = Input
PGEDx = Output
A delay of 25 ms is required between commands.
DS30010073A-page 48
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6.1.3
TIME-OUTS
6.2.1
The PE uses no Watchdog Timer or time-out for
transmitting responses to the programmer. If the
programmer does not follow the flow control mechanism,
using PGECx as described in Section 6.1.1
“Communication Interface and Protocol”, it is possible
that the PE will behave unexpectedly while trying to send
a response to the programmer. Since the PE has no
time-out, it is imperative that the programmer correctly
follow the described communication protocol.
As a safety measure, the programmer should use the
command time-outs identified in Table 6-1. If the
command time-out expires, the programmer should
reset the PE and start programming the device again.
6.2
FIGURE 6-3:
15
COMMAND FORMAT
12 11
0
Opcode
Length
Command Data First Word (if required)
•
•
Command Data Last Word (if required)
The PE command set is shown in Table 6-1. This table
contains the opcode, mnemonic, length, time-out
and description for each command. Functional
details on each command are provided in the
command descriptions (Section 6.2.4 “Command
Descriptions”).
Opcode
All PE commands have a general format, consisting of
a 16-bit header and any required data for the command
(see Figure 6-3). The 16-bit header consists of a 4-bit
opcode field, which is used to identify the command,
followed by a 12-bit command length field.
Programming Executive
Commands
TABLE 6-1:
COMMAND FORMAT
The command opcode must match one of those in the
command set. Any command that is received which
does not match the list in Table 6-1 will return a “NACK”
response (see Section 6.3.1.1 “Opcode Field”).
The command length is represented in 16-bit words since
the SPI operates in 16-bit mode. The PE uses the command length field to determine the number of words to
read from the SPI port. If the value of this field is incorrect,
the command will not be properly received by the PE.
PROGRAMMING EXECUTIVE COMMAND SET
Mnemonic
Length
(16-bit words)
Time-Out
Description
0x0
SCHECK
1
1 ms
Sanity check.
0x1
READC
3
1 ms
Read an 8-bit word from the specified Configuration register
or Device ID register.
0x2
READP
4
1 ms/row
Read ‘N’ 24-bit instruction words of primary Flash memory,
starting from the specified address.
0x3
PROG2W
6
5 ms
Program a double instruction word of code memory at the
specified address and verify.
0x4
Reserved
N/A
N/A
This command is reserved; it will return a NACK.
0x5
PROGP
99
5 ms
Program 64 words of program memory at the specified
starting address, then verify.
0x6
Reserved
N/A
N/A
0x7
ERASEB
1
125 ms
0x8
Reserved
0x9
ERASEP
0xA
Reserved
0xB
QVER
0xC
CRCP
0xD
Reserved
0xE
QBLANK
 2015 Microchip Technology Inc.
N/A
N/A
3
25 ms
This command is reserved; it will return a NACK.
Chip Erase the device.
This command is reserved; it will return a NACK.
Command to erase a page.
N/A
N/A
This command is reserved; it will return a NACK.
1
1 ms
Query the PE software version.
5
1s
N/A
N/A
5
700 ms
Performs a CRC-16 on the specified range of memory.
This command is reserved; it will return a NACK.
Query to check whether the code memory is blank.
DS30010073A-page 49
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6.2.2
PACKED DATA FORMAT
6.2.4
When 24-bit instruction words are transferred across
the 16-bit SPI interface, they are packed to conserve
space using the format illustrated in Figure 6-4. This
format minimizes traffic over the SPI and provides the
PE with data that is properly aligned for performing
Table Write operations.
FIGURE 6-4:
15
PACKED INSTRUCTION
WORD FORMAT
8 7
0
LSW1
MSB2
MSB1
LSW2
LSWx: Least Significant 16 bits of instruction word
MSBx: Most Significant Byte of instruction word
Note:
6.2.3
When the number of instruction words
transferred is odd, MSB2 is zero and
LSW2 cannot be transmitted.
PROGRAMMING EXECUTIVE
ERROR HANDLING
The PE will “NACK” all unsupported commands. Additionally, due to the memory constraints of the PE, no
checking is performed on the data contained in the
programmer command. It is the responsibility of the
programmer to command the PE with valid command
arguments or the programming operation may fail.
Additional information on error handling is provided in
Section 6.3.1.3 “QE_Code Field”.
DS30010073A-page 50
COMMAND DESCRIPTIONS
All commands supported by the PE are described in
Section 6.2.4.1 “SCHECK Command” through
Section 6.2.4.10 “QBLANK Command”.
6.2.4.1
SCHECK Command
15
12 11
0
Opcode
Length
Table 6-2 shows the description for the SCHECK
command.
TABLE 6-2:
COMMAND DESCRIPTION
Field
Description
Opcode
0x0
Length
0x1
The SCHECK command instructs the PE to do nothing
but generate a response. This command is used as a
“Sanity Check” to verify that the PE is operational.
Expected Response (2 words):
0x1000 0x0002h
Note:
This instruction is not required for
programming, but is provided for
development purposes only.
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6.2.4.2
15
READC Command
12 11
6.2.4.3
8 7
Opcode
0
15
12 11
8 7
Opcode
Length
N
READP Command
N
Addr_MSB
Reserved
Addr_LS
Table 6-3 shows the description for the READC
command.
TABLE 6-3:
COMMAND DESCRIPTION
Field
Description
0
Length
Addr_MSB
Addr_LS
Table 6-4 shows the description for the READP
command.
TABLE 6-4:
COMMAND DESCRIPTION
Field
Description
Opcode
0x1
Length
0x3
Opcode
0x2
N
Number of 8-bit Configuration registers
or Device ID registers to read
(maximum of 256)
Length
0x4
N
Number of 24-bit instructions to read
(maximum of 32768)
Addr_MSB
MSB of 24-bit source address.
Reserved
0x0
Addr_LS
Least Significant 16 bits of 24-bit
source address
Addr_MSB
MSB of 24-bit source address
Addr_LS
Least Significant 16 bits of 24-bit
source address
The READC command instructs the PE to read N Configuration registers or Device ID registers, starting from
the 24-bit address specified by Addr_MSB and
Addr_LS. This command can only be used to read 8-bit
or 16-bit data.
When this command is used to read Configuration
registers, the upper byte in every data word returned
by the PE is 0x00 and the lower byte contains the
Configuration register value.
Expected Response (4 + 3 * (N – 1)/2 words
for N odd):
0x1100
Expected Response (2 + 3 * N/2 words for N even):
0x1200
2 + 3 * N/2
Least Significant Program Memory Word 1
2+N
Configuration register or Device ID Register 1
...
Configuration register or Device ID Register N
Note:
The READP command instructs the PE to read N 24-bit
words of code memory, starting from the 24-bit address
specified by Addr_MSB and Addr_LS. This command
can only be used to read 24-bit data. All data returned
in response to this command uses the packed data
format described in Section 6.2.2 “Packed Data
Format”.
Reading unimplemented memory will
cause the PE to reset. To prevent this
from occurring, ensure that only memory
locations present on a particular device
are accessed.
...
Least Significant Data Word N
Expected Response (4 + 3 * (N – 1)/2 words
for N odd):
0x1200
4 + 3 * (N – 1)/2
Least Significant Program Memory Word 1
...
MSB of Program Memory Word N (zero-padded)
Note:
 2015 Microchip Technology Inc.
Reading unimplemented memory will
cause the PE to reset. To prevent this
from occurring, ensure that only memory
locations present on a particular device
are accessed.
DS30010073A-page 51
PIC24FJ256GA412/GB412 FAMILY
6.2.4.4
PROG2W Command
15
12 11
6.2.4.5
8 7
Opcode
0
15
12 11
8 7
Opcode
Length
Reserved
PROGP Command
Reserved
Addr_MSB
D_1
DataL_LS
D_2
DataL_MSB
...
DataH_LS
Table 6-5 shows the description for the PROG2W
command.
TABLE 6-5:
COMMAND DESCRIPTION
Field
Description
Opcode
0x3
Length
0x6
Addr_MSB
Addr_LS
Addr_LS
DataH_MSB
0
Length
D_N
Table 6-6 shows the description for the PROGP
command.
TABLE 6-6:
COMMAND DESCRIPTION
Field
Description
Opcode
0x5
DataL_MSB MSB of 24-bit data for low instruction
word
Length
0x63
Reserved
0x0
DataH_MSB MSB of 24-bit data for high instruction
word
Addr_MSB
MSB of 24-bit destination address
Addr_LS
Least Significant 16 bits of 24-bit
destination address
Addr_MSB
MSB of 24-bit destination address
Addr_LS
Least Significant 16 bits of 24-bit
destination address
D_1
16-bit Data Word 1
DataL_LS
Least Significant 16 bits of 24-bit data
for low instruction word
D_2
16-bit Data Word 2
...
16-bit Data Word 3 through 95
DataH_LS
Least Significant 16 bits of 24-bit data
for high instruction word
D_96
16-bit Data Word 96
The PROG2W command instructs the PE to program
two instruction words of code memory (6 bytes) to the
specified memory address.
After the words have been programmed to code
memory, the PE verifies the programmed data against
the data in the command.
Expected Response (2 words):
0x1300
0x0002
The PROGP command instructs the PE to program one
row of code memory (128 instruction words) to the
specified memory address. Programming begins with
the row address specified in the command. The
destination address should be a multiple of 0x100.
The data to program the memory, located in command
words, D_1 through D_96, must be arranged using the
packed instruction word format illustrated in Figure 6-4.
After all data has been programmed to code memory,
the PE verifies the programmed data against the data
in the command.
Expected Response (2 words):
0x1500
0x0002
Note:
DS30010073A-page 52
Refer to Table 2-2 for code memory size
information.
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6.2.4.6
ERASEB Command
15
12 11
6.2.4.8
8 7
0
Opcode
Table 6-7 shows the description for the ERASEB
command.
COMMAND DESCRIPTION
Field
Description
Opcode
0x7
Length
0x1
12 11
0
Opcode
Length
TABLE 6-7:
15
QVER Command
Length
Table 6-9 shows the description for the QVER command.
TABLE 6-9:
COMMAND DESCRIPTION
Field
The ERASEB command instructs the PE to perform a
Chip Erase (i.e., erase all of the primary Flash memory,
executive memory and code-protect bits).
Expected Response (2 words):
0x1700
Description
Opcode
0xB
Length
0x1
The QVER command queries the version of the PE software stored in test memory. The “version.revision”
information is returned in the response’s QE_Code,
using a single byte with the following format: main version in upper nibble and revision in the lower nibble
(i.e., 0x23 means Version 2.3 of PE software).
Expected Response (2 words):
0x0002
0x1BMN (where “MN” stands for version M.N)
0x0002
6.2.4.7
ERASEP Command
15
12 11
8 7
Opcode
0
Length
Addr_MSB
NUM_PAGES
Addr_LS
Table 6-6 shows the description for the ERASEP
command.
TABLE 6-8:
COMMAND DESCRIPTION
Field
Description
Opcode
0x9
Length
0x3
NUM_PAGES Up to 255
Addr_MSB
Most Significant Byte of the 24-bit
address
Addr_LS
Least Significant 16 bits of the 24-bit
address
The ERASEP command instructs the PE to Page Erase
[NUM_PAGES] of code memory. The code memory
must be erased at an “even” 1024 instruction words
address boundary
Expected Response (2 words):
0x1900
0x0002
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6.2.4.9
CRCP Command
15
12 11
6.2.4.10
8 7
Opcode
0
Length
Reserved
15
12 11
0
Opcode
Length
Reserved
Addr_MSB
Reserved
Reserved
Size_LSW
Table 6-11 shows the description for the CRCP command.
COMMAND DESCRIPTION
Description
Addr_MSB
Addr_LSW
Size_MSB
Field
Size_MSB
Size_LSW
Addr_LSW
TABLE 6-10:
QBLANK Command
Table 6-11 shows the description for the QBLANK
command.
TABLE 6-11:
COMMAND DESCRIPTION
Field
Description
Opcode
0xE
Length
0x5
Size
Length of program memory to check
(in 24-bit words) + Addr_MS
Opcode
Ch
Length
5h
Addr_MSB
Most Significant Byte of 24-bit
address
Addr_MSB
Addr_LSW
Least Significant 16 bits of 24-bit
address
Most Significant Byte of the 24-bit
address
Addr_LSW
Size
Number of 24-bit locations (address
range divided by 2)
Least Significant 16 bits of the 24-bit
address
The CRCP command performs a CRC-16 on the range of
memory specified. This command can substitute for a
full chip verify. Data is shifted in a packed method, as
demonstrated in Figure 6-4: byte-wise, Least Significant
Byte (LSB) first.
Example:
The QBLANK command queries the PE to determine if
the contents of code memory are blank (contains all
‘1’s). The size of code memory to check must be
specified in the command.
The Blank Check for code memory begins at [Addr] and
advances toward larger addresses for the specified
number of instruction words.
CRC-CCITT-16 with test data of “123456789” becomes
29B1h
QBLANK returns a QE_Code of F0h if the specified
code memory is blank; otherwise, QBLANK returns a
QE_Code of 0Fh.
Expected Response (3 words):
Expected Response (2 words for blank device):
QE_Code: 0x1C00
0x1EF0
Length: 0x0003
0x0002
CRC Value: 0xXXXX
Expected Response (2 words for non-blank device):
0x1E0F
0x0002
Note:
DS30010073A-page 54
The QBLANK command does not check the
system operation Configuration bits since
these bits are not set to ‘1’ when a Chip
Erase is performed.
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6.3
Programming Executive
Responses
Table 6-13 shows the description of the response
format.
The PE sends a response to the programmer for each
command that it receives. The response indicates if the
command was processed correctly. It includes any
required response data or error data.
TABLE 6-13:
Field
RESPONSE FORMAT
DESCRIPTION
Description
The PE response set is shown in Table 6-12. This table
contains the opcode, mnemonic and description for
each response. The response format is described in
Section 6.3.1 “Response Format”.
Opcode
Response opcode.
Last_Cmd
Programmer command that
generated the response.
QE_Code
Query code or error code.
TABLE 6-12:
Length
Response length in 16-bit words
(includes 2 header words).
D_1
First 16-bit data word (if applicable).
D_N
Last 16-bit data word (if applicable).
Opcode
PROGRAMMING EXECUTIVE
RESPONSE OPCODES
Mnemonic
0x1
PASS
Description
Command successfully
processed.
6.3.1.1
0x2
FAIL
Command unsuccessfully
processed.
0x3
NACK
Command not known.
6.3.1
RESPONSE FORMAT
All PE responses have a general format, consisting of a
two-word header and any required data for the
command.
15
12 11
Opcode
8 7
Last_Cmd
0
QE_Code
Length
D_1 (if applicable)
Opcode Field
The opcode is a 4-bit field in the first word of the
response. The opcode indicates how the command
was processed (see Table 6-12). If the command was
processed successfully, the response opcode is PASS.
If there was an error in processing the command, the
response opcode is FAIL and the QE_Code indicates
the reason for the failure. If the command sent to the
PE is not identified, the PE returns a NACK response.
6.3.1.2
Last_Cmd Field
The Last_Cmd is a 4-bit field in the first word of the
response and indicates the command that the PE
processed. Since the PE can only process one command
at a time, this field is technically not required. However, it
can be used to verify that the PE correctly received the
command that the programmer transmitted.
...
D_N (if applicable)
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6.3.1.3
QE_Code Field
6.3.1.4
Response Length
The QE_Code is a byte in the first word of the
response. This byte is used to return data for query
commands and error codes for all other commands.
The response length indicates the length of the PE’s
response in 16-bit words. This field includes the 2 words
of the response header.
When the PE processes one of the two query
commands (QBLANK or QVER), the returned opcode is
always PASS and the QE_Code holds the query
response data. The format of the QE_Code for both
queries is shown in Table 6-14.
With the exception of the response for the read
commands, the length of each response is only 2 words.
TABLE 6-14:
QE_Code FOR QUERIES
Query
QE_Code
QBLANK
0x0F = Code memory is NOT blank
0xF0 = Code memory is blank
QVER
0xMN, where PE Software Version = M.N
(i.e., 0x32 means Software Version 3.2).
The response to the READP commands uses the packed
instruction word format described in Section 6.2.2
“Packed Data Format”. When reading an odd number
of program memory words (N odd), the response to the
READP command is (3 * (N + 1)/2 + 2) words. When
reading an even number of program memory words
(N even), the response to the READP command is
(3 * N/2 + 2) words.
When the PE processes any command other than a
query, the QE_Code represents an error code.
Supported error codes are shown in Table 6-15. If a
command is successfully processed, the returned
QE_Code is set to 0x0, which indicates that there is no
error in the command processing. If the verify of the
programming for the PROGW command fails, the
QE_Code is set to 0x1. For all other PE errors, the
QE_Code is 0x02.
TABLE 6-15:
QE_Code FOR NON-QUERY
COMMANDS
QE_Code
Description
0x0
No error
0x1
Verify failed
0x2
Other error
DS30010073A-page 56
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7.0
DUAL PARTITION FLASH
PROGRAMMING
CONSIDERATIONS
The PIC24FJ256GA412/GB412 family of devices
supports a Single Partition Flash mode and two Dual
Partition Flash modes. The Dual Partition modes allow
the device to be programmed with two separate
applications to facilitate bootloading or to allow an
application to be programmed at run time without
stalling the CPU.
The part’s Partition Flash mode is determined by the
BTMODE<1:0> bits in the FBOOT Configuration
register (Table 7-1). The device will automatically
check FBOOT on Reset and determine the appropriate
Partition Flash mode.
TABLE 7-1:
FBOOT<1:0>
7.1
PARTITION FLASH MODE
SELECT
Partition Flash Mode
00
Reserved
01
Protected Dual Partition Flash mode
10
Dual Partition Flash mode
11
Single Partition Flash mode (default)
Dual Partition Flash Memory
Organization
In the Dual Partition Flash modes, the device’s memory
is divided evenly into two physical sections, known as
Partition 1 and Partition 2. Each of these partitions contains its own program memory and Configuration
Words. During program execution, the code on only
one of these partitions is executed; this is the Active
Partition. The other partition, or the Inactive Partition, is
not used, but can be programmed.
The Active Partition is always mapped to logical address,
000000h, while the Inactive Partition will always be
mapped to logical address, 400000h. Note that even
when the code partitions are switched between Active
and Inactive Partitions by the user, the address of the
Active Partition will still be 000000h, and the address of
the Inactive Partition will still be at 400000h.
boot sequence number is corrupted, the device will use
the partition without a corrupted boot sequence number
as the Active Partition.
The user can also change which partition is active at run
time using the BOOTSWP instruction. Issuing a BOOTSWP
instruction does not affect which partition will be the
Active Partition after a Reset. Figure 7-1 demonstrates
how the relationship between Partitions 1 and 2, shown
in red and blue respectively, and the Active and Inactive
Partitions are affected by reprogramming the boot
sequence number or issuing a BOOTSWP instruction.
The P2ACTIV bit (NVMCON<10>) can be used to
determine which physical partition is the Active Partition.
If P2ACTIV = 1, Partition 2 is active; if P2ACTIV = 0,
Partition 1 is active.
7.2
Erase Operations with Dual
Partition Flash
PIC24FJ256GA412/GB412 family devices support
three erase operations: Chip Erase, Inactive Partition
Erase and Page Erase.
A Chip Erase operation erases all of user memory,
including the Flash Configuration Words and the
FBOOT Configuration register. This resets the Partition
Flash mode of the device to its default, Single Partition
Flash mode. Chip Erase is not available during
run-time operation.
An Inactive Partition Erase operation can be executed
at run time from the Active Partition. It will erase all user
memory and Flash Configuration Words in the Inactive
Partition. Note that the Inactive Partition Erase
command is only functional when the device is in one
of the Dual Partition modes and permitted by the
device’s code protection settings.
Since the Flash Configuration Words reside in the last
locations of user program space, they may be erased
using a Chip Erase, an Inactive Partition Erase or a
Page Erase that targets the last page of user Flash
memory. Note that a Page Erase of the Configuration
Words page may also erase the last lines of user
code, which will need to be restored. See Section 3.7
“Writing Configuration Bits” for more information.
The Boot Sequence Configuration Words (FBTSEQ)
determine whether Partition 1 or Partition 2 will be
active after Reset. If the part is operating in Dual
Partition mode, the partition with the lower boot
sequence number will operate as the Active Partition
(FBTSEQ is unused in Single Partition mode). The
partitions can be switched between Active and
Inactive by reprogramming their boot sequence
numbers, but the Active Partition will not change until a
device Reset is performed. If both boot sequence
numbers are the same, or if both are corrupted, the part
will use Partition 1 as the Active Partition. If only one
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DS30010073A-page 57
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FIGURE 7-1:
RELATIONSHIP BETWEEN PARTITIONS 1 AND 2 AND
ACTIVE/INACTIVE PARTITIONS
000000h
Partition 1
000000h
000000h
Partition 2
Partition 1
Active Partition
BSEQ = 10
BOOTSWP Instruction
400000h
Partition 2
BSEQ = 10
BSEQ = 15
400000h
Reset
400000h
Partition 1
Partition 2
Inactive Partition
BSEQ = 15
000000h
Partition 1
BSEQ = 15
BSEQ = 10
000000h
000000h
Partition 1
Partition 2
Active Partition
BSEQ = 10
Reset
Reprogram BSEQ
400000h
Partition 2
BSEQ = 5
BSEQ = 10
400000h
Partition 2
400000h
Partition 1
Inactive Partition
BSEQ = 15
DS30010073A-page 58
BSEQ = 5
BSEQ = 10
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7.3
Dual Partition Configuration
Words
In Dual Partition modes, each partition has its own set
of Flash Configuration Words. The full set of Configuration registers in the Active Partition is used to determine the device’s configuration; the Configuration
Words in the Inactive Partition are used to determine
the device’s configuration when that partition becomes
active. However, some of the Configuration registers in
the Inactive Partition (FSEC, FBSLIM and FSIGN) may
be used to determine how the Active Partition is able or
allowed to access the Inactive Partition.
7.4
When programming a PIC24FJ256GA412/GB412
family device with multiple applications, the following
sequence of steps is recommended to program the
device correctly.
1.
2.
3.
4.
5.
 2015 Microchip Technology Inc.
Programming in Dual Partition
Flash Mode
Perform a Chip Erase on the device.
Program the FBOOT register to one of the Dual
Partition modes, then reset the device to put it in
Dual Partition Flash mode. At this point, the
device’s program memory is functionally divided
into two partitions.
Program the first application (including its boot
sequence number and Configuration Words)
into the Active Partition at address, 000000h.
Program the second application, its boot
sequence number and its Configuration Words
into the Inactive Partition at address, 400000h.
Finally, perform a device Reset. The Active/
Inactive Partitions may switch at this point,
depending on the values that the user used for
the boot sequence numbers for each application.
DS30010073A-page 59
PIC24FJ256GA412/GB412 FAMILY
8.0
DEVICE ID
TABLE 8-1:
The Device ID region of memory can be used to
determine variant and manufacturing information about
the chip. This region of memory is read-only and can be
read when code protection is enabled. The DEVID
register (FF0000h) identifies the specific part number
of the device, while DEVREV (FF0002h) shows the
silicon revision level.
Table 8-1 lists the identification information for each
device. Table 8-2 shows the Device ID registers and
Table 8-3 describes the bit field of each register.
TABLE 8-2:
Address
Device
DEVID
PIC24FJ64GA406
6100h
PIC24FJ64GA410
6101h
PIC24FJ64GA412
6102h
PIC24FJ64GB406
6104h
PIC24FJ64GB410
6105h
PIC24FJ64GB412
6106h
PIC24FJ128GA406
6108h
PIC24FJ128GA410
6109h
PIC24FJ128GA412
610Ah
PIC24FJ128GB406
610Ch
PIC24FJ128GB410
610Dh
PIC24FJ128GB412
610Eh
PIC24FJ256GA406
6110h
PIC24FJ256GA410
6111h
PIC24FJ256GA412
6112h
PIC24FJ256GB406
6114h
PIC24FJ256GB410
6115h
PIC24FJ256GB412
6116h
PIC24FJ256GA412/GB412 FAMILY DEVICE ID REGISTERS
Bit
Name
FF0000h
DEVID
FF0002h
DEVREV
TABLE 8-3:
DEVICE IDs
15
14
13
12
11
10
9
8
7
6
5
FAMID<7:0>
4
3
2
1
0
DEV<7:0>
—
REV<3:0>
DEVICE ID BIT FIELD DESCRIPTIONS
Bit Field
Register
Description
FAMID<7:0>
DEVID
Encodes the family ID of the device.
DEV<7:0>
DEVID
Encodes the individual ID of the device.
REV<3:0>
DEVREV
Encodes the sequential (numerical) revision identifier of the device.
DS30010073A-page 60
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
9.0
CHECKSUM COMPUTATION
Checksums for devices are 16 bits in size. The
checksum is calculated by summing the following:
• Contents of code memory locations
• Contents of Flash Configuration Words
All memory locations, including Configuration Words,
are summed by adding all three bytes of each memory
address.
Since the configuration memory space in these devices
is Flash-based, the erased value of all memory bits,
except FSIGN, is a ‘1’. The FSIGN Configuration Word
is the only register that uses a mask value. Certain
Configuration bits will be reserved and these bits may
require a ‘0’ or a ‘1’ to be written in order for the device
to operate properly. There is no error checking in either
hardware or in MPLAB® X IDE to prevent the user from
improperly programming these bits. The device checksum is calculated based on the contents of the Hex file,
even if the reserved bits are incorrectly programmed.
These devices use a Dual Partition Flash memory,
whose behavior is controlled by the FBOOT register.
Table 9-2 shows a Single Partition set of checksums
and Table 9-3 shows a Dual Partition set of checksums.
The difference in the two is the inclusion of a second
FSIGN register in Dual Partition mode and the values
for FBOOT; this will alter the computed checksum.
The entire Flash-based Configuration Word area is
used when computing the checksum, with the exception of the Configuration Word, FBTSEQ. FBTSEQ is
not used in the checksum calculation since it can be
altered by a bootloader.
The checksum is computed “bytewise”, with the final
result truncated to 16 bits. In the PIC24 architecture,
each Flash memory address contains two bytes (if an
even address) or one byte (if an odd address, since the
upper byte is implemented and is always 0x00). When
computing the checksum, both the upper and lower
bytes of the word at a given address should be added
to the running sum separately as bytes, instead of as a
single 16-bit word.
 2015 Microchip Technology Inc.
For example, in a program that contains two words with
contents such as:
Contents at address 0x0000 = 0xABCD
Contents at address 0x0001 = 0x00EF
The checksum over the [0x0000:0x0001] region is:
0xCD + 0xAB + 0xEF + 0x00 = 0x0267.
The CFGB block checksum is also a “bytewise” sum of
all contents of the configuration block address region,
and is computed identically to the PROG region, with
the exception of the FSIGN Configuration Word. The
FSIGN Configuration Word contains a reserved bit that
should be AND masked out and excluded during the
checksum computation.
TABLE 9-1:
CONFIGURATION BIT MASKS
FOR ALL DEVICES
Mask Value
Default Reset
Value
FSEC
FFFFh
FFFFh
FBSLIM
FFFFh
FFFFh
Register
FSIGN
7FFFh
7FFFh
FOSCSEL
FFFFh
FFFFh
FOSC
FFFFh
FFFFh
FWDT
FFFFh
FFFFh
FPOR
FFFFh
FFFFh
FICD
FFFFh
FFFFh
FDS
FFFFh
FFFFh
FDEVOPT
FFFFh
FFFFh
FBTSEQ
FFFFFFh
FFFFFFh
FBOOT
FFFFh
FFFFh
DS30010073A-page 61
PIC24FJ256GA412/GB412 FAMILY
TABLE 9-2:
CHECKSUM COMPUTATION (SINGLE PARTITION)
Read Code
Protection
Device
PIC24FJ256GB412
PIC24FJ128GB412
PIC24FJ64GB412
Disabled
Checksum Computation
PROG[0:2AF7F] + CFGB[2AF80:2AFFF]
Enabled
0
Disabled
PROG[0:1577F] + CFGB[15780:157FF]
Enabled
0
Disabled
PROG[0:AF7F] + CFGB[AF80:AFFF]
Enabled
0
Erased
Value
Value with
0xAAAAAA at 0x0
and Last
Code Address
F780h(1)
F582h(1)
0000h
0000h
FB80h(1)
F982h(1)
0000h
0000h
F780h(1)
F582h(1)
0000h
0000h
Legend: PROG[a:b]= Program memory byte sum of locations, a to b inclusive (all 3 bytes of code memory)
CFGB[c:d] = Configuration memory byte sum of locations, c to d inclusive, with FSIGN masked
(FSIGN & 7FFFF)
Note 1: For the checksum computation example, the Configuration bits are set to the default configuration values
after erasing the part.
TABLE 9-3:
CHECKSUM COMPUTATION (DUAL PARTITION)
Device
Read Code
Protection
Checksum Computation
Disabled
PROG[0:1577F] + CFGB[15780:157FF] +
PROG[400000:41577F] + CFGB[415780:4157FF]
Enabled
0
PIC24FJ256GB412
Disabled
PROG[0:AA7F] + CFGB[AA80:ABFF] +
PROG[400000:40AA7F] + CFGB[40AA80:40ABFF]
Enabled
0
PIC24FJ128GB412
Disabled
PROG[0:577F] + CFGB[5780:57FF] +
PROG[400000:40577F] + CFGB[405780:4057FF]
Enabled
0
PIC24FJ64GB412
Value with
Erased 0xAAAAAA at 0x0
Value
and Last
Code Address
F700h(1)
F304h(1)
0000h
0000h
FB00h(1)
F704h(1)
0000h
0000h
F700h(1)
F304h(1)
0000h
0000h
Legend: PROG[a:b] = Program memory byte sum of locations, a to b inclusive (all 3 bytes of code memory)
CFGB[c:d] = Configuration memory byte sum of locations, c to d inclusive, with FSIGN masked
(FSIGN & 7FFFF)
Note 1: For the checksum computation example, the Configuration bits are set to the default configuration values
after erasing the part.
DS30010073A-page 62
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
10.0
AC/DC CHARACTERISTICS
AND TIMING REQUIREMENTS
Table 10-1 lists the AC/DC characteristics and timing
requirements.
TABLE 10-1:
AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
Standard Operating Conditions
Operating Temperature: -40ºC to +85ºC. Programming at +25ºC is recommended.
Param.
Symbol
No.
Characteristic
Min.
Max.
Units
—
—
V
Conditions
D111
VDD
Supply Voltage During Programming
D113
IDDP
Supply Current During Programming
—
—
mA
See Note 2
D114
IPEAK
Instantaneous Peak Current During Start-up
—
—
mA
See Note 2
D031
VIL
Input Low Voltage
—
—
V
See Note 2
D041
VIH
Input High Voltage
—
—
V
See Note 2
D080
VOL
Output Low Voltage
—
—
V
See Note 2
D090
VOH
Output High Voltage
—
—
V
See Note 2
D012
CIO
Capacitive Loading on I/O Pin (PGEDx)
—
—
pF
See Note 2
P1
TPGC
Serial Clock (PGECx) Period (ICSP™)
200
—
ns
P1
TPGC
Serial Clock (PGECx) Period (Enhanced
ICSP)
500
—
ns
P1A
TPGCL
Serial Clock (PGECx) Low Time (ICSP)
80
—
ns
P1A
TPGCL
Serial Clock (PGECx) Low Time (Enhanced
ICSP)
200
—
ns
P1B
TPGCH
Serial Clock (PGECx) High Time (ICSP)
80
—
ns
P1B
TPGCH
Serial Clock (PGECx) High Time (Enhanced
ICSP)
200
—
ns
ns
P2
TSET1
Input Data Setup Time to Serial Clock 
15
—
P3
THLD1
Input Data Hold Time from PGECx
15
—
ns
P4
TDLY1
Delay Between 4-Bit Command and
Command Operand
40
—
ns
P4A
TDLY1A
Delay Between Command Operand and
Next 4-Bit Command
40
—
ns
P5
TDLY2
Delay Between Last PGECx  of Command
to First PGECx  of Read of Data Word
20
—
ns
P6
TSET2
VDD Setup Time to MCLR 
100
—
ns
P7
THLD2
Input Data Hold Time from MCLR 
50
—
ms
P8
TDLY3
Delay Between Last PGECx  of Command
Byte to PGEDx  by PE
12
—
s
Note 1:
2:
3:
See Note 1 and Note 2
VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within
±0.3V of VDD and VSS, respectively.
Time depends on the FRC accuracy and the value of the FRC Oscillator Tuning register. Refer to the
“Electrical Characteristics” chapter in the specific device data sheet.
This time applies to Program Memory Words, Configuration Words and User ID Words.
 2015 Microchip Technology Inc.
DS30010073A-page 63
PIC24FJ256GA412/GB412 FAMILY
TABLE 10-1:
AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS (CONTINUED)
Standard Operating Conditions
Operating Temperature: -40ºC to +85ºC. Programming at +25ºC is recommended.
Param.
Symbol
No.
Characteristic
Min.
Max.
Units
Conditions
P9A
TDLY4
PE Command Processing Time
10
—
s
P9B
TDLY5
Delay Between PGEDx by PE to PGEDx,
Released by PE
15
23
s
P10
TDLY6
PGECx Low Time After Programming
400
—
ns
P11
TDLY7
Chip Erase Time
18
27
ms
P12
TDLY8
Page Erase Time
18
27
ms
See Note 2
P13
TDLY9
Double-Word Programming Time
18
—
s
See Note 2 and Note 3
P14
TR
MCLR Rise Time to Enter ICSP mode
—
1.0
s
P15
TVALID
Data Out Valid from PGECx 
10
—
ns
P16
TDLY10 Delay Between Last PGECx  and MCLR 
P17
THLD3
MCLR to VDD 
P18
TKEY1
P19
TKEY2
P21
TMCLRH MCLR High Time
Note 1:
2:
3:
0
—
s
100
—
ns
Delay from First MCLR to First PGECx 
for Key Sequence on PGEDx
1
—
ms
Delay from Last PGECx for Key
Sequence on PGEDx to Second MCLR 
25
—
ns
—
500
s
VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within
±0.3V of VDD and VSS, respectively.
Time depends on the FRC accuracy and the value of the FRC Oscillator Tuning register. Refer to the
“Electrical Characteristics” chapter in the specific device data sheet.
This time applies to Program Memory Words, Configuration Words and User ID Words.
DS30010073A-page 64
 2015 Microchip Technology Inc.
PIC24FJ256GA412/GB412 FAMILY
APPENDIX A:
REVISION HISTORY
Revision A (February 2015)
Original version of this document.
 2015 Microchip Technology Inc.
DS30010073A-page 65
PIC24FJ256GA412/GB412 FAMILY
NOTES:
DS30010073A-page 66
 2015 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-63277-108-7
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2015 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS30010073A-page 67
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