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1-888
®
Continuously Variable Slope
Delta-Modulator (CVSD)
HC-55564/883
FN3738.1
Features
The HC-55564/883 is a half duplex modulator/demodulator
CMOS intergrated circuit used to convert voice signals into
serial NRZ digital data and to reconvert that data into voice.
The conversion is by delta-modulation, using the
Continuously Variable Slope (CVSD) method of
modulation/demodulation.
While the signals are compatible with other CVSD circuits,
the internal design is unique. The analog loop filters have
been replaced by very low power digital filters which require
no external timing components. This approach allows
inclusion of many desirable features which would be difficult
to implement using other approaches.
The fundamental advantages of delta-modulation, along with
its simplicity and serial data format, provide an efficient (low
data rate/low memory requirements) method for voice
digitization. The device may be easily configured with the
National TP3040 PCM/CVSD filter.
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of Paragraph 1.2.1.Requires Few External Parts
• All Digital
• Requires Few External Parts
• Low Power Drain
• Time Constants Determined by Clock Frequency; No Calibration or Drift Problems: Automatic Offset Adjustment
• Half Duplex Operation Under Digital Control
• Filter Reset Under Digital Control
• Automatic Overload Recovery
• Automatic “Quiet” Pattern Generation
• AGC Control Signal Available
Applications
• Voice Transmission Over Data Channels (Modems)
• Voice/Data Multiplexing (Pair Gain)
• Voice Encryption/Scrambling
The HC-55564/883 is usable from 9k bits/sec to above
64kbps. For more applications information, see Application
Notes AN576 and AN607.
• Voicemail
Ordering Information
• Pagers/Satellites
• Audio Manipulations: Delay Lines, Time Compression,
Echo Generation/Suppression, Special Effects, etc.
• Data Acquisition Systems
PART
NUMBER
TEMPERATURE
RANGE
PACKAGE
HC1-55564/883
-55oC to +125oC
14 Lead CerDIP
HC4-55564/883
-55oC to +125oC
20 Lead Ceramic LCC
• Voice I/O for Digital Systems and Speech Synthesis
Requiring Small Size, Low Weight, and Ease of Reprogrammability
Pinouts
14 DIG OUT
ANALOG GND 2
13 FZ
AOUT 3
12 DIG IN
AGC 4
11 APT
ANALOG GND
1 20 19
18 DIGITAL IN
17 NC
AOUT 4
16 APT
NC 5
15 NC
AGC 6
10 ENC/DEC
NC 7
NC 6
9 CLOCK
AIN
8 DIG GND
2
3
AIN 5
NC 7
NC
DIGITAL
OUT
FZ
VDD 1
VDD
HC-55564/883
(CLCC)
TOP VIEW
HC-55564/883
(CERDIP)
TOP VIEW
14 ENCODE/DECODE
13 CLOCK
8
9 10 11 12
DIGITAL
GND
NC
NC
NC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
HC-55564/883
Pin Description
PIN NO.
14 LEAD
DIP
PIN NO.
20 LEAD
LCC
SYMBOL
1
2
VDD
Positive Supply Voltage. Voltage range is +3.2V to +6.0V.
2
3
Analog
GND
Analog Ground connection to D/A ladders and comparator.
3
4
AOUT
Audio Out recovered from 10-bit DAC. May be used as side tone at the transmitter. Presents
approximately 75kΩ source with DC offset of VDD/2. Within ±2dB of Audio Input. Should be externally
AC coupled.
4
6
AGC
Automatic Gain Control output. A logic low level will appear at this output when the recovered signal excursion reaches one-half of full scale value. In each half cycle full scale is VDD/2. The mark-space ratio
is proportional to the average signal level.
5
8
AIN
Audio Input to comparator. Should be externally AC coupled. Presents approximately 200kΩ in series
with VDD/2.
6, 7
1, 5, 7, 9,
10, 11, 15,
17
NC
No internal connection is made to these pins.
8
12
Digital
GND
Logic ground. 0V reference for all logic inputs and outputs.
9
13
Clock
Sampling rate clock. In the decode mode, must be synchronized with the digital input data such that the
data is valid at the positive clock transition. In the encode mode, the digital data is clocked out on the
negative going clock transition. The clock rate equals the data rate.
10
14
Encode/
Decode
A single CVSD can provide half-duplex operation. The encode or decode function is selected by the logic
level applied to this input. A low level selects the encode mode, a high level the decode mode.
11
16
APT
Alternate Plain Text input. Activating this input caused a digital quieting pattern to be transmitted, however;
internally the CVSD is still functional and a signal is still available at the AOUT port. Active low.
12
18
Digital In
13
19
FZ
14
20
Digital Out
DESCRIPTION
Input for the received digital NRZ data.
Force Zero input. Activating this input resets the internal logic and forces the digital output and the recovered audio output into the “quieting” condition. An alternating 1-0 pattern appears at the digital output at
1/2 the clock rate. When this is decoded by a receive CVSD, a 10mVP-P inaudible signal appears at audio
output. Active low.
Output for transmitted digital NRZ data.
NOTE:
1. No active input should be left in a “floating condition”.
Functional Diagram
(12)
DIGITAL
IN
(1)
VDD
3V TO 6V
(10)
ENC/DEC
APT
(11) (13) FORCE
ZERO
RESET
T
VDD
2
(5)
CLOCK
F/F
Q
D
AIN
ZIN
(2)
ANALOG
GND
COMPARATOR
10-BIT
DAC
10
10
(3) AOUT
(SIDE TONE)
ZOUT
(4) AGC OUT
2
(8)
(9)
(14)
DIGITAL
OUT
3-BIT
SHIFT
REGISTER
STEP
SIZE
LOGIC
RESET
SIGNAL
ESTIMATE
FILTER 1ms
DIGITAL
GND
6
DIGITAL
MODULATOR
±1
SYLLABIC
FILTER
4ms
10-BIT
DAC
RESET
HC-55564/883
Absolute Maximum Ratings
Thermal Information
Voltage at Any Pin . . . . . . . . . . . . . . . . . . .GND -0.3V to VDD +0.3V
Maximum V DD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
Minimum V DD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.2V
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . .+300oC
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<2000V
Thermal Resistance
θJA
θJC
CerDIP Package . . . . . . . . . . . . . . . . . . .
66oC/W
16oC/W
Ceramic LCC Package . . . . . . . . . . . . . .
65oC/W
15oC/W
Package Power Dissipation Limit at +75oC for TJ at ≤ +175oC
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.52W
Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.54W
Package Power Dissipation Derating Factor Above +75oC
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2W/oC
Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . 15.4W/oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC
Operating Supply Voltage (VDD Range) . . . . . . . . . . . +3.2V to +6.0V
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: VSUPPLY = +5V, fclk = 16kHz, Operating Temperature = -55oC ≤ TA ≤ +125oC, Unless Otherwise Specified.
PARAMETER
SYMBOL
Supply Current
IDD
Logic Input High (Note 2)
VIH
Logic Input Low (Note 2)
VIL
Logic Output High (Note 3)
VOH
Logic Output Low (Note 3)
VOL
Quieting Pattern
Amplitude (Note 8)
VQP
AGC Threshold (Note 9)
VATH
CONDITIONS
Encode Mode: A IN = 0V
Input Level: ‘1’ = +3.5V,
‘0’ = +1.5V
Input Level: ‘1’ = +3.5V,
‘0’ = +1.5V
ILOAD = -40µA
ILOAD = +0.8mA
FZ = 0; Clock Inputs
Switched Statically
Encode Mode
LIMITS
GROUP A
SUBGROUP
TEMPERATURE
TYP
MAX
UNITS
1
+25oC
-
1.5
mA
2, 3
+125oC, -55oC
-
1.5
mA
1
+25oC
3.5
-
V
2, 3
+125oC, -55oC
3.5
-
V
1
+25oC
-
1.5
V
2, 3
+125oC, -55oC
-
1.5
V
1
+25oC
4.0
-
V
2, 3
+125oC, -55oC
4.0
-
V
1
+25oC
-
0.4
V
2, 3
+125oC, -55oC
-
0.4
V
1
+25oC
-
14
mVP-P
2, 3
+125oC, -55oC
-
14
mVP-P
1
+25oC
0.45
0.65
F.S.
2, 3
+125oC, -55oC
0.45
0.65
F.S.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Table 2 Intentionally Left Blank.
TABLE 3. ELECTRICL PERFORMANCE CHARACTERISTICS
Devices Characterized at: VDD = +5.0V, TA = +25oC, Operating Temperature, fclk = 16kHz Clock Sampling Rate.
ENC/DDC = ENC = Encode Mode, Unless Otherwise Specified.
LIMITS
PARAMETER
SYMBOL
Sampling Rate
CLK
CONDITIONS
AIN = 0.775 VRMS at 20Hz
AIN = 0.775 VRMS at
100Hz
CLK Duty Cycle
3
NOTE
TEMPERATURE
1, 12
+25oC
9
64
kBS
+125oC, -55oC
9
64
kBS
+25oC
30
70
%
+125oC, -55oC
30
70
%
12
TYP
MAX
UNITS
HC-55564/883
TABLE 3. ELECTRICL PERFORMANCE CHARACTERISTICS (Continued)
Devices Characterized at: VDD = +5.0V, TA = +25oC, Operating Temperature, fclk = 16kHz Clock Sampling Rate.
ENC/DDC = ENC = Encode Mode, Unless Otherwise Specified. (Continued)
LIMITS
PARAMETER
SYMBOL
Audio Input Voltage
AIN
Audio Output Voltage
AOUT
Input Impedance
ZIN
Output Impedance
ZOUT
Transfer Gain
AE-D
CONDITIONS
AIN = 100Hz
AIN = 100Hz
AIN = 100Hz
AIN = 100Hz
AIN = 0.775 VRMS at
100Hz
AIN at 100Hz. Note 8
NOTE
TEMPERATURE
TYP
MAX
UNITS
4, 12
+25oC
-
1.2
VRMS
+125oC, -55oC
-
1.2
VRMS
+25oC
-
1.2
VRMS
+125oC, -55oC
-
1.2
VRMS
5, 12
+25oC
150
500
kΩ
+125oC, -55oC
150
500
kΩ
+25oC
35
25
kΩ
+125oC, -55oC
35
25
kΩ
+25oC
-2
+2
dB
-55oC, +125oC
-2
+2
dB
12, 13
+25oC
0.3
-
% of
Supply
6, 12
6, 12
11, 12
Resolution
RES
MIN Step Size
MSS
7, 12
+25oC
0.10
0.14
% of
Supply
Clamping Threshold
VCTH
10, 12
+25oC
0.70
0.90
F.S.
NOTES:
1. There is one NRZ (Non-Return Zero) data bit per clock period. Data is clocked out on the negative clock edge. Data is clocked into the CVSD
on the positive going edge (see Figure 2). Clock may be run at less than 9kbps.
2. Logic inputs are CMOS compatible at supply voltage and are diode protected. Digital data input is NRZ at clock rate.
3. Logic outputs are CMOS compatible at supply voltage and will withstand short-circuits to VDD or ground; however, the short circuit duty cycle
must not exceed 5% in order to maintain an acceptable current density level. Digital data output is NRZ and changes with negative clock transitions. Each output will drive one LS TTL loads.
4. Recommended voice input range for best voice performance. Should be externally AC coupled.
5. May be used for side-tone in encode mode. Should be externally AC coupled.
6. Presents series impedance with audio signal. Zero signal reference is approximately VDD/2. Varies with audio input level by ±2dB.
7. The minimum audio output voltage change that can be produced by the internal DAC.
8. The “quieting” pattern or idle-channel audio output steps at 1/2 the bit rate, changing state on negative clock transitions.
9. A logic “0” will appear at the AGC output pin when the recovered signal reaches one-half of full-scale value (positive or negative), i.e. at VDD/2
±25% of VDD.
10. The recovered signal will be clamped, and the computation will be inhibited, when the recovered signal reaches three-quarters of full-scale value, and will unclamp when it falls below this value (positive or negative).
11. No load condition measured from audio in to audio out.
12. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics.
13. The minimum audio input voltage above which encoding is guaranteed to take place.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
Interim Electrical Parameters (Pre Burn-In)
Final Electrical Test Parameters
SUBGROUPS (SEE TABLE 1)
1
1 (Note 1), 2, 3
Group A Test Requirements
1, 2, 3
Groups C and D Endpoints
1
NOTE:
1. PDA applies to Subgroup 1 only.
4
HC-55564/883
Die Characteristics
DIE DIMENSIONS:
82 x 147 x 20 ± 1 mils
GLASSIVATION:
Type: Silane, 3% Phosphorous
Thickness: 13kÅ ± 2.6kÅ
METALLIZATION:
Type: AlSi
Thickness: 10kÅ ± 1kÅ
WORST CASE CURRENT DENSITY:
2.0 x 105A/cm2
TRANSISTOR COUNT: 1896
PROCESS: CMOS; SAJI
Metallization Mask Layout
HC-55564/883
ANALOG
GND
VDD
DIGITAL
OUT
FZ
DIGITAL IN
AOUT
APT
AGC
ENC/DEC
AIN
CLOCK
DIGITAL
GND
5