HIP1011B ® Data Sheet November 18, 2004 FN4640.5 PCI Hot Plug Controller Features The HIP1011B, the third product in the HIP1011 family, is an electronic circuit breaker that monitors, reports and protects circuits from excessive load currents. As a pin-for-pin drop-in alternative offering similar functionality to the widely used HIP1011, the HIP1011B is compatible with CompactPCI peripheral boards and PCI Hot Plug systems where voltage “health” monitoring and reporting are centralized by the system controller IC. The HIP1011B does not monitor nor respond to under voltage conditions thus making control of a wide range of voltages possible. • Allows for System Centralized Voltage Monitoring The HIP1011B creates a small and simple yet complete power control solution to control the four independent supplies (+5V, +3.3V, +12V, and -12V) found in PCI and CompactPCI systems. For the +12V and -12V supplies, overcurrent protection is provided internally with integrated current sensing FET switches. For the +5V and +3.3V supplies, overcurrent protection is provided by sensing the voltage across the external current-sense resistors. The PWRON input controls the state of both internal and external switches. During an overcurrent condition on any output, all MOSFETs are latched-off and a LOW (0V) is asserted on the FLTN output. The FLTN latch is cleared when the PWRON input is toggled low again. During initial power-up of the main VCC supply (+12V), the PWRON input is inhibited from turning on the switches, and the latch is held in the Reset state until the VCC input is greater than 10V. User programmability of the overcurrent threshold, response time and turn-on slew rate is provided. A resistor connected to the OCSET pin programs the overcurrent thresholds. A capacitor may be added to the FLTN pin to adjust the fault reporting and power-supply latch-off response times after an over-current event. Capacitors connected to the gate pins determine the turn-on rate. • Adjustable Delay to Fault Notification and Latch-Off • Controls Four Supplies: +5V, +3.3V, +12V, and -12V • Internal MOSFET Switches for +12V and -12V Outputs • µP Interface for On/Off Control and Fault Reporting • Adjustable Overcurrent Protection for All Supplies • Provides Overcurrent Fault Isolation • Adjustable Turn-On Slew Rate • Minimum Parts Count Solution • No Charge Pump • Pb-Free Available (RoHS Compliant) Applications • PCI Hot Plug • CompactPCI Pinout HIP1011B (SOIC) TOP VIEW M12VIN 1 FLTN 2 15 M12VG 3V5VG 3 14 12VG 16 M12VO VCC 4 13 GND 12VIN 5 12 12VO 3VISEN 6 11 5VISEN 3VS 7 10 5VS OCSET 8 9 PWRON Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. DWG. # HIP1011BCB 0 to 70 16 Ld SOIC M16.15 HIP1011BCB-T 0 to 70 Tape and Reel HIP1011BCBZA (See Note) 0 to 70 16 Ld SOIC (Pb-free) HIP1011BCBZA-T (See Note) 0 to 70 Tape and Reel (Pb-free) M16.15 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HIP1011B Typical Application 3.3V INPUT 3.3V, 7.6A OUT 5mΩ, 1% 12V, 0.5A OUT -12V, 0.1A OUT 5V, 5A OUT 5mΩ, 1% 5V INPUT HUF761315K8 HIP1011B -12V INPUT M12VIN FLTN 3V5VG VCC 12VIN 3VISEN 3VS OCSET 12V INPUT 6.04kΩ 1% POWER CONTROL INPUT 0.033µF M12VO M12VG 12VG GND 12VO 5VISEN 5VS PWRON 0.033µF 0.033µF NOTE: ALL CAPACITORS ARE ±10%. (OPTIONAL) FAULT OUTPUT (ACTIVE LOW) Simplified Schematic VCC SET (LOW = FAULT) FAULT LATCH LOW = FAULT FLTN VCC - COMP + VOCSET/17 RESET VCC 5VS + - VCC VCC 3V5VG 5VREF 5V ZENER REFERENCE 5VISEN + - VOCSET/13.3 COMP VCC 3VS + - 3VISEN LOW WHEN VCC < 10V COMP VCC VOCSET/0.8 + 12VIN + 12VIN POWER-ON RESET 0.3Ω VCC - 12VG 100µA VOCSET HIGH = FAULT OCSET 12VO HIGH = SWITCHES ON VCC M12VO PWRON + M12VG - GND + - COMP VOCSET/3.3 0.7Ω M12VIN 2 FN4640.5 November 18, 2004 HIP1011B Pin Descriptions PIN DESIGNATOR FUNCTION 1 M12VIN -12V Input 2 FLTN Fault Output 5V CMOS Fault Output; LOW = FAULT. A capacitor may be placed from this pin to ground to provide delay time to fault notification and power supply latch-off. 3 3V5VG 3.3V/5V Gate Output Drive the Gates of the 3.3V and 5V MOSFETs. Connect a capacitor to ground to set the startup ramp. During turn on, this capacitor is charged with a 25µA current source. 4 VCC 12V VCC Input Connect to unswitched 12V supply. 5 12VIN 12V Input 6 3VISEN 3.3V Current Sense Connect to the load side of the current sense resistor in series with source of external 3.3V MOSFET. This pin tied to GND when FET switch outputs disabled. 7 3VS 3.3V Source Connect to Source of 3.3V MOSFET. This connection along with pin 6 (3VISEN) senses the voltage drop across the sense resistor. 8 OCSET Overcurrent Set Connect a resistor from this pin to ground to set the overcurrent trip point of all four switches. All four over current trips can be programmed by changing the value of this resistor. The default (6.04kΩ, 1%) is compatible with the maximum allowable currents as outlined in the PCI specification. 9 PWRON Power On Control 10 5VS 5V Source Connect to Source of 5V MOSFET Switch. This connection along with pin 11 (5VISEN) senses the voltage drop across the sense resistor. 11 5VISEN 5V Current Sense Connect to the load side of the current sense resistor in series with source of external 5V MOSFET. This pin tied to GND when FET switch outputs disabled. 12 12VO Switched 12V Output 13 GND Ground 14 12VG Gate of Internal PMOS Connect a capacitor between 12VG and 12VO to set the start up ramp for the +12V supply. This capacitor is charged with a 25µA current source during start-up. 15 M12VG Gate of Internal NMOS Connect a capacitor between M12VG and M12VO to set the start-up ramp for the M12V supply. This capacitor is charged with 25µA during start-up. 16 M12VO Switched -12V Output Switched 12V Output. This pin tied to GND when FET switch outputs disabled. 3 DESCRIPTION -12V Supply Input. Also provides power to the -12V overcurrent circuitry. Switched 12V supply input. Controls all Four Switches. High to Turn Switches ON, Low to turn them OFF. Switched 12V output. This pin tied to GND when FET switch outputs disabled. Connect to common of power supplies. FN4640.5 November 18, 2004 HIP1011B Absolute Maximum Ratings Thermal Information VCC, 12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V 12VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V12VIN + 0.5V 12VO, 12VG, 3V5VG . . . . . . . . . . . . . . . . . . . . -0.5V to VCC + 0.5V M12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15.0V to + 0.5V M12VO, M12VG . . . . . . . . . . . . . . . . . . . . . VM12VIN-0.5V to + 0.5V 3VISEN, 5VISEN . . . . . . . . . . . -0.5V to the lesser of VCC or + 7.0V Voltage, Any Other Pin. . . . . . . . . . . . . . . . . . . . . . . -0.5V to + 7.0V 12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3A M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8A ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4KeV (HBM) Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 125oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Die Characteristics Number of Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Operating Conditions VCC Supply Voltage Range. . . . . . . . . . . . . . . . . +10.8V to +13.2V 12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +0.5A M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +0.1A Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. All voltages are relative to GND, unless otherwise specified. Electrical Specifications Nominal 5V and 3.3V Input Supply Voltages, VCC = 12VIN = 12V, M12VIN = -12V, TA = TJ = 0 to 70oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 8 - A 5V/3.3V SUPPLY CONTROL 5V Overcurrent Threshold IOC5V See Figure 1, Typical Application 5V Overcurrent Threshold Voltage VOC5V_1 VOCSET = 0.6V 30 36 42 mV 5V Overcurrent Threshold Voltage VOC5V_2 VOCSET = 1.2V 66 72 79 mV 5V Turn-On Time (PWRON High to 5VOUT = 4.75V) tON5V C3V5VG = 0.022µF, C5VOUT = 2000µF, RL = 1Ω - 6.5 - ms 5VS Input Bias Current IB5VS PWRON = High -40 -26 -20 µA 5VISEN Input Bias Current IB5VISEN PWRON = High -160 -140 -110 µA 3V Overcurrent Threshold IOC3V See Figure 1, Typical Application 10 A 3V Overcurrent Threshold Voltage VOC3V_1 VOCSET = 0.6V 42 49 56 mV 3V Overcurrent Threshold Voltage VOC3V_2 VOCSET = 1.2V 88 95 102 mV 3V Turn-On Time (PWRON High to 3VOUT = 3.00V) tON3V C3V5VG = 0.022µF, C3VOUT = 2000µF, RL = 0.43Ω - 6.5 - ms 3VS Input Bias Current IB3VS PWRON = High -40 -26 -20 µA IB3VISEN PWRON = High -160 -140 -110 µA 11 11.7 - V 22.5 25.0 27.5 µA 3VISEN Input Bias Current 3V5VG VOUT High VOUT_HI_35VG 3V5VG IOUT = 5µΑ Gate Output Charge Current IC3V5VG PWRON = High, V3V5VG = 2V Gate Turn-On Time (PWRON High to 3V5VG = 11V) tON3V5V C3V5VG = 0.1µF - 280 500 µs Gate Turn-Off Time tOFF3V5V C3V5VG = 0.1µF, 3V5VG from 9.5V to 1V - 13 17 µs C3V5VG = 0.022µF, 3V5VG Falling 90% to 10% - 2 - µs Gate Turn-Off Time 4 FN4640.5 November 18, 2004 HIP1011B Electrical Specifications Nominal 5V and 3.3V Input Supply Voltages, VCC = 12VIN = 12V, M12VIN = -12V, TA = TJ = 0 to 70oC, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS +12V SUPPLY CONTROL On Resistance of Internal PMOS rDS(ON)12 PWRON = High, ID = 0.5A, TA = TJ = 25oC 0.18 0.3 0.35 Ω Overcurrent Threshold IOC12V_1 VOCSET = 0.6V 0.6 0.75 0.9 A Overcurrent Threshold IOC12V_2 VOCSET = 1.2V 1.25 1.50 1.8 A 22.5 25 28.5 µA Gate Charge Current IC12VG PWRON = High, V12VG = 3V Turn-On Time (PWRON High to 12VG = 1V) tON12V C12VG = 0.022µF - 16 20 ms Turn-Off Time tOFF12V C12VG = 0.1µF, 12VG - 9 12 µs C12VG = 0.022µF, 12VG Rising 10% - 90% - 3 - µs PWRON = High, ID = 0.1A, TA = TJ = 25oC 0.5 0.7 0.9 Ω Turn-Off Time -12V SUPPLY CONTROL On Resistance of Internal NMOS rDS(ON)M12 Overcurrent Threshold IOC12V_1 VOCSET = 0.6V 0.15 0.18 0.25 A Overcurrent Threshold IOC12V_2 VOCSET = 1.2V 0.30 0.37 0.50 A Gate Output Charge Current ICM12VG PWRON = High, V3VG = -4V 22.5 25 28.5 µA Turn-On Time (PWRON High to M12VG = -1V) tONM12V CM12VG = 0.022µF - 160 300 µs Turn-On Time (PWRON High to M12VO = -10.8V) tONM12V CM12VG = 0.022µF, CM12VO = 50µF, RL = 120Ω - 16 - ms Turn-Off Time tOFFM12V CM12VG = 0.1µF, M12VG - 18 23 µs CM12VG = 0.022µF, M12VG Falling 90% to 10% - 3 - µs PWRON = High - 2 2.6 mA Turn-Off Time M12VIN Input Bias Current IBM12VIN CONTROL I/O PINS Supply Current IVCC 4 5 5.8 mA OCSET Current IOCSET 95 100 105 µA tOC - 500 960 ns VTHPWRON 0.8 1.6 2.1 V - 0.6 0.9 V 3.9 4.3 4.9 V 1.45 1.8 2.25 V 8.7 9.4 9.9 V Overcurrent Fault Response Time PWRON Threshold Voltage FLTN Output Low Voltage VFLTN,OL IFLTN = 2mA FLTN Output High Voltage VFLTN,OH IFLTN = 0 to -4mA FLTN Output Latch Threshold VFLTN,TH 12V Power On Reset Threshold VPOR,TH 5 VCC Voltage Falling FN4640.5 November 18, 2004 HIP1011B Typical Performance Curves 105 900 95 NMOS -12 rON 300 800 PMOS +12 rON 280 700 260 0 5 OC VTH (mV) 320 1000 NMOS rON -12 (mΩ) PMOS rON + 12 (mΩ) 340 3V OCVTH 85 5V OCVTH 75 65 600 10 15 20 25 30 35 40 45 50 55 60 65 70 0 5 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 1. rON vs TEMPERATURE FIGURE 2. OC VTH vs TEMPERATURE (VROCSET = 1.21V) 102 9.5 101 9.4 VPOR VTH (V) I OCSET (µA) 10 15 20 25 30 35 40 45 50 55 60 65 70 100 99 9.3 9.2 98 9.1 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC) FIGURE 3. OCSET CURRENT vs TEMPERATURE FIGURE 4. VCC POWER ON RESET VTH vs TEMPERATURE Adjusting the Fault Reporting and Power Supply Latch-Off Delay Times Figure 5 illustrates the relationship between the FLTN signal and the gate drive outputs. Duration a, indicates the time between FLTN starting to transition from High to Low, (indicating a fault has occurred) and the start of the gate drive outputs latching off. The latch-off is initiated by the falling FLTN signal reaching the output latch threshold voltage, VFLTN, TH. For additional details and wave forms see HIP1011A Data Sheet FN4631. Table 1 illustrates the effect of the FLTN capacitor on the response times. VFLTN,TH FLTN a TABLE 1. RESPONSE TIME TABLE 3V5VG Response a 3V5VG 0.001µF 0.1µF 10µF 0.85µs 37µs 3.8ms T1 T2 FIGURE 5. TIMING DIAGRAM 6 FN4640.5 November 18, 2004 HIP1011B Applications PWRON is being held low. With the logic devices powered the inverter U2 input is pulled high putting a low on the three-state driver U1 input which is passed through to the PWRON pin. Implementing the HIP1011B in the CompactPCI Hot Swap Application Upon complete insertion the shortest length pin, “board present” which is tied to ground on the backplane finally contacts the inverter input. The inverter output pulls high turning on the HIP1011B through U1 thus, the board is fully powered on only upon complete insertion. This application offers to the CompactPCI peripheral board designer programmable Over Current (OC) protection, programmable delays to latch off, and soft start ramp turn on for all four supplies with simultaneous latch off upon OC fault detection. Fault Reset Figure 6 illustrates the HIP1011EVAL2 evaluation board for CompactPCI Hot Swap implementation. The shaded components are the external components necessary to accomplish both controlled power up and turn-on. For minimum PCB area single gate logic can be used. If an overcurrent condition is detected on the board by the HIP1011B the FLTN signal transitions low, once the VFLTN,TH is reached all the switches are simultaneously switched off protecting the system, the board and its components. The system controller is notified of the fault occurrence by the FLTN signal. Insertion Sequence Because of the staggered pin lengths in the CompactPCI connector, as the board is inserted into the slot, the ground bus plane is connected first via the longest pins referencing the HIP1011B by way of the PWRON, OCSET and GND pins through R4 and R3. Additionally the three-state driver, U1 address line is referenced through R6. Reset of the faulted card is accomplished by a positive pulse on the three-state oe input. The pulse puts U1 output into a high Z state allowing R4 to pull the HIP1011B PWRON pin low, resetting the HIP1011B. The HIP1011B switches turn back on when U1 oe input returns to a low state resulting in PWRON going high. The reset pulse can be generated by either the system restart/reset to the master board or from the master system board to any of the peripheral boards in the system. Subsequently the medium length pins engage to connect the +3.3V, +5V, +12V, -12V lines to the inputs, activating the HIP1011B, and the 2 logic devices, U1 and U2. At this time the HIP1011B is in control holding off all the MOSFET switches, as -12VOUT 5VOUT 3.3VOUT 5V INPUT R1 3.3V INPUT R2 Q1, Q2 Q3, Q4 HIP1011 M12VO M12VIN -12V INPUT M12VG FLTN 12VG 3V5VG 12V INPUT VCC GND 12VIN 12VO 3VISEN OCSET C2 5VISEN R5 5VS 3VS R3 C3 C1 PWRON U1 R4 FLTN U2 +12VOUT BOARD PRESENT PIN ON BACKPLANE R6 C4 oe PULSE HIGH TO RESET FAULT FIGURE 6. HIP1011B CompactPCI APPLICATION CIRCUIT NOTES: 3. Each test point (TP) on HIP1011EVAL2 refers to device pin number. 4. SIGNAL_GND, SHIELD_GND and SHORTPIN_GND can be jumpered together for ease of evaluation. 5. HIP1011B devices can be placed into HIP1011EVAL2 board for evaluation or contact INTERSIL for a HIP1011B equipped evaluation board. 7 FN4640.5 November 18, 2004 HIP1011B HIP1011 Split Load Application HIP1011 High Power Circuit All of the members of the HIP1011 family, including the HIP1011B, can be used in an application where two electrically isolated loads are to be powered from a common bus. This may occur in a system that has a power management feature controlled by a system controller IC invoking a sleep or standby state. Thus one load can be shut down while maintaining power to a second isolated circuit. The circuit shown in Figure 7 shows the external FETs, and sense resistor configuration for the 3.3V and/or 5V load that has such a requirement. The HIP1011 is represented by pin names in rectangles. Q1 and Q2 are the N-Channel FETs for each load on this rail, these are sized appropriately for each load. R1 and R2 are needed to pull down the supply slot pins or load when slot power is disabled as the load discharge FETs (Q3) on the VISEN pins are no longer attached to the load. When power is turned off to the load these (~100Ω) FETs turn on, thus some low current, (10mA) continues to be drawn from the supply in addition to the sleep load current resulting in a 4oC die temperature rise. Instances occur when a noncompliant card is designed for use in a PCI environment. Although the HIP1011 family has proven to be very design flexible, controlling high power +12V supplies requires special attention. This is due to thermal considerations that limit the integrated power device on the +12V supply to about 1.5A. To address this an external add on circuit as shown in Figure 8 enables the designer to add the OC monitoring and control of a high power +12V supply in addition to the 3 other power supplies. The HIP1011 is represented by pin names in rectangles. VSUPPLY VS This circuit primarily requires that an external P-Channel MOSFET be connected in parallel to the internal HIP1011 PMOS device and that the discrete device have a much lower rDS(ON) value than the internal PMOS device in order to carry the majority of the current load. By monitoring the voltage across the sense resistor carrying the combined load current of both the internal and external FETs and by using a comparator with a common mode input voltage range to the positive rail and a low input voltage threshold offset to reduce distribution losses, a high precision OC detector can be designed to control a much higher current load than can be tolerated by the HIP1011. RSENSE VISEN Q3 3V5VG Q1 TO FULL LOAD R1 PWRON Q2 TO SLEEP LOAD An alternative circuit for moderate current levels where both accuracy and cost are lowered can be accomplished by a single external P-Channel MOSFET in parallel with the internal P-Channel MOSFET. For example, if 2X the OC level is desired a 0.3Ω rDS(ON) P-Channel MOSFET can be used thus approximately doubling the +12 IOUT before latch-off. IOCTOTAL = IOCINTERNAL (1 + rDS(ON) of internal FET/rDS(ON) of external FET). R2 SYSTEM POWER MGT CONTROLLER 12VIN FLTN R2 FIGURE 7. SPLIT LOAD CIRCUIT 12VG Q1 12VIN R1 12VO + RSENSE R3 Q2 - TO +12V LOAD FIGURE 8. HIGH POWER +12V CIRCUIT 8 FN4640.5 November 18, 2004 HIP1011B Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INCHES INDEX AREA H 0.25(0.010) M B M SYMBOL E -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- e B 0.25(0.010) M C 0.10(0.004) C A M B S MILLIMETERS MAX MIN MAX NOTES A 0.053 0.069 1.35 1.75 - A1 0.004 0.010 0.10 0.25 - B 0.014 0.019 0.35 0.49 9 C 0.007 0.010 0.19 0.25 - D 0.386 0.394 9.80 10.00 3 E 0.150 0.157 3.80 4.00 4 e µα A1 MIN 0.050 BSC 1.27 BSC - H 0.228 0.244 5.80 6.20 - h 0.010 0.020 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α 16 0o 16 7 8o Rev. 1 02/02 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN4640.5 November 18, 2004