ISL6115, ISL6116, ISL6117, ISL6120 ® Data Sheet March 2004 FN9100.1 Power Distribution Controllers Features This family of fully featured hot swap power controllers targets applications in the +2.5V to +12V range. The ISL6115 is for +12V control, the ISL6116 for +5V, the ISL6117 for +3.3V and the ISL6120 for +2.5V control applications. Each has a hard wired undervoltage (UV) monitoring and reporting threshold level approximately 80% of the aforementioned voltage. • HOT SWAP Single Power Distribution Control (ISL6115 for +12V, ISL6116 for +5V, ISL6117 for +3.3V and ISL6120 for +2.5V) The ISL6115 has an integrated charge pump allowing control of up to +16V rails using an external N-Channel MOSFET whereas the other devices utilize the +12V bias voltage to fully enhance the N-channel pass FET. All ICs feature programmable overcurrent (OC) detection, current regulation (CR) with time delay to latch off and soft start. • Rail to Rail Common Mode Input Voltage Range (ISL6115) The current regulation level is set by 2 external resistors; RISET sets the CR Vth and the other is a low ohmic sense element across which the CR Vth is developed. The CR duration is set by an external capacitor on the CTIM pin which is charged with a 20µA current once the CR Vth level is reached. If the voltage on the CTIM cap reaches 1.9V the IC then quickly pulls down the GATE output latching off the pass FET. • Protection During Turn On This family although designed for high side switch control the ISL6116, ISL6117, ISL6120 can also be used in a low side configuration for control of much higher voltage potentials. PART NUMBER • Programmable Current Regulation Level • Programmable Current Regulation Time to Latch-Off • Internal Charge Pump Allows the use of N-Channel MOSFET for +12V control (ISL6115) • Undervoltage and Overcurrent Latch Indicators • Adjustable Turn-On Ramp • Two Levels of Overcurrent Detection Provide Fast Response to Varying Fault Conditions • 1µs Response Time to Dead Short • Pb-Free Packages Available • Tape & Reel Packing with ‘-T’ Part Number Suffix Applications • Power Distribution Control • Hot Plug Components and Circuitry Pinout Ordering Information TEMP. RANGE (°C) • Overcurrent Fault Isolation PACKAGE PKG. DWG. # ISL6115CB 0 to 85 8 Lead SOIC M8.15 ISL6116CB 0 to 85 8 Lead SOIC M8.15 ISL6117CB 0 to 85 8 Lead SOIC M8.15 ISL6120CB 0 to 85 8 Lead SOIC M8.15 ISL6115CBZA (Note) 0 to 85 8 Lead SOIC (Pb-free) M8.15 ISL6116CBZA (Note) 0 to 85 8 Lead SOIC (Pb-free) M8.15 ISL6117CBZA (Note) 0 to 85 8 Lead SOIC (Pb-free) M8.15 ISL6120CBZA 0 to 85 8 Lead SOIC (Pb-free) M8.15 ISL6115, ISL6116, ISL6117, ISL6120 (SOIC) TOP VIEW ISET 1 8 PWRON ISEN 2 7 PGOOD GATE 3 6 CTIM VSS 4 5 VDD NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6115, ISL6116, ISL6117, ISL6120 Application One - High Side Controller Application Two - Low Side Controller +VBUS LOAD + 1 8 2 7 - LOAD PWRON OC ISL6116/7/20 5 PWRON 8 7 6 5 2 1 6 +12V +V supply to be controlled 2 PGOOD 3 4 4 3 ISL6115 ISL6116 ISL6117 ISL6120 12V REG OC ISL6115, ISL6116, ISL6117, ISL6120 Simplified Block Diagram VDD + POR + QN 8V ISET R + R Q UV PWRON S + - VREF ENABLE 12V ISEN PGOOD ISL611X UV DISABLE 20µA CLIM OC GATE FALLING EDGE DELAY 10µA + - 7.5K + ENABLE VSS + 1.86V WOCLIM 18V CTIM + - - 20µA RISING EDGE PULSE 18V VDD Pin Descriptions PIN # SYMBOL FUNCTION 1 ISET Current Set Connect to the low side of the current sense resistor through the current limiting set resistor. This pin functions as the current limit programming pin. 2 ISEN Current Sense Connect to the more positive end of sense resistor to measure the voltage drop across this resistor. 3 GATE External FET Gate Drive Pin Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to VDD +5V (ISL6115) and to VDD (ISL6116, ISL6117, ISL6120) by a 10µA current source. 4 VSS Chip Return 5 VDD Chip Supply 12V chip supply. This can be either connected directly to the +12V rail supplying the switched load voltage or to a dedicated VSS +12V supply. 6 CTIM Current Limit Timing Capacitor Connect a capacitor from this pin to ground. This capacitor determines the time delay between an overcurrent event and chip output shutdown (current limit time-out). The duration of current limit time-out is equal to 93kΩ x CTIM . 7 PGOOD Power Good Indicator Indicates that the voltage on the ISEN pin is satisfactory. PGOOD is driven by an open drain N-Channel MOSFET and is pulled low when the output voltage (VISEN) is less than the UV level for the particular IC. 8 PWRON Power ON PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is driven high or is open. After a current limit time out, the chip is reset by a low level signal applied to this pin. This input has 20µA pull up capability. 3 DESCRIPTION ISL6115, ISL6116, ISL6117, ISL6120 Absolute Maximum Ratings TA = 25°C Thermal Information VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16V GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+8V ISEN, PGOOD, PWRON, CTIM, ISET. . . . . . . -0.3V to VDD + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5kV Thermal Resistance (Typical, Note 1) Operating Conditions θJA (°C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C (SOIC - Lead Tips Only) VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . +12V ±15% Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. (See Tech Brief, #TB379.1 for details.) 2. All voltages are relative to GND, unless otherwise specified. Electrical Specifications VDD = 12V, TA = TJ = 0°C to 85°C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 18.5 20 21.5 µA TJ = 15°C to 55°C 19 20 21 µA CURRENT CONTROL ISET Current Source IISET_ft ISET Current Source IISET_pt Current Limit Amp Offset Voltage Vio_ft VISET - VISEN -6 0 6 mV Current Limit Amp Offset Voltage Vio_pt VISET - VISEN, TJ = 15°C to 55°C -2 0 2 mV GATE DRIVE GATE Response Time To Severe OC pd_woc_amp VGATE to 10.8V - 100 - ns GATE Response Time to Overcurrent pd_oc_amp VGATE to 10.8V - 600 - ns IGATE VGATE to = 6V 8.4 10 11.6 µA GATE Turn-On Current GATE Pull Down Current OC_GATE_I_4V GATE Pull Down Current WOC_GATE_I_4V ISL6115 Undervoltage Threshold ISL6115 GATE High Voltage Overcurrent 45 75 Severe Overcurrent 0.5 0.8 1.5 A 9.2 9.6 10 V VDD+4.5V VDD+5V - V 12VUV_VTH 12VG GATE Voltage mA ISL6116 Undervoltage Threshold 5VUV_VTH 4.0 4.35 4.5 V ISL6117 Undervoltage Threshold 3VUV_VTH 2.4 2.6 2.8 V ISL6120 Undervoltage Threshold 2VUV_VTH 1.8 1.85 1.9 V VDD-1.5V VDD - V - 3 5 mA ISL6116, 17, 20 GATE High Voltage VG GATE Voltage BIAS VDD Supply Current IVDD VDD POR Rising Threshold VDD_POR_L2H VDD Low to High 7.8 8.4 9 V VDD POR Falling Threshold VDD_POR_H2L VDD High to Low 7.5 8.1 8.7 V VDD POR Threshold Hysteresis VDD_POR_HYS VDD_POR_L2H - VDD_POR_H2L 0.1 0.3 0.6 V PWRON Pin Open 2.7 3.2 - V PWRON Pull-Up Voltage PWRN_V PWRON Rising Threshold PWR_Vth 1.4 1.7 2.0 V PWRON Hysteresis PWR_hys 130 170 250 mV PWRON Pull-Up Current PWRN_I 9 17 25 µA 16 20 23 µA 16 20 23 mA 1.3 1.8 2.3 V CURRENT REGULATION DURATION CTIM Charging Current CTIM_ichg0 VCTIM = 0V CTIM Fault Pull-Up Current Current Limit Time-Out Threshold Voltage 4 CTIM_Vth CTIM Voltage ISL6115, ISL6116, ISL6117, ISL6120 Description and Operation The members of this family are single power supply distribution controllers for generic hot swap applications across the +2.5V to +12V supply range. The ISL6115 is targeted for +12V switching applications whereas the ISL6116 is targeted for +5V, the ISL6117 for +3.3V and the ISL6120 for +2.5V applications. Each IC has a hardwired undervoltage (UV) threshold level approximately 17% lower than the stated voltages. These ICs feature a highly accurate programmable overcurrent (OC) detecting comparator, programmable current regulation (CR) with programmable time delay to latch off, and programmable soft start turn-on ramp all set with a minimum of external passive components. The ICs also include severe OC protection that immediately shuts down the MOSFET switch should a rapid load current transient such as a near dead short cause the CR Vth to exceed the programmed level by 150mV. Additionally, the ICs have a UV indicator and an OC latch indicator. The functionality of the PGOOD feature is enabled once the IC is biased, monitoring and reporting any UV condition on the ISEN pin. Upon initial power up, the IC can either isolate the voltage supply from the load by holding the external N-Channel MOSFET switch off or apply the supply rail voltage directly to the load for true hot swap capability. The PWRON pin must be pulled low for the device to isolate the power supply from the load by holding the external N-channel MOSFET off. With the PWRON pin held high or floating the IC will be in true hot swap mode. In both cases the IC turns on in a soft start mode protecting the supply rail from sudden in-rush current. At turn-on, the external gate capacitor of the N-Channel MOSFET is charged with a 10µA current source resulting in a programmable ramp (soft start turn-on). The internal ISL6115 charge pump supplies the gate drive for the 12V supply switch driving that gate to ~VDD +5V, for the other three ICs the gate drive voltage is limited to the chip bias voltage, VDD. Load current passes through the external current sense resistor. When the voltage across the sense resistor exceeds the user programmed CR voltage threshold value, (see Table 1 for RISET programming resistor value and resulting nominal current regulation threshold voltage, VCR) the controller enters its current regulation mode. At this time, the time-out capacitor, on CTIM pin is charged with a 20µA current source and the controller enters the current limit time to latch-off period. The length of the current limit time to latch-off duration is set by the value of a single external capacitor (see Table 2 for CTIM capacitor value and resulting nominal current limited time out to latch-off duration) placed from the CTIM pin (pin 6) to ground. The programmed current level is held until either the OC event passes or the time out period expires. If the former 5 is the case then the N-Channel MOSFET is fully enhanced and the CTIM capacitor is discharged. Once CTIM charges to 1.87V, signaling that the time out period has expired an internal latch is set whereby the FET gate is quickly pulled to 0V turning off the N-Channel MOSFET switch, isolating the faulty load. TABLE 1. RISET RESISTOR NOMINAL OC VTH 10kΩ 200mV 4.99kΩ 100mV 2.5kΩ 50mV 750Ω 15mV NOTE: Nominal Vth = RISET x 20µA. TABLE 2. CTIM CAPACITOR NOMINAL CURRENT LIMITED PERIOD 0.022µF 2ms 0.047µF 4.4ms 0.1µF 9.3ms NOTE: Nominal time-out period = CTIM x 93kΩ. This IC responds to a severe overcurrent load (defined as a voltage across the sense resistor >150mV over the OC Vth set point) by immediately driving the N-Channel MOSFET gate to 0V in about 10µs. The gate voltage is then slowly ramped up turning on the N-Channel MOSFET to the programmed current regulation level; this is the start of the time out period. Upon a UV condition the PGOOD signal will pull low when tied high through a resistor to the logic or VDD supply. This pin is a UV fault indicator. For an OC latch off indication, monitor CTIM, pin 6. This pin will rise rapidly from 1.9V to VDD once the time out period expires. See Figures 12 to 16 for waveforms relevant to text. The IC is reset after an OC latch-off condition by a low level on the PWRON pin and is turned on by the PWRON pin being driven high. Application Considerations During the soft start and the time-out delay duration with the IC in its current limit mode, the VGS of the external N-Channel MOSFET is reduced driving the MOSFET switch into a (linear region) high rDS(ON) state. Strike a balance between the CR limit and the timing requirements to avoid periods when the external N-Channel MOSFETs may be damaged or destroyed due to excessive internal power dissipation. Refer to the MOSFET SOA information in the manufacturer’s data sheet. When driving particularly large capacitive loads a longer soft start time to prevent current regulation upon charging and a short CR time may offer the best application solution relative to reliability and FET MTF. Physical layout of RSENSE resistor is critical to avoid the possibility of false overcurrent occurrences. Ideally, trace routing between the RSENSE resistors and the IC is as direct ISL6115, ISL6116, ISL6117, ISL6120 and as short as possible with zero current in the sense lines. (See Figure 1.) CORRECT INCORRECT Biasing the ISL6116 Table 3 gives typical component values for biasing the ISL6116 in a ±48V application. The formulas and calculations deriving these values are also shown below. TABLE 3. TYPICAL VALUES FOR A -48V HOT SWAP APPLICATION SYMBOL TO ISEN AND RISET CURRENT SENSE RESISTOR FIGURE 1. SENSE RESISTOR PCB LAYOUT Using the ISL6116 as a -48V Low Side Hot Swap Power Controller To supply the required VDD, it is necessary to maintain the chip supply 10 to 16V above the -48V bus. This may be accomplished with a suitable regulator between the voltage rail and pin 5 (VDD). By using a regulator, the designer may ignore the bus voltage variations. However, a low-cost alternative is to use a Zener diode (See Figure 2 for typical 5A load control); this option is detailed below. Note that in this configuration the PGOOD feature (pin 7) is not operational as the ISEN pin voltage is always < UV threshold. See Figures 17 to 20 for waveforms relevant to -48V and other high voltage applications. 0.005 1% LOAD 0.001µF 1.47kΩ 1% 2kΩ 1 2 3 4 RCL 1.58kΩ 1W ISL6116 8 7 6 5 NC 0.047µF 12V PWRON VBUS -48V FIGURE 2. 6 RCL 1.58kΩ, 1W DD1 12V Zener Diode, 50mA Reverse Current When using the ISL6116 to control -48V, a Zener diode may be used to provide the +12V bias to the chip. If a Zener is used then a current limit resistor should also be used. Several items must be taken into account when choosing values for the current limit resistor (RCL) and Zener Diode (DD1): • The variation of the VBUS (in this case, -48V nominal) • The chip supply current needs for all functional conditions • The power rating of RCL. • The current rating of DD1 Formulas 1. Sizing RCL: RCL = (VBUS,MIN - 12)/ICHIP 2. Power Rating of RCL: PRCL = IC(VBUS,MAX - 12) 3. DD1 Current Rating: IDD1 = (VBUS,MAX - 12)/RCL Example A typical -48V supply may vary from -36 to -72V. Therefore, VBUS,MAX = -72V VBUS,MIN = -36V ICHIP = 15mA (max) Sizing RCL: RCL = (VBUS,MIN - 12)/IC RCL = (36 - 12)/0.015 RCL = 1.6kΩ [Typical Value = 1.58kΩ] Power Rating of RCL: PRCL = IC(VBUS,MAX - 12) PRCL = (0.015)(72 - 12) PRCL = 0.9W [Typical Value = 1W] 0.01µF DD1 PARAMETER DD1 Current Rating: IDD1 = (VBUS,MAX - 12)/RCL IDD1 = (72 - 12)/1.58kΩ IDD1 = 38mA [Typical Value = 12V rating, 50mA reverse current] ISL6115, ISL6116, ISL6117, ISL6120 5.0 20.2 4.5 20.0 ISET CURRENT µA) 4.0 3.5 3.0 19.8 19.6 19.4 19.2 2.5 19.0 0 2.0 0 20 10 30 50 40 60 70 80 90 100 10 20 30 TEMPERATURE (°C) CTIM OC VOLTAGE THRESHOLD (V) CTIM = 0V, CURRENT SOURCE (µA) 20.32 70 80 90 100 CTIM - 0V 20.16 20.0 19.82 19.66 90 100 1.88 1.87 1.86 1.85 1.84 1.83 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 FIGURE 5. CTIM CURRENT SOURCE 9.76 9.75 4.36 9.74 40 50 60 70 80 90 TEMPERATURE (°C) FIGURE 7. ISL6115/6116 UV THRESHOLD 7 4.35 100 ISL6117 3.3V UV THRESHOLD (V) ISL6115 30 60 70 80 2.70 ISL6116, 5V UV THRESHOLD (V) ISL6116 20 50 FIGURE 6. CTIM OC VOLTAGE THRESHOLD 4.37 10 40 TEMPERATURE (°C) TEMPERATURE (°C) ISL6115, 12V UV THRESHOLD (V) 60 1.89 20.5 0 50 FIGURE 4. ISET SOURCE CURRENT FIGURE 3. VDD BIAS CURRENT 19.5 40 TEMPERATURE (°C) 1.860 ISL6117 2.65 1.855 ISL6120 2.60 0 10 20 30 40 50 60 70 80 90 1.850 100 TEMPERATURE (°C) FIGURE 8. ISL6117/6120 UV THRESHOLD ISL6120, 2.5V UV THRESHOLD (V) SUPPLY CURRENT (mA) Typical Performance Curves ISL6115, ISL6116, ISL6117, ISL6120 10.2 17.200 12.00 10.1 17.183 11.99 17.166 11.98 17.150 11.97 17.133 11.96 17.116 11.95 10.0 9.9 9.8 9.7 17.100 9.6 0 10 20 30 40 50 60 70 80 90 100 0 10 TEMPERATURE (°C) 20 30 40 50 60 70 80 90 11.94 100 TEMPERATURE (°C) FIGURE 9. GATE CHARGE CURRENT FIGURE 10. GATE DRIVE VOLTAGE, VDD = 12V POWER ON RESET (V) 8.5 VDD LO TO HI 8.4 GATE 8.3 VOUT 8.2 PGOOD VDD HI TO LO 8.1 IOUT PWRON 8.0 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) 5V/DIV. 0.5A/DIV 1ms/DIV FIGURE 11. POWER ON RESET VOLTAGE THRESHOLD FIGURE 12. ISL6115 +12V TURN-ON GATE PGOOD GATE IOUT PWRON VOUT VOUT IOUT PGOOD CTIM 2V/DIV 0.5A/DIV 1ms/DIV 5V/DIV 0.5A/DIV 1ms/DIV FIGURE 13. ISL6116 +5V TURN-ON FIGURE 14. ISL6115 ‘LOW’ OVERCURRENT RESPONSE 8 ISL6116,17,20 GATE DRIVE (V) (Continued) ISL6115, GATE DRIVE (V) GATE CHARGE CURRENT (µA) Typical Performance Curves ISL6115, ISL6116, ISL6117, ISL6120 Typical Performance Curves (Continued) IOUT IOUT VOUT GATE PGOOD CTIM VOUT GATE CTIM PGOOD 5V/DIV 0.5A/DIV 1ms/DIV 2V/DIV 0.5A/DIV 1ms/DIV FIGURE 15. ISL6115 ‘HIGH’ OVERCURRENT RESPONSE VDRAIN 10V/DIV. FIGURE 16. ISL6116 ‘HIGH’ OVERCURRENT RESPONSE VDRAIN 10V/DIV. IOUT 1A/DIV. IOUT 1A/DIV. 0V +50V VGATE 5V/DIV. VGATE 5V/DIV. PWRON 5V/DIV. EN 5V/DIV. 0V 0V -50V 0V 5ms/DIV 5ms/DIV FIGURE 17. +50V LOW SIDE SWITCHING CGATE = 100pF FIGURE 18. -50V LOW SIDE SWITCHING CGATE = 1000pF +350V +350V IOUT 1A/DIV VDRAIN 50V/DIV IOUT 1A/DIV VDRAIN 50V/DIV VGATE 5V/DIV VGATE 5V/DIV. PWRON 5V/DIV PWRON 5V/DIV 0V 0V 2ms/DIV FIGURE 19. +350V LOW SIDE SWITCHING CGATE = 100pF 9 2ms/DIV FIGURE 20. +350V LOW SIDE SWITCHING CGATE = 1000pF ISL6115, ISL6116, ISL6117, ISL6120 ISL6115EVAL1 Board The ISL6115EVAL1 is configured as a +12V high side switch controller with the CR level set at ~1.5A. (See Figure 21 for ISL6115EVAL1 schematic and Table 4. for BOM.) Bias and load connection points are provided along with test points for each IC pin. With the chip to be biased from the +12V bus being switched, through B2, GND B5, the load connected between B3 and B4 and with jumper J1 installed the ISL6115 can be evaluated. PWRON pin pulls high enabling the ISL6115 if not driven low. With R2 = 750Ω the CR Vth is set to 15mV and with the 10mΩ sense resistor the ISL6115EVAL1 has a nominal CR level of 1.5A. The 0.047µF delay time to latch-off capacitors results in a nominal 4.4ms before latch-off of outputs after an OC event. Also included with the ISL6115EVAL1 board are one each of the ISL6116, ISL6117 and ISL6120 for evaluation. ISL6116EVAL1 Board The ISL6116EVAL1 is default configured as a negative voltage low side switch controller with a ~2.4A CR level. (See Figure 22 for ISL6116EVAL1 schematic and Table 4 for BOM and component description.) This basic configuration is capable of controlling both larger positive or negative potential voltages with minimal changes. Bias and load connection points are provided in addition to test points, TP1-8 for each IC pin. The terminals, J1 and J4 are for the bus voltage and return, respectively, with the more negative potential being connected to J4. With the load between terminals J2 and J3 the board is now configured for evaluation. The device is enabled through LOGIN, TP9 with a TTL signal. ISL6116EVAL1 includes a level shifting circuit with an opto-coupling device for the PWRON input so that standard TTL logic can be translated to the -V reference for chip control. When controlling a positive voltage, PWRON can be accessed at TP8. The ISL6116EVAL1 is provided with a high voltage linear regulator for convenience to provide chip bias from ±24V to ±350V. This can be removed and replaced with the zener & resistor bias scheme as discussed earlier. High voltage regulators and power discrete devices are no longer available from Intersil but can be purchased from other semiconductor manufacturers. Reconfiguring the ISL6116EVAL1 board for a higher CR level can be done by changing the RSENSE and RISET resistor values as the provided FET is 75A rated. If evaluation at >60V, an alternate FET must be chosen with an adequate BVDSS. HI J2 LOAD J3 LO R1 Q2 + LOAD B3 B4 J1 +VBUS - J4 -VBUS C1 R2 R7 1 2 3 4 R2 1 R1 2 3 8 ISL6115 7 U1 6 C2 D2 R4 C3 R G 1 8 DD1 3.3V 7 D1 6 R3 C3 R5 5 ISL6116 U1 5 4 Q1 PWRON TP8 PWRON LOGIN TP9 B5 JP1 V+ B2 +12V VBIAS R11 B1 R10 R8 R6 C1 D2 DD1 3.3V R5 R9 OFF 0-5V OT1 FIGURE 21. ISL6115EVAL1 HIGH SIDE SWITCH APPLICATION 10 ON FIGURE 22. ISL6116EVAL1 NEGATIVE VOLTAGE LOW SIDE CONTROLLER ISL6115, ISL6116, ISL6117, ISL6120 TABLE 4. BILL OF MATERIALS, ISL6115EVAL1, ISL6116EVAL1 COMPONENT DESIGNATOR COMPONENT NAME COMPONENT DESCRIPTION Q1 HUF76132SK8 11.5mΩ, 30V, 11.5A Logic Level N-Channel Power MOSFET or equiv. Q2 HUF7554S3S 10mΩ, 80V, 75A N-Channel Power MOSFET or equiv. R1 Load Current Sense Resistor Dale, WSL-2512 10mΩ 1W Metal Strip Resistor High Side R2 Overcurrent Voltage Threshold Set Resistor 750Ω 805 Chip Resistor (Vth = 15mV) Low side R2 Overcurrent Voltage Threshold Set Resistor 1.21kΩ 805 Chip Resistor (Vth = 24mV) C2 Time Delay Set Capacitor 0.047µF 805 Chip Capacitor (4.5ms) C1 Gate Timing Capacitor 0.001µF 805 Chip Capacitor (<2ms) C3 IC Decoupling Capacitor 0.1µF 805 Chip Capacitor R3 Gate Stability Resistor 20Ω 805 Chip Resistor R7 Gate to Drain Resistor 2kΩ 805 Chip Resistor JP1 Bias Voltage Selection Jumper Install if switched rail voltage is = +12V ±15%. Remove and provide separate +12V bias voltage to U1 via TP5 if ISL6116, ISL6117, ISL6120 being evaluated. R4, R5 LED Series Resistors 2.32kΩ 805 Chip Resistor D1, D2 Fault Indicating LEDs Low Current Red SMD LED DD1 Fault Voltage Dropping Diode 3.3V Zener Diode, SOT-23 SMD 350mW OT1 PWRON Level Shifting Opto-Coupler PS2801-1 NEC R8 Level Shifting Bias Resistor 2.32kΩ 805 Chip Resistor R9 Level Shifting Bias Resistor 1.18kΩ 805 Chip Resistor R10 Level Shifting Bias Resistor 200Ω 805 Chip Resistor RG1 HIP5600IS High Voltage Linear Regulator R6 Linear Regulator RF1 1.78kΩ 805 Chip Resistor R11 Linear Regulator RF2 15kΩ 805 Chip Resistor TP1-TP8 Test Points for Device Pin Numbers 1-8 11 ISL6115, ISL6116, ISL6117, ISL6120 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N INDEX AREA 0.25(0.010) M H 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- µα e A1 B 0.25(0.010) M C C A M B S 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. MILLIMETERS MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N NOTES: MAX A1 e 0.10(0.004) MIN α 8 0o 8 7 8o Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12