NS ESIG D EW t RN O F ter a n D e E C ND 175 ort tsc MME ee HI1 l Supp il.com/ O C S a s r ic RE c hn . i nt e N OT r Te r w w w u o o ct R S IL onta or c 8-INTE 1-88 HI-5700 ® May 1997 Features 8-Bit, 20 MSPS Flash A/D Converter Description • 20 MSPS with No Missing Codes The HI-5700 is a monolithic, 8-bit, CMOS Flash Analog-toDigital Converter. It is designed for high speed applications where wide bandwidth and low power consumption are essential. Its 20 MSPS speed is made possible by a parallel architecture which also eliminates the need for an external sample and hold circuit. The HI-5700 delivers ±0.5 LSB differential nonlinearity while consuming only 725mW (typical) at 20 MSPS. Microprocessor compatible data output latches are provided which present valid data to the output bus 1.5 clock cycles after the convert command is received. An overflow bit is provided to allow the series connection of two converters to achieve 9-bit resolution. • 18MHz Full Power Input Bandwidth • No Missing Codes Over Temperature • Sample and Hold Not Required • Single +5V Supply Voltage • CMOS/TTL • Overflow Bit • Improved Replacement for MP7684 • Evaluation Board Available • /883 Version Available Ordering Information Applications PART NUMBER • Video Digitizing TEMPERATURE RANGE HI3-5700J-5 • Medical Imaging HI9P5700J-5 o 0 C to +70 C • Communication Systems HI3-5700A-9 -40oC to +85oC 28 Lead Plastic DIP • High Speed Data Acquisition Systems HI9P5700A -9 -40oC to +85oC 28 Lead Plastic SOIC (W) • Radar Systems to +70oC PACKAGE 0oC o 28 Lead Plastic DIP 28 Lead Plastic SOIC (W) Pinout HI-5700 (PDIP, SOIC) TOP VIEW CLK 1 28 VIN (MSB) D7 2 27 VREF - D6 3 26 AVDD D5 4 25 AGND D4 5 24 AGND /4R 6 23 AVDD 1 VDD 7 GND 8 3 /4R 22 1 /2R 21 AVDD 9 20 AGND D3 10 19 AGND D2 11 18 AVDD (LSB) D1 12 17 VREF + D0 13 16 CE1 OVF 14 15 CE2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved File Number 3174.4 HI-5700 Functional Block Diagram ýφ1 ý φ2 φý1 ýφ1 ýφ2 VIN 28 VREF + 17 R/2 R COMP 256 D Q CL 14 OVERFLOW (OVF) D Q CL 2 D7 (MSB) 3 D6 D Q CL 4 D5 D Q CL 5 D4 D Q CL 10 D3 D Q CL 11 D2 D Q CL 12 D1 D Q CL 13 R 3 /4R 9 D Q CL R COMP 193 R 1 /2R 22 R COMP 129 COMPARATOR LATCHES AND ENCODER LOGIC R 1 /4R 6 R COMP 65 R R VREF - 27 COMP 2 R/2 D0 (LSB) COMP 1 16 CE1 15 CE2 φý1 VDD 7 CLK 1 GND φý2 4-1492 8 AVDD 23 21 26 18 24 25 19 20 AGND Specifications HI-5700 Absolute Maximum Ratings Thermal Information Supply Voltage, V DD to GND . . . . . . . . . (GND - 0.5) < VDD < +7.0V Analog and Reference Input Pins . . . .(VSS - 0.5) < VINA < (VDD +0.5V) Digital I/O Pins . . . . . . . . . . . . . . . (GND - 0.5) < VI/O < (VDD +0.5V) Storage Temperature Range . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Thermal Resistance θJA HI3-5700J-5, HI3-5700A-9 . . . . . . . . . . . . . . . . . . . . . 55oC/W HI9P5700J-5, HI9P5700A-9 . . . . . . . . . . . . . . . . . . . . 75oC/W Maximum Power Dissipation +70oC . . . . . . . . . . . . . . . . . . . . 1.05W Operating Temperature Range HI3-5700J-5, HI9P5700J-5 . . . . . . . . . . . . . . . . . . . 0oC to +70oC HI3-5700A-9, HI9P5700A-9 . . . . . . . . . . . . . . . -40oC to +85oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC CAUTION: Stresses above those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Electrical Specifications AVDD = VDD = +5.0V; VREF+ = +4.0V; VREF- = GND = AGND = 0V; FS = Specified Clock Frequency at 50% Duty Cycle; C L = 30pF; Unless Otherwise Specified (NOTE 2) 0o C TO +70oC -40oC TO +85oC +25oC PARAMETER TEST CONDITION MIN TYP MAX MIN MAX UNITS 8 - - 8 - Bits SYSTEM PERFORMANCE Resolution Integral Linearity Error (INL) (Best Fit Method) FS = 15MHz, fIN = DC FS = 20MHz, fIN = DC - ±0.9 ±1.0 ±2.0 ±2.25 - ±2.25 ±3.25 LSB LSB Differential Linearity Error (DNL) (Guaranteed No Missing Codes) FS = 15MHz, fIN = DC FS = 20MHz, fIN = DC - ±0.4 ±0.5 ±0.9 ±0.9 - ±1.0 ±1.0 LSB LSB Offset Error (VOS) FS = 15MHz, fIN = DC FS = 20MHz, fIN = DC - ±5.0 ±5.0 ±8.0 ±8.0 - ±9.5 ±9.5 LSB LSB Full Scale Error (FSE) FS = 15MHz, fIN = DC FS = 20MHz, fIN = DC - ±0.5 ±0.6 ±4.5 ±4.5 - ±8.0 ±8.0 LSB LSB 20 25 - 20 - MSPS DYNAMIC CHARACTERISTICS Maximum Conversion Rate No Missing Codes Minimum Conversion Rate No Missing Codes (Note 2) - - 0.125 - 0.125 MSPS Full Power Input Bandwidth FS = 20MHz - 18 - - - MHz Signal to Noise Ratio (SNR) FS = 15MHz, fIN FS = 15MHz, fIN FS = 15MHz, fIN FS = 20MHz, fIN FS = 20MHz, fIN FS = 20MHz, fIN = 100kHz = 3.58MHz = 4.43MHz = 100kHz = 3.58MHz = 4.43MHz - 46.5 44.0 43.4 45.9 42.0 41.6 - - - dB dB dB dB dB dB FS = 15MHz, fIN FS = 15MHz, fIN FS = 15MHz, fIN FS = 20MHz, fIN FS = 20MHz, fIN FS = 20MHz, fIN = 100kHz = 3.58MHz = 4.43MHz = 100kHz = 3.58MHz = 4.43MHz - 43.4 34.3 32.3 42.3 35.2 32.8 - - - dB dB dB dB dB dB Total Harmonic Distortion (THD) FS = 15MHz, fIN FS = 15MHz, fIN FS = 15MHz, fIN FS = 20MHz, fIN FS = 20MHz, fIN FS = 20MHz, fIN = 100kHz = 3.58MHz = 4.43MHz = 100kHz = 3.58MHz = 4.43MHz - -46.9 -34.8 -32.8 -46.6 -36.6 -33.5 - - - dBc dBc dBc dBc dBc dBc Differential Gain FS = 14MHz, fIN = 3.58MHz - 3.5 - - - % Differential Phase Error FS = 14MHz, fIN = 3.58MHz - 0.9 - - - Degree RM S Signal = --------------------------------RMS Noise Signal to Noise and Distortion Ratio (SINAD) RM S Signal = -------------------------------------------------------------RMS Noise + Distortion 4-1493 Specifications HI-5700 Electrical Specifications AVDD = VDD = +5.0V; VREF+ = +4.0V; VREF- = GND = AGND = 0V; FS = Specified Clock Frequency at 50% Duty Cycle; C L = 30pF; Unless Otherwise Specified (Continued) (NOTE 2) 0o C TO +70oC -40oC TO +85oC +25oC PARAMETER TEST CONDITION MIN TYP MAX MIN MAX UNITS 4 - 10 60 ±0.01 ±1.0 - ±1.0 MΩ pF µA 250 330 - 235 - Ω - +0.31 - - - Ω/°C 2.0 - 7 0.8 1.0 1.0 - 2.0 - 0.8 1.0 1.0 - V V µA µA pF 3.2 - 5.0 ±1.0 - - ±1.0 - mA mA µA pF 10 6 30 18 15 20 20 25 20 25 - 5 30 25 30 - ns ps ns ns ns ns VDD = 5V ±10% VDD = 5V ±10% - ±0.1 ±0.1 ±2.75 ±2.75 - ±5.0 ±5.0 LSB LSB FS = 20MHz - 145 180 - 190 mA ANALOG INPUTS Analog Input Resistance, RIN Analog Input Capacitance, CIN Analog Input Bias Current, IB VIN = 4V VIN = 0V VIN = 0V, 4V REFERENCE INPUTS Total Reference Resistance, RL Reference Resistance Tempco, TC DIGITAL INPUTS Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic High Current, IIH Input Logic Low Current, IIL Input Capacitance, CIN VIN = 5V VIN = 0V DIGITAL OUTPUTS Output Logic Sink Current, IOL Output Logic Source Current, IOH Output Leakage, IOZ Output Capacitance, COUT VO = 0.4V VO = 4.5V CE2 = 0V, VO = 0V, 5V CE2 = 0V -3.2 3.2 -3.2 TIMING CHARACTERISTICS Aperture Delay, tAP Aperture Jitter, tAJ Data Output Enable Time, tEN Data Output Disable Time, tDIS Data Output Delay, tOD Data Output Hold, tH POWER SUPPLY REJECTION Offset Error PSRR, ∆VOS Gain Error PSRR, ∆FSE POWER SUPPLY CURRENT Supply Current, IDD NOTES: 9. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 10. Parameter guaranteed by design or characterization and not production tested. 4-1494 HI-5700 Timing Waveforms COMPARATOR DATA IS LATCHED CLOCK INPUT SAMPLE N- 2 AUTO BALANCE tAB SAMPLE N-1 AUTO BALANCE ANALOG INPUT SAMPLE N AUTO BALANCE SAMPLE N+ 1 AUTO BALANCE ENCODER DATA IS LATCHED INTO THE OUTPUT REGISTERS SAMPLE N+2 tAP tH tAJ tOD DATA OUTPUT DATA N-4 DATA N-3 DATA N-2 FIGURE 1. INPUT-TO-OUTPUT TIMING CE1 CE2 tEN tDIS D0 - D7 OVF DATA HIGH IMPEDANCE DATA tDIS DATA tEN HIGH IMPEDANCE HIGH IMPEDANCE DATA DATA FIGURE 2. OUTPUT ENABLE TIMING 4-1495 DATA N-1 DATA N HI-5700 Typical Performance Curves 8 8 VDD = 5V, VREF + = 4V VDD = 5V, VREF+ = 4V TA = 25o C 7 6 EFFECTIVE BITS EFFECTIVE BITS 7 FS = 15MHz FS = 20MHz FS = 20MHz, fIN = 100kHz 6 FS = 20MHz, fIN = 3.85MHz FS = 15MHz, fIN = 3.85MHz 5 5 4 4 0 0.5 1 1.5 2 2.5 3 3.5 INPUT FREQUENCY - fIN (MHz) 4 4.5 50 48 -60 5 -20 0 A. -32 B. 42 +80 +100 +120 +140 B. VDD = 5V, VREF+ = 4V D. -36 A. F S = 15MHz, fIN = B. F S = 15MHz, fIN = C. F S = 20MHz, fIN = D. F S = 20MHz, fIN = -38 40 FS = 15MHz, FS = 15MHz, FS = 20MHz, FS = 20MHz, C. fIN = 100kHz fIN = 4.43MHz fIN = 100kHz fIN = 4.43MHz dBc 38 A. 36 B. C. 34 D. 32 -20 0 +20 C. +40 +60 A. -46 D. -40 100kHz 4.43MHz 100kHz 4.43MHz -44 -48 28 26 -60 -40 -42 30 -50 -60 +80 +100 +120 +140 -40 -20 0 +20 +40 +60 +80 +100 +120 +140 TEMPERATURE (oC) o TEMPERATURE ( C) FIGURE 5. SNR vs TEMPERATURE FIGURE 6. TOTAL HARMONIC DISTORTION vs TEMPERATURE 1.0 VDD = 5V, VREF+ = 4V fIN = 100kHz VDD = 5V, VREF + = 4V fIN = 100kHz 0.75 3.0 FS = 20MHz 2.5 FS = 20MHz LSB LSB +60 -34 44 3.5 +40 FIGURE 4. EFFECTIVE NUMBER OF BITS vs TEMPERATURE 46 4.0 +20 TEMPERATURE ( C) -30 VDD = 5V, VREF+ = 4V -40 o FIGURE 3. EFFECTIVE NUMBER OF BITS vs fIN dB FS = 15MHz, fIN = 100kHz 2.0 0.5 FS = 15MHz 1.5 FS = 15MHz 1.0 0.25 0.5 0 -60 -40 -20 0 +20 +40 +60 +80 +100 +120 +140 o 0 -60 -40 -20 0 +20 +40 +60 +80 +100 +120 +140 o TEMPERATURE ( C) TEMPERATURE ( C) FIGURE 7. INL vs TEMPERATURE FIGURE 8. DNL vs TEMPERATURE 4-1496 HI-5700 Typical Performance Curves (Continued) 8 2.0 VDD = 5V, VREF+ = 4V VDD = 5V, VREF + = 4V 7 FS = 20MHz 1.5 FS = 15MHz LSB LSB 6 5 1.0 FS = 20MHz 4 0.5 FS = 15MHz 3 2 -60 -40 -20 0 +20 +40 +60 0 -60 +80 +100 +120 +140 -40 -20 0 TEMPERATURE (o C) FIGURE 9. OFFSET VOLTAGE vs TEMPERATURE 35 +20 +40 +60 FIGURE 10. FULL SCALE ERROR vs TEMPERATURE 1.0 VDD = 5V, VREF + = 4V VDD = 5V, VREF + = 4V 30 0.5 CLOAD = 30pF PSRR VOS tOD LSB 25 ns tHOLD 0 PSRR FSE 20 -0.5 15 10 -60 -40 -20 0 +20 +40 +60 -1.0 -60 +80 +100 +120 +140 TEMPERATURE (oC) 200 190 180 170 160 mA FS = 20MHz 140 130 120 110 FS = 1MHz 100 90 80 -60 -40 -20 0 +20 +40 +60 -20 0 +20 +40 +60 +80 +100 +120 +140 FIGURE 12. POWER SUPPLY REJECTION vs TEMPERATURE VDD = 5V, VREF + = 4V 150 -40 TEMPERATURE (oC) FIGURE 11. OUTPUT DELAY vs TEMPERATURE mA +80 +100 +120 +140 TEMPERATURE (o C) +80 +100 +120 +140 TEMPERATURE (o C) 180 170 VDD = 5V, VREF + = 4V 160 TA = 25o C 150 140 130 tAB 120 D= 110 tAB + tS 100 90 80 70 60 50 40 30 0.1 1 D = 50% D = 25% D = 10% 10 100 CLOCK FREQUENCY (MHz) FIGURE 13. SUPPLY CURRENT vs TEMPERATURE FIGURE 14. SUPPLY CURRENT vs CLOCK DUTY CYCLE 4-1497 HI-5700 TABLE 1. PIN DESCRIPTION PIN # NAME output word, plus an additional comparator to detect an overflow condition. DESCRIPTION 1 CLK 2 D7 Bit 7, Output (MSB) 3 D6 Bit 6, Output 4 D5 Bit 5, Output 5 D4 Bit 4, Output 6 1/ 1/ 7 V DD Digital Power Supply 8 GND Digital Ground 9 3 3 The CMOS HI-5700 works by alternately switching between a “Sample” mode and an “Auto Balance” mode. Splitting up the comparison process in this CMOS technique offers a number of significant advantages. The offset voltage of each CMOS comparator is dynamically canceled with each conversion cycle such that offset voltage drift is virtually eliminated during operation. The block diagram and timing diagram illustrate how the HI-5700 CMOS flash converter operates. Clock Input 4R /4R 4th Point of Reference Ladder The input clock which controls the operation of the HI-5700 is first split into a non-inverting φ1 clock and an inverting φ2 clock. These two clocks, in turn, synchronize all internal timing of analog switches and control logic within the converter. /4th Point of Reference Ladder 10 D3 Bit 3, Output 11 D2 Bit 2, Output 12 D1 Bit 1, Output 13 D0 Bit 0, Output (LSB) 14 OVF Overflow, Output 15 CE2 Three-State Output Enable Input, Active High. (See Table 2) 16 CE1 Three-State Output Enable Input, Active Low. (See Table 2) 17 V REF + Reference Voltage Positive Input 18 AV DD Analog Power Supply, +5V 19 AGND Analog Ground 20 AGND Analog Ground 21 AV DD Analog Power Supply, +5V 22 1/ 1/ 23 AV DD Analog Power Supply, +5V 24 AGND Analog Ground 25 AGND Analog Ground 26 AV DD Analog Power Supply, +5V 27 V REF - Reference Voltage Negative Input 28 V IN Analog Input 2R 2 In the “Sample” mode (φ2), all φ1 switches open and φ2 switches close. This places each comparator in a sensitive high gain amplifier configuration. In this open loop state, the input impedance is very high and any small voltage shift at the input will drive the output either high or low. The φ2 state also switches each input capacitor from its reference tap to the input signal. This instantly transfers any voltage difference between the reference tap and input voltage to the comparator input. All 256 comparators are thus driven simultaneously to a defined logic state. For example, if the input voltage is at mid-scale, capacitors precharged near zero during φ1 will push comparator inputs higher than the self bias voltage at φ2; capacitors precharged near the reference voltage push the respective comparator inputs lower than the bias point. In general, all capacitors precharged by taps above the input voltage force a “low” voltage at comparator inputs; those precharged below the input voltage force “high” inputs at the comparators. Point of Reference Ladder TABLE 2. CHIP ENABLE TRUTH TABLE D0 - D7 CE1 CE2 0 1 Valid Valid 1 1 Three-State Valid X 0 Three-State Three-State In the “Auto Balance” mode (φ1), all φ1 switches close and φ2 switches open. The output of each comparator is momentarily tied to its own input, self-biasing the comparator midway between GND and VDD and presenting a low impedance to a small input capacitor. Each capacitor, in turn, is connected to a reference voltage tap from the resistor ladder. The Auto Balance mode quickly precharges all 256 input capacitors between the self-bias voltage and each respective tap voltage. OVF X’s = Don’t Care. Theory of Operation The HI-5700 is an 8-bit analog-to-digital converter based on a parallel CMOS “flash” architecture. This flash technique is an extremely fast method of A/D conversion because all bit decisions are made simultaneously. In all, 256 comparators are used in the HI-5700: (28-1) comparators to encode the During the next φ1 Auto-Balancing state, comparator output data is latched into the encoder logic block and the first stage of encoding takes place. The following φ2 state completes the encoding process. The 8 data bits (plus overflow bit) are latched into the output flip-flops at the next falling clock edge. The Overflow bit is set if the input voltage exceeds VREF + - 0.5 LSB. The output bus may be either enabled or disabled according to the state of CE1 and CE2 (See Table 2). When disabled, output bits assume a high impedance state. As shown in the timing diagram, the digital output word becomes valid after the second φ1 state. There is thus a one and a half cycle pipeline delay between input sample and digital output. “Data Output Delay” time indicates the slight time delay for data to become valid at the end of the φ1 4-1498 HI-5700 HA-5033 +9V TO +12V 100Ω 0.01µF 10µF 0.01µF 10µF 0.01µF 10µF 0.01µF 10µF CLOCK INPUT VIN 28 1 CLK 50 Ω OUTPUT PINS DIGITAL VDD TO ANALOG +5V 10µF 2 D7 VREF - 27 3 D6 AVDD 26 4 D5 AGND 25 5 D4 AGND 24 6 1/4R 0.01µF TO ANALOG GND DIGITAL GROUND OUTPUT PINS ANALOG SIGNAL INPUT +9V TO +12V AVDD 23 1 7 VDD /2R 22 8 GND 9 3/4R AGND 20 10 D3 AGND 19 11 D2 AVDD 18 12 D1 VREF + 17 13 D0 CE1 16 14 OVF CE2 15 ANALOG VDD (+5V) ANALOG GROUND AVDD 21 0.01µF 10µF PRECISION DC REFERENCE +5V FIGURE 15. TEST CIRCUIT Applications Information Voltage Reference Digital Control and Interface The reference voltage is applied across the resistor ladder between VREF + and V REF -. In most applications, V REF - is simply tied to analog ground such that the reference source drives VREF +. The reference must be capable of supplying enough current to drive the minimum ladder resistance of 235Ω over temperature. The HI-5700 provides a standard high speed interface to external CMOS and TTL logic families. Two chip enable inputs control the three-state outputs of output bits D0 through D7 and the Overflow (OVF) bit. As indicated in the Truth Table, all output bits are high impedance when CE2 is low, and output bits D0 through D7 are independently controlled by CE1. The HI-5700 is specified for a reference voltage of 4.0V, but will operate with voltages as high as the VDD supply. In the case of 4.0V reference operation, the converter encodes the analog input into a binary output in LSB increments of (VREF + - VREF -)/256, or 15.6mV. Reducing the reference voltage reduces the LSB size proportionately and thus increases linearity errors. The minimum practical reference voltage is about 2.5V. Because the reference voltage terminals are subjected to internal transient currents during conversion, it is important to drive the reference pins from a low impedance source and to decouple thoroughly. Again, ceramic and tantalum (0.01µF and 10µF) capacitors near the package pin are recommended. It is not necessary to decouple the 1/4R, 1/2R, and 3/4R tap point pins for most applications. It is possible to elevate VREF - from ground if necessary. In this case, the VREF - pin must be driven from a low impedance reference capable of sinking the current through the resistor ladder. Careful decoupling is again recommended. Although the Digital Outputs are capable of handling typical data bus loading, the bus capacitance charge/discharge currents will produce supply and local group disturbances. Therefore, an external bus driver is recommended. Clock The clock should be properly terminated to digital ground near the clock input pin. Clock frequency defines the conversion frequency and controls the converter as described in the “Theory of Operation” section. The Auto Balance φ1 half cycle of the clock may be reduced to approximately 20ns; the Sample φ2 half cycle may be varied from a minimum of 25ns to a maximum of 5µs. Signal Source A current pulse is present at the analog input (VIN) at the beginning of every sample and auto balance period. The transient current is due to comparator charging and switch feedthrough in the capacitor array. It varies with the amplitude of the analog input and the converter’s sampling 4-1499 HI-5700 rate. reference voltage is the ideal location. The signal source must absorb these transients prior to the end of the sample period to ensure a valid signal for conversion. Suitable broad band amplifiers or buffers which exhibit low output impedance and high output drive include the HA-5004, HA-5002, and HA-5003. Quarter Point Adjustment The signal source may drive above or below the power supply rails, but should not exceed 0.5V beyond the rails or damage may occur. Input voltages of -0.5V to +0.5 LSB are converted to all zeroes; input voltages of VREF+ -0.5 LSB to VDD +0.5V are converted to all ones with the Overflow bit set. Full Scale Offset Error Adjustment In applications where accuracy is of utmost importance, three adjustments can be made; i.e., offset, gain, and reference tap point trims. In general, offset and gain correction can be done in the preamp circuitry. Offset Adjustment Offset correction can be done in the preamp driving the converter by introducing a DC component to the input signal. An alternate method is to adjust VREF- to produce the desired offset. It is adjusted such that the 0 to 1 code transition occurs at 0.5 LSB. Gain Adjustment In general, full scale error correction can be done in the preamp circuitry by adjusting the gain of the op amp. An alternate method is to adjust the VREF+ voltage. The The reference tap points are brought out for linearity adjustment or creating a nonlinear transfer function if desired. It is not necessary to decouple the 1/4R, 1/2R, and 3/ 4R tap points in most applications. Power Supplies The HI-5700 operates nominally from 5V supplies but will work from 3V to 6V. Power to the device is split such that analog and digital circuits within the HI-5700 are powered separately. The analog supply should be well regulated and “clean” from significant noise, especially high frequency noise. The digital supply should match the analog supply within about 0.5V and should be referenced externally to the analog supply at a single point. Analog and digital grounds should not be separated by more that 0.5V. It is recommended that power supply decoupling capacitors be placed as close to the supply pins as possible. A combination of 0.01µF ceramic and 10µF tantalum capacitors is recommended for this purpose as shown in the test circuit. Reducing Power Consumption Power dissipation in the HI-5700 is related to clock frequency and clock duty cycle. For a fixed 50% clock duty cycle, power may be reduced by lowering the clock frequency. For a given conversion frequency, power may be reduced by decreasing the Auto-Balance (φ1) portion of the clock duty cycle. This relationship is illustrated in the TABLE 3. CODE TABLE BINARY OUTPUT CODE INPUT VOLTAGE † VREF + = 4.0V VREF - = 0.0V (V) DECIMAL COUNT OVF D7 D6 D5 D4 D3 D2 D1 D0 Overflow (OVF) 4.000 511 1 1 1 1 1 1 1 1 1 Full Scale (FS) 3.9766 255 0 1 1 1 1 1 1 1 1 FS - 1 LSB 3.961 254 0 1 1 1 1 1 1 1 0 3/4 FS 2.992 192 0 1 1 0 0 0 0 0 0 1/2 FS 1.992 128 0 1 0 0 0 0 0 0 0 1/4 FS 0.992 64 0 0 1 0 0 0 0 0 0 1 LSB 0.0078 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 CODE DESCRIPTION Zero MSB LSB † The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage. 4-1500 HI-5700 Glossary of Terms Aperture Delay: Aperture delay is the time delay between the external sample command (the rising edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays. Aperture Jitter: This is the RMS variation in the aperture delay due to variation of internal φ1 and φ2 clock path delays and variation between the individual comparator switching times. Differential Linearity Error (DNL): The differential linearity error is the difference in LSBs between the spacing of the measured midpoint of adjacent codes and the spacing of ideal midpoints of adjacent codes. The ideal spacing of each midpoint is 1.0 LSB. The range of values possible is from -1.0 LSB (which implies a missing code) to greater than +1.0 LSB. Full Power Input Bandwidth: Full power input bandwidth is the frequency at which the amplitude of the fundamental of the digital output word has decreased 3dB below the amplitude of an input sine wave. The input sine wave has a peak-to-peak amplitude equal to the reference voltage. The bandwidth given is measured at the specified sampling frequency. Full Scale Error (FSE): Full Scale Error is the difference between the actual input voltage of the 254 to 255 code transition and the ideal value of VREF + - 1.5 LSB. This error is expressed in LSBs. LSB: Least Significant Bit = (VREF + - VREF -)/256. All HI5700 specifications are given for a 15.6mV LSB size VREF + = 4.0V, VREF - = 0.0V. Offset Error (VOS): Offset error is the difference between the actual input voltage of the 0 to 1 code transition and the ideal value of VREF - + 0.5 LSB, VOS Error is expressed in LSBs. Power Supply Rejection Ratio (PSRR): PSRR is expressed in LSBs and is the maximum shift in code transition points due to a power supply voltage shift. This is measured at the 0 to 1 code transition point and the 254 to 255 code transition point with a power supply voltage shift from the nominal value of 5.0V. Signal to Noise Ratio (SNR): SNR is the ratio in dB of the RMS signal to RMS noise at specified input and sampling frequencies. Signal to Noise and Distortion Ratio (SINAD): SINAD is the ratio in dB of the RMS signal to the RMS sum of the noise and harmonic distortion at specified input and sampling frequencies. Total Harmonic Distortion (THD): THD is the ratio in dBc of the RMS sum of the first five harmonic components to the RMS signal for a specified input and sampling frequency. Integral Linearity Error (INL): The integral linearity error is the difference in LSBs between the measured code centers and the ideal code centers. The ideal code centers are calculated using a best fit line through the converter’s transfer function. 4-1501 HI-5700 Die Characteristics DIE DIMENSIONS: 154.3 x 173.2 x 19 ± 1mils METALLIZATION: Type: Si - Al Thickness: 11kÅ ± 1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ TRANSISTOR COUNT: 8000 SUBSTRATE POTENTIAL (Powered Up): V+ Metallization Mask Layout 6 VDD 7 28 27 AVDD CLK VREF- D7 VIN D6 1 26 25 AGND 24 AGND 23 AVDD 22 1/ R 2 7 8 21 AVDD 20 AGND 8 19 11 12 13 14 15 16 17 VREF + 10 CE1 D3 CE2 9 OVF 3/4R D0 GND 2 D1 GND 3 5 1/4R VDD 4 D2 D4 D5 HI-5700 4-1502 18 AGND AVDD