HI5808 TM Data Sheet April 2001 File Number 4233.5 12-Bit, 9MSPS A/D Converter Features The HI5808 is a monolithic, 12-bit, Analog-to-Digital Converter fabricated in Intersil’s HBC10 BiCMOS process. It is designed for high speed, high resolution applications where wide bandwidth and low power consumption are essential. • Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9MSPS The HI5808 is designed in a fully differential pipelined architecture with a front end differential-in-differential-out sample-and-hold (S/H). The HI5808 has excellent dynamic performance while consuming 325mW power at 9MSPS. • Full Power Input Bandwidth . . . . . . . . . . . . . . . . . 100MHz The 100MHz full power input bandwidth is ideal for communication systems and document scanner applications. Data output latches are provided which present valid data to the output bus with a latency of 3 clock cycles. The digital outputs have a separate supply pin which can be powered from a 3V to 5V supply. • TTL/CMOS Compatible Digital I/O HI5808BIB HI5808EVAL1 SAMPLE RATE TEMP. RANGE (oC) 9MSPS -40 to 85 25 • Internal Sample and Hold • Fully Differential Architecture • Low Distortion • Internal Voltage Reference • Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 3.0V Applications • Digital Communication Systems • Undersampling Digital IF Ordering Information PART NUMBER • Low Power • Document Scanners PKG. NO. PACKAGE 28 Ld SOIC M28.3 • Additional Reference Documents - AN9214 Using Intersil High Speed A/D Converters - AN9724 Using the HI5808EVAL1 Evaluation Board Evaluation Board Pinout HI5808 (SOIC) TOP VIEW 1 CLK 1 28 D0 DVCC1 2 27 D1 DGND1 3 26 D2 DVCC1 4 25 D3 DGND1 5 24 D4 AVCC 6 23 D5 AGND 7 22 DVCC2 VIN+ 8 21 DGND2 VIN - 9 20 D6 VDC 10 19 D7 VROUT 11 18 D8 VRIN 12 17 D9 AGND 13 16 D10 AVCC 14 15 D11 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001, All Rights Reserved HI5808 Functional Block Diagram BIAS VDC VINVIN+ CLOCK REF S/H CLK VROUT VRIN STAGE 1 DVCC2 4-BIT FLASH 4-BIT DAC + ∑ - D11 (MSB) D10 DIGITAL DELAY AND DIGITAL ERROR CORRECTION X8 STAGE 3 4-BIT FLASH 4-BIT DAC + ∑ - D9 D8 D7 D6 D5 D4 D3 D2 D1 X8 D0 (LSB) STAGE 4 4-BIT FLASH AVCC AGND DGND2 DVCC1 DGND1 Typical Applications Schematic (LSB) (28) D0 (27) D1 VROUT (11) (26) D2 (25) D3 VRIN (12) (24) D4 AGND (7) (23) D5 AGND (13) (20) D6 DGND1 (3) (19) D7 DGND1 (5) (18) D8 DGND2 (21) (17) D9 (16) D10 (MSB) (15) D11 VIN+ VIN+ (8) VIN - BNC D11 (2) DVCC1 VIN- (9) (22) DVCC2 +5V 0.1µF + 10µF 0.1µF +5V + 10µF (6) AVCC (14) AVCC HI5808 2 AGND DGND (4) DVCC1 VDC (10) CLK (1) CLOCK D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 10µF AND 0.1µF CAPS ARE PLACED AS CLOSE TO PART AS POSSIBLE HI5808 Absolute Maximum Ratings Thermal Information Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . +6.0V DGND to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND to DVCC Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications AVCC = DVCC1 = DVCC2 = +5V, fS = 9MSPS at 50% Duty Cycle, VRIN = 3.5V, CL = 10pF, TA = -40oC to 85oC, Differential Analog Input, Typical Values are Test Results at 25oC, Unless Otherwise Specified HI5808BIB -40oC TO 85oC PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 12 - - Bits ACCURACY Resolution Integral Linearity Error, INL fIN = DC - ±1 ±2 LSB Differential Linearity Error, DNL (Guaranteed No Missing Codes) fIN = DC - ±0.5 ±1 LSB Offset Error, VOS fIN = DC - 19 - LSB Full Scale Error, FSE fIN = DC - 32 - LSB DYNAMIC CHARACTERISTICS Minimum Conversion Rate No Missing Codes - 0.5 - MSPS Maximum Conversion Rate No Missing Codes 9 - - MSPS Effective Number of Bits, ENOB fIN = 1MHz 10.0 10.8 - Bits Signal to Noise and Distortion Ratio, SINAD fIN = 1MHz - 66.5 - dB Signal to Noise Ratio, SNR RMS Signal = ------------------------------RMS Noise fIN = 1MHz - 67.3 - dB Total Harmonic Distortion, THD fIN = 1MHz - -75 - dBc 2nd Harmonic Distortion fIN = 1MHz - -80 3rd Harmonic Distortion fIN = 1MHz - -77 - dBc RMS Signal = -------------------------------------------------------------RMS Noise + Distortion dBc Spurious Free Dynamic Range, SFDR fIN = 1MHz - 77 - dBc Intermodulation Distortion, IMD f1 = 1MHz, f2 = 1.02MHz - -65 - dBc - 1 - Cycle - 2 - Cycle - ±2.0 - V Transient Response Overvoltage Recovery 0.2V Overdrive ANALOG INPUT Maximum Peak-to-Peak Differential Analog Input Range (VIN+ - VIN-) Maximum Peak-to-Peak Single-Ended Analog Input Range (Notes 2, 3) Analog Input Resistance, RIN Analog Input Capacitance, C IN - 4.0 - V 1 - - MΩ - 10 - pF -10 - +10 µA Differential Analog Input Bias Current IB DIFF = (IB+ - IB-) - ±0.5 - µA Full Power Input Bandwidth, FPBW - 100 - MHz Analog Input Bias Current, IB+ or IB- 3 (Note 3) HI5808 Electrical Specifications AVCC = DVCC1 = DVCC2 = +5V, fS = 9MSPS at 50% Duty Cycle, VRIN = 3.5V, CL = 10pF, TA = -40oC to 85oC, Differential Analog Input, Typical Values are Test Results at 25oC, Unless Otherwise Specified (Continued) HI5808BIB -40oC TO 85oC PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 1 2.3 4 V Reference Output Voltage, VROUT (Loaded) - 3.5 - V Reference Output Current - - 1 mA Reference Temperature Coefficient - 50 - ppm/oC Reference Voltage Input, VRIN - 3.5 - V Total Reference Resistance, RL - 7.8 - kΩ Reference Current - 450 - µA DC Bias Voltage Output, VDC - 2.3 - V Max Output Current (Not To Exceed) - - 1 mA 2.0 - - V Analog Input Common Mode Voltage Range (VIN+ + VIN-)/2 Differential Mode (Note 2) INTERNAL VOLTAGE REFERENCE REFERENCE VOLTAGE INPUT DC BIAS VOLTAGE DIGITAL INPUTS (CLK) Input Logic High Voltage, VIH - - 0.8 V Input Logic High Current, IIH VCLK = 5V - - 10.0 µA Input Logic Low Current, IIL VCLK = 0V - - 10.0 µA - 7 - pF 1.6 - - mA Input Logic Low Voltage, VIL Input Capacitance, C IN DIGITAL OUTPUTS (D0-D11) VO = 0.4V (Note 2) Output Logic Sink Current, IOL DVCC3 = 3.0V, VO = 0.4V Output Logic Source Current, IOH VO = 2.4V (Note 2) DVCC3 = 3.0V, VO = 2.4V - 1.6 - mA -0.2 - - mA - -0.2 - mA - 5 - pF Aperture Delay, tAP - 5 - ns Aperture Jitter, tAJ - 5 - ps (RMS) Data Output Delay, tOD - 8 - ns - 8 - ns - - 3 Cycles Output Capacitance, COUT TIMING CHARACTERISTICS Data Output Hold, t H For a Valid Sample (Note 2) Data Latency, tLAT Clock Pulse Width (Low) 9MSPS Clock 45 50 55 ns Clock Pulse Width (High) 9MSPS Clock 45 50 55 ns POWER SUPPLY CHARACTERISTICS Total Supply Current, ICC VIN+ - VIN- = 2V - 65 73 mA Analog Supply Current, AICC VIN+ - VIN- = 2V - 46 - mA Digital Supply Current, DICC1 VIN+ - VIN- = 2V - 17 - mA Output Supply Current, DICC2 VIN+ - VIN- = 2V - 2 - mA Power Dissipation VIN+ - VIN- = 2V - 325 365 mW Offset Error PSRR, ∆V OS AVCC or DVCC = 5V ±5% - 2 - LSB Gain Error PSRR, ∆FSE AVCC or DVCC = 5V ±5% - 30 - LSB NOTES: 2. Parameter guaranteed by design or characterization and not production tested. 3. With the clock off (clock low, hold mode). 4 HI5808 Timing Waveforms ANALOG INPUT CLOCK INPUT SN - 1 HN - 1 SN HN SN + 1 H N + 1 SN + 2 HN + 2 S N + 3 HN + 3 S N + 4 HN + 4 S N + 5 HN + 5 SN + 6 HN + 6 INPUT S/H 1ST STAGE 2ND STAGE B1, N - 1 B2, N - 2 3RD STAGE 4TH STAGE B1, N B2, N - 1 B3, N - 2 B4, N - 3 DATA OUTPUT B1, N + 1 B2, N B3, N - 1 B4, N - 2 DN - 3 B1, N + 2 B2, N + 1 B3, N B4, N - 1 DN - 2 B2, N + 2 B3, N + 1 B4, N DN - 1 B1, N + 3 B2, N + 3 B3, N + 2 B4, N + 1 DN DN + 1 NOTES: 4. SN : N-th sampling period. 5. HN : N-th holding period. 6. BM , N : M-th stage digital output corresponding to N-th sampled input. 7. DN : Final data output corresponding to N-th sampled input. FIGURE 1. INTERNAL CIRCUIT TIMING ANALOG INPUT tAP tAJ 1.5V 1.5V tOD tH 2.0V DATA OUTPUT DATA N - 1 DATA N 0.8V FIGURE 2. INPUT-TO-OUTPUT TIMING 5 B1, N + 5 B2, N + 4 B3, N + 3 B 4, N + 2 tLAT CLOCK INPUT B1, N + 4 B3, N + 4 B4, N + 3 DN + 2 DN + 3 HI5808 Typical Performance Curves 11 70 fS = 9MSPS fS = 9MSPS 10 TEMPERATURE = 25 oC TEMPERATURE = 25oC 60 SINAD (dB) ENOB 9 8 50 7 40 6 30 5 10 INPUT FREQUENCY (MHz) 1 100 INPUT FREQUENCY (MHz) FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT FREQUENCY FIGURE 4. SIGNAL TO NOISE AND DISTORTION (SINAD) vs INPUT FREQUENCY -40 70 fS = 9MSPS fS = 9MSPS TEMPERATURE = 25oC TEMPERATURE = 25 oC -50 THD (dBc) 60 SNR (dB) 10 1 100 50 -60 -70 40 -80 30 10 1 10 1 100 100 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) FIGURE 5. SIGNAL TO NOISE RATIO (SNR) vs INPUT FREQUENCY FIGURE 6. TOTAL HARMONIC DISTORTION (THD) vs INPUT FREQUENCY 80 11 2MHz fS = 9MSPS 10 TEMPERATURE = 25oC 1MHz 5MHz 10MHz 9 ENOB SFDR (dBc) 70 60 8 7 fS = 9MSPS TEMPERATURE = 25oC 20MHz 50MHz 50 6 100MHz 40 1 10 INPUT FREQUENCY (MHz) 100 FIGURE 7. SPURIOUS FREE DYNAMIC RANGE (SFDR) vs INPUT FREQUENCY 6 5 0.4 0.5 DUTY CYCLE (tCLK-LOW/tCLK) 0.6 FIGURE 8. EFFECTIVE NUMBER OF BITS (ENOB) vs CLOCK DUTY CYCLE AND INPUT FREQUENCY HI5808 Typical Performance Curves (Continued) 11 3.525 2MHz 1MHz 10 9 VREFNOM 10MHz VROUT (V) ENOB 3.515 5MHz 20MHz 8 fS = 9MSPS 3.505 3.495 VREFLD 7 50MHz 3.485 6 100MHz 5 -40 -20 0 40 20 TEMPERATURE (oC) 60 3.475 -40 80 FIGURE 9. EFFECTIVE NUMBER OF BITS (ENOB) vs TEMPERATURE AND INPUT FREQUENCY 0 20 40 TEMPERATURE (oC) 60 80 FIGURE 10. INTERNAL VOLTAGE REFERENCE OUTPUT (VROUT) vs TEMPERATURE AND LOAD 70 326 60 ITOT CURRENT (mA) 324 fS = 9MSPS 322 VIN + = VIN- = VDC 320 50 AI CC 40 fS = 9MSPS VIN+ = VIN- = VDC 30 20 DICC1 318 10 DICC2 316 -40 -20 0 20 40 60 0 -40 80 -20 TEMPERATURE (oC) FIGURE 11. POWER DISSIPATION vs TEMPERATURE 0 0 20 40 TEMPERATURE (oC) fIN = 1MHz, fS = 9MSPS -20 -30 -40 -50 -60 -70 -80 -90 -100 0 1024 FREQUENCY BIN FIGURE 13. 4096 POINT FFT SPECTRAL PLOT 7 60 80 FIGURE 12. POWER SUPPLY CURRENT vs TEMPERATURE -10 OUTPUT LEVEL (dB) POWER DISSIPATION (mW) -20 2048 HI5808 Pin Descriptions PIN NO. NAME DESCRIPTION 1 CLK Sample Clock Input. 2 DVCC1 Digital Supply (5.0V). 3 DGND1 Digital Ground. 4 DVCC1 Digital Supply (5.0V). 5 DGND1 Digital Ground. 6 AVCC Analog Supply (5.0V). 7 AGND Analog Ground. 8 VIN+ Positive Analog Input. 9 VIN- Negative Analog Input. 10 VDC DC Bias Voltage Output. 11 VROUT 12 VRIN Reference Voltage Input. 13 AGND Analog Ground. 14 AVCC Analog Supply (5.0V). 15 D11 Data Bit 11 Output (MSB). 16 D10 Data Bit 10 Output. 17 D9 Data Bit 9 Output. 18 D8 Data Bit 8 Output. 19 D7 Data Bit 7 Output. 20 D6 Data Bit 6 Output. 21 DGND2 Digital Output Ground. 22 DVCC2 Digital Output Supply (3.0V to 5.0V). 23 D5 Data Bit 5 Output. 24 D4 Data Bit 4 Output. 25 D3 Data Bit 3 Output. 26 D2 Data Bit 2 Output. 27 D1 Data Bit 1 Output. 28 D0 Data Bit 0 Output (LSB). fully-differential output for the converter core. During the sampling phase, the VIN pins see only the on-resistance of a switch and CS . The relatively small values of these components result in a typical full power input bandwidth of 100MHz for the converter. φ1 VIN + φ1 φ1 φ1 CS VOUT + -+ +- φ2 VIN - CH VOUT - CS φ1 CH φ1 Reference Voltage Output. Detailed Description Theory of Operation The HI5808 is a 12-bit fully differential sampling pipeline A/D converter with digital error correction. Figure 14 depicts the circuit for the front end differential-in-differential-out sampleand-hold (S/H). The switches are controlled by an internal clock which is a non-overlapping two phase signal, φ1 and φ2 , derived from the master clock. During the sampling phase, φ1 , the input signal is applied to the sampling capacitors, CS . At the same time the holding capacitors, CH , are discharged to analog ground. At the falling edge of φ1 the input signal is sampled on the bottom plates of the sampling capacitors. In the next clock phase, φ2 , the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op-amp output nodes. The charge then redistributes between CS and CH completing one sample-and-hold cycle. The output is a fully-differential, sampled-data representation of the analog input. The circuit not only performs the sample-andhold function but will also convert a single-ended input to a 8 FIGURE 14. ANALOG INPUT SAMPLE-AND-HOLD As illustrated in the functional block diagram and the timing diagram in Figure 1, three identical pipeline subconverter stages, each containing a four-bit flash converter, a four-bit digital-to-analog converter and an amplifier with a voltage gain of 8, follow the S/H circuit with the fourth stage being only a 4bit flash converter. Each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase. Each individual sub-converter clock signal is offset by 180 degrees from the previous stage clock signal, with the result that alternate stages in the pipeline will perform the same operation. The digital output of each of the three identical 4-bit subconverter stages is a four-bit digital word containing a supplementary bit to be used by the digital error correction logic. The output of each subconverter stage is input to a digital delay line which is controlled by the internal sampling clock. The function of the digital delay line is to time align the digital outputs of the three identical four-bit subconverter stages with the corresponding output of the fourth stage flash converter before applying the sixteen bit result to the digital error correction logic. The digital error correction logic uses the supplementary bits to correct any error that may exist before generating the final twelve bit digital data output of the converter. Because of the pipeline nature of this converter, the digital data representing an analog input sample is output to the digital data bus on the 3rd cycle of the clock after the analog sample is taken. This time delay is specified as the data latency. After the data latency time, the digital data representing each succeeding analog sample is output on the following clock pulse. The digital output data is synchronized to the external sampling clock with an output latch. The output of the digital error correction circuit is available in offset binary format (see Table 1, A/D Code Table). HI5808 TABLE 1. A/D CODE TABLE CODE CENTER DESCRIPTION DIFFERENTIAL INPUT VOLTAGE † (USING INTERNAL REFERENCE) OFFSET BINARY OUTPUT CODE MSB LSB D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 +Full Scale (+FS) - 1/4 LSB +1.99976V 1 1 1 1 1 1 1 1 1 1 1 1 +FS - 11/4 LSB 1.99878V 1 1 1 1 1 1 1 1 1 1 1 0 + 3/4 LSB 732.4µV 1 0 0 0 0 0 0 0 0 0 0 0 - 1/4 LSB -244.1µV 0 1 1 1 1 1 1 1 1 1 1 1 -FS + 13/4 LSB -1.99829V 0 0 0 0 0 0 0 0 0 0 0 1 -Full Scale (-FS) + 3/4 LSB -1.99927V 0 0 0 0 0 0 0 0 0 0 0 0 † The voltages listed above represent the ideal center of each offset binary output code shown. Internal Reference Generator, VROUT and VRIN The HI5808 has an internal reference generator, therefore, no external reference voltage is required. VROUT must be connected to VRIN when using the internal reference voltage. The HI5808 can be used with an external reference. The converter requires only one external reference voltage connected to the VRIN pin with VROUT left open. The HI5808 is tested with VRIN equal to 3.5V. Internal to the converter, two reference voltages of 1.3V and 3.3V are generated for a fully differential input signal range of ±2V. In order to minimize overall converter noise, it is recommended that adequate high frequency decoupling be provided at the reference voltage input pin, V RIN . Analog Input, Differential Connection The analog input to the HI5808 can be configured in various ways depending on the signal source and the required level of performance. A fully differential connection (Figure 15) will give the best performance for the converter. using a differential input. This low output impedance voltage source is not designed to be a reference but makes an excellent bias source and stays within the analog input common mode voltage range over temperature. The difference between the converter’s two internal voltage references is 2V. For the AC coupled differential input, (Figure 15), if VIN is a 2VP-P sinewave with -VIN being 180 degrees out of phase with VIN , then VIN+ is a 2VP-P sinewave riding on a DC bias voltage equal to VDC and VIN- is a 2VP-P sinewave riding on a DC bias voltage equal to VDC . Consequently, the converter will be at positive full scale, all 1’s digital data output code, when the VIN+ input is at VDC +1V and the VIN- input is at V DC -1V (V IN+- VIN - = 2V). Conversely, the ADC will be at negative full scale, all 0’s digital data output code, when the VIN + input is equal to VDC -1V and V IN- is at VDC + 1V (VIN + -VIN - = -2V). From this, the converter is seen to have a peak-to-peak differential analog input voltage range of ±2V. The analog input can be DC coupled (Figure 16) as long as the inputs are within the analog input common mode voltage range (1.0V ≤ VDC ≤ 4.0V). VIN VIN+ VIN VIN+ VDC HI5808 R VDC VIN- HI5808 VDC -VIN -VIN C VDC R VIN - FIGURE 15. AC COUPLED DIFFERENTIAL INPUT FIGURE 16. DC COUPLED DIFFERENTIAL INPUT Since the HI5808 is powered off a single +5V supply, the analog input must be biased so it lies within the analog input common mode voltage range of 1.0V to 4.0V. The performance of the ADC does not change significantly with the value of the analog input common mode voltage. The resistors, R, in Figure 16 are not absolutely necessary but may be used as load setting resistors. A capacitor, C, connected from VIN+ to VIN - will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. A 2.3V DC bias voltage source, VDC , half way between the top and bottom internal reference voltages, is made available to the user to help simplify circuit design when 9 HI5808 Analog Input, Single-Ended Connection Digital I/O and Clock Requirements The configuration shown in Figure 17 may be used with a single ended AC coupled input. Sufficient headroom must be provided such that the input voltage never goes above +5V or below AGND . The HI5808 provides a standard high-speed interface to external TTL/CMOS logic families. The digital CMOS clock input has TTL level thresholds. The low input bias current allows the HI5808 to be driven by CMOS logic. VIN+ VIN HI5808 VDC VIN- FIGURE 17. AC COUPLED SINGLE ENDED INPUT Again, the difference between the two internal voltage references is 2V. If V IN is a 4VP-P sinewave, then V IN + is a 4V P- P sinewave riding on a positive voltage equal to VDC. The converter will be at positive full scale when V IN + is at VDC + 2V (VIN + - V IN - = 2V) and will be at negative full scale when VIN + is equal to VDC - 2V (VIN+ - V IN - = -2V). In this case, VDC could range between 2V and 3V without a significant change in ADC performance. The simplest way to produce VDC is to use the VDC bias voltage output of the HI5808. The single ended analog input can be DC coupled (Figure 18) as long as the input is within the analog input common mode voltage range. The digital CMOS outputs have a separate digital supply. This allows the digital outputs to operate from a 3.0V to 5.0V supply. When driving CMOS logic, the digital outputs will swing to the rails. When driving standard TTL loads, the digital outputs will meet standard TTL level requirements even with a 3.0V supply. In order to ensure rated performance of the HI5808, the duty cycle of the clock should be held at 50% ±5%. It must also have low jitter and operate at standard TTL levels. Performance of the HI5808 will only be guaranteed at conversion rates above 0.5MSPS. This ensures proper performance of the internal dynamic circuits. Supply and Ground Considerations The HI5808 has separate analog and digital supply and ground pins to keep digital noise out of the analog signal path. The part should be mounted on a board that provides separate low impedance connections for the analog and digital supplies and grounds. For best performance, the supplies to the HI5808 should be driven by clean, linear regulated supplies. The board should also have good high frequency decoupling capacitors mounted as close as possible to the converter. If the part is powered off a single supply then the analog supply and ground pins should be isolated by ferrite beads from the digital supply and ground pins. VIN VIN+ VDC R C VDC HI5808 Static Performance Definitions VIN - FIGURE 18. DC COUPLED SINGLE ENDED INPUT The resistor, R, in Figure 18 is not absolutely necessary but may be used as a load setting resistor. A capacitor, C, connected from VIN+ to VIN - will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. A single ended source will give better overall system performance if it is first converted to differential before driving the HI5808. 10 Refer to the Application Note AN9214, “Using Intersil High Speed A/D Converters” for additional considerations when using high speed converters. Offset Error (VOS) The midscale code transition should occur at a level 1/4 LSB above half-scale. Offset is defined as the deviation of the actual code transition from this point. Full-Scale Error (FSE) The last code transition should occur for an analog input that is 3/4 LSB below positive full scale with the offset error removed. Full-scale error is defined as the deviation of the actual code transition from this point. Differential Linearity Error (DNL) DNL is the worst case deviation of a code width from the ideal value of 1 LSB. Integral Linearity Error (INL) INL is the worst case deviation of a code center from a best fit straight line calculated from the measured data. HI5808 Each of the power supplies are moved plus and minus 5% and the shift in the offset and gain error (in LSBs) is noted. distortion terms is calculated. The terms included in the calculation are (f1 + f2), (f1 - f2), (2f1), (2f2), (2f1 + f2), (2f1 - f2), (f1 + 2f2), (f1 - 2f2). The ADC is tested with each tone 6dB below full scale. Dynamic Performance Definitions Transient Response Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5808. A low distortion sine wave is applied to the input, it is coherently sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with an FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from full scale for all these tests. SNR and SINAD are quoted in dB. The distortion numbers are quoted in dBc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to full scale. Transient response is measured by providing a full-scale transition to the analog input of the ADC and measuring the number of cycles it takes for the output code to settle within 12-bit accuracy. Signal-to-Noise Ratio (SNR) Full power input bandwidth is the analog input frequency at which the amplitude of the digitally reconstructed output has decreased 3dB below the amplitude of the input sinewave. The input sinewave has an amplitude which swings from -fS to +fS . The bandwidth given is measured at the specified sampling frequency. Power Supply Rejection Ratio (PSRR) SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics. Signal-to-Noise + Distortion Ratio (SINAD) SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency, fS/2, excluding DC. Overvoltage Recovery Overvoltage Recovery is measured by providing a full-scale transition to the analog input of the ADC which overdrives the input by 200mV, and measuring the number of cycles it takes for the output code to settle within 12-bit accuracy. Full Power Input Bandwidth (FPBW) Timing Definitions Refer to Figure 1, Internal Circuit Timing, and Figure 2, InputTo-Output Timing, for these definitions. Effective Number Of Bits (ENOB) Aperture Delay (t AP) The effective number of bits (ENOB) is calculated from the SINAD data by: Aperture delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays. ENOB = ( SINAD + V C ORR -1.76 )/6.02, Aperture Jitter (tAJ) where: VCORR = 0.5dB. VCORR adjusts the ENOB for the amount the input is below full scale. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the fundamental input signal. Aperture Jitter is the RMS variation in the aperture delay due to variation of internal clock path delays. Data Hold Time (tH) Data hold time is the time to where the previous data (N - 1) is no longer valid. Data Output Delay Time (tOD) 2nd and 3rd Harmonic Distortion Data output delay time is the time to where the new data (N) is valid. This is the ratio of the RMS value of the applicable harmonic component to the RMS value of the fundamental input signal. Data Latency (t LAT) Spurious Free Dynamic Range (SFDR) SFDR is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component in the spectrum below fS/2. Intermodulation Distortion (IMD) Nonlinearities in the signal path will tend to generate intermodulation products when two tones, f1 and f2 , are present at the inputs. The ratio of the measured signal to the 11 After the analog sample is taken, the digital data is output on the bus at the third cycle of the clock. This is due to the pipeline nature of the converter where the data has to ripple through the stages. This delay is specified as the data latency. After the data latency time, the data representing each succeeding sample is output at the following clock pulse. The digital data lags the analog input sample by 3 clock cycles. HI5808 Small Outline Plastic Packages (SOIC) M28.3 (JEDEC MS-013-AE ISSUE C) N 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA 0.25(0.010) M H B M INCHES E -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 e µα B S 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α NOTES: MILLIMETERS SYMBOL 28 0o 28 7 8o Rev. 0 12/93 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 NORTH AMERICA Intersil Corporation 2401 Palm Bay Road Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7240 12 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369