[ /Title (IH505 3) /Subject (Quad CMOS Analog Switch es) /Autho r () /Keywords (Intersil Corporation, semiconductor, Quad CMOS Analog Switch es) /Creator () /DOCI NFO pdfmark IH5053 T CT DUC PRO PRODU E T E E L T O U OBS UBSTIT 442 S G D E , Data Sheet March 2000 SIBL DG445 POS TM File Number 3131.3 Quad CMOS Analog Switch Features The IH5053 analog switch uses an improved, high voltage CMOS technology, which provides performance advantages not previously available from solid state switches. Key performance advantages are TTL compatibility and ultra lowpower operation. The quiescent current requirement is less than 10µA. • Switches Greater Than 20VP-P Signals with ±15V Supplies The IH5053 also guarantees Break-Before-Make switching. This is accomplished by extending the tON time (1000ns) such that it exceeds the tOFF time (500ns). This insures that an ON channel will be turned OFF before an OFF channel can turn ON, and eliminates the need for external logic required to avoid channel to channel shorting during switching. Pinout • Quiescent Current . . . . . . . . . . . . . . . . . . . . . . . . . <10µA • Break-Before-Make Switching - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns • TTL, CMOS Compatible • 4 Normally Open Switches • Low rDS(ON) (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Ω Part Number Information TEMP. RANGE (oC) PART NUMBER IH5053 (SBDIP) TOP VIEW IH5053CDE 0 to 70 PKG. NO. PACKAGE 16 Ld SBDIP D16.3 Schematic Diagram IN1 1 16 IN4 D1 2 15 D4 S1 3 14 S4 V- 4 13 V+ GND 5 12 VL S2 6 11 S3 D2 7 10 D3 IN2 8 9 IN3 ( 1/4 AS SHOWN) V+ Q3 5K Q4 Q1 SWITCH STATES SHOWN FOR LOGIC “1” INPUT 2K TRUTH TABLE GND IN LOGIC SWITCHES VL 0 Off Q2 1 On Q11 FLOATS 400Ω Q12 1K 10K Q7 Q6 Q8 Q5 400Ω [ /PageMode V- 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation Copyright © Intersil Corporation 2000 IH5053 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <36V V+ to VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VD to VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <±22V VL to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <33V VL to VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V Continuous Current (S-D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current IN or OUT (Pulsed 1ms, 10% Duty Cycle, Max) . . . 70mA Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .175oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications V+ = +15V, V- = -15V, VL = +5V (NOTES 1, 2) PER CHANNEL PARAMETER TEST CONDITIONS 0 oC 25oC 70oC UNITS - 1000 - ns - 500 - ns DYNAMIC CHARACTERISTICS Turn ON Time, tON RL = 1kΩ, VANALOG = -10V to +10V (Figure 6) Turn OFF Time, tOFF Charge Injection, Q Figure 7 - 20 (Typ) - mV OFF Isolation, OIRR f = 1MHz, RL = 100Ω, CL ≤ 5pF (Figure 4) - 50 (Typ) - dB Crosstalk, CCRR One Channel Off (Figure 3) - 50 (Typ) - dB Input Logic Current, IIN(ON) VlN = 2.4V - ±10 - µA Input Logic Current, IIN(OFF) VlN = 0.8V - ±10 - µA 80 80 100 Ω Channel-to-Channel, rDS(ON) Match - 30 (Typ) - Ω Minimum Analog Signal Handling Capability, VANALOG - ±10 (Typ) - V DIGITAL INPUT CHARACTERISTICS ANALOG SWITCH CHARACTERISTICS Drain-Source ON Resistance, rDS(ON) IS = 10mA, VANALOG = -10V to +10V Switch OFF Leakage Current, ID(OFF) , IS(OFF) VANALOG = -10V to +10V - ±5 100 nA Switch ON Leakage Current, ID(ON) + IS(ON) VD = VS = -10V to +10V - ±10 100 nA + Power Supply Quiescent Current, I+ 10 10 100 µA - Power Supply Quiescent Current, I- 10 10 100 µA +5V Supply Quiescent Current, IL 10 10 100 µA POWER SUPPLY CHARACTERISTICS NOTES: 1. Typical values are for Design Aid only, not guaranteed nor production tested. 2. Min or Max value unless otherwise specified. 2 IH5053 Test Circuits and Waveforms 160 100 IS = 1mA VS = ±15V 140 80 rDS(ON) (Ω) rDS(ON) (Ω) 120 125oC 60 25oC -55oC 40 VS = ±10V 100 VS = ±12V 80 VS = ±15V 60 40 20 20 0 -10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0 0 -10.0 -7.5 -5.0 VANALOG (V) -2.5 0 2.5 5.0 7.5 10.0 VANALOG (V) FIGURE 1. rDS(ON) vs ANALOG INPUT VOLTAGE -120 CCRR = 20LOG FIGURE 2. rDS(ON) vs POWER SUPPLY VOLTAGE VOUT (VP-P) 2VP-P CROSSTALK (dB) -100 OFF STATE -80 VOUT 100Ω -60 -40 2VP-P AT 1MHz ON STATE -20 51Ω 0 100Ω 1 10 100 1K 10K 100K 1M FREQUENCY (Hz) FIGURE 3B. TEST CIRCUIT FIGURE 3A. CROSSTALK vs FREQUENCY FIGURE 3. CROSSTALK 120 OIRR = 20LOG OFF ISOLATION (dB) 100 2VP-P VOUT (VP-P) 80 60 2VP-P AT 1MHz 51Ω 40 OFF STATE 20 VOUT 0 1 10 100 1K 10K 100K 1M 100Ω FREQUENCY (Hz) FIGURE 4A. OFF ISOLATION vs FREQUENCY FIGURE 4. OFF ISOLATION 3 FIGURE 4B. TEST CIRCUIT IH5053 Test Circuits and Waveforms (Continued) LOGIC INPUT TTL LEVEL 0.1T IQUIESCENT (EITHER + OR - SUPPLY) (µA) T 1000 100 ANALOG INPUT 10V 3V 0V 10 TTL LOGIC INPUT VOUT 10pF 1kΩ 1 1 10 100 1K 10K 100K LOGIC FREQUENCY AT 10% DUTY CYCLE (Hz) FIGURE 5. SUPPLY CURRENT vs LOGIC FREQUENCY FIGURE 6. tON AND tOFF TEST CIRCUIT 45 40 QINJECT (mVP-P) 35 30 ANALOG INPUT 25 3V 20 0V TTL LOGIC INPUT 15 10nF 10 0 -10.0 VOUT -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0 VANALOG (V) FIGURE 7A. CHARGE INJECTION vs ANALOG INPUT VOLTAGE, CL = 10nF FIGURE 7. CHARGE INJECTION 4 FIGURE 7B. TEST CIRCUIT IH5053 Typical Applications 10kΩ 15V REXT (1kΩ TO 20kΩ) GND IN TTL LOGIC INPUT LOGIC INPUT VL V+ +15V 15V TTL GATE 20kΩ FIGURE 8. +15V OPEN COLLECTOR TTL INTERFACE +15V 13 +15V 5 7 IH5053 VIN1 2 3 3 -15V + 4 LM101A CH1 2 VIN2 30pF 15 14 VOUT 1 - 1 6 CH2 16 +15V VIN3 11 13 10 5 IH5053 CH3 9 VIN4 7 6 1X 2 GAIN1 18kΩ 3 1 CH4 10X 8 4 12 -15V 15 GAIN2 9.9kΩ 14 2kΩ 16 +5V 100kΩ 100X 10 GAIN3 11 100Ω 9 1000X 7 GAIN4 6 100Ω 8 4 -15V 12 +5V FIGURE 9. ACTIVE LOW PASS FILTER WITH DIGITALLY SELECTED BREAK FREQUENCY All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. 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