INTERSIL IH5043CPE

[ /Title
(IH504
3)
/Subject
(Dual
SPDT
CMOS
Analog
Switch
)
/Autho
r ()
/Keywords
(Intersil
Corporation,
semiconductor,
Dual
SPDT
CMOS
Analog
Switch
)
/Creator ()
/DOCI
NFO
pdfmark
[
IH5043
T
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DUC
PRO PRODU
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OBS UBSTIT
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4
0
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I-5
Data Sheet
March 2000
IBL
H
S
S
PO
TM
File Number
Dual SPDT CMOS Analog Switch
Features
The IH5043 analog switch uses an improved, high voltage
CMOS monolithic technology. These devices provide ease
of use and performance advantages not previously
available from solid state switches.
• See HI504X for Other Functions
Key performance advantage is TTL compatibility and ultra
low power operation. The quiescent current requirement is
less than 1mA. Also, the IH5043 guarantees Break-BeforeMake switching, accomplished by extending the tON time
(300ns Typ), so that it exceeds tOFF time (200ns Typ). This
insures that an ON channel will be turned OFF before an
OFF channel can turn ON. The need for external logic
required to avoid channel to channel shorting during
switching is eliminated.
• Quiescent Current Less than 1mA
• Dual SPDT
• Switches Greater than 20VP-P Signals with ±15V Supplies
• Break-Before-Make Switching tOFF 200ns, tON 300ns (Typ)
• TTL, DTL, CMOS, PMOS Compatible
Pinout
IH5043
(PDIP, SOIC)
TOP VIEW
D1
1
16 S1
NC
2
15 IN1
D3
3
14 V-
S3
4
13 GND
S4
5
12 VL
D4
6
11 V+
Schematic Diagram
NC
7
10 IN2
FUNCTIONAL DRIVER, TYPICAL DRIVER, GATE (1/2 AS SHOWN)
D2
8
9
Part Number Information
PART NUMBER
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
IH5043CPE
0 to 70
16 Ld PDIP
E16.3
IH5043CY
0 to 70
16 Ld SOIC
M16.15
3130.3
S2
V+
Functional Diagram
VL
V+
12
Q3
5K
S1
Q4
11
16
1
4
3
D1
Q9
S3
Q1
S1
2K
FLOATS
GND
Q10
VL
Q2
Q11
IN1 15
IN
S3
400Ω
IN2
S2
D3
Q12
1K
10K
FLOATS
S4
Q7
Q6
400Ω
10
9
8
5
6
13
Q8
Q5
D3
D1
D2
D4
14
V-
GND
SWITCH STATES SHOWN ARE FOR LOGIC “1” INPUT
TRUTH TABLE
V-
1
LOGIC
SWITCH 1, 2
SWITCH 3, 4
0
Off
On
1
On
Off
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
IH5043
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <36V
V+ to VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
VD to VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<±22V
VL to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <33V
VL to VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V
Continuous Current (S-D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current S-D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . . 70mA
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
Maximum Junction Temperature (Plastic Packages) . . . . . . .150oC
Maximum Storage Temperature. . . . . . . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V+ = +15V, V- = -15V, VL = +5V
(NOTES 2, 3)
PER CHANNEL PARAMETER
TEST CONDITIONS
0 oC
25oC
70oC
UNITS
-
1000
-
ns
-
500
-
ns
DYNAMIC CHARACTERISTICS
Turn ON Time, tON
RL = 1kΩ, VANALOG = -10V to +10V, See
Figure 6
Turn OFF Time, tOFF
Charge Injection, Q
See Figure 7
-
20 (Typ)
-
mV
OFF Isolation, OIRR
f = 1MHz, RL = 100Ω, CL ≤ 5pF, See Figure 4
-
50 (Typ)
-
dB
Crosstalk, CCRR
One Channel Off; Any Other Channel
Switches as per Figure 3
-
-50 (Typ)
-
dB
DIGITAL INPUT CHARACTERISTICS
Input Logic Current, IIN(ON)
VIN = 2.4V
±1
±1
10
µA
Input Logic Current, IIN(OFF)
VIN = 0.8V
±1
±1
10
µA
IS = 10mA, VANALOG = -10V to +10V
80
80
130
Ω
Channel-to-Channel rDS(ON) Match, ∆rDS(ON)
-
30 (Typ)
-
Ω
Minimum Analog Signal Handling Capability, VANALOG
-
±10 (Typ)
-
V
ANALOG SWITCH CHARACTERISTICS
Drain-Source ON Resistance, rDS(ON)
Switch OFF Leakage Current, ID(OFF), IS(OFF)
VANALOG = -10V to +10V
-
±5
100
nA
Switch ON Leakage Current, ID(ON)+IS(ON)
VD = VS = -10V to +10V
-
±10
100
nA
+ Power Supply Quiescent Current, I+
10
10
100
µA
- Power Supply Quiescent Current, I-
10
10
100
µA
+5V Supply Quiescent Current, IL
10
10
100
µA
Ground Quiescent Current, IGND
10
10
100
µA
POWER SUPPLY CHARACTERISTICS
NOTES:
2. Typical values are for design aid only, not guaranteed and not subject to production testing.
3. Min or Max value unless otherwise specified.
2
IH5043
Test Circuits and Waveforms
160
100
IS = 1mA
VS = ±15V
IS = 1mA
140
120
125oC
rDS(ON) (Ω)
rDS(ON) (Ω)
80
60
25oC
-55oC
40
VS = ±10V
100
VS = ±12V
80
VS = ±15V
60
40
20
20
0
-10.0
-7.5
-5.0
-2.5
0
2.5
5.0
7.5
10.0
0
-10.0
-7.5
-5.0
-2.5
0
2.5
5.0
7.5
VANALOG (V)
VANALOG (V)
FIGURE 1. rDS(ON) vs ANALOG INPUT VOLTAGE
FIGURE 2. rDS(ON) vs POWER SUPPLY VOLTAGE
-120
CCRR = 20LOG
CROSSTALK (dB)
-100
VOUT (mVP-P)
2000mVP-P
OFF
STATE
VOUT
-80
100Ω
-60
-40
2VP-P
AT 1MHz
ON
STATE
-20
51Ω
100Ω
0
1
10
100
1K
10K
100K
1M
FREQUENCY (Hz)
FIGURE 3A. CROSSTALK vs FREQUENCY
FIGURE 3B. TEST CIRCUIT
FIGURE 3. CROSSTALK
120
OIRR = 20LOG
OFF ISOLATION (dB)
100
2000mVP-P
VOUT (mVP-P)
2VP-P
AT 1MHz
80
51Ω
60
OFF STATE
VOUT
40
100Ω
20
0
1
10
100
1K
10K
FREQUENCY (Hz)
100K
1M
FIGURE 4A. OFF ISOLATION vs FREQUENCY
FIGURE 4. OFF ISOLATION
3
FIGURE 4B. TEST CIRCUIT
10.0
IH5043
Test Circuits and Waveforms (Continued)
3V
LOGIC INPUT
0V
0.1T
T
IQUIESCENT (EITHER + OR - SUPPLY) (µA)
1000
ANALOG INPUT
10V
3V
100
0V
LOGIC
INPUT
VOUT
10pF
10
1kΩ
0
1
10
100
1K
10K
100K
LOGIC FREQUENCY AT 10% DUTY CYCLE (Hz)
FIGURE 5. SUPPLY CURRENT vs LOGIC FREQUENCY
FIGURE 6. tON AND tOFF TEST CIRCUIT
45
40
QINJECT (mVP-P)
35
ANALOG INPUT
30
3V
0V
25
LOGIC
INPUT
20
VOUT
10nF
15
10
0
-10.0
-7.5
-5.0
-2.5
0
2.5
VANALOG (V)
5.0
7.5
10.0
FIGURE 7A. CHARGE INJECTION vs ANALOG INPUT VOLTAGE
FIGURE 7. CHARGE INJECTION
4
FIGURE 7B. TEST CIRCUIT
IH5043
Typical Applications
+15V
7
+15V
2
2
ANALOG
INPUT
3
7
CA741
6
4
-15V
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
3 CA5420
OUTPUT
4
-15V
51Ω
-15V
6
10,000pF
POLYSTYRENE
+5V
LOGIC INPUT
+15V
+3V = SAMPLE MODE
0V = HOLD MODE
IH5043
FIGURE 8. IMPROVED SAMPLE AND HOLD
-VANALOG
EXAMPLE: If -VANALOG = -10VDC and
+VANALOG = +10VDC , then Ladder Legs
are switched between ±10VDC , depending
upon state of Logic Strobe.
2R
R
ETC.
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
2R
R
+VANALOG
T2L LOGIC
STROBE
-15V
+5V
+15V
T2L LOGIC
STROBE
+VANALOG
IH5043
R
0V = HOLD MODE
ETC.
FIGURE 9. USING THE CMOS SWITCH TO DRIVE AN R/2R LADDER NETWORK (2 LEGS)
5
IH5043
Typical Applications
(Continued)
SIGNAL
INPUT
C
CA3440
+
3M
HI PASS
OUTPUT
CA3440
+
3M
100kΩ
10,000pF
100kΩ
100kΩ
100kΩ
10,000pF
C
CA3440
+
3M
BANDPASS
OUTPUT
LO PASS
OUTPUT
100kΩ
1kΩ
680kΩ
R
68kΩ
R
Constant gain, constant Q, variable frequency
filter which provides simultaneous Lowpass,
Bandpass, and Highpass outputs. With the
component values shown, center frequency will
be 235Hz and 23.5Hz for high and low logic
inputs respectively, Q = 100, and Gain = 100.
68kΩ
R
680kΩ
R
IH5043
1
f N = Center Frequency = ----------------2π RC
3V
0V
LOGIC STROBE
FIGURE 10. DIGITALLY TUNED LOW POWER ACTIVE FILTER
10kΩ
10kΩ
+15V
V+
REXT
(1kΩ TO
20kΩ)
GND
V+
IN
T2L
LOGIC
LOGIC
INPUT
IN
GND
V-
VL
VL
1N914
+15V
V+
15V ≥ V+ ≥ 5V
0V ≥ V- ≥ -15V
20kΩ
15V TTL GATE
FIGURE 11. INTERFACING WITH TTL OPEN COLLECTOR
LOGIC (TYP EXAMPLE FOR +15V CASE SHOWN)
VCMOS GATE
5kΩ
GND
IN
+5V
VL
5V TTL GATE
V+
+15V OR +VCC
(VI TERMINAL)
10Ω
FIGURE 13. TTL LOGIC INTERFACE
6
20kΩ
FIGURE 12. INTERFACING WITH CMOS LOGIC
+5V
T2L
LOGIC
V+
VDD
IH5043
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
1778µm x 1905µm
Type: PSG/Nitride
PSG Thickness: 7kÅ ±1.4kÅ
Nitride Thickness: 8kÅ ±1.2kÅ
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104 A/cm2
Metallization Mask Layout
IH5043
D3
D1
S1
IN1
S3
V-
GND
VL
S4
V+
(SUBSTRATE)
D4
D2
S2
IN2
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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