IH5352 Data Sheet July 1999 File Number 3134.2 Quad SPST, CMOS RF/Video Switch Features The IH5352 is a quad SPST, CMOS monolithic switch which uses a “Series/Shunt” (“T” switch) configuration to obtain high OFF isolation while maintaining good frequency response in the ON condition. • rDS(ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Ω Construction of remote and portable video equipment with extended battery life is facilitated by the extremely low current requirements. Switching speeds are typically tON = 150ns and tOFF = 80ns. “Break-Before-Make” switching is guaranteed. Switch ON resistance is typically 40Ω - 50Ω with ±15V power supplies, increasing to typically 175Ω for ±5V supplies. • OFF Isolation at 10MHz . . . . . . . . . . . . . . . . . . . . . >70dB • Crosstalk Isolation at 10MHz . . . . . . . . . . . . . . . . . >60dB • Compatible With TTL, CMOS Logic • Wide Operating Power Supply Range • Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . <1µA • “Break-Before-Make” Switching • Fast Switching (Typ) . . . . . . . . . . . . . . . . . . . . 80ns/150ns Ordering Information PART NUMBER • Switch Attenuation Varies Less Than 3dB From DC to 100MHz TEMP. RANGE (oC) PACKAGE PKG. NO. IH5352CPE 0 to 70 16 Ld PDIP E16.3 IH5352CBP 0 to 70 20 Ld SOIC M20.3 Applications • Video Switch • Communications Equipment • Disk Drives Pinouts • Instrumentation IH5352 (PDIP) TOP VIEW • CATV Functional Diagram IIN1 1 16 D1 S1 2 15 V+ IIN2 3 14 D2 13 GND S2 4 IIN3 5 12 D3 S3 6 11 V- IIN4 7 10 D4 S4 8 9 VL S1 D1 IIN1 S2 D2 IIN2 S3 IH5352 (SOIC) TOP VIEW D3 IIN3 IIN1 1 20 D1 S1 2 19 V+ NC 3 18 NC IIN2 4 17 D2 S2 5 SWITCH STATE SHOWN FOR LOGIC “0” INPUT S4 D4 IIN4 16 GND IIN3 6 15 D3 S3 7 14 V- NC 8 13 NC IIN4 9 12 D4 S4 10 11 VL 1 TRUTH TABLE LOGIC SWITCHES 0 Off 1 On CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IH5352 Schematic Diagram 1/ IH5352 4 +15V -15V Q3 Q5 Q7 Q20 Q18 Q17 +15V Q19 10kΩ 5kΩ Q3 S -15V Q1 Q8 TTL -15V Q16 Q22 5 Q9 Q10 +15V Q21 +15V +5V 5kΩ Q4 Q15 3kΩ Q 12 Q6 +15V Q11 D Q13 -15V 2 Q14 IH5352 Absolute Maximum Ratings Thermal Information V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +18V V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18V VL to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to VLogic Control Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to VAnalog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to VCurrent (Any Terminal). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Junction Temperature (Plastic Packages) . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Supply Voltage Range V+, VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 15V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to -15V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V+ = +15V, VL = +5V, V- = -15V, Unless Otherwise Specified PARAMETER TEST CONDITIONS (NOTE 2) TYP 25oC (NOTE 4) 0 oC 25oC 70oC UNITS 150 - - - ns 80 - - - ns DYNAMIC CHARACTERISTICS Turn ON Time, tON Figure 1 Turn OFF Time, tOFF OFF Isolation, OIRR Figure 2 70 - - - dB Crosstalk, CCRR Figure 3 -60 - - - dB Switch Attenuation 3dB Frequency, f3dB Figure 4 100 - - - MHz Logic “1” Input Voltage, VIH >2.4 - - - V Logic “0” Input Voltage, VIL <0.8 - - - V VIN > 2.4V or < 0V 0.1 ±1 ±1 10 µA VD = ±5V, IS = 10mA, VIN ≥ 2.4V 50 75 75 100 Ω VD = ±10V, IS = 10mA, VIN ≥ 2.4V 100 150 150 175 Ω V+ = VL = +5V, VIN = 3V, V- = -5V, VD = ±3V, IS = 10mA 175 300 300 350 Ω DIGITAL INPUT CHARACTERISTICS Input Logic Current, IIN ANALOG SWITCH CHARACTERISTICS Drain-Source ON Resistance, rDS(ON) On Resistance Match Between Channels, ∆rDS(ON) IS = 10mA, VD = ±5V 5 - - - Ω Switch OFF Leakage Current, ID(OFF) or IS(OFF) VS/D = ±5V or ±14V, VIN ≤ 0.8V (Note 3) - - ±2 100 nA Switch ON Leakage Current, ID(ON) + IS(ON) VS/D = ±5V or ±14V, VIN ≥ 2.4V - - ±2 100 nA 0.1 1 1 10 µA Negative Supply Quiescent Current, I- 0.1 1 1 10 µA Logic Supply Quiescent Current, IL 0.1 1 1 10 µA POWER SUPPLY CHARACTERISTICS Positive Supply Quiescent Current, I+ VIN = 0V or +5V NOTES: 2. Typical values are not tested in production. They are given as a design aid only. 3. Positive and negative voltages applied to opposite sides of switch, in both directions successively. 4. Min or Max value, unless otherwise specified. 3 IH5352 Test Circuits and Waveforms VANALOG (±5V) VOUT +3V 0V TTL IN S1 15V 5V V+ VL +3V TTL INPUT 0V S2 50% 50% ≈ +3.5V D1 D2 IN1 90% VOUT (VANALOG + 5V) 10% 0V IN2 tOFF tON 0V RL = 100Ω GND 90% VOUT (VANALOG - 5V) -15V 10% ≈ -3.5V NOTE: Only one channel shown. Others act identically. FIGURE 1B. MEASUREMENT POINTS FIGURE 1A. TEST CIRCUIT FIGURE 1. tON AND tOFF 75Ω VIN VOUT 75Ω S1 15V 5V V+ VL 75Ω D1 D2 IN1 IN2 S1 VIN V+ VL S2 D1 D2 IN1 IN2 OPEN 75Ω VOUT +5V V- 5V S2 RG-59 COAX RG-59 COAX 15V GND V- GND -15V -15V V IN = ± 5V ( 10V P-P ) at f = 10MHz V IN = 225mV RMS at f = 10MHz V IN OIRR = 20Log ---------------V OUT NOTE: V OUT CCRR = 20Log ---------------V IN Only one channel shown. Others act identically. FIGURE 2. OFF ISOLATION TEST CIRCUIT FIGURE 3. CROSSTALK TEST CIRCUIT 75Ω VIN S1 15V 5V V+ VL S2 NC RG-59 COAX VOUT 75Ω RG-59 COAX +5V D1 D2 IN1 IN2 V- 75Ω GND -15V RL ATTN: = 20Log -----------------------------------r DS ( ON ) + R L Nominally, at DC, ATTN equals -4dB. When the attenuation reaches -1dB, the frequency at which this occurs is f3dB . NOTE: Only one channel shown. Others act identically. FIGURE 4. SWITCH ATTENUATION TEST CIRCUIT 4 IH5352 Detailed Description Figure 5 shows the internal circuit of one channel of the IH5352. Here, a shunt switch is closed, and the two series switches are open when the video switch channel is open or off. This provides much better isolation between the input and output terminals than a simple series switch does, especially at high frequencies. The result is excellent offisolation in the Video and RF frequency ranges when compared to conventional analog switches. The control input level shifting circuitry is very similar to that of the IH5140 series of Analog Switches, and gives very high speed, guaranteed “Break-Before-Make” action, low static power consumption and TTL compatibility. SWITCH SOURCE (VIDEO INPUT) LOGIC CONTROL INPUT SWITCH DRAIN (VIDEO OUTPUT) SHUNT SWITCH DRIVER TRANSLATOR NOTE: 1 channel of 4 shown. FIGURE 5. INTERNAL SWITCH CONFIGURATION Since individual parts are very consistent in their charge injection, it is possible to replace the potentiometer with a pair of fixed resistors, and achieve less than 5mV error for all devices without adjustment. An alternative arrangement, using a standard TTL inverter to generate the required inversion, is shown in Figure 7. The capacitor needs to be increased, and becomes the only method of adjustment. A fixed value of 22pF is good for analog values referred to ground, while 35pF is optimum for AC coupled signals referred to -5V as shown in the figure. The choice of -5V is based on the virtual disappearance at this analog level of the transient component of switching charge injection. This combination will lead to a virtually “glitch-free” switch. 75Ω 15V 1µF VOUT 5V S1 ANALOG INPUT Typical Applications V+ VL S2 D1 D2 IN1 IN2 V- GND -15V 1kΩ CERMET NOT WIRE WOUND (NOTE) 75Ω Charge Compensation Techniques Charge injection results from the signals out of the level translation circuit being coupled through the gate-channel and gate-source/drain capacitances to the switch inputs and outputs. This feedthrough is particularly troublesome in Sample-and-Hold or Track-and-Hold applications, as it causes a Sample (Track) to Hold offset. The IH5352 has a typical injected charge of 30pC-50pC (corresponding to 30mV-50mV on a 1000pF capacitor), at VS-D of about 0V. This Sample (Track) to Hold offset can be compensated by bringing in a signal equal in magnitude but of the opposite polarity. The circuit of Figure 6 accomplishes this charge injection compensation by using one side of the device as a S & H (T & H) switch, and the other side as a generator of a compensating signal. The 1kΩ potentiometer allows the user to adjust the net injected charge to exactly zero for any analog voltage in the -5V to +5V range. 5 10pF CHOLD 1000pF +3V 0V TTL IN (STROBE) 1µF NOTE: Adjust pot for 0mVP-P step at VOUT with no analog (AC) signal present. FIGURE 6. CHARGE INJECTION COMPENSATION IH5352 VOUT DC BIAS VOLTAGE = -5V ANALOG INPUT S1 15V 5V V+ VL 75Ω D1 D2 IN1 IN2 22pF-35pF 1 14 2 13 3 12 4 1µF V- CHOLD 1000pF S2 GND SN7400 +5V 11 5 10 6 9 7 8 -15V +3V 0V TTL CONTROL IN ≈ +4V 0V FIGURE 7. ALTERNATIVE COMPENSATION CIRCUIT Overvoltage Protection 15V If sustained operation with no supplies but with analog signals applied is possible, it is recommended that diodes (such as 1N914) be inserted in series with the supply lines to the IH5352. Such conditions can occur if these signals come from a separate power supply or another location, for example. The diodes will be reverse biased under this type of operation, preventing heavy currents from flowing from the analog source through the IH5352. The same method of protection will provide over ±25V overvoltage protection on the analog inputs when the supplies are present. The schematic for this connection is shown in Figure 8. 1N914 5V 1µF S1 V+ VL S2 D1 D2 IN1 IN2 V- GND 1N914 -15V 1µF FIGURE 8. OVERVOLTAGE PROTECTION 6 IH5352 Typical Performance Curves 180 70 PIN 3 = PIN10 = +5V PIN 7 = -5V, TA = 25oC PIN 3 = +15V, PIN 7 = -15V PIN 10 = +5V, TA = 25oC 160 rDS(ON) (Ω) rDS(ON) (Ω) 60 50 140 120 40 100 30 -15 -10 -5 0 5 10 80 15 -5 ANALOG INPUT VOLTAGE (V) FIGURE 9. rDS(ON) vs ANALOG INPUT VOLTAGE WITH ±15V POWER SUPPLIES -100 TA = 25oC 90 -90 80 -80 70 60 50 TA = 25oC -70 -60 -50 -40 40 30 0.1 5 FIGURE 10. rDS(ON) vs ANALOG INPUT LEVEL WITH ±5V POWER SUPPLIES CROSSTALK (dB) OFF ISOLATION (dB) 100 0 ANALOG INPUT VOLTAGE (V) 1 10 FREQUENCY (MHz) -30 0.1 100 FIGURE 11. OFF ISOLATION vs FREQUENCY (SEE FIGURE 2) -3.3 1 10 FREQUENCY (MHz) FIGURE 12. CROSSTALK vs FREQUENCY (SEE FIGURE 3) TA = 25oC SWITCH ATTENUATION (dB) -3.4 -3.5 -3.6 -3.7 -3.8 -3.9 -4.0 0.1 1 10 FREQUENCY (MHz) 100 FIGURE 13. SWITCH ATTENUATION vs FREQUENCY (RL = 75Ω, SEE FIGURE 4) 7 100 IH5352 Die Characteristics DIE DIMENSIONS: PASSIVATION: 2617µm x 5233µm Type: PSG/Nitride PSG Thickness: 7kÅ ±1.4kÅ Nitride Thickness: 8kÅ ±1.2kÅ METALLIZATION: Type: Al Thickness: 10kÅ ±1kÅ WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2 Metallization Mask Layout IH5352 S1 IN1 D1 V+ (SUBSTRATE) IN2 D2 S2 GND IN3 D3 S3 V- IN4 D4 S4 VL All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. 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