[ /Title (IH515 1) /Subject (Dual SPDT, CMOS Analog Switch ) /Autho r () /Keywords (Intersil Corporation, semiconductor, Dual SPDT, CMOS Analog Switch ) /Creator () /DOCI NFO pdfmark IH5151 CT ODU ODUCT R P PR TE OLE UTE OBS UBSTIT G4030J rD E S DataoSheet SIBL -5051-2 S O P HI1 TM March 2000 File Number 3133.3 Dual SPDT, CMOS Analog Switch Features The IH5151 solid state analog switch is designed using an improved, high voltage CMOS technology. • Low rDS(ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Ω Key performance advantages in the IH5151 are TTL compatibility and ultra low power operation. rDS(ON) switch resistance is typically in the 14Ω to 18Ω area, for signals in the -10V to +10V range. Quiescent current is less than 10µA. The IH5151 also guarantees Break-Before-Make switching which is logically accomplished by extending the tON time (200ns typical) such that it exceeds tOFF time (120ns typical). This insures that an ON channel will be turned OFF before an OFF channel can turn ON. The need for external logic required to avoid channel to channel shorting during switching is thus eliminated. Part Number Information PART NUMBER TEMP. RANGE (oC) • Switches Greater than 20VP-P Signals with ±15V Supplies • Quiescent Current (Max) . . . . . . . . . . . . . . . . . . . . 100µA • Break-Before-Make Switching - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120ns - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200ns • TTL, CMOS Compatible • Complete Monolithic Construction • Supply Range. . . . . . . . . . . . . . . . . . . . . . . . . ±5V to ±15V Functional Diagram SWITCH STATE SHOWN FOR LOGIC “1” INPUT PACKAGE PKG. NO. VL V+ 12 IH5151MJE -55 to 125 16 Ld CERDIP F16.3 S1 Pinout S3 IH5151 (CERDIP) TOP VIEW 11 16 1 4 3 D1 D3 IN1 15 IN2 D1 1 16 S1 NC 2 15 IN1 D3 3 14 V- S3 4 13 GND S4 5 12 VL D4 6 11 V+ NC 7 10 IN2 D2 8 9 S2 S2 S4 10 9 8 5 6 13 D2 D4 14 V- GND TRUTH TABLE LOGIC SWITCH 1, 2 SWITCH 3, 4 0 Off On 1 On Off [ 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 IH5151 Schematic Diagram ONE SET OF SWITCHES SHOWN +15V (V+) Q3 Q5 Q7 Q20 Q18 D +15V S Q19 4kΩ 5kΩ Q2 100Ω Q1 V- Q8 TTL IN Q16 3kΩ Q17 Q9 GND Q10 V+ VL = +5V Q15 Q12 +15V +15V 5kΩ Q4 S Q6 Q11 D -15V (V-) 2 Q14 Q13 IH5151 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <36V V+ to VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VD to VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <±22V VL to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <33V VL to VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V Current (Any Terminal). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 75 18 Maximum Junction Temperature CERDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature. . . . . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V+ = +15V, V- = -15V, VL = +5V (NOTES 3, 5) -55oC 25oC 125oC UNITS RL = 1kΩ, VANALOG = -10V to +10V; (Figure 6, Note 4) - - 500 ns - - 250 ns Charge Injection, Q Figure 5 - 10 (Typ) - mV OFF Isolation, OIRR f = 1MHz, RL = 100Ω, CL ≤ 5pF (Figure 3) - 54 (Typ) - dB Crosstalk, CCRR Figure 2 - -54 (Typ) - dB PER CHANNEL PARAMETER TEST CONDITIONS DYNAMIC CHARACTERISTICS Turn ON Time, tON Turn OFF Time, tOFF DIGITAL INPUT CHARACTERISTICS Input Logic Current, IIN(ON) VIN = 2.4V (Note 2) ±1 ±1 ±10 µA Input Logic Current, IIN(OFF) VIN = 0.8V (Note 2) ±1 ±1 ±10 µA VD = ±10V, IS = -10mA 25 25 50 Ω - 10 (Typ) - Ω ANALOG SWITCH CHARACTERISTICS Drain-Source ON Resistance, rDS(ON) Channel-to-Channel rDS(ON) Match, ∆rDS(ON) - ±14 (Typ) - V Switch OFF Leakage Current, ID(OFF), IS(OFF) VANALOG = -10V to +10V - ±1.0 100 nA Switch ON Leakage Current, ID(ON)+IS(ON) VD = VS = -10V to +10V - ±1.0 100 nA + Power Supply Quiescent Current, I+ 10 10 100 µA - Power Supply Quiescent Current, I- 10 10 100 µA +5V Supply Quiescent Current, IL 10 10 100 µA Ground Quiescent Current, IGND 10 10 100 µA Minimum Analog Signal Handling Capability, VANALOG POWER SUPPLY CHARACTERISTICS NOTES: 2. Some channels are turned on by high (1) logic inputs and other channels are turned on by low (0) inputs; however 0.8V to 2.4V describes the minimum range for switching properly. Refer to logic diagrams to find logical value of logic input required to produce ON or OFF state. 3. Typical values are for design aid only, not guaranteed or production tested. 4. For IH5151 devices, channels which are off for logic input ≥ 2.4V (Pins 3 and 4, 5 and 6) have slower tON time, than channels on Pins 1, 16 and 8, 9. This is done so switch will maintain break-before-make action when connected in DT configuration, i.e., Pin 1 connected in Pin 3. 5. Min or Max value, unless otherwise specified. 3 IH5151 Test Circuits and Waveforms 100 90 80 rDS(ON) (Ω) 70 60 50 40 ±5V SUPPLIES 30 ±15V SUPPLIES 20 10 0 -12 -10 -8 -6 -4 -2 0 2 VANALOG (V) 4 6 8 10 12 FIGURE 1. rDS(ON) vs ANALOG INPUT VOLTAGE -120 CCRR = 20LOG CROSSTALK (dB) -100 VOUT (mVP-P) 2000mVP-P OFF STATE -80 VOUT 100Ω -60 -40 ON STATE -20 2VP-P AT 1MHz 51Ω 0 100Ω 1 10 100 1K 10K FREQUENCY (Hz) 100K 1M FIGURE 2A. CROSSTALK vs FREQUENCY FIGURE 2B. TEST CIRCUIT FIGURE 2. CROSSTALK 120 OIRR = 20LOG OFF ISOLATION (dB) 100 2000mVP-P VOUT (mVP-P) 80 2VP-P AT 1MHz 60 51Ω 40 OFF STATE 20 VOUT 100Ω 0 1 10 100 1K 10K FREQUENCY (Hz) 100K 1M FIGURE 3A. OFF ISOLATION vs FREQUENCY FIGURE 3. OFF ISOLATION 4 FIGURE 3B. TEST CIRCUIT IH5151 Test Circuits and Waveforms (Continued) IQUIESCENT (EITHER + OR - SUPPLY) (µA) 2000 200 3V LOGIC INPUT 0V 0.1T 20 T I ƒ= T 2 1 10 100 1K 10K 100K LOGIC FREQUENCY AT 10% DUTY CYCLE (Hz) FIGURE 4A. SUPPLY CURRENT vs FREQUENCY FIGURE 4B. LOGIC INPUT WAVEFORM FIGURE 4. SUPPLY CURRENT vs LOGIC FREQUENCY VOUT A 1 16 1kΩ 2 15 10pF ANALOG INPUT 3V tON ±10V 0V 3 14 -15V 4 13 tOFF VOUT +10V +3V LOGIC INPUT 0V 0V LOGIC INPUT VOUT 10nF VOUT B 5 12 +5V 6 11 +15V 7 10 FIGURE 5. CHARGE INJECTION TEST CIRCUIT -10V VOUT 9 ±10V 8 10pF 0V tON 1kΩ tOFF FIGURE 6. tON AND tOFF TEST CIRCUIT AND MEASUREMENT POINTS Typical Applications Nulling Out Charge Injection Charge injection (QINJ on spec. sheet) is caused by gate to drain, or gate to source capacitance of the output switch MOSFETs. The gates of these MOSFETs typically swing from -15V to +15V as a rapidly changing pulse; thus this 30VP-P pulse is coupled through gate capacitance to output load capacitance, and the output “step” is a voltage divider from this combination. For example: To null this error step out to zero the circuit in Figure 7 can be used. 27pF 1000pF S&H CAPACITOR 1 0V 2 15 3 14 4 13 5 12 +5V C GATE = 1.5pF, C LOAD = 1000pF, then 6 11 +15V 1.5pF Qinject (V P-P ) = --------------------- × 30V step = 45mV P-P 1000pF 7 10 8 9 C GATE Qinject (V P-P ) ≅ -------------------- × 30V step. C LOAD i.e., Thus if you are using a switch in a Sample and Hold application with CSAMPLE = 1000pF, a 45mVP-P “Sampleto-Hold Error Step” will occur. 5 3V 16 FIGURE 7. ADJUSTABLE CHARGE INJECTION COMPENSATION CIRCUIT TTL STROBE 50K POT -15V IH5151 The circuit in Figure 7 nulls out charge injection effects on switch pins 1 and 16; a similar circuit would be required on switch pins 8 and 9. Simply adjust the pot until VOUT = 0mVP-P pulse, with VANALOG = 0V. If you do not desire to do any adjusting, but wish the least amount of charge injection possible, then the circuit in Figure 8 should be used. 27pF 1000pF S&H CAPACITOR 3V 1 16 2 15 3 14 4 13 5 12 +5V 39kΩ 6 11 +15V -15V 7 10 8 9 0V TTL 10 STROBE kΩ Fault Condition Protection If your system has analog voltage levels which are independent of the ±15V (Power Supplies), and these analog levels can be present when supplies are shut off, you should add fault protection diodes as shown in Figure 9. If the analog input levels are below ±15V, the PN junctions of Q13 and Q15 are reversed biased. However if the ±15V supplies are shut off and analog levels are still present, the configuration becomes as shown in Figure 10. The need for the diodes in this circumstance is shown in Figure 11. If ANALOG INPUT is greater than 1V, then the PN junction of Q15 is forward biased and excessive current will be drawn. The addition of 1N914 diodes prevents the fault currents from destroying the switch. A similar event would occur if ANALOG INPUT was less than or equal to -1V, wherein Q13 would become forward biased. The 1N914 diodes form a “back to back” diode arrangement with Q13 and Q15 bodies. This structure provides a degree of overvoltage protection when supplies are on normally, and analog input level exceeds supplies. FIGURE 8. NO-ADJUST CHARGE INJECTION COMPENSATION CIRCUIT This configuration will produce a typical charge injection of VOUT ±10mVP-P into the 1000pF S & H capacitor shown. This circuit will switch up to about ±8V ANALOG overvoltages. Beyond this drain (N) to body (P) breakdown VOLTAGE of Q13 limits overvoltage protection. FROM DRIVER 1 16 2 15 3 14 4 13 5 12 +5V 6 11 7 10 8 9 P P 1N914 Q15 N +15 -15V 1 1N914 ANALOG INPUT OUTPUT SWITCH PAIR 16 -15V Q13 +15V 5 P N N FROM DRIVER FIGURE 9. ADDING DIODES PROTECTS SWITCH FIGURE 10. SWITCH WITHOUT PROTECTION DIODES Q15 Q15 N N 0V WHEN +15V SUPPLY SHUT OFF 1 1N914 ANALOG INPUT 16 0V WHEN -15V IS SHUT OFF +15V 16 1 SAY -10V TO +10V N Q 13 FIGURE 11. FAULT CONDITION WITHOUT PROTECTION DIODES 6 OVERVOLTAGE ANALOG INPUT -15V 1N914 P P N P P P P N N Q13 FIGURE 12. FAULT CONDITION WITH PROTECTION DIODES IH5151 Die Characteristics DIE DIMENSIONS: PASSIVATION: 2515µm x 3074µm Type: PSG Over Nitride PSG Thickness: 7kÅ ±1.4kÅ Nitride Thickness: 8kÅ ±1.2kÅ METALLIZATION: Type: Al Thickness: 10kÅ ±1kÅ WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2 Metallization Mask Layout IH5151 PIN 5 S4 PIN 4 S3 PIN 3 D3 PIN 6 D4 PIN 8 D2 PIN 1 D1 PIN 9 S2 PIN 6 S1 PIN 10 IN2 PIN 5 IN1 PIN 11 PIN 12 V+ VL SUBSTRATE PIN 13 GND PIN 14 V- All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 7