X9C102, X9C103, X9C104, X9C503
®
Data Sheet
July 20, 2009
Digitally Controlled Potentiometer
(XDCP™)
Features
The X9C102, X9C103, X9C104, X9C503 are Intersils’
digitally controlled (XDCP) potentiometers. The device
consists of a resistor array, wiper switches, a control section,
and non-volatile memory. The wiper position is controlled by
a three-wire interface.
• Three-Wire Serial Interface
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs.
The position of the wiper can be stored in non-volatile
memory and then be recalled upon a subsequent power-up
operation.
• 99 Resistive Elements
- Temperature Compensated
- End-to-End Resistance, ±20%
- Terminal Voltages, ±5V
FN8222.3
• Solid-State Potentiometer
The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications ranging from control to signal processing to
parameter adjustment.
Pinout
• 100 Wiper Tap Points
- Wiper Position Stored in Non-volatile Memory and
Recalled on Power-up
• Low Power CMOS
- VCC = 5V
- Active Current, 3mA max.
- Standby Current, 750µA max.
• High Reliability
- Endurance, 100,000 Data Changes per Bit
- Register Data Retention, 100 years
• X9C102 = 1kΩ
X9C102, X9C103, X9C104, X9C503
(8 LD SOIC, 8 LD PDIP)
TOP VIEW
• X9C103 = 10kΩ
• X9C503 = 50kΩ
• X9C104 = 100kΩ
INC
1
8
VCC
U/D
2
7
CS
VH/RH
3
6
VL/RL
VSS
4
5
VW/RW
• Packages
- 8 Ld SOIC
- 8 Ld PDIP
• Pb-Free Available (RoHS Compliant)
Block Diagram
U/D
INC
CS
7-BIT
UP/DOWN
COUNTER
99
98
VCC (SUPPLY VOLTAGE)
UP/DOWN
INCREMENT (INC)
DEVICE
SELECT
97
7-BIT
NON-VOLATILE
MEMORY
VH/RH
(U/D)
CONTROL
AND
MEMORY
RH/VH
RW/VW
(CS)
VL/RL
96
ONE
OF
ONEHUNDRED
DECODER
TRANSFER
GATES
RESISTOR
ARRAY
2
VSS (GROUND)
GENERAL
VCC
GND
STORE AND
RECALL
CONTROL
CIRCUITRY
1
0
DETAILED
1
RL/VL
RW/VW
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9C102, X9C103, X9C104, X9C503
Ordering Information
PART
NUMBER
PART
MARKING
RTOTAL
(kΩ)
TEMP RANGE
(°C)
1
0 to +70
8 Ld PDIP
MDP0031
8 Ld PDIP (Pb-free)
MDP0031
PACKAGE
PACKAGE
DWG. #
X9C102P
X9C102P
X9C102PZ (Notes 1, 2)
X9C102P Z
0 to +70
X9C102PI
X9C102P I
-40 to +85
8 Ld PDIP
MDP0031
X9C102PIZ (Notes 1, 2)
X9C102P ZI
-40 to +85
8 Ld PDIP (Pb-free)
MDP0031
X9C102S*, **
X9C102S
0 to +70
8 Ld SOIC
MDP0027
X9C102SZ* (Note 1)
X9C102S Z
0 to +70
8 Ld SOIC (Pb-free)
MDP0027
X9C102SI*, **
X9C102S I
-40 to +85
8 Ld SOIC
MDP0027
X9C102SIZ*, **
(Note 1)
X9C102S ZI
8 Ld SOIC (Pb-free)
MDP0027
0 to +70
8 Ld PDIP
MDP0031
X9C103P Z
0 to +70
8 Ld PDIP (Pb-free)
MDP0031
X9C103PI
X9C103P I
-40 to +85
8 Ld PDIP
MDP0031
X9C103PIZ (Note 1)
X9C103P ZI
-40 to +85
8 Ld PDIP (Pb-free)
MDP0031
X9C103S*, **
X9C103S
0 to +70
8 Ld SOIC
MDP0027
X9C103SZ*, ** (Note 1)
X9C103S Z
0 to +70
8 Ld SOIC (Pb-free)
MDP0027
X9C103SI*, **
X9C103S I
-40 to +85
8 Ld SOIC
MDP0027
X9C103P
X9C103P
X9C103PZ (Notes 1, 2)
X9C103SIZ*, **
(Note 1)
-40 to +85
10
X9C103S ZI
8 Ld SOIC (Pb-free)
MDP0027
0 to +70
8 Ld PDIP
MDP0031
X9C503P Z
0 to +70
8 Ld PDIP (Pb-free)
MDP0031
X9C503PI
X9C503P I
-40 to +85
8 Ld PDIP
MDP0031
X9C503PIZ (Notes 1, 2)
X9C503P ZI
-40 to +85
8 Ld PDIP (Pb-free)
MDP0031
X9C503S*
X9C503S
0 to +70
8 Ld SOIC
MDP0027
X9C503SZ* (Note 1)
X9C503S Z
0 to +70
8 Ld SOIC (Pb-free)
MDP0027
X9C503SI*, **
X9C503S I
-40 to +85
8 Ld SOIC
MDP0027
X9C503P
X9C503P
X9C503PZ (Notes 1, 2)
X9C503SIZ*, **
(Note 1)
-40 to +85
50
X9C503S ZI
8 Ld SOIC (Pb-free)
MDP0027
0 to +70
8 Ld PDIP
MDP0031
X9C104P I
-40 to +85
8 Ld PDIP
MDP0031
X9C104PIZ (Notes 1, 2)
X9C104P ZI
-40 to +85
X9C104S*, **
X9C104S
X9C104P
X9C104P
X9C104PI
-40 to +85
100
8 Ld PDIP (Pb-free)
MDP0031
0 to +70
8 Ld SOIC
MDP0027
X9C104SZ*, ** (Note 1)
X9C104S Z
0 to +70
8 Ld SOIC (Pb-free)
MDP0027
X9C104SI*, **
X9C104S I
-40 to +85
8 Ld SOIC
MDP0027
X9C104SIZ*, ** (Note 1)
X9C104S ZI
-40 to +85
8 Ld SOIC (Pb-free)
MDP0027
*Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
**Add “T2” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
2. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
2
FN8222.3
July 20, 2009
X9C102, X9C103, X9C104, X9C503
Pin Descriptions
PIN
NUMBER
PIN NAME
1
INC
INCREMENT The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or
decrement the counter in the direction indicated by the logic level on the U/D input.
2
U/D
UP/DOWN The U/D input controls the direction of the wiper movement and whether the counter is incremented or
decremented.
3
VH/RH
4
VSS
5
VW/RW
VW/RW VW/RW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The
position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically
40Ω.
6
RL/VL
RL/VL The low (VL/RL) terminals of the X9C102, X9C103, X9C104, X9C503 are equivalent to the fixed terminals of a
mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL
references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and
not the voltage potential on the terminal.
7
CS
CS The device is selected when the CS input is LOW. The current counter value is stored in non-volatile memory when
CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9C102, X9C103,
X9C104, X9C503 device will be placed in the low power standby mode until the device is selected once again.
8
VCC
VCC
DESCRIPTION
VH/RH The high (VH/RH) terminals of the X9C102, X9C103, X9C104, X9C503 are equivalent to the fixed terminals of
a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL
references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and
not the voltage potential on the terminal.
VSS
3
FN8222.3
July 20, 2009
X9C102, X9C103, X9C104, X9C503
Absolute Maximum Ratings
Thermal Information
Voltage on CS, INC, U/D and VCC with Respect to VSS . -1V to +7V
Voltage on VH/RH and VL/RL Referenced to VSS . . . . . . . -8V to +8V
ΔV = |VH/RH - VL/RL|
X9C102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V
X9C103, X9C104, and X9C503 . . . . . . . . . . . . . . . . . . . . . . . .10V
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.8mA
Power Rating
X9C102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16mW
X9C103 X0C104, and X9C503 . . . . . . . . . . . . . . . . . . . . . .10mW
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through-hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Recommended Operating Conditions
Commercial Temperature Range. . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range (VCC) . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Electrical Specifications
Over recommended operating conditions unless otherwise stated.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 6)
MAX
UNIT
POTENTIOMETER CHARACTERISTICS
RTOTAL
End-to-End Resistance Variation
-20
+20
%
VVH/RH
VH Terminal Voltage
-5
+5
V
VVL/RL
VL Terminal Voltage
-5
+5
V
-4.4
4.4
mA
100
Ω
IW
Wiper Current
RW
Wiper Resistance
Wiper Current = ±1mA
Resistor Noise (Note 7)
Ref 1kHz
-120
dBV
Charge Pump Noise (Note 7)
@ 850kHz
20
mVRMS
1
%
40
Resolution
Absolute Linearity (Note 3)
VW(n)(actual) - VW(n)(EXPECTED)
-1
+1
MI (Note 5)
Relative Linearity (Note 4)
VW(n + 1)(ACTUAL) - [VW(n) + MI]
-0.2
+0.2
MI (Note 5)
RTOTAL Temperature Coefficient
X9C103, X9C503, X9C104
±300 (Note 7)
ppm/°C
RTOTAL Temperature Coefficient
X9C102
±600 (Note 7)
ppm/°C
±20
ppm/°C
10/10/25
pF
Ratiometric Temperature Coefficient
CH/CL/CW
(Note 7)
Potentiometer Capacitances
See “Circuit #3 SPICE Macro
Model” on page 5.
DC OPERATING CHARACTERISTICS
ICC
VCC Active Current
CS = VIL, U/D = VIL or VIH and
INC = 0.4V to 2.4V at Max tCYC
ISB
Standby Supply Current
CS = VCC - 0.3V, U/D and
INC = VSS or VCC - 0.3V
ILI
CS, INC, U/D Input Leakage Current
VIN = VSS to VCC
VIH
CS, INC, U/D input HIGH Voltage
VIL
CS, INC, U/D input LOW Voltage
CIN
CS, INC, U/D Input Capacitance (Note 7)
4
1
3
mA
200
750
µA
±10
µA
2
V
0.8
VCC = 5V, VIN = VSS, TA = +25°C,
f = 1MHz
10
V
pF
FN8222.3
July 20, 2009
X9C102, X9C103, X9C104, X9C503
Electrical Specifications
Over recommended operating conditions unless otherwise stated. (Continued)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 6)
MAX
UNIT
AC OPERATION CHARACTERISTICS
tCl
CS to INC Setup
100
ns
tlD
INC HIGH to U/D Change
100
ns
tDI
U/D to INC Setup
2.9
µs
tlL
INC LOW Period
1
µs
tlH
INC HIGH Period
1
µs
tlC
INC Inactive to CS Inactive
1
µs
tCPH
CS Deselect Time (STORE)
20
ms
tCPH
CS Deselect Time (NO STORE)
100
ns
tIW (5)
INC to VW/RW Change
tCYC
INC Cycle Time
tCYC
INC Input Rise and Fall Time
t R , tF
Power-up to Wiper Stable (Note 7)
tPU
100
µs
2
µs
500
µs
500
VCC Power-up Rate (Note 7)
µs
0.2
50
V/ms
NOTES:
3. Absolute linearity is utilized to determine actual wiper voltage vs expected voltage = [VW(n)(actual) - VW(n)(expected )] = ±1 MI Maximum.
4. Relative linearity is a measure of the error in step size between taps = VW(n + 1) - [VW(n) + MI] = +0.2 MI.
5. 1 MI = Minimum Increment = RTOT/99.
6. Typical values are for TA = +25°C and nominal supply voltage.
7. This parameter is not 100% tested.
Test Circuit #1
Test Circuit #2
Circuit #3 SPICE Macro Model
VH/RH
VR/RH
RTOTAL
TEST POINT
VS
TEST POINT
Vw/RW
VL/RL
VL/RL
VW/Rw
FORCE
CURRENT
RH
RL
CL
CW
10pF
25pF
CL
10pF
RW
Power-up and Down Requirements
Endurance and Data Retention
PARAMETER
Medium Endurance
Data Retention
MIN
100,000
100
UNIT
Data changes per bit
per register
years
At all times, voltages on the potentiometer pins must be less
than ±VCC. The recall of the wiper position from non-volatile
memory is not in effect until the VCC supply reaches its final
value. The VCC ramp rate specification is always in effect.
AC Conditions of Test
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
10ns
Input Reference Levels
1.5V
5
FN8222.3
July 20, 2009
X9C102, X9C103, X9C104, X9C503
AC Timing Diagram
CS
tCYC
tCI
tIL
tIC
tIH
tCPH
90%
INC
90%
10%
tID
tDI
tF
tR
U/D
tIW
MI (NOTE)
VW
NOTE: MI REFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE VW OUTPUT DUE TO A CHANGE IN THE WIPER POSITION.
Pin Descriptions
Principles of Operation
RH/VH and RL/VL
There are three sections of the X9C102, X9C103, ISL9C104
and ISL9C503: the input control, counter and decode section;
the non-volatile memory; and the resistor array. The input
control section operates just like an up/down counter. The
output of this counter is decoded to turn on a single electronic
switch connecting a point on the resistor array to the wiper
output. Under the proper conditions, the contents of the
counter can be stored in non-volatile memory and retained for
future use. The resistor array is comprised of 99 individual
resistors connected in series. At either end of the array and
between each resistor is an electronic switch that transfers the
potential at that point to the wiper.
The high (VH/RH) and low (V /R ) terminals of the
L L
ISLX9C102, X9C103, X9C104, X9C503 are equivalent to
the fixed terminals of a mechanical potentiometer. The
minimum voltage is -5V and the maximum is +5V. The
terminology of VH/RH and V /R references the relative
L L
position of the terminal in relation to wiper movement
direction selected by the U/D input and not the voltage
potential on the terminal.
RW/VW
VW/RW is the wiper terminal, and is equivalent to the
movable terminal of a mechanical potentiometer. The
position of the wiper within the array is determined by the
control inputs. The wiper terminal series resistance is typically
40Ω.
Up/Down (U/D)
The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
counter in the direction indicated by the logic level on the
U/D input.
Chip Select (CS)
The device is selected when the CS input is LOW. The
current counter value is stored in non-volatile memory when
CS is returned HIGH while the INC input is also HIGH. After
the store operation is complete the ISLX9C102, X9C103,
X9C104, X9C503 device will be placed in the low power
standby mode until the device is selected once again.
6
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
The electronic switches on the device operate in a
“make-before-break” mode when the wiper changes tap
positions. If the wiper is moved several positions, multiple
taps are connected to the wiper for tIW (INC to VW/RW
change). The RTOTAL value for the device can temporarily be
reduced by a significant amount if the wiper is moved
several positions.
When the device is powered-down, the last wiper position
stored will be maintained in the non-volatile memory. When
power is restored, the contents of the memory are recalled
and the wiper is reset to the value last stored.
The internal charge pump allows a wide range of voltages
(from -5V to 5V) applied to XDCP terminals yet given a
convenience of single power supply. The typical charge
pump noise of 20mV at 850kHz should be taken in
consideration when designing an application circuit.
FN8222.3
July 20, 2009
X9C102, X9C103, X9C104, X9C503
Instructions and Programming
The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS set LOW, the device is
selected and enabled to respond to the U/D and INC inputs.
HIGH to LOW transitions on INC will increment or decrement
(depending on the state of the U/D input) a 7-bit counter. The
output of this counter is decoded to select one of one-hundred
wiper positions along the resistive array.
The value of the counter is stored in non-volatile memory
whenever CS transitions HIGH while the INC input is also
HIGH.
The system may select the X9Cxxx, move the wiper and
deselect the device without having to store the latest wiper
position in non-volatile memory. After the wiper movement is
performed as previously described and once the new
position is reached, the system must keep INC LOW while
taking CS HIGH. The new wiper position will be maintained
until changed by the system or until a power-down/up cycle
recalled the previously stored data.
This procedure allows the system to always power-up to a
pre-set value stored in non-volatile memory; then during
system operation, minor adjustments could be made. The
adjustments might be based on user preference, i.e.: system
parameter changes due to temperature drift, etc.
The state of U/D may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.
Mode Selection
CS
INC
U/D
MODE
L
H
Wiper Up
L
L
Wiper Down
H
X
Store Wiper Position
X
X
Standby Current
L
X
No Store, Return to Standby
L
H
Wiper Up (not recommended)
L
L
Wiper Down (not recommended)
H
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Performance Characteristics
Contact the factory for more information.
Applications Information
Electronic digitally controlled (XCDP) potentiometers provide
three powerful application advantages:
1. The variability and reliability of a solid-state
potentiometer.
2. The flexibility of computer-based digital controls.
3. The retentivity of non-volatile memory used for the
storage of multiple potentiometer settings or data.
7
FN8222.3
July 20, 2009
X9C102, X9C103, X9C104, X9C503
Basic Configurations of Electronic Potentiometers
VR
VR
VH/RH
VW/RW
VL/RL
I
THREE TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER
TWO TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT
Basic Circuits
+V
R1
+V
+5V
VS
+V
+5V
VW
VREF
X
VW/RW
VOUT
–
VO
–
OP-07
+
LM308A
+
-5V
+V
R2
-5V
R1
VW/RW
VOUT = VW/RW
(a)
BUFFERED REFERENCE VOLTAGE
CASCADING TECHNIQUES
R1
VIN
VO (REG)
317
VO = (1+R2/R1)VS
(b)
NONINVERTING AMPLIFIER
R2
VS
VS
LT311A
100kΩ
R1
VO
+
10kΩ
10kΩ
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
+12V
}
10kΩ
}
TL072
R2
VO
+
–
Iadj
–
R1
R2
VUL = {R1/(R1 + R2)} VO(MAX)
VLL = {R1/(R1 + R2)} VO(MIN)
-12V
(FOR ADDITIONAL CIRCUITS SEE AN1145)
OFFSET VOLTAGE ADJUSTMENT
VOLTAGE REGULATOR
8
COMPARATOR WITH HYSTERESIS
FN8222.3
July 20, 2009
X9C102, X9C103, X9C104, X9C503
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
9
FN8222.3
July 20, 2009
X9C102, X9C103, X9C104, X9C503
Plastic Dual-In-Line Packages (PDIP)
E
D
A2
SEATING
PLANE
L
N
A
PIN #1
INDEX
E1
c
e
b
A1
NOTE 5
1
eA
eB
2
N/2
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
TOLERANCE
A
0.210
0.210
0.210
0.210
0.210
MAX
A1
0.015
0.015
0.015
0.015
0.015
MIN
A2
0.130
0.130
0.130
0.130
0.130
±0.005
b
0.018
0.018
0.018
0.018
0.018
±0.002
b2
0.060
0.060
0.060
0.060
0.060
+0.010/-0.015
c
0.010
0.010
0.010
0.010
0.010
+0.004/-0.002
D
0.375
0.750
0.750
0.890
1.020
±0.010
E
0.310
0.310
0.310
0.310
0.310
+0.015/-0.010
E1
0.250
0.250
0.250
0.250
0.250
±0.005
e
0.100
0.100
0.100
0.100
0.100
Basic
eA
0.300
0.300
0.300
0.300
0.300
Basic
eB
0.345
0.345
0.345
0.345
0.345
±0.025
L
0.125
0.125
0.125
0.125
0.125
±0.010
N
8
14
16
18
20
Reference
NOTES
1
2
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
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10
FN8222.3
July 20, 2009