X9319
®
Data Sheet
September 26, 2006
DESCRIPTION
Digitally Controlled Potentiometer
(XDCP™)
The Intersil X9319 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory.
The wiper position is controlled by a 3-wire interface.
FEATURES
•
•
•
•
•
•
•
•
•
•
Solid-state potentiometer
3-wire serial interface
Terminal voltage, 0 to +10V
100 wiper tap points
—Wiper position stored in nonvolatile memory
and recalled on power-up
99 resistive elements
—Temperature compensated
—End to end resistance range ±20%
Low power CMOS
—VCC = 5V
—Active current, 3mA max.
—Standby current, 1mA max.
High reliability
—Endurance, 100,000 data changes per bit
—Register data retention, 100 years
RTOTAL value = 10kΩ and 50kΩ
Packages
—8 Ld SOIC and PDIP
Pb-free plus anneal available (RoHS compliant)
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper switching network. Between each element and at either end
are tap points accessible to the wiper terminal. The
position of the wiper element is controlled by the CS,
U/D, and INC inputs. The position of the wiper can be
stored in nonvolatile memory and then be recalled
upon a subsequent power-up operation.
The device can be used as a three-terminal potentiometer
for voltage control or as a two-terminal variable resistor for
current control in a wide variety of applications.
PIN CONFIGURATION
PDIP/SOIC
APPLICATIONS
•
•
•
•
•
FN8185.2
INC
1
8
VCC
U/D
2
7
CS
RH
3
6
RL
VSS
4
5
RW
X9319
LCD bias control
DC bias adjustment
Gain and offset trim
Laser diode bias control
Voltage regulator output control
BLOCK DIAGRAM
U/D
INC
CS
VCC (Supply Voltage)
Device Select
(CS)
Control
and
Memory
RH
99
98
97
RH
Up/Down
(U/D)
Increment
(INC)
Up/Down
Counter
7-Bit
Nonvolatile
Memory
RW
RL
One 96
of
One
Hundred
Decoder
Wiper
Switches
Resistor
Array
2
VSS (Ground)
General
VCC
VSS
Store and
Recall
Control
Circuitry
1
0
RL
RW
Detailed
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9319
Ordering Information
PART NUMBER
PART MARKING
RTOTAL (kΩ)
TEMP RANGE (°C)
PACKAGE
PKG. DWG. #
10
0 to +70
8 Ld PDIP
MDP0031
-40 to +85
8 Ld PDIP
MDP0031
MDP0027
X9319WP8
X9319WP
X9319WP8I
X9319WP I
X9319WS8*
X9319W
0 to +70
8 Ld SOIC (150 mil)
X9319WS8Z* (Note)
X9319W Z
0 to +70
8 Ld SOIC (150 mil) (Pb-free) MDP0027
X9319WS8I*
X9319W I
-40 to +85
8 Ld SOIC (150 mil)
X9319WS8IZ* (Note)
X9319W ZI
-40 to +85
8 Ld SOIC (150 mil) (Pb-free) MDP0027
X9319UP8I
X9319UP I
-40 to +85
8 Ld PDIP
MDP0031
X9319US8I*
X9319U I
-40 to +85
8 Ld SOIC (150 mil)
MDP0027
X9319US8IZ (Note)
X9319U ZI
-40 to +85
8 Ld SOIC (150 mil) (Pb-free) MDP0027
50
MDP0027
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN DESCRIPTIONS
DIP/SOIC
Symbol
1
INC
Increment. Toggling INC while CS is low moves the wiper either up or down.
Brief Description
2
U/D
Up/Down. The U/D input controls the direction of the wiper movement.
3
RH
The high terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.
4
VSS
Ground.
5
RW
The wiper terminal is equivalent to the movable terminal of a mechanical potentiometer.
6
The low terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.
7
RL
CS
8
VCC
Chip Select. The device is selected when the CS input is LOW, and de-selected when CS is
high.
Supply Voltage.
2
FN8185.2
September 26, 2006
X9319
ABSOLUTE MAXIMUM RATINGS
COMMENT
Junction Temperature under bias...... -65°C to +135°C
Storage temperature ..........................-65 C to +150 C
Voltage on CS, INC, U/D and VCC
with respect to VSS ................................. -1V to +7V
RH, RW, RL to ground..........................................+12V
Lead temperature (soldering 10s) ................... +300 C
IW (10s) ..............................................................±6mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
POTENTIOMETER CHARACTERISTICS
(VCC = 5V ±10%, TA = Full Operating Temperature Range unless otherwise stated)
Limits
Symbol
Parameter
VRH/RL
Typ.(4)
Min.
+20
%
See ordering information
for values
RH/RL terminal voltage
VSS
10
V
VSS = 0V
25
mW
200
Ω
+3.0
mA
See test circuit
-120
dBV
Ref: 1kHz
1
%
40
Wiper current(5)
Noise(7)
-3.0
Resolution
Absolute linearity(1)
-1
Relative linearity(2)
-0.2
RTOTAL temperature coefficient(5)
VCC
+1
MI(3)
+0.2
MI(3)
±300
Ratiometric temperature coefficient(5),(6)
CH/CL/CW(5)
Test Conditions/Notes
-20
Wiper resistance
IW
Unit
End to end resistance tolerance
Power rating
RW
Max.
-20
Potentiometer capacitances
+20
4.5
V(RH) = 10V,
V(RL) = 0V
ppm/ C
ppm/ C
10/10/25
Supply Voltage
IW = 1mA
pF
5.5
See equivalent circuit
V
D.C. OPERATING CHARACTERISTICS
(VCC = 5V ±10%, TA = Full Operating Temperature Range unless otherwise stated)
Limits
Symbol
Parameter
Typ.(4)
Max.
Unit
1
3
mA
CS = VIL, U/D = VIL or VIH and
INC = 0.4V/2.4V @ min. tCYC
RL, RH, RW not connected
300
1000
µA
CS ≥ 2.4V, U/D and INC = 0.4V
RL, RH, RW not connected
-10
+10
µA
VIN = VSS to VCC
Min.
ICC
VCC active current (Increment)
ISB
Standby supply current
ILI
CS, INC, U/D input leakage
current
VIH
CS, INC, U/D input HIGH voltage
2
VCC + 1
V
VIL
CS, INC, U/D input LOW voltage
-1
0.8
V
10
pF
CIN
(5)
CS, INC, U/D input capacitance
3
Test Conditions
VCC = 5V, VIN = VSS, TA = +25 C,
f = 1MHz
FN8185.2
September 26, 2006
X9319
ENDURANCE AND DATA RETENTION
(VCC = 5V ±10%, TA = Full Operating Temperature Range)
Parameter
Min.
Unit
Minimum endurance
100,000
Data changes per bit
Data retention
100
Years
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(RW(n)(actual)) - V(RW(n)(expected))]/MI
V(RW(n)(expected)) = n(V(RH) - V(RL))/99 + V(RL), with n from 0 to 99.
(2) Relative linearity is a measure of the error in step size between taps = [V(RW(n+1)) - (V(RW(n)) - MI)]/MI
(3) 1 Ml = Minimum Increment = [V(RH) - V(RL)]/99.
(4) Typical values are for TA = 25 C and nominal supply voltage.
(5) Guaranteed by device characterization.
(6) Ratiometric temperature coefficient = (V(RW)T1(n) - V(RW)T2(n))/[V(RW)T1(n)(T1 - T2) x 106], with T1 & T2 being 2 temperatures,
and n from 0 to 99.
(7) Measured with wiper at tap position 31, RL grounded, using test circuit.
Test Circuit
Equivalent Circuit
RTOTAL
Test Point
RH
CW
CH
RW
Force
Current
CL
RL
10pF
25pF
10pF
RW
A.C. CONDITIONS OF TEST
Input pulse levels
0.8V to 2.0V
Input rise and fall times
10ns
Input reference levels
1.4V
4
FN8185.2
September 26, 2006
X9319
A.C. OPERATING CHARACTERISTICS
(VCC = 5V ±10%, TA = Full Operating Temperature Range unless otherwise stated)
Limits
Symbol
tCl
Parameter
Typ.(4)
Min.
Unit
Max.
CS to INC setup
100
ns
(5)
INC HIGH to U/D change
100
ns
(5)
U/D to INC setup
1
µs
tlL
INC LOW period
1
µs
tlH
INC HIGH period
1
µs
tlC
INC inactive to CS inactive
1
µs
tCPHS
CS deselect time (STORE)
20
ms
CS deselect time (NO STORE)
1
µs
tlD
tDI
tCPHNS(5)
tIW(5)
INC to RW change
tCYC
INC cycle time
tR, tF(5)
tPU
(5)
(5)
tR VCC
100
500
µs
4
µs
INC input rise and fall time
500
µs
Power-up to wiper stable
500
µs
50
V/ms
VCC power-up rate
0.2
POWER-UP AND DOWN REQUIREMENTS
In order to prevent unwanted tap position changes, or an inadvertant store, bring the CS and INC high before or concurrently with the VCC pin on powerup. The potentiometer voltages must be applied after this sequence is completed.
During power-up, the data sheet parameters for the DCP do not fully apply until 1 millisecond after VCC reaches its
final value. The VCC ramp spec is always in effect.
A.C. TIMING
CS
tCYC
tCI
tIL
tIC
tIH
tCPHNS
tCPHS
90%
90%
10%
INC
tID
tDI
tF
tR
U/D
tIW
MI
RW
5
(3)
FN8185.2
September 26, 2006
X9319
PIN NAMES
PIN DESCRIPTIONS
RH and RL
Symbol
The high (RH) and low (RL) terminals of the X9319 are
equivalent to the fixed terminals of a mechanical
potentiometer. The terminology of RL and RH references the relative position of the terminal in relation to
wiper movement direction selected by the U/D input
and not the voltage potential on the terminal.
Description
RH
High terminal
RW
Wiper terminal
RL
Low terminal
VSS
Ground
VCC
Supply voltage
RW
U/D
Up/Down control input
Rw is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the
control inputs. The wiper terminal series resistance is
typically 40Ω.
INC
Increment control input
CS
Chip select control input
Up/Down (U/D)
The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented.
Increment (INC)
The INC input is negative-edge triggered. Toggling
INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic
level on the U/D input.
Chip Select (CS)
The device is selected when the CS input is LOW. The
current counter value is stored in nonvolatile memory
when CS is returned HIGH while the INC input is also
HIGH. After the store operation is complete the X9319
will be placed in the low power standby mode until the
device is selected once again.
PIN CONFIGURATION
PDIP/SOIC
8
VCC
7
CS
3
6
RL
4
5
RW
INC
1
U/D
2
RH
VSS
X9319
6
PRINCIPLES OF OPERATION
There are three sections of the X9319: the control
section, the nonvolatile memory, and the resistor
array. The control section operates just like an
up/down counter. The output of this counter is
decoded to turn on a single electronic switch
connecting a point on the resistor array to the wiper
output. The contents of the counter can be stored in
nonvolatile memory and retained for future use. The
resistor array is comprised of 99 individual resistors
connected in series. Electronic switches at either end
of the array and between each resistor provide an
electrical connection to the wiper pin, RW.
The wiper acts like its mechanical equivalent and does
not move beyond the first or last position. That is, the
counter does not wrap around when clocked to either
extreme.
The electronic switches on the device operate in a
“make before break” mode when the wiper changes
tap positions. If the wiper is moved several positions,
multiple taps are connected to the wiper for tIW (INC to
VW change). The RTOTAL value for the device can
temporarily be reduced by a significant amount if the
wiper is moved several positions.
When the device is powered-down, the last wiper position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the
memory are recalled and the wiper is set to the value
last stored.
FN8185.2
September 26, 2006
X9319
INSTRUCTIONS AND PROGRAMMING
The INC, U/D and CS inputs control the movement of
the wiper along the resistor array. With CS set LOW
the device is selected and enabled to respond to the
U/D and INC inputs. HIGH to LOW transitions on INC
will increment or decrement (depending on the state of
the U/D input) the seven bit counter. The output of this
counter is decoded to select one of one hundred wiper
positions along the resistive array.
The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input
is also HIGH.
The system may select the X9319, move the wiper
and deselect the device without having to store the latest wiper position in nonvolatile memory. After the
wiper movement is performed as described above and
once the new position is reached, the system must
keep INC LOW while taking CS HIGH. The new wiper
position will be maintained until changed by the system or until a powerup/down cycle recalled the previously stored data. This procedure allows the system to
always power-up to a preset value stored in nonvolatile memory; then during system operation minor
adjustments could be made. The adjustments might
be based on user preference, system parameter
changes due to temperature drift, etc.
MODE SELECTION
CS
INC
U/D
Mode
L
H
Wiper up
L
L
Wiper down
H
X
Store wiper position to
nonvolatile memory
X
X
Standby
L
X
No store, return to standby
L
H
Wiper Up (not recommended)
L
L
Wiper Down
(not recommended)
H
The state of U/D may be changed while CS remains
LOW. This allows the host system to enable the
device and then move the wiper up and down until the
proper trim is attained.
7
FN8185.2
September 26, 2006
X9319
APPLICATIONS INFORMATION
Electronic digitally controlled (XDCP) potentiometers provide three powerful application advantages; (1) the variability
and reliability of a solid-state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity
of nonvolatile memory used for the storage of multiple potentiometer settings or data.
Basic Configurations of Electronic Potentiometers
VREF
VREF
RH
RW
RL
I
Three terminal potentiometer;
variable voltage divider
Two terminal variable resistor;
variable current
Basic Circuits
Buffered Reference Voltage
R1
+V
+V
Single Supply Inverting Amplifier
Cascading Techniques
+V
R1
+5V
RW
VREF
+
VS
LMC7101
VOUT
–
+8V
R2
X
RW
–
100K
+V
VO
+
+10V
LMC7101
(a)
Voltage Regulator
VIN
100K
RW
VOUT = VW/RW
(b)
VO = (R2/R1)VS
Offset Voltage Adjustment
VO (REG)
317
R1
R2
VS
R1
VS
–
+
10kΩ
+15V
10kΩ
VO
VO
R1
}
LMC7101
10kΩ
–
+
}
R2
LT311A
+12V
100kΩ
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Comparator with Hysteresis
R2
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
(for additional circuits see AN115)
8
FN8185.2
September 26, 2006
X9319
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
SO-8
SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
N
8
14
16
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
9
FN8185.2
September 26, 2006
X9319
Plastic Dual-In-Line Packages (PDIP)
E
D
A2
SEATING
PLANE
L
N
A
PIN #1
INDEX
E1
c
e
b
A1
NOTE 5
1
eA
eB
2
N/2
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
SYMBOL
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
TOLERANCE
A
0.210
0.210
0.210
0.210
0.210
MAX
A1
0.015
0.015
0.015
0.015
0.015
MIN
A2
0.130
0.130
0.130
0.130
0.130
±0.005
b
0.018
0.018
0.018
0.018
0.018
±0.002
b2
0.060
0.060
0.060
0.060
0.060
+0.010/-0.015
c
0.010
0.010
0.010
0.010
0.010
+0.004/-0.002
D
0.375
0.750
0.750
0.890
1.020
±0.010
E
0.310
0.310
0.310
0.310
0.310
+0.015/-0.010
E1
0.250
0.250
0.250
0.250
0.250
±0.005
e
0.100
0.100
0.100
0.100
0.100
Basic
eA
0.300
0.300
0.300
0.300
0.300
Basic
eB
0.345
0.345
0.345
0.345
0.345
±0.025
L
0.125
0.125
0.125
0.125
0.125
±0.010
N
8
14
16
18
20
Reference
NOTES
1
2
Rev. B 2/99
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN8185.2
September 26, 2006