ISL6161 ® Data Sheet July 2004 FN9104.3 Dual Power Distribution Controller Features The ISL6161 is a HOT SWAP dual supply power distribution controller that can be used in PCI-Express applications. • HOT SWAP Dual Power Distribution and Control for +12V and +3.3V Two external N-Channel MOSFETs are driven to distribute and control power while providing load fault isolation. At turnon, the gate of each external N-Channel MOSFET is charged with a 10µA current source. Capacitors on each gate (see the Typical Application Diagram), create a programmable ramp (soft turn-on) to control inrush currents. A built in charge pump supplies the gate drive for the 12V supply N-Channel MOSFET switch. • Provides Fault Isolation Over current protection is facilitated by two external current sense resistors and FETs. When the current through either resistor exceeds the user programmed value the controller enters the current regulation mode. The time-out capacitor, CTIM, starts charging as the controller enters the time out period. Once CTIM charges to a 2V threshold, both the N-Channel MOSFETs are latched off. In the event of a hard and fast fault of at least three times the programmed current limit level, the N-Channel MOSFET gates are pulled low immediately before entering the time out period. The controller is reset by a rising edge on the ENABLE pin. • Two Levels of Current Limit Detection Provide Fast Response to Varying Fault Conditions • Programmable Current Regulation Level • Programmable Time Out • Charge Pump Allows the Use of N-Channel MOSFETs • Power Good and Over Current Latch Indicators • Adjustable Turn-On Ramp • Protection During Turn-On • 1µs Response Time to Dead Short • 3µs Response Time to 200% Current Overshoot • Pb-free available Applications • PCI-Express Applications • Power Distribution and Control • Hot Plug, Hot Swap Components The ISL6161 constantly monitors both output voltages and reports either one being low on the PGOOD output as a low. The 12V PGOOD Vth is ~10.8V and the 3.3V Vth is ~2.8V nominally. PART NUMBER TEMP. RANGE (oC) PKG. DWG. # PACKAGE ISL6161CB -0 to 70 14 Ld SOIC M14.15 ISL6161CBZA (See Note) -0 to 70 14 Ld SOIC (Pb-free) M14.15 *Add “-T” suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. Pinout Typical Application Diagram ISL6161 (SOIC) TOP VIEW CPUMP RSENSE 12VS 1 12VG 2 13 RILIM VDD 3 12 GND NC 4 11 CPUMP 14 12VISEN ENABLE 5 10 CTIM 3VG 6 9 PGOOD 3VS 7 8 3VISEN 12V 12VS OPTIONAL CGATE VDD RFILTER ENABLE INPUT 3.3V 12VISEN RILIM RILIM GND CPUMP CTIM ENABLE PGOOD 3VG 3VS CGATE 1 12VG VDD CFILTER RLOAD ISL6161 CTIM 3.3V 3ISEN RSENSE RLOAD CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001, 2003-2004. All Rights Reserved. Hot Plug™ is a trademark of Core International, Inc. All other trademarks mentioned are the property of their respective owners. Simplified Schematic RSENSE TO LOAD 12VIN 12VS 2 OC 12V R CLIM 12ISEN 100µA + 2R 10µA 12VG ENABLE OPTIONAL POR GND ENABLE QPUMP 12V TO VDD CPUMP RISING EDGE RESET CPUMP 10µA 12V ENABLE ENABLE 12V CGATE 10µA 3VG FALLING EDGE DELAY CTIM 3X + CLIM CTIM + - + 2V 2R - + PGOOD OC LATCH PGOOD OC R OPTIONAL 3VS 3ISEN ISL6161 RSENSE 5VIN TO LOAD ISL6161 R QN R Q S NC RILIM 18V VDD VDD RFILTER CFILTER + 3X 18V CGATE RILIM FALLING EDGE DELAY ISL6161 Pin Descriptions PIN # SYMBOL FUNCTION 1 12VS 12V Source Connect to source of associated external N-Channel MOSFET switch to sense output voltage. 2 12VG 12V Gate Connect to the gate of associated N-Channel MOSFET switch. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to ~17.4V by a 10µA current source. 3 VDD Chip Supply Connect to 12V supply. This can be either connected directly to the +12V rail supplying the load voltage or to a dedicated VDD +12V supply. If the former is chosen special attention to VDD decoupling must be paid to prevent sagging as heavy loads are switched on. 4 NC Not Connected 5 ENABLE Enable / Reset ENABLE is used to turn-on and reset the chip. Both outputs turn-on when this pin is driven low. After a current limit time out, the chip is reset by the rising edge of a reset signal applied to the ENABLE pin. This input has 100µA pull up capability which is compatible with 3V and 5V open drain and standard logic. 6 3VG 3V Gate Connect to the gate of the external 3V N-Channel MOSFET. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to ~11.4V by a 10µA current source. 7 3VS 3 Source Connect to the source side of 3V external N-Channel MOSFET switch to sense output voltage. 8 3VISEN 3V Current Sense Connect to the load side of the 3V sense resistor to measure the voltage drop across this resistor between 3VS and 3VISEN pins. 9 PGOOD Power Good indicator Indicates that all output voltages are within specification. PGOOD is driven by an open drain N-Channel MOSFET. It is pulled low when any output is not within specification. 10 CTIM Current Limit Timing Capacitor Connect a capacitor from this pin to ground. This capacitor controls the time between the onset of current limit and chip shutdown (current limit time-out). The duration of current limit time-out (in seconds) = 200kΩ x CTIM (Farads). 11 CPUMP Charge Pump Capacitor Connect a 0.1µF capacitor between this pin and VDD (pin 3). Provides charge storage for 12VG drive. 12 GND Chip Ground 13 RILIM Current Limit Set Resistor A resistor connected between this pin and ground determines the current level at which current limit is activated. This current is determined by the ratio of the RILIM resistor to the sense resistor (RSENSE). The current at current limit onset is equal to 10µA x (RILIM/ RSENSE). The ISL6161 is limited to a 10kΩ min. value (OC Vth = 100mV) resistor whereas the ISL6161 can accommodate a 5kΩ resistor for a lower OC Vth (50mV). 14 12VISEN 12V Current Sense Connect to the load side of sense resistor to measure the voltage drop across this resistor. 3 DESCRIPTION ISL6161 Absolute Maximum Ratings TA = 25oC Thermal Information VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16V 12VG, CPUMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 21V 12VISEN, 12VS . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to VDD + 0.3V 3VISEN, 3VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to 7.5V PGOOD, RILIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7.5V ENABLE, CTIM, 3VG . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV (Class 2) Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . +10.5V to +13.2V Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. All voltages are relative to GND, unless otherwise specified. VDD = 12V, CVG = 0.01µF, CTIM = 0.1µF, RSENSE = 0.1Ω, CBULK = 220µF, ESR = 0.5Ω, TA = TJ = 0oC to 70oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS RILIM = 10kΩ 92 100 108 mV RILIM = 5kΩ 47 53 59 mV RILIM = 10kΩ 250 300 350 mV RILIM = 5kΩ 100 165 210 mV 12V CONTROL SECTION Current Limit Threshold Voltage (Voltage Across Sense Resistor) VIL12V 3X Current Limit Threshold Voltage (Voltage Across Sense Resistor) 3XVIL12V ±20% Current Limit Response Time (Current within 20% of Regulated Value) 20%iLrt 200% Current Overload, RILIM = 10kΩ, RSHORT = 6.0Ω - 2 - µs ±10% Current Limit Response Time (Current within 10% of Regulated Value) 10%iLrt 200% Current Overload, RILIM = 10kΩ, RSHORT = 6.0Ω - 4 - µs ±1% Current Limit Response Time (Current within 1% of Regulated Value) 1%iLrt 200% Current Overload, RILIM = 10kΩ, RSHORT = 6.0Ω - 10 - µs RTSHORT C12VG = 0.01µF - 500 1000 ns Gate Turn-On Time tON12V C12VG = 0.01µF - 12 - ms Gate Turn-On Current ION12V C12VG = 0.01µF 8 10 12 µA 3XdisI 12VG = 18V Response Time To Dead Short 3X Gate Discharge Current 12V Under Voltage Threshold 12VVUV Charge Pumped 12VG Voltage V12VG 0.5 0.75 - A 10.5 10.8 11.0 V 16.8 17.3 17.9 V RILIM = 10kΩ 92 100 108 mV RILIM = 5kΩ 47 53 59 mV RILIM = 10kΩ 250 300 350 mV RILIM = 5kΩ 100 155 210 mV CPUMP = 0.1µF 3.3V CONTROL SECTION Current Limit Threshold Voltage (Voltage Across Sense Resistor) VIL3V 3X Current Limit Threshold Voltage (Voltage Across Sense Resistor) 3XVIL3V ±20% Current Limit Response Time (Current within 20% of regulated value) 200% Current Overload, RILIM = 10kΩ, RSHORT = 2.5Ω - 2 - µs ±10% Current Limit Response Time (Current within 10% of Regulated Value) 200% Current Overload, RILIM = 10kΩ, RSHORT = 2.5Ω - 4 - µs ±1% Current Limit Response Time (Current within 1% of Regulated Value) 200% Current Overload, RILIM = 10kΩ, RSHORT = 2.5Ω - 10 - µs CVG = 0.01µF - 500 800 ns Response Time To Dead Short RTSHORT 4 ISL6161 VDD = 12V, CVG = 0.01µF, CTIM = 0.1µF, RSENSE = 0.1Ω, CBULK = 220µF, ESR = 0.5Ω, TA = TJ = 0oC to 70oC, Unless Otherwise Specified (Continued) Electrical Specifications PARAMETER SYMBOL Gate Turn-On Time tON3V TEST CONDITIONS CVG = 0.01µF MIN TYP MAX UNITS - 5 - ms 8 10 12 µA 0.5 0.75 - A 3.3VVUV 2.7 2.85 3.0 V 3VG 11.2 11.9 - V 4 8 10 mA VDD POR Rising Threshold 9.5 10.0 10.7 V VDD POR Falling Threshold 9.3 9.8 10.3 V Gate Turn-On Current ION3V CVG = 0.01µF 3X Gate Discharge Current 3XdisI CVG = 0.01µF, ENABLE = Low 3.3V Under Voltage Threshold 3.3VG High Voltage SUPPLY CURRENT AND IO SPECIFICATIONS VDD Supply Current IVDD CTIM = 0.1µF 16 20 24 ms ENABLE pin open 1.8 2.4 3.2 V PWR_Vth 1.1 1.5 2 V ENABLE Hysteresis PWR_hys 0.1 0.2 0.3 V ENABLE Pull-Up Current PWRN_I 60 80 100 µA Current Limit Time-Out Threshold (CTIM) CTIM_Vth 1.8 2 2.2 V CTIM Charging Current CTIM_I 8 10 12 µA CTIM Discharge Current CTIM_disI 1.7 2.6 3.5 mA CTIM Pull-Up Current CTIM_disI RILIM Pin Current Source Output RILIM_Io Charge Pump Output Current Qpmp_Io Charge Pump Output Voltage Current Limit Time-Out TILIM ENABLE Pull-up Voltage PWRN_V ENABLE Rising Threshold VCTIM = 8V 3.5 5 6.5 mA 90 100 110 µA CPUMP = 0.1µF, CPUMP = 16V 320 560 800 µA Qpmp_Vo No load 17.2 17.4 - V Charge Pump Output Voltage - Loaded Qpmp_VIo Load current = 100µA 16.2 16.7 - V Charge Pump POR Rising Threshold Qpmp+Vth 15.6 16 16.5 V Charge Pump POR Falling Threshold Qpmp-Vth 15.2 15.7 16.2 V ISL6161 Description and Operation The ISL6161 is a multi featured +12V and +3.3V dual power supply distribution controller, features include programmable current regulation (CR) limiting and time to latch off. At turn-on, the gate capacitor of each external N-Channel MOSFET is charged with a 10µA current source. These capacitors create a programmable ramp (soft turn-on). A charge pump supplies the gate drive for the 12V supply control FET switch driving that gate to 17V. The load currents pass through two external current sense resistors. When the voltage across either resistor quickly exceeds the user programmed Current Regulation voltage threshold (CRVth) level, the controller enters current regulation. The CRVth is set by the external resistor value on RILIM pin. At this time the time-out capacitor, CTIM, starts charging with a 10µA current source and the controller enters the time out period. The length of the time out period is set by the single external capacitor (see Table 2) placed from the CTIM pin (pin 10) to ground and is characterized by a lowered gate drive 5 voltage to the appropriate external N-Channel MOSFET. Once CTIM charges to 2V, an internal comparator is tripped resulting in both N-Channel MOSFETs being latched off. If the voltage across the sense resistors rises slowly in response to an OC condition, then the CR mode is entered at ~95% of the programmed CR level. This difference is due to the necessary hysteresis and response time in the CR control circuitry. Table 1 shows Rsense and Rilim recommendations and resulting CR level for the PCI-Express add-in card connector sizes specified. TABLE 1. PCI-EXPRESS ADD-IN CARD CONNECTOR X1 3.3V RSENSE 12V RSENSE NOMINAL (mΩ), (mΩ), CRVth NOMINAL NOMINAL RILIM (mV) CR (A) CR (A) (kΩ) 10 30, 3.3 150, 0.7 100 4.99 15, 3.5 90, 0.6 53 ISL6161 TABLE 1. (Continued) PCI-EXPRESS ADD-IN CARD CONNECTOR 3.3V RSENSE 12V RSENSE NOMINAL (mΩ), (mΩ), CRVth RILIM NOMINAL NOMINAL (mV) CR (A) CR (A) (kΩ) X4/X8 10 30, 3.3 40, 2.5 100 4.99 15, 3.5 20, 2.6 53 10 30, 3.3 16, 6.3 100 4.99 15, 3.5 8, 6.6 53 X16 NOTE: Nominal CR Vth = Rilim x 10µA. TABLE 2. CTIM CAPACITOR NOMINAL TIME OUT PERIOD 0.022µF 4.4ms 0.047µF 9.4ms 0.1µF 20ms NOTE: Nominal time-out period in seconds = CTIM x 200kΩ. The ISL6161 responds to a load short (defined as a current level 3X the OC set point with a fast transition) by immediately driving the relevant N-Channel MOSFET gate to 0V in ~3µs. The gate voltage is then slowly ramped up soft starting the N-Channel MOSFET to the programmed current regulation limit level, this is the start of the time out period if the abnormal load condition still exists. The programmed current regulation level is held until either the OC event passes or the time out period expires. If the former is the case then the N-Channel MOSFET is fully enhanced and the CTIM charging current is diverted away from the capacitor. If the time out period expires prior to OC resolution then both gates are quickly pulled to 0V turning off both N-Channel MOSFETs simultaneously. Upon any UV condition the PGOOD signal will pull low when tied high through a resistor to the logic supply. This pin is a fault indicator but not the OC latch off indicator. For an OC latch off indication, monitor CTIM, pin 10. This pin will rise rapidly to 12V once the time out period expires. See block diagram for OC latch off circuit suggestion. The ISL6161 is reset by a rising edge on the ENABLE pin and is turned on by the ENABLE pin being driven low. ISL6161 Application Considerations In a non PCI-Express, motor drive application Current loop stabilization is facilitated through a small value resistor in series with the gate timing capacitor. As the ISL6161 drives a highly inductive current load, instability characterized by the gate voltage repeatedly ramping up and down may appear. A simple method to enhance stability is provided by the substitution of a larger value gate resistor. Typically this situation can be avoided by eliminating long point to point wiring to the load. 6 With the ENABLE internal pull-up the ISL6161 is well suited for implementation on either side of the connector where a motherboard prebiased condition or a load board staggered connection is present. In either case the ISL6161 turns on in a soft start mode protecting the supply rail from sudden current loading. During the Time Out delay period with the ISL6161 in current limit mode, the VGS of the external N-Channel MOSFETs is reduced driving the N-Channel MOSFET switch into a high rDS(ON) state. Thus avoid extended time out periods as the external N-Channel MOSFETs may be damaged or destroyed due to excessive internal power dissipation. Refer to the MOSFET manufacturers data sheet for SOA information. With the high levels of inrush current e.g., highly capacitive loads and motor start up currents, choosing the current regulation (CR) level is crucial to provide both protection and still allow for this inrush current without latching off. Consider this in addition to the time out delay when choosing MOSFETs for your design. Physical layout of Rsense resistors is critical to avoid inadvertently lowering the CR and trip levels. Ideally trace routing between the Rsense resistors and the ISL6161 is direct and as short as possible with zero current in the sense lines. CORRECT INCORRECT TO ISEN AND RISET CURRENT SENSE RESISTOR FIGURE 1. SENSE RESISTOR PCB LAYOUT Open load detection can be accomplished by monitoring the ISEN pins. Although gated off the external FET IDSS will cause the ISEN pin to float above ground to some voltage when there is no attached load. If this is not desired 5K resistors from the xISEN pins to ground will prevent the outputs from floating when the external switch FETs are disabled and the outputs are open. For PCI-Express applications the ISL6161 and the ISL6118 provide the fundamental hotswap function for the +12V & +3.3V main rails and the +3.3V aux respectively as shown in Figure 13. ISL6161 Typical Performance Curves 8.4 105 8.0 CURRENT (µA) SUPPLY CURRENT (mA) 8.2 7.8 7.6 104 103 7.4 7.2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 102 -40 80 -30 -20 -10 TEMPERATURE (oC) 40 50 60 70 80 60 70 80 2.04 CTIM OC VOLTAGE THRESHOLD (V) CTIM CURRENT SOURCE (µA) 30 FIGURE 3. RILIM SOURCE CURRENT 10.7 10.6 10.5 10.4 -30 -20 -10 0 10 20 30 40 50 60 70 80 2.02 2.00 1.98 1.96 1.94 -40 -30 -20 -10 TEMPERATURE (oC) 10 20 30 40 50 FIGURE 5. CTIM OC VOLTAGE THRESHOLD 2.875 3.3V UV THRESHOLD (V) 10.92 10.902 10.886 10.87 -40 0 TEMPERATURE (oC) FIGURE 4. CTIM CURRENT SOURCE 12V UV THRESHOLD (V) 20 TEMPERATURE (oC) FIGURE 2. SUPPLY CURRENT 10.3 -40 10 0 -20 0 20 40 TEMPERATURE (oC) FIGURE 6. 12V UV THRESHOLD 7 60 80 2.8725 2.870 2.8675 2.865 -40 -20 0 20 40 TEMPERATURE (oC) FIGURE 7. 3.3V UV THRESHOLD 60 80 ISL6161 Typical Performance Curves (Continued) 11.935 17.36 17.6 11.930 17.4 11.920 11.915 17.30 11.910 3.3VG VOLTAGE (V) 17.32 CHARGE PUMP VOLTAGE NO LOAD 3.3V GATE DRIVE (V) 11.925 12V VG 17.28 17.26 -40 -20 0 20 40 60 17.2 17.0 CHARGE PUMP VOLTAGE 100µA LOAD 16.8 11.905 11.900 80 16.6 -40 -20 0 20 40 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 8. 12V, 3V GATE DRIVE 80 102.5 VOLTAGE THRESHOLD (mV) 54.0 12 OC Vth 53.5 3.3 OC Vth 53.0 52.5 -40 60 FIGURE 9. PUMP VOLTAGE 54.5 VOLTAGE THRESHOLD (mV) -20 0 20 40 60 12 OC VTth 102.0 101.5 3.3 OC Vth 101.0 100.5 -40 80 -20 0 TEMPERATURE (oC) VDD LOW TO HIGH 10.0 9.6 -40 VDD HIGH TO LOW -30 -20 -10 0 10 20 30 40 50 60 70 TEMPERATURE (oC) FIGURE 12. POWER ON RESET VOLTAGE THRESHOLD 8 40 60 80 FIGURE 11. OC VOLTAGE THRESHOLD WITH RLIM = 10kΩ 10.2 9.8 20 TEMPERATURE (oC) FIGURE 10. OC VOLTAGE THRESHOLD WITH RLIM = 5kΩ POWER ON RESET (V) 12V GATE DRIVE (V) 17.34 80 PCI-EXPRESS Implementation of ISL6161 and ISL6118 INTERSIL ISL6161 INTERSIL ISL6161 12V, 3.3V POWER CONTROLLER SLOT 2 PWREN# SLOT 1 PWRGD +12V GATE SWITCH SLOT 2 PWRGD 3.3V GATE SWITCH 3.3V 3.3V +12V GATE SWITCH 9 3.3V GATE SWITCH 12V, 3.3V POWER CONTROLLER SLOT 1 PWREN# CONTROLLER 3.3V +12V 3.3V PCI-EXPRESS SLOT 2 SLOT 2 PWREN# SLOT 1 PWREN# INTERSIL ISL6118 3.3VSB DUAL 3.3VAUX POWER CONTROLLER FIGURE 13. 3.3VAUX 3.3VAUX SLOT 2 PWRFLT# SLOT 1 PWRFLT# ISL6161 PCI-EXPRESS SLOT 1 SLOT 2 PRSNT SLOT 1 PRSNT +12V 12V +12V ISL6161 Small Outline Plastic Packages (SOIC) M14.15 (JEDEC MS-012-AB ISSUE C) N INDEX AREA 0.25(0.010) M H 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- µα e A1 B 0.25(0.010) M C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3367 0.3444 8.55 8.75 3 E 0.1497 0.1574 3.80 4.00 4 e C 0.10(0.004) B S 0.050 BSC 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N NOTES: MILLIMETERS α 14 0o 14 8o 0o 7 8o Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10