TB9408VA www.vishay.com Vishay Semiconductors Specification of GaAlAs IR Emitting Diode Chip FEATURES • Package type: chip • Package form: single chip • Technology: multi quantum well (MQW) • Dimensions chip (L x W x H in mm): 0.2 x 0.2 x 0.19 • Peak wavelength: λ = 940 nm • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 DESCRIPTION TB9408VA is an infrared, 940 nm emitting diode in GaAlAs multi quantum well technology with high radiant power and high speed. Anode is the bond pad on top. GENERAL INFORMATION The datasheet is based on Vishay optoelectronics sample testing under certain predetermined and assumed conditions, and is provided for illustration purpose only. Customers are encouraged to perform testing in actual proposed packaged and used conditions. Vishay optoelectronics die products are tested using Vishay optoelectronics based quality assurance procedures and are manufactured using Vishay optoelectronics established processes. Estimates such as those described and set forth in this datasheet for semiconductor die will vary depending on a number of packaging, handling, use, and other factors. Therefore sold die may not perform on an equivalent basis to standard package products. PRODUCT SUMMARY COMPONENT φe (mW) Ie (mW/sr) ϕ (deg) λp (nm) tr (ns) 3.5 4.0 ± 80 940 15 TB9408VA Note • Test condition see table “Basic Characteristics” ORDERING INFORMATION ORDERING CODE TB9408VA-SF-F PACKAGING REMARKS PACKAGE FORM wafer sawn on foil MOQ: 100 000 pcs chip Note • MOQ: minimum order quantity ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C, unless otherwise specified) PARAMETER SYMBOL VALUE UNIT Forward current IF 75 mA Reverse voltage VR 5 V IFSM 500 mA Tj 100 °C Surge forward current Junction temperature TEST CONDITION tp = 100 μs Operating temperature range Tamb -40 to +85 °C Storage temperature range chip Tstg1 -40 to +100 °C Storage temperature range on foil Tstg2 -40 to +50 °C Rev. 1.1, 28-Jul-14 Document Number: 84227 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 TB9408VA www.vishay.com Vishay Semiconductors BASIC CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITION SYMBOL MIN. TYP. MAX. UNIT IF = 5 mA VF 1.1 1.18 1.25 V 1.13 1.26 1.4 V IF = 20 mA VF IF = 100 mA VF 1.45 V IF = 500 mA, tp = 100 μs VF 2.0 V Radiant power (1) IF = 100 mA φe 22 mW Radiant intensity (2) IF = 100 mA Ie 4.0 mW/sr Radiant power (epoxy encapsulated) IF = 100 mA φe Radiant power chip (3) IF = 50 mA φe Temperature coefficient of radiant power IF = 1 mA TKφe Reverse voltage IR = 10 μA VR Temperature coefficient of forward voltage IF = 1 mA TKVF Forward voltage 40 2.5 mW 3.5 5.0 mW -1.1 7 %/K 18 V -1.5 mV/K Angle of half intensity IF = 100 mA ϕ Peak wavelength IF = 30 mA λp Spectral bandwidth IF = 30 mA λ0.5 25 nm Rise time / fall time IF = 100 mA tr, tf 15 ns > ± 80 920 deg 945 960 nm Notes (1) The measurements are based on samples of die which are mounted on a TO-18 gold header without resin coating (2) The radiant intensity, I , is measured on the geometric axis of the TO-18 header e (3) The radiant power, φ , is measured with chip on bare plate and aperture angle about 30°, as indicated on the label of each wafer e BASIC CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) ϕe rel - Relative Radiant Power 1.25 - 70° - 80° 90° 80° 70° - 60° 1.0 60° - 50° 50° 40° - 40° 0.75 - 30° 0.5 30° - 20° 20° 10° - 10° 0.25 0 750 0° 100 800 850 900 950 1000 1050 1100 21630 0° 50 0 50 100 Relative Angular Intensity λ - Wavelength (nm) 21632 Fig. 1 - Relative Spectral Emission φe rel = f (λ) Fig. 2 - Radiant Characteristics Irel = f(ϕ) DIMENSIONS Sectional view (schematic): Electrode pattern: P (anode) side N (cathode) side anode P N typ. 185 µm substrate Fig. 3 Rev. 1.1, 28-Jul-14 Document Number: 84227 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 TB9408VA www.vishay.com Vishay Semiconductors MECHANICAL DIMENSIONS PARAMETER SYMBOL MIN. TYP. MAX. UNIT Lx 0.185 0.200 0.215 mm Length of chip edge (y-direction) Ly 0.185 0.200 0.215 Emission area AE Die height H Diameter of bondpad d Length of chip edge (x-direction) 0.175 mm mm2 0.18 x 0.18 0.190 0.205 0.110 mm mm ADDITIONAL INFORMATION Frontside metallization, anode Backside metallization, cathode Dicing Die bonding technology gold gold alloy sawing epoxy bonding Note • All chips are checked in accordance with the Vishay Semiconductor, specification of visual inspection FVOV6870. The visual inspection shall be made in accordance with the “specification of visual inspection as referenced”. The visual inspection of chip backside is performed with stereo microscope with incident light and 40x to 80x magnification. The quality inspection (final visual inspection) is performed by production. An additional visual inspection step as special release procedure by QM is not installed. HANDLING AND STORAGE CONDITIONS • The hermetically sealed shipment lots shall be opened in temperature and moisture controlled cleanroom environment only. It is mandatory to follow the rules for disposition of material that can be hazardous for humans and environment. • Product must be handled only at ESD safe workstations. Standard ESD precautions and safe work environments are as defined in MIL-HDBK-263. • Singulated die are not to be handled with tweezers. A vacuum wand with non metallic ESD protected tip should be used. PACKING Chips are fixed on adhesive foil. Upon request the foils can be mounted on plastic frame or disco frame. For shipment, the wafers are arranged to stacks and hermetically sealed in plastic bags to ensure protection against environmental influence (humidity and contamination). Use for recycling reliable operators only. We can help getting in touch with your nearest sales office. By agreement we will take back packing material, if it is sorted. You will have to bear the costs of transport. We will invoice you for any costs incurred for packing material that is returned unsorted or which we are not obliged to accept. Rev. 1.1, 28-Jul-14 Document Number: 84227 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000