CT T O D U C EM E N t R P E A ® ra T L e ent O LE R EP OBS ENDED upport C om/tsc M S il.c COM chnical w.inters E R e T NO Sheet January 1996, Rev B ww urData I L or act o cont -INTERS 8 1-88 EL4393 FN7165 Triple 80MHz Video Amplifier w/Disable Features The EL4393 is three wideband currentfeedback amplifiers optimized for video performance. Each amplifier can drive a load of 150Ω at video levels. Each amplifier has a disable capability, which is controlled by a TTL/CMOS compatible logic signal. The EL4393 operates on supplies as low as ±4V up to ±15V. • 80MHz -3dB bandwidth for gains of 1 to 10 Being a current-feedback design, the bandwidth stays relatively constant at approximately 80MHz over the ±1 to ±10 gain range. The EL4393 has been optimized for use with 1300Ω feedback resistors at a gain of 2. When the outputs are disabled, the supply current consumption drops, by about 4mA per channel that is disabled. This feature can be used to reduce power dissipation. • 900V/µs slew rate • 10MHz bandwidth flat to 0.1dB • Excellent differential gain and phase • TTL/CMOS compatible • Available in SOL-16 Applications • RGB drivers • RGB multiplexers • RGB gain blocks Pinout • Video gain blocks • Coax cable driver EL4393 (16-PIN PDIP, SO) TOP VIEW • ADC drivers/input multiplexer Ordering Information PART NUMBER 1 TEMP. RANGE PACKAGE PKG. NO. EL4393CN -40°C to +85°C 16-Pin PDIP MDP0031 EL4393CM -40°C to +85°C 16-Pin SOL MDP0027 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. EL4393 Absolute Maximum Ratings (TA = 25°C) Voltage between VS+ and VS-. . . . . . . . . . . . . . . . . . . . . . . . . .+33V Voltage at VS+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V Voltage at VS- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18V Voltage between VIN+ and VIN-. . . . . . . . . . . . . . . . . . . . . . . . . .±6V Current into VIN+ or VIN- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . See Curves Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Open-Loop DC Electrical Specifications PARAMETER Supplies at ±15V, Load = 1kΩ DESCRIPTION TEMP MIN TYP MAX UNITS +25°C 2 ±15 mV Full 50 VOS Input Offset Voltage TCVOS Temperature Coefficient of VOS IB+ IIN+ Input Bias Current +25°C 0.2 5 µA IB- IIN- Input Bias Current +25°C 10 65 µA TCIB- Temperature Coefficient of IB- Full 25 nA/°C CMRR Common-Mode Rejection Ratio (Note 1) +25°C 58 dB -ICMR IIN- Input Common-Mode Current (Note 1) +25°C PSRR Power Supply Rejection Ratio (Note 2) +25°C -IPSR IIN- Current Supply Rejection (Note 2) +25°C ROL Transimpedance +25°C RIN IN+ Input Impedance +25°C VIN IN+ Input Range +25°C VO Output Voltage Swing; RL = 1kΩ ISC 50 3 50 8 58 2 µA/V dB 5 µA/V 217 kΩ 2 MΩ ±13 ±13.5 V +25°C ±12 ±13 V Short-Circuit Current (Note 3) +25°C 40 70 mA IO, DIS Output Current when Disabled +25°C DIS VIL Disable Voltage for Logic Low +25°C DIS VIH Disable Voltage for Logic High +25°C DIS IIL Disable Logic Low Input Current +25°C 3 25 µA DIS IIH Disable Logic High Input Current +25°C 0 5 µA ICC (en) Positive Supply Current all Channels Enabled +25°C 15 20 ±29 mA ICC (dis) Positive Supply Current all Channels Disabled +25°C 6 11 16 mA IEE (en) Negative Supply Current all Channels Enabled +25°C 13 18 ±28 mA IEE (dis) Negative Supply Current all Channels Disabled +25°C 4 9 14 mA NOTES: 1. VCM = ±10V for VS = ±15V. 2. VOS is measured at VS = ±4.5V and VS = ±16V, both supplies are changed simultaneously. 3. Only one output short-circuited. Pulse test or use heatsink. 2 100 µV/°C 5 150 µA 0.8 V 2.2 V EL4393 AC Electrical Specifications Supplies at ±15V, Load = 150Ω and 15pF, except where noted. Rf1 and Rf2 = 1500Ω; AV = 2, TA = 25°C.(Note 1) PARAMETER DESCRIPTION MIN TYP MAX UNITS SR Slew Rate (Note 2) 960 V/µs SR Slew Rate w/±5V Supplies (Note 3) 470 V/µs tS Settling Time to 1% 5VP-P 5V Step (Note 4) 32 ns BW Bandwidth, -3dB ±5V Supplies, -3dB 80 60 MHz MHz BW Bandwidth, -0.1dB ±5V Supplies, -0.1dB 16 21 MHz MHz Peaking -3dB BW Tests 0.6 dB dG Differential Gain at 3.58MHz at ±5V Supplies (Note 5) 0.03 0.30 % % dθ Differential Phase at 3.58MHz at ±5V Supplies (Note 5) 0.088 0.096 (°) (°) NOTES: 1. Test fixture was designed to minimize capacitance at the IN+ input. A “good” fixture should have less than 2pF of stray capacitance to ground at this very sensitive pin. See application notes for further details. 2. RL = 300Ω, -5V to +5V swing, SR measured at 20% to 80% 3. -2V to +2V swing, SR measured at 20% to 80%. 4. RL = 300Ω. 5. DC offset from -0.7V through +0.7V AC amplitude is 286mVP-P, equivalent to 40 ire. 3 EL4393 Typical Performance Curves Gain Flatness vs Rf at ± 5V Gain Flatness vs Rf at ± 15V Phase vs Rf at ± 5V Phase vs Rf at ±15V Gain of 5, 10 vs Various Rf, Rg at ±5V 4 Gain of 5, 10 vs Rf, Rg at ± 15V EL4393 Typical Performance Curves (Continued) Disabled Isolation Test at ±5V Cin—vs Peaking Differential Gain & Phase at 3.58MHz 5 Disabled Isolation Test at ± 15V Voltage Noise EL4393 MUX Channel Channel Isolation EL4393 Typical Performance Curves (Continued) Supply Current vs Supply Voltage Maximum Power Dissipation vs Ambient Temperature— 16-Pin PDIP Small Signal Pulse Response Small Signal Enable/Disable with +VE Voltage Maximum Power Dissipation vs Ambient Temperature— 16-Pin SOL Large Signal Pulse Response Enable/Disable with -VE Voltage Output Typical Application for EL4393, and General Rules for PCB Layout The circuit gives channel isolations of typically better than -50dB at 10MHz, and with a 20dB/decade slope, extending down to better than -90dB at frequencies below 100kHz. The figure shows two EL4393s configured as a 2:1 RGB multiplexer, and cable driver, driving 75Ω, back terminated cables. Each channel of the EL4393 is configured to give a gain of two, to make up for the losses of the back terminating resistor. The schematic does not show things like power supply decoupling, or pcb layout, grounding and signal returns, but these will all affect the overall performance of the circuit, and care should be taken with these aspects. In this example, the Disable pins of each RGB section are driven by a complementary TTL “select” signal. Larger multiplexers can be assembled, with a 1-of-n TTL decoder selecting each RGB triplet. It is recommended that the VCC and VEE pins each be decoupled by a 0.1µF NPO or X7R dielectric ceramic capacitors to ground within 0.1 inch of the part, and in parallel with the 0.1µF, a 47µF tantalum capacitor, also to ground. The 47µF capacitors should be within 0.25 inch of their power 6 EL4393 pins. The ground plane should be underneath the package, but cut away from the In- inputs. Care should be taken with the center channel feedback—it must be kept away from any of the In+ or In- pins, if it has to go under the package. Route the G-out line between the pin 3 ground and the pin 4 In- if going under the package is essential. Otherwise, loop the Gout trace around all the other circuitry, to its Rf resistor. The Rf and if used, Rg resistors should be on the input side of the package, to minimize trace length on the In- pins. The digital input disables are on the output side of the package, so that a good ground plane down the center of the board underneath the package will isolate any fast edges from the sensitive inputs. TYPICAL APPLICATION CIRCUIT 7 EL4393 EL4393 Macromodel * Revision A, July 1993 * Enhancements include PSRR, CMRR, and Slew Rate Limiting * Connections: +input * | -Input * | | +Vsupply * | | | -Vsupply * | | | | Putput * | | | | | * subckt EL4393/EL 3 2 7 4 6 * * Input Stage * e1 10 0 3 0 1.0 vis 10 9 0V h2 9 12 vxx 1.0 r1 2 11 50 l 1 11 12 29 nH iinp 3 0 0.2 µA iinm 2 0 10 µA * * Slew Rate Limiting * h1 13 0 vis 600 r2 13 14 1K d1 14 0 dclamp d2 0 14 dclamp * * High Frequency Pole * e2 30 0 14 0 0.00166666666 l5 30 17 1.2 µH c5 17 0 1 pF r5 17 0 500 * * Transimpedance Stage * g1 0 18 17 0 1.0 rol 18 0 250k cdp 18 0 2.2 pF * * Output Stage * q1 4 18 19 qp q2 7 18 20 qn q3 7 19 21 qn q4 4 20 22 qp r7 21 6 4 r8 22 6 4 ios1 7 19 2.5 mA ios2 20 4 2.5 mA * * Error Terms * ivos 0 23 2 mA vxx 23 0 0V e4 24 0 3 0 1.0 e5 25 0 7 0 1.0 e6 26 0 4 0 1.0 r9 24 23 1K 8 EL4393 r10 25 23 1K r11 26 33 1K * * Models * .model qn npn (is=5e-15 bf=100 tf=0.2nS) .model qp pnp (is=5e-15 bf=100 tf=0.2nS) .model dclamp d (is=1e-30 ibv=0.266 bv=1.5 n=4) .ends SIMPLIFIED SCHEMATIC OF ONE CHANNEL OF EL4393 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9