ICL8049 ® UCT NT ROD ACEME at P E r L T OLE REP rt Cente tsc / O BS E NDE D o p m p o MM nical Su tersil.c O C E h .in NO R our Tec or www t L c I a cont -INTERS 8 1-88 July 1999 Features Antilog Amplifier Description • Full Scale Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . 0.5% • Temperature Compensated Operation . . . . 0o The ICL8049 is a monolithic antilogarithmic amplifier that is fully temperature compensated and is nominally designed to provide 1 decade of output voltage for each 1V change of input voltage. For increased flexibility, the scale factor, reference current and offset voltage are externally adjustable. o C to 70 C • Scale Factor, Adjustable . . . . . . . . . . . . . . . . 1V/Decade • Dynamic Voltage Range . . . . . . . . . . . . . . . . . . . . .60dB • Dual JFET Input Op Amps Part Number Information ERROR (25oC) TEMPERATURE RANGE (o C) ICL8049BCJE 10mV 0 to 70 16 Ld CERDIP ICL8049CCJE 25mV 0 to 70 16 Ld CERDIP PART NUMBER PACKAGE Functional Diagram Pinout ICL8049 ICL8049 (CERDIP) TOP VIEW A1 INPUT 1 16 VIN GAIN 2 15 GND IREF 3 14 A2 INPUT 4 13 A1 OFFSET NULL A1 OFFSET NULL V- 6 A2 OFFSET NULL 12 A2 OFFSET NULL 11 V+ A1 OUTPUT 7 10 VOUT NC 8 9 NC 5 VREF 3 VIN IREF A2 INPUT 14 Q1 Q2 16 GAIN - 2 - A1 + 1 A1 INPUT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1 A2 + 7 fOUT 10 VOUT 15 GND A1 OUTPUT File Number 4768 ICL8049 Absolute Maximum Ratings Operating Conditions Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V VIN (Input Current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V IREF (Reference Current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mA Voltage Between Offset Null and V+ . . . . . . . . . . . . . . . . . . . ±0.5V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . . Indefinite Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750mW Lead Temperature (Soldering 10 Sec.) . . . . . . . . . . . . . . . . . 300oC Operating Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 70oC Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to 150oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications VS = ±15V, TA = 25oC, IREF = 1mA, Scale Factor Adjusted for 1 Decade (Out) per Volt (In), Unless Otherwise Specified ICL4049BC PARAMETERS TEST CONDITIONS ICL8049CC MIN TYP MAX MIN TYP MAX UNITS 60 - - 60 - - dB Dynamic Range (VOUT) VOUT = 10mV to 10V Error, Absolute Value 0V ≤ VIN ≤ 2V - 3 15 - 5 25 mV TA = 0oC to 70oC, 0V ≤ VIN ≤ 3V - 20 75 - 30 150 mV Temperature Coefficient, Referred to VIN VIN = 3V - 0.38 - - 0.55 - mV/oC Power Supply Rejection Ratio Referred to Input, for VIN = 0V - 2.0 - - 2.0 - µV/V Offset Voltage (A1 and A2) Before Nulling - 15 25 - 15 50 mV Wideband Noise Referred to Input, for VIN = 0V - 26 - - 26 - µVRMS Output Voltage Swing RL = 10kΩ ±12 ±14 - ±12 ±14 - V RL = 2kΩ ±10 ±13 - ±10 ±13 - V Power Consumption - 150 200 - 150 200 mW Supply Current - 5 6.7 - 5 6.7 mA 2 ICL8049 VREF (+15V) V+ R3 15kΩ VIN 7 200pF 1kΩ IREF 3 14 IOUT 2 680Ω (LOW T.C.) R5 15kΩ 16 R1 15.9kΩ R6 100kΩ R4 2kΩ RREF 15kΩ C1 Q1 Q2 ROUT 10kΩ R2 - + A1 - + V- 15 1 12 10 A2 VOUT R7 2kΩ 13 V+ FIGURE 1. ICL8049 OFFSET AND SCALE FACTOR ADJUSTMENT ICL8049 Detailed Description For voltage references Equation 3 becomes The ICL8049 relies on the same logarithmic properties of the transistor as the ICL8048. The input voltage forces a specific ∆VBE between Q 1 and Q2 (Figure 1). This VBE difference is converted into a difference of collector currents by the transistor pair. The equation governing the behavior of the transistor pair is derived from (2) on the previous page and is as follows: I C1 q∆VBE C2 kT REF ex p -R 2 qV IN --------------------- × --------kT ( R1 + R2 ) (4) 2. Connect the input to Ground. Adjust R4 for VOUT = 10V. Disconnect the input from Ground. 3. Connect the input to a precise 2V supply and adjust R2 for VOUT = 100mV. The procedure outlined above optimizes the performance over a 3 decade range at the output (i.e., VOUT from 10mV) to 10V). For a more limited range of output voltages, for example 1V to 10V, it would be better to use a precise 1V supply and adjust for VOUT = 1V. For other scale factors and/ or starting points, different values for R2 and RREF will be needed, but the same basic procedure applies. (2) Substituting VOUT = IOUT x ROUT gives: –R2 qV IN V OUT = R OUT IREF exp ------------------------- × -----------kT ( R1 + R2 ) R –R2 qV IN OUT × ----------exp --------------------- × --------REF R ( R 1 + R 2 ) kT REF 1. Connect the input (pin #16) to +15V. This reverse biases the base-emitter of Q2. Adjust R7 for VOUT = 0V. Disconnect the input from +15V. The overall transfer function is as follows: OUT --------- = I V As with the log amplifier, the antilog amplifier requires three adjustments. The first step is to null out the offset voltage of A2. This is accomplished by reverse biasing the base-emitter of Q2. A2 then operates as a unity gain buffer with a grounded input. The second step forces VIN = 0; the output is adjusted for V OUT = 10V. This step essentially “anchors” one point on the transfer function. The third step applies a specific input and adjusts the output to the correct voltage. This sets the scale factor. Referring to Figure 1 the exact procedure for 1 decade/volt is as follows: When numerical values for q/kT are put into this equation, it is found that a ∆VBE of 59mV (at +25oC) is required to change the collector current ratio by a factor of ten. But for ease of application, it is desirable that a 1V change at the input generate a tenfold change at the output. The required input attenuation is achieved by the network comprising R1 and R 2. In order that scale factors other than one decade per volt may be selected, R2 is external to the chip. It should have a value of 1kΩ, adjustable ±20%, for one decade per volt. R1 is a thin film resistor deposited on the monolithic chip; its temperature characteristics are chosen to compensate the temperature dependence of Equation 1, as explained on the previous page. I OUT = ICL8049 Offset and Scale Factor Adjustment (1) -------- = exp -----------------I V (3) 3