INTERSIL ICL7116CPL

ICL7116, ICL7117
3 1/2 Digit, LCD/LED Display,
A/D Converter with Display Hold
January 1998
Features
Description
• HOLD Reading Input Allows Indefinite Display Hold
The Intersil ICL7116 and ICL7117 are high performance, low
power, 31/2 digit, A/D converters. Included are seven segment
decoders, display drivers, a reference, and a clock. The
ICL7116 is designed to interface with a liquid crystal display
(LCD) and includes a multiplexed backplane drive. The
ICL7117 will directly drive an instrument size, light emitting
diode (LED) display.
• Guaranteed Zero Reading for 0V Input
• True Polarity at Zero for Precise Null Detection
• 1pA Typical Input Current
• Direct Display Drive
- LCD ICL7116
- LED lCL7117
The ICL7116 and ICL7117 have all of the features of the
ICL7106 and ICL7107 with the addition of a HOLD Reading
input. With this input, it is possible to make a measurement
and retain the value on the display indefinitely. To make room
for this feature the reference low input has been connected
to Common internally rather than being fully differential.
These circuits retain the accuracy, versatility, and true economy of the ICL7106 and ICL7107. They feature auto-zero to
less than 10µV, zero drift of less than 1µV/oC, input bias current of 10pA maximum, and roll over error of less than one
count. The versatility of true differential input is of particular
advantage when measuring load cells, strain gauges and
other bridge-type transducers. And finally, the true economy
of single power supply operation (ICL7116) enables a high
performance panel meter to be built with the addition of only
eleven passive components and a display.
• Low Noise - Less Than 15µVP-P (Typ)
• On Chip Clock and Reference
• Low Power Dissipation - Typically Less Than 10mW
• No Additional Active Circuits Required
• Surface Mount Package Available
Ordering Information
TEMP.
RANGE (oC)
PART NUMBER
PACKAGE
PKG. NO.
ICL7116CPL
0 to 70
40 Ld PDIP
E40.6
ICL7116CM44
0 to 70
44 Ld MQFP
Q44.10x10
ICL7117CPL
0 to 70
40 Ld PDIP
E40.6
Pinouts
(1’s)
6
35 V+
G1
7
34 CREF+
8
33 CREF-
D2
9
32 COMMON
C2
10
31 IN HI
B2
11
V-
36 REF HI
F1
INT
5
BUFF
37 TEST
A1
A-Z
4
IN LO
38 OSC 3
B1
IN HI
3
CREF -
39 OSC 2
C1
COMMON
40 OSC 1
2
CREF+
1
D1
V+
HLDR
E1
(10’s)
ICL7116 (MQFP)
TOP VIEW
REF HI
ICL7116, ICL7117 (PDIP)
TOP VIEW
44 43 42 41 40 39 38 37 36 35 34
33
2
32
NC
TEST
3
31
C3
OSC 3
4
30
A3
NC
5
29
G3
OSC 2
6
28
BP
OSC 1
7
27
POL
HLDR
8
26
AB4
NC
NC
30 IN LO
1
G2
A2
12
29 A-Z
F2
13
28 BUFF
E2
14
27 INT
D3
15
26 V-
D1
9
25
E3
B3
16
25 G2 (10’s)
C1
10
24
F3
F3
17
24 C3
B1
11
23
12 13 14 15 16 17 18 19 20 21 22
B3
E3
18
23 A3
(1000) AB4
19
22 G3
POL
20
21 BP/GND
(100’s)
(MINUS)
(100’s)
A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number
3083.2
ICL7116, ICL7117
Absolute Maximum Ratings
Thermal Information
Supply Voltage
ICL7116, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
ICL7117, V+ to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
ICL7117, V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-9V
Analog Input Voltage (Either Input) (Note 1). . . . . . . . . . . . . V+ to VReference Input Voltage (Either Input) . . . . . . . . . . . . . . . . . V+ to VClock Input
ICL7116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+
ICL7117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V+
Thermal Resistance (Typical, Note 2)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(MQFP - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
(Note 3) TA = 25oC, fCLOCK = 48kHz, VREF = 100mV
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-000.0
±000.0
+000.0
Digital
Reading
999
999/
1000
1000
Digital
Reading
SYSTEM PERFORMANCE
Zero Input Reading
VIN = 0V, Full Scale = 200mV
Ratiometric Reading
VlN = VREF , VREF = 100mV
Rollover Error
-VIN = +VlN ≅ 195mV Difference in Reading for Equal
Positive and Negative Inputs Near Full Scale
-
±0.2
±1
Counts
Linearity
Full Scale = 200mV or Full Scale = 2V Maximum
Deviation from Best Straight Line Fit (Note 5)
-
±0.2
±1
Counts
Common Mode Rejection Ratio
VCM = ±1V, VIN = 0V, Full Scale = 200mV (Note 5)
-
50
-
µV/V
Noise
VIN = 0V, Full Scale = 200mV (Peak-To-Peak Value
Not Exceeded 95% of Time) (Note 5)
-
15
-
µV
Leakage Current Input
VlN = 0 (Note 5)
-
1
10
pA
Zero Reading Drift
VlN = 0, 0oC To 70oC (Note 5)
-
0.2
1
µV/oC
Scale Factor Temperature Coefficient
VIN = 199mV, 0oC To 70oC (Note 5)
-
1
5
ppm/oC
V+ Supply Current
VIN = 0 (Does Not Include LED Current for ICL7117)
-
1.0
1.8
mA
V- Supply Current
ICL7117 Only
-
0.6
1.8
mA
COMMON Pin Analog Common Voltage
25kΩ Between Common and Positive Supply (With
Respect to + Supply)
2.4
3.0
3.2
V
-
80
-
ppm/oC
4
5.5
6
V
mA
Temperature Coefficient of Analog Common 25kΩ Between Common and Positive Supply (With
Respect to + Supply) (Note 5)
DISPLAY DRIVER (ICL7116 ONLY)
Peak-To-Peak Segment Drive Voltage
Peak-To-Peak Backplane Drive Voltage
V+ = to V- = 9V, (Note 4)
DISPLAY DRIVER (ICL7117 ONLY)
Segment Sinking Current
(Except Pins 19 and 20)
V+ = 5V, Segment Voltage = 3V
5
8
-
Pin 19 Only
10
16
-
mA
Pin 20 Only
4
7
-
mA
NOTES:
3. Unless otherwise noted, specifications apply to both the ICL7116 and ICL7117. ICL7116 is tested in the circuit of Figure 1. ICL7117 is
tested in the circuit of Figure 2.
4. Back plane drive is in phase with segment drive for ‘off’ segment, 180 degrees out of phase for ‘on’ segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV.
5. Not tested, guaranteed by design.
2
ICL7116, ICL7117
Typical Applications and Test Circuits
-
+
9V
C5
R4
C2 R2
C3
A3 23
G3 22
BP 21
20 POL
C3 24
17 F3
19 AB4
V- 26
G2 25
14 E2
16 B3
INT 27
13 F2
15 D3
A-Z 29
BUFF 28
12 A2
IN HI 31
IN LO 30
COM 32
DISPLAY
CREF- 33
V+ 35
CREF+ 34
TEST 37
REF HI 36
OSC 3 38
OSC 2 39
C1
OSC 1 40
C1 = 0.1µF
C2 = 0.47µF
C3 = 22µF
C4 = 100pF
C5 = 0.01µF
R1 = 24kΩ
R2 = 47kΩ
R3 = 100kΩ
R4 = 1kΩ
R5 = 1MΩ
R5
18 E3
C4
R3
+
R1
-
IN
11 B2
D2
9
10 C2
E1
8
A1
5
F1
B1
4
G1
C1
3
7
D1
2
6
HLDR
1
ICL7116
DISPLAY
FIGURE 1. ICL7116 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV
FULL SCALE
+5V
-
+
R6
-5V
TO
DECIMAL
POINT
IN
R5
R1
TP3
TP1 TP2
C5 C R2
2
R4
A3 23
G3 22
GND 21
19 AB4
20 POL
C3 24
17 F3
18 E3
V- 26
INT 27
14 E2
A-Z 29
BUFF 28
13 F2
IN HI 31
IN LO 30
COM 32
CREF- 33
V+ 35
CREF+ 34
TEST 37
REF HI 36
OSC 3 38
OSC 2 39
DISPLAY
TP4
C1
OSC 1 40
C3
G2 25
C4
16 B3
R3
15 D3
TP5
C1 = 0.1µF
C2 = 0.47µF
C3 = 22µF
C4 = 100pF
C5 = 0.01µF
R1 = 24kΩ
R2 = 47kΩ
R3 = 100kΩ
R4 = 1kΩ
R5 = 1MΩ
R6 = 150Ω
12 A2
11 B2
D2
9
10 C2
E1
8
A1
5
F1
B1
4
G1
C1
3
7
D1
2
6
HLDR
1
ICL7117
DISPLAY
FIGURE 2. ICL7117 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV
FULL SCALE
3
ICL7116, ICL7117
Design Information Summary Sheet
• DISPLAY COUNT
• OSCILLATOR FREQUENCY
V IN
COUNT = 1000 × --------------V REF
fOSC = 0.45/RC
COSC > 50pF; ROSC > 50kΩ
fOSC (Typ) = 48kHz
• CONVERSION CYCLE
• OSCILLATOR PERIOD
tCYC = tCL0CK x 4000
tCYC = tOSC x 16,000
when fOSC = 48KHz; tCYC = 333ms
tOSC = RC/0.45
• INTEGRATION CLOCK FREQUENCY
• COMMON MODE INPUT VOLTAGE
fCLOCK = fOSC /4
(V- + 1V) < VlN < (V+ - 0.5V)
• INTEGRATION PERIOD
• AUTO-ZERO CAPACITOR
tINT = 1000 x (4/fOSC)
0.01µF < CAZ < 1µF
• 60/50Hz REJECTION CRITERION
• REFERENCE CAPACITOR
tINT /t60Hz or tlNT /t50Hz = Integer
0.1µF < CREF < 1µF
• OPTIMUM INTEGRATION CURRENT
• VCOM
IINT = 4µA
Biased between V+ and V-.
• FULL SCALE ANALOG INPUT VOLTAGE
• VCOM ≅ V+ - 2.8V
VlNFS (Typ) = 200mV or 2V
Regulation lost when V+ to V- < ≅6.8V.
If VCOM is externally pulled down to (V + to V -)/2,
the VCOM circuit will turn off.
• INTEGRATE RESISTOR
V INFS
R INT = ----------------I INT
• ICL7116 POWER SUPPLY: SINGLE 9V
V+ - V- = 9V
Digital supply is generated internally
VTEST ≅ V+ - 4.5V
• INTEGRATE CAPACITOR
( t INT ) ( I INT )
C INT = -------------------------------V INT
• ICL7116 DISPLAY: LCD
• INTEGRATOR OUTPUT VOLTAGE SWING
Type: Direct drive with digital logic supply amplitude.
( t INT ) ( I INT )
V INT = -------------------------------C INT
• ICL7117 POWER SUPPLY: DUAL ±5.0V
V+ = +5V to GND
V- = -5V to GND
Digital Logic and LED driver supply V+ to GND
• VINT MAXIMUM SWING:
(V- + 1.0V) < VINT < (V+ - 0.5V), VINT (Typ) = 2V
• ICL7117 DISPLAY: LED
Type: Non-Multiplexed Common Anode
Typical Integrator Amplifier Output Waveform (INT Pin)
AUTO ZERO PHASE
(COUNTS)
2999 - 1000
SIGNAL INTEGRATE
PHASE FIXED
1000 COUNTS
DE-INTEGRATE PHASE
0 - 1999 COUNTS
TOTAL CONVERSION TIME = 4000 x tCLOCK = 16,000 x tOSC
4
ICL7116, ICL7117
Pin Descriptions
PIN NUMBER
40 PIN DIP
44 PIN
FLATPACK
NAME
FUNCTION
1
8
HLDR
Input
2
9
D1
Output
Driver Pin for Segment “D” of the display units digit.
3
10
C1
Output
Driver Pin for Segment “C” of the display units digit.
4
11
B1
Output
Driver Pin for Segment “B” of the display units digit.
5
12
A1
Output
Driver Pin for Segment “A” of the display units digit.
6
13
F1
Output
Driver Pin for Segment “F” of the display units digit.
7
14
G1
Output
Driver Pin for Segment “G” of the display units digit.
8
15
E1
Output
Driver Pin for Segment “E” of the display units digit.
9
16
D2
Output
Driver Pin for Segment “D” of the display tens digit.
10
17
C2
Output
Driver Pin for Segment “C” of the display tens digit.
11
18
B2
Output
Driver Pin for Segment “B” of the display tens digit.
12
19
A2
Output
Driver Pin for Segment “A” of the display tens digit.
13
20
F2
Output
Driver Pin for Segment “F” of the display tens digit.
14
21
E2
Output
Driver Pin for Segment “E” of the display tens digit.
15
22
D3
Output
Driver pin for segment “D” of the display hundreds digit.
16
23
B3
Output
Driver pin for segment “B” of the display hundreds digit.
17
24
F3
Output
Driver pin for segment “F” of the display hundreds digit.
18
25
E3
Output
Driver pin for segment “E” of the display hundreds digit.
19
26
AB4
Output
Driver pin for both “A” and “B” segments of the display thousands digit.
20
27
POL
Output
Driver pin for the negative sign of the display.
21
28
BP/GND
Output
Driver pin for the LCD backplane/Power Supply Ground.
22
29
G3
Output
Driver pin for segment “G” of the display hundreds digit.
23
30
A3
Output
Driver pin for segment “A” of the display hundreds digit.
24
31
C3
Output
Driver pin for segment “C” of the display hundreds digit.
25
32
G2
Output
Driver pin for segment “G” of the display tens digit.
26
34
V-
Supply
Negative power supply.
27
35
INT
Output
Integrator amplifier output. To be connected to integrating capacitor.
28
36
BUFF
Output
Input buffer amplifier output. To be connected to integrating resistor.
DESCRIPTION
Display Hold Control.
29
37
A-Z
Input
Integrator amplifier input. To be connected to auto-zero capacitor.
30
31
38
39
IN LO
IN HI
Input
Differential inputs. To be connected to input voltage to be measured. LO and HI
designators are for reference and do not imply that LO should be connected to
lower potential, e.g., for negative inputs IN LO has a higher potential than IN HI.
32
40
COMMON
Supply/
Output
33
34
41
42
CREF CREF+
35
36
43
44
V+
REF HI
Supply
37
3
TEST
Input
38
39
40
4
6
7
OSC3
OSC2
OSC1
Output
Output
Input
Internal voltage reference output.
Connection pins for reference capacitor.
Power Supply.
Display test. Turns on all segments when tied to V+.
Device clock generator circuit connection pins.
5
ICL7116, ICL7117
Detailed Description
output to return to zero is proportional to the input signal.
Specifically the digital reading displayed is:
Analog Section
 V IN 
DISPLAY COUNT = 1000  ----------------- .
 V REF
Figure 3 shows the Analog Section for the ICL7116 and
ICL7117. Each measurement cycle is divided into three
phases. They are (1) auto-zero (A-Z), (2) signal integrate
(INT) and (3) de-integrate (DE).
Differential Input
The input can accept differential voltages anywhere within the
common mode range of the input amplifier, or specifically from
0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical.
However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large
positive common mode voltage with a near full scale negative
differential input voltage. The negative input signal drives the
integrator positive when most of its swing has been used up
by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less
than the recommended 2V full scale swing with little loss of
accuracy. The integrator output can swing to within 0.5V of
either supply without loss of linearity.
Auto-Zero Phase
During auto-zero three things happen. First, input high and low
are disconnected from the pins and internally shorted to analog
COMMON. Second, the reference capacitor is charged to the
reference voltage. Third, a feedback loop is closed around the
system to charge the auto-zero capacitor CAZ to compensate
for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case, the
offset referred to the input is less than 10µV.
Signal Integrate Phase
During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are
connected to the external pins. The converter then integrates
the differential voltage between IN HI and IN LO for a fixed time.
This differential voltage can be within a wide common mode
range: up to 1V from either supply. If, on the other hand, the
input signal has no return with respect to the converter power
supply, IN LO can be tied to analog COMMON to establish the
correct common mode voltage. At the end of this phase, the
polarity of the integrated signal is determined.
Differential Reference
The reference voltage can be generated anywhere within the
power supply voltage of the converter. The main source of
common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge to stray capacity
on its nodes. If there is a large common mode voltage, the
reference capacitor can gain charge (increase voltage) when
called up to de-integrate a positive signal but lose charge
(decrease voltage) when called up to de-integrate a negative
input signal. This difference in reference for positive or
negative input voltage will give a roll-over error. However, by
selecting the reference capacitor such that it is large enough
in comparison to the stray capacitance, this error can be
held to less than 0.5 count worst case. (See Component
Value Selection.)
De-Integrate Phase
The final phase is de-integrate, or reference integrate. Input
low is internally connected to analog COMMON and input
high is connected across the previously charged reference
capacitor. Circuitry within the chip ensures that the capacitor
will be connected with the correct polarity to cause the
integrator output to return to zero. The time required for the
STRAY
STRAY
CREF
RINT
CREF+
REF HI
34
36
V+
CREF-
28
33
A-Z
CAZ
BUFFER V+
35
CINT
A-Z
INT
29
27
INTEGRATOR
-
+
-
10µA
+
+
2.8V
31
IN HI
INT
DE-
DE+
INPUT
HIGH
6.2V
A-Z
A-Z
COMPARATOR
A-Z
+
N
DE+
32
-
DE-
COMMON
30
INT
INPUT
LOW
A-Z AND DE(±)
IN LO
26
V-
FIGURE 3. ANALOG SECTION OF ICL7116 AND ICL711
6
TO
DIGITAL
SECTION
ICL7116, ICL7117
Analog COMMON
V+
This pin is included primarily to set the common mode
voltage for battery operation (ICL7116) or for any system
where the input signals are floating with respect to the power
supply. The COMMON pin sets a voltage that is approximately 2.8V less than the positive supply. This is selected to
give a minimum end-of-life battery voltage of about 6.8V.
However, analog COMMON has some of the attributes of a
reference voltage. When the total supply voltage is large
enough to cause the zener to regulate (>6.8V), the COMMON voltage will have a low voltage coefficient (0.001%/V),
low output impedance (≅15Ω), and a temperature coefficient
typically less than 80ppm/oC.
V
6.8V
ZENER
REF HI
COMMON
IZ
ICL7116
ICL7117
V-
FIGURE 4A.
The limitations of the on chip reference should also be
recognized, however. With the ICL7117, the internal heating which results from the LED drivers can cause some
degradation in performance. Due to their higher thermal
resistance, plastic parts are poorer in this respect than
ceramic. The combination of reference Temperature
Coefficient (TC), internal chip dissipation, and package
thermal resistance can increase noise near full scale from
25µV to 80µVP-P . Also the linearity in going from a high
dissipation count such as 1000 (20 segments on) to a low
dissipation count such as 1111 (8 segments on) can suffer
by a count or more. Devices with a positive TC reference
may require several counts to pull out of an over-range condition. This is because over-range is a low dissipation
mode, with the three least significant digits blanked. Similarly, units with a negative TC may cycle between over
range and a non-over range count as the die alternately
heats and cools. All these problems are of course
eliminated if an external reference is used.
V+
V
6.8kΩ
20kΩ
ICL7116
ICL7117
ICL8069
1.2V
REFERENCE
REF HI
COMMON
FIGURE 4B.
FIGURE 4. USING AN EXTERNAL REFERENCE
TEST
The TEST pin serves two functions. On the ICL7116 it is
coupled to the internally generated digital supply through a
500Ω resistor. Thus it can be used as the negative supply for
externally generated segment drivers such as decimal points
or any other annunciator the user may want to include on the
LCD display. Figures 5 and 6 show such an application. No
more than a 1mA load should be applied.
The ICL7116, with its negligible dissipation, suffers from
none of these problems. In either case, an external
reference can easily be added, as shown in Figure 4.
Analog COMMON is also used as the input low return during
auto-zero and de-integrate. If IN LO is different from analog
COMMON, a common mode voltage exists in the system
and is taken care of by the excellent CMRR of the converter.
However, in some applications IN LO will be set at a fixed
known voltage (power supply common for instance). In this
application, analog COMMON should be tied to the same
point, thus removing the common mode voltage from the
converter. The same holds true for the reference voltage. If
reference can be conveniently tied to analog COMMON, it
should be since this removes the common mode voltage
from the reference system.
V+
1MΩ
TO LCD
DECIMAL
POINT
ICL7116
BP
TEST
Within the lC, analog COMMON is tied to an N-Channel FET
that can sink approximately 30mA of current to hold the
voltage 2.8V below the positive supply (when a load is trying
to pull the common line positive). However, there is only
10µA of source current, so COMMON may easily be tied to a
more negative voltage thus overriding the internal reference.
21
37
TO LCD
BACKPLANE
FIGURE 5. SIMPLE INVERTER FOR FIXED DECIMAL POINT
The second function is a “lamp test”. When TEST is pulled
high (to V+) all segments will be turned on and the display
should read “-1888”. The TEST pin will sink about 5mA under
these conditions.
CAUTION: On the ICL7116, in the lamp test mode, the segments
have a constant DC voltage (no square-wave) and may burn the
LCD display if left in this mode for several minutes.
7
ICL7116, ICL7117
Digital Section
V+
Figures 7 and 8 show the digital section for the ICL7116 and
ICL7117, respectively. In the ICL7116, an internal digital
ground is generated from a 6V Zener diode and a large
P-Channel source follower. This supply is made stiff to absorb
the relative large capacitive currents when the back plane
(BP) voltage is switched. The BP frequency is the clock frequency divided by 800. For three readings/second this is a
60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude and
are in phase with BP when OFF, but out of phase when ON. In
all cases negligible DC voltage exists across the segments.
V+
BP
ICL7116
TO LCD
DECIMAL
POINTS
DECIMAL
POINT
SELECT
TEST
CD4030
GND
FIGURE 6. EXCLUSIVE ‘OR’ GATE FOR DECIMAL POINT DRIVE
Figure 8 is the Digital Section of the ICL7117. It is identical
to the ICL7116 except that the regulated supply and back
plane drive have been eliminated and the segment drive has
been increased from 2mA to 8mA, typical for instrument size
common anode LED displays. Since the 1000 output (pin 19)
must sink current from two LED segments, it has twice the
drive capability or 16mA.
HOLD Reading Input
The HLDR input will prevent the latch from being updated
when this input is at logic “1”. The chip will continue to make
A/D conversions, however, the results will not be updated to
the internal latches until this input goes low. This input can be
left open or connected to TEST (ICL7116) or GROUND
(ICL7117) to continuously update the display. This input is
CMOS compatible, and has a 70kΩ (See Figure 7) typical
resistance to either TEST (ICL7116) or GROUND (ICL7117).
In both devices, the polarity indication is “on” for negative
analog inputs. If IN LO and IN HI are reversed, this indication
can be reversed also, if desired.
a
a
a
f
g
b
e
a
f
b
b
f
g
c
e
c
d
b
g
c
d
e
c
d
BACKPLANE
21
LCD PHASE DRIVER
7
SEGMENT
DECODE
TYPICAL SEGMENT OUTPUT
V+
7
SEGMENT
DECODE
7
SEGMENT
DECODE
÷200
0.5mA
LATCH
SEGMENT
OUTPUT
2mA
1000’s
COUNTER
100’s
COUNTER
10’s
COUNTER
1’s
COUNTER
INTERNAL DIGITAL GROUND
TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
35
V+
CLOCK
† THREE INVERTERS
÷4
†
ONE INVERTER SHOWN
FOR CLARITY
LOGIC CONTROL
6.2V
500Ω
TEST
INTERNAL
DIGITAL
GROUND
70kΩ
VTH = 1V
37
26
40
OSC 1
39
OSC 2
38
OSC 3
FIGURE 7. ICL7116 DIGITAL SECTION
8
1
HLDR
V-
ICL7116, ICL7117
a
f
a
a
g
e
b
a
f
b
c
c
f
b
g
e
e
c
d
d
7
SEGMENT
DECODE
TYPICAL SEGMENT OUTPUT
V+
b
g
c
d
7
SEGMENT
DECODE
7
SEGMENT
DECODE
LATCH
0.5mA
TO
SEGMENT
1000’s
COUNTER
100’s
COUNTER
10’s
COUNTER
1’s
COUNTER
8mA
TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
DIGITAL GROUND
V+
35
V+
CLOCK
†
÷4
37
LOGIC CONTROL
† THREE INVERTERS
ONE INVERTER SHOWN
FOR CLARITY
OSC 1
21
70kΩ
40
39
OSC 2
TEST
500Ω
38
DIGITAL
GROUND
1
HLDR
OSC 3
FIGURE 8. ICL7117 DIGITAL SECTION
System Timing
INTERNAL TO PART
Figure 9 shows the clocking arrangement used in the
ICL7116 and ICL7117. Two basic clocking arrangements
can be used:
÷4
CLOCK
1. Figure 9A, an external oscillator connected to pin 40.
2. Figure 9B, an R-C oscillator using all three pins.
40
The oscillator frequency is divided by four before it clocks the
decade counters. It is then further divided to form the three
convert-cycle phases. These are signal integrate (1000
counts), reference de-integrate (0 to 2000 counts) and autozero (1000 counts to 3000 counts). For signals less than full
scale, auto-zero gets the unused portion of reference deintegrate. This makes a complete measure cycle of 4,000
counts (16,000 clock pulses) independent of input voltage.
For three readings/second, an oscillator frequency of 48kHz
would be used.
39
38
GND ICL7117
TEST ICL7116
FIGURE 9A. EXTERNAL OSCILLATOR
INTERNAL TO PART
÷4
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz,
40kHz, 331/3kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 100kHz, 662/3kHz,
50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5
readings/second) will reject both 50Hz and 60Hz (also
400Hz and 440Hz).
40
39
38
R
C
FIGURE 9B. RC OSCILLATOR
FIGURE 9. CLOCK CIRCUITS
9
CLOCK
ICL7116, ICL7117
Component Value Selection
have a full scale reading when the voltage from the
transducer is 0.682V. Instead of dividing the input down to
200mV, the designer should use the input voltage directly
and select VREF = 0.341V. Suitable values for integrating
resistor and capacitor would be 120kΩ and 0.22µF. This
makes the system slightly quieter and also avoids a divider
network on the input. The ICL7117 with ±5V supplies can
accept input signals up to ±4V. Another advantage of this
system occurs when a digital reading of zero is desired for
VIN ≠ 0. Temperature and weighing systems with a variable
fare are examples. This offset reading can be conveniently
generated by connecting the voltage transducer between IN
HI and COMMON and the variable (or fixed) offset voltage
between COMMON and IN LO.
Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 100µA of quiescent current. They can
supply 4µA of drive current with negligible nonlinearity. The
integrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 2V full scale, 470kΩ is near optimum and
similarly a 47kΩ for a 200mV scale.
Integrating Capacitor
The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance buildup will
not saturate the integrator swing (approximately. 0.5V from
either supply). In the ICL7116 or the ICL7117, when the
analog COMMON is used as a reference, a nominal +2V fullscale integrator swing is fine. For the ICL7117 with +5V
supplies and analog COMMON tied to supply ground, a
±3.5V to +4V swing is nominal. For three readings/second
(48kHz clock) nominal values for ClNT are 0.22µF and 0.1µF,
respectively. Of course, if different oscillator frequencies are
used, these values should be changed in inverse proportion
to maintain the same output swing.
ICL7117 Power Supplies
3. The ICL7117 is designed to work from ±5V supplies.
However, if a negative supply is not available, it can be
generated from the clock output with 2 diodes, 2
capacitors, and an inexpensive lC. Figure 10 shows this
application. See ICL7660 data sheet for an alternative.
V+
An additional requirement of the integrating capacitor is that
it must have a low dielectric absorption to prevent roll-over
errors. While other types of capacitors are adequate for this
application, polypropylene capacitors give undetectable
errors at reasonable cost.
CD4009
V+
OSC 1
Auto-Zero Capacitor
OSC 2
The size of the auto-zero capacitor has some influence on
the noise of the system. For 200mV full scale where noise is
very important, a 0.47µF capacitor is recommended. On the
2V scale, a 0.047µF capacitor increases the speed of recovery from overload and is adequate for noise on this scale.
OSC 3
IN914
0.047
µF
ICL7117
+
10
µF
-
IN914
GND
V-
Reference Capacitor
A 0.1µF capacitor gives good results in most applications.
Generally 1µF will hold the roll-over error to 0.5 counts in this
instance.
V- = 3.3V
FIGURE 10.
Oscillator Components
For all ranges of frequency a 100kΩ resistor is recommended
and the capacitor is selected from the equation:
GENERATING NEGATIVE SUPPLY FROM +5V
In fact, in selected applications no negative supply is
required. The conditions to use a single +5V supply are:
0.45
f = ------------ For 48kHz Clock (3 Readings/sec), C = 100pF.
RC
1. The input signal can be referenced to the center of the
common mode range of the converter.
2. The signal is less than ±1.5V.
Reference Voltage
3. An external reference is used.
The analog input required to generate full scale output (2000
counts) is: VlN = 2VREF . Thus, for the 200mV and 2V scale,
VREF should equal 100mV and 1V, respectively. However, in
many applications where the A/D is connected to a
transducer, there will exist a scale factor other than unity
between the input voltage and the digital reading. For
instance, in a weighing system, the designer might like to
10
ICL7116, ICL7117
Typical Applications
Application Notes
The ICL7116 and ICL7117 may be used in a wide variety of
configurations. The circuits which follow show some of the
possibilities, and serve to illustrate the exceptional versatility of these A/D converters.
NOTE #
The following application notes contain very useful
information on understanding and applying this part and
are available from Intersil Corporation.
AnswerFAX
DOC. #
DESCRIPTION
AN016
“Selecting A/D Converters”
9016
AN017
“The Integrating A/D Converter”
9017
AN018
“Do’s and Don’ts of Applying A/D
Converters”
9018
AN023
“Low Cost Digital Panel Meter Designs”
9023
AN032
“Understanding the Auto-Zero and
Common Mode Performance of the
ICL7136/7/9 Family”
9032
AN046
“Building a Battery-Operated Auto
Ranging DVM with the ICL7106”
9046
AN047
“Games People Play with Intersil’ A/D
Converters,” edited by Peter Bradshaw
9047
AN052
“Tips for Using Single Chip 31/2 Digit A/D
Converters”
9052
Typical Applications
OSC 1 40
OSC 1 40
100kΩ
OSC 3 38
TEST 37
OSC 3 38
SET VREF
= 100mV
100pF
TEST 37
1kΩ
22kΩ
CREF 34
0.1µF
COMMON 32
CREF 33
1MΩ
A-Z 29
BUFF 28
IN
0.01µF
0.47µF
IN LO 30
-
47kΩ
A-Z 29
+
-
BUFF 28
9V
A3 23
0.1µF
1MΩ
+
IN
0.01µF
0.47µF
-
47kΩ
INT 27
0.22µF
V - 26
0.22µF
-5V
G2 25
G2 25
C3 24
22kΩ
IN HI 31
INT 27
V - 26
1kΩ
COMMON 32
+
IN HI 31
IN LO 30
+5V
V+ 35
V+ 35
CREF 33
SET VREF
= 100mV
100pF
REF HI 36
REF HI 36
CREF 34
100kΩ
OSC 2 39
OSC 2 39
C3 24
TO DISPLAY
A3 23
G3 22
G3 22
BP 21
GND 21
TO BACKPLANE
TO DISPLAY
Values shown are for 200mV full scale, 3 readings/sec., floating
supply voltage (9V battery).
Values shown are for 200mV full scale, 3 readings/sec. IN LO may
be tied to either COMMON for inputs floating with respect to
supplies, or GND for single ended inputs. (See discussion under
Analog COMMON.)
FIGURE 11. ICL7116 USING THE INTERNAL REFERENCE
FIGURE 12. ICL7117 USING THE INTERNAL REFERENCE
11
ICL7116, ICL7117
Typical Applications
OSC 1 40
(Continued)
OSC 1 40
100kΩ
OSC 2 39
OSC 3 38
TEST 37
OSC 3 38
SET VREF
= 1.000V
100pF
REF HI 36
V+ 35
V+
25kΩ
CREF 34
1MΩ
CREF 34
0.01µF
1MΩ
+
-
0.47µF
A-Z 29
470kΩ
IN
0.01µF
IN LO 30
-
47kΩ
BUFF 28
INT 27
INT 27
0.22µF
V
-
0.22µF
V - 26
G2 25
A3 23
1.2V (ICL8069)
IN HI 31
IN
0.047µF
A-Z 29
0.1µF
COMMON 32
+
IN HI 31
BUFF 28
1kΩ 10kΩ 15kΩ
CREF 33
COMMON 32
IN LO 30
+5V
V+ 35
24kΩ
0.1µF
CREF 33
C3 24
SET VREF
= 100mV
100pF
TEST 37
REF HI 36
V - 26
100kΩ
OSC 2 39
G2 25
C3 24
TO DISPLAY
TO DISPLAY
A3 23
G3 22
G3 22
GND 21
GND 21
An external reference must be used in this application, since the
voltage between V+ and V- is insufficient for correct operation of the
internal reference.
FIGURE 13. ICL7116 AND ICL7117: RECOMMENDED
COMPONENT VALUES FOR 2.0V FULL SCALE
FIGURE 14. ICL7117 OPERATED FROM SINGLE +5V SUPPLY
V+
OSC 1 40
OSC 1 40
100kΩ
OSC 3 38
OSC 3 38
TEST 37
100pF
REF HI 36
V+ 35
V+ 35
CREF 34
CREF 34
0.1µF
CREF 33
IN HI 31
IN HI 31
IN LO 30
IN LO 30
BUFF 28
0.47µF
A-Z 29
47kΩ
BUFF 28
0.22µF
V - 26
V
A3 23
0.1µF
22kΩ
ZERO
ADJUST
0.01µF
0.47µF
SILICON NPN
MPS 3704 OR
SIMILAR
47kΩ
9V
0.22µF
G2 25
G2 25
C3 24
100kΩ 1MΩ
100kΩ 220kΩ
INT 27
INT 27
V - 26
SCALE
FACTOR
ADJUST
COMMON 32
COMMON 32
A-Z 29
100pF
TEST 37
REF HI 36
CREF 33
100kΩ
OSC 2 39
OSC 2 39
C3 24
TO DISPLAY
A3 23
G3 22
G3 22
GND 21
BP 21
TO DISPLAY
TO BACKPLANE
A silicon diode-connected transistor has a temperature coefficient of
about -2mV/oC. Calibration is achieved by placing the sensing
transistor in ice water and adjusting the zeroing potentiometer for a
000.0 reading. The sensor should then be placed in boiling water
and the scale-factor potentiometer adjusted for a 100.0 reading.
The resistor values within the bridge are determined by the desired
sensitivity.
FIGURE 15. ICL7117 MEASUREING RATIOMETRIC VALUES OF
QUAD LOAD CELL
FIGURE 16. ICL7116 USED AS A DIGITAL CENTIGRADE
THERMOMETER
12
ICL7116, ICL7117
Dual-In-Line Plastic Packages (PDIP)
E40.6 (JEDEC MS-011-AC ISSUE B)
N
40 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
SYMBOL
-B-
A2
-C-
SEATING
PLANE
e
B1
D1
B
0.010 (0.25) M
A1
eC
C A B S
MAX
NOTES
-
0.250
-
6.35
4
0.015
-
0.39
-
4
A2
0.125
0.195
3.18
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.030
0.070
0.77
1.77
8
eA
C
0.008
0.015
0.204
0.381
-
D
1.980
2.095
D1
0.005
-
A
L
D1
MIN
A
E
BASE
PLANE
MAX
A1
-AD
MILLIMETERS
MIN
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
50.3
53.2
5
-
5
0.13
E
0.600
0.625
15.24
15.87
6
E1
0.485
0.580
12.32
14.73
5
e
0.100 BSC
2.54 BSC
-
eA
0.600 BSC
15.24 BSC
6
eB
-
0.700
-
17.78
7
L
0.115
0.200
2.93
5.08
4
N
40
40
9
Rev. 0 12/93
13
ICL7116, ICL7117
Metric Plastic Quad Flatpack Packages (MQFP/PQFP)
Q44.10x10 (JEDEC MO-108AA-2 ISSUE A)
D
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
D1
-D-
-B-
-AE E1
e
PIN 1
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.093
-
2.35
-
A1
0.004
0.010
0.10
0.25
-
A2
0.077
0.083
1.95
2.10
-
B
0.012
0.018
0.30
0.45
6
B1
0.012
0.016
0.30
0.40
-
D
0.510
0.530
12.95
13.45
3
D1
0.390
0.398
9.90
10.10
4, 5
E
0.510
0.530
12.95
13.45
3
E1
0.390
0.398
9.90
10.10
4, 5
L
0.026
0.037
0.65
0.95
N
44
44
e
0.032 BSC
0.80 BSC
SEATING
A PLANE
-H-
7
Rev. 1 1/94
NOTES:
0.10
0.004
0.40
0.016 MIN
-C-
5o-16o
0.20
A-B S
0.008 M C
0o MIN
A2 A1
L
5o-16o
2. All dimensions and tolerances per ANSI Y14.5M-1982.
D S
3. Dimensions D and E to be determined at seating plane -C- .
B
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
B1
0o-7o
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
0.13/0.17
0.005/0.007
6. Dimension B does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
7. “N” is the number of terminal positions.
BASE METAL
WITH PLATING
0.13/0.23
0.005/0.009
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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14
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