TECHNICAL DATA 3 ½ - Digit LED Display, A/D Converters KL7107 DESCRIPTION The KL7107 are high performance, low power, 3 ½ digit A/D converters. Included are seven segment decoders, display drivers, a reference, and a clock. The KL7107 will directly drive an instrument size light emitting diode (LED) display. The KL7107 bring together a combination of high accuracy,versatility, and true economy. It features autozero to less than 10 µV, zero drift of less than 1µV/°C, input bias current of 10pA (Max), and rollover error of less than one count. True differential inputs and reference are useful in all systems, but give the designer an uncommon advantage when measuring load cells, strain gauges and other bridge type transducers. 40 1 DIP-40 ORDERING INFORMATION Device KL7107N Temperature Range ТA= 0°C …+70°C FEATURES Package DIP-40 Packing Tube PIN CONNECTIONS • Guaranteed Zero Reading for 0V Input on All Scales • True Polarity at Zero for Precise Null Detection • 1pA Typical Input Current • True Differential Input and Reference, Direct LED Display Drive • Low Noise – Less Than 15µVp-p • On Chip Clock and Reference • Low Power Dissipation – Typically Less Than 10mW • No Additional Active Circuits Required • Enhanced Display Stability TOP VIEW V+ 1 40 OSC 1 D1 2 39 OSC 2 C1 3 38 OSC 3 B1 4 37 TEST A1 5 36 REF H1 F1 6 35 REF L0 G1 7 34 CREF+ E1 8 33 CREF- D2 9 32 COMMON С2 10 31 IN HI B2 11 30 IN LO A2 12 29 A-Z F2 13 28 BUFF E2 14 27 INT D3 15 26 V- B3 16 25 G2 (10 s) , C3 F3 17 24 E3 18 23 A3 (1000) AB4 19 22 G3 POL 20 21 GND , (100 s) (MINUS) 1 July 2011, ver.00 KL7107 Absolute Maximum Ratings Supply Voltage : V+ to GND V- to GND Thermal Information 6V -9V Thermal Resistance (Typical, Note 2) PDIP Package 50 Analog Input Voltage (Either Input) (Note 1) V+ to V- Maximum Junction Temperature 150°C Reference Input Voltage (Either Input) V+ to V- Maximum Storage Temperature Range -65°C to 150°C Clock Input GND to V+ Maximum Lead Temperature (Soldering 10s) 300°C Operating Conditions Temperature Range 0°C to 70°C CAUTION: * Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µА. 2. ΘJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications (Note 3) Parameter Test Conditions Min Typ Max Unit Zero Input Reading VIN = 0.0V, Full Scale = 200mV -000.0 ±000.0 +000.0 Stability (Last Digit) Fixed Input Voltage (Note 5) -000.0 ±000.0 +000.0 Ratiometric Reading VIN = VREF,VREF = 100mV 999 999/1000 1000 Rollover Error -VIN= +VIN ≈ 200mV Difference in Reading for Equal Positive and Negative Inputs Near Full Scale Full Scale = 200mV or Full Scale = 2V Maximum Deviation from Best Straight Line Fit (Note 4) VCM = 1V, VIN= 0V, Full Scale = 200mV (Note 4) VIN= 0V, Full Scale = 200mV (Peak-To-Peak Value Not Exceeded 95% of Time) VIN = 0 (Note 4) VIN = 0, 0°C to 70°C (Note 5) - ±0.2 ±1 Digital Reading Digital Reading Digital Reading Counts - ±0.2 ±1 Counts - 50 - µV/V - 15 - µV - 1 0.2 1 10 1 5 pA µV/°C ppm/°C - 1.0 1.8 mA SYSTEM PERFORMANCE Linearity Common Mode Rejection Ratio Noise Leakage Current Input Zero Reading Drift Scale Factor Temperature Coefficient End Power Supply Character V+ Supply Current End Power Supply Character V- Supply Current COMMON Pin Analog Common Voltage Temperature Coefficient of Analog Common VIN = 199mV,0°C to 70oC, (Ext. Ref. 0ppm/x°C) (Note 4) VIN = 0 (Does Not Include LED Current) - 0.6 - 25kΩ Between Common and Positive Supply (With Respect to + Supply) 25kΩ Between Common and Positive Supply (With Respect to + Supply) 2 1.8 mA 2.4 3.0 3.2 V - 80 - ppm/°C July 2011, ver.00 KL7107 Electrical Specifications (Note 3) (Continued) Parameter Test Conditions Min Typ Max Unit 5 8 - mA 10 16 - 4 7 - mA mA DISPLAY DRIVER Segment Sinking Current Except Pins AB4 and POL Pin AB4 Only Pin POL Only V+ = 5V, Segment Voltage = 3V NOTES: o 3. Unless otherwise noted, specifications apply at TA = 25 C, fCLOCK = 48kHz. MTr10 is tested in the circuit of Figure 1. 4. Not tested, guaranteed by design. 5. Sample Tested. MTr10 Figure 1. TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE 3 July 2011, ver.00 KL7107 Design Information Summary Sheet • OSCILLATOR FREQUENCY • DISPLAY COUNT f0SC = 0.45/RC COSC > 50pF; RQSC > 50kΩ f0SC (Тyp) = 48kHz • CONVERSION CYCLE t0SC = RC/0.45 tCYC = tCLOCK x 4000 • INTEGRATION CLOCK FREQUENCY tCYC = t0SC x 16,000 when fosc = 48kHz; tcyc = 333ms fCLOCK = f0SC /4 • COMMON MODE INPUT VOLTAGE • INTEGRATION PERIOD (V-+ 1V ) <V INT <(V +-0 .5V ) tINT = 1000 x (4/fOSC) • AUTO-ZERO CAPACITOR 0.01µF < СAZ< 1µF • 60/50HZ REJECTION CRITERION tINT/t60Hz or tINT/t60Hz = Integer • REFERENCE CAPACITOR • OPTIMUM INTEGRATION CURRENT 0.1µF < CREF< 1µF IINT= 4µA • VCOM Biased between Vi and V-. • FULL SCALE ANALOG INPUT VOLTAGE VINFS(Typ) = 200mV or 2V • VCOM=V+-2.8V Regulation lost when V+ to V- < ≈ 6.8V If VCOM is externally pulled down to (V+ to V-)/2, the VCOM circuit will turn off. • INTEGRATE RESISTOR VINFS IINT • POWER SUPPLY: DUAL ± 5.0V V+ = +5V to GND V- = -5V to GND Digital Logic and LED driver supply V+ to GND • INTEGRATE CAPACITOR CINT = ; VREF • OSCILLATOR PERIOD RINT = VIN COUNT = 1000x (tINT )( IINT ) • DISPLAY: LED VINT Type: Non-Multiplexed Common Anode • INTEGRATOR OUTPUT VOLTAGE SWING VINT = (tINT )( IINT ) CINT VINT MAXIMUM SWING: (V- + 0.5V) < VINT< (V+ - 0.5V), VINT (Тур) = 2V Typical Integrator Amplifier Output Waveform (INT Pin) 4 July 2011, ver.00 KL7107 Detailed Description Analog Section proportional to the input signal. Specifically the digital reading displayed is: Figure 2 shows the Analog Section. Each measurement cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-integrate (DE). DISPLAY COUNT = 1000 ( Auto-Zero Phase During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor СAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10µV. Signal Integrate Phase During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined. De-Integrate Phase The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is VIN ) VREF Differential Input The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a near full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity. Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (See Component Value Selection.) FIGURE 2. ANALOG SECTION 5 July 2011, ver.00 KL7107 Digital Section Figure 3 show the Digital Section for, respectively. FIGURE 3. DIGITAL SECTION System Timing Figure 4 shows the clocking arrangement used in the. Two basic clocking arrangements can be used: 1. Figure 4A. An external oscillator connected to pin 40. 2. Figure 4B. An R-C oscillator using all three pins. The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form the three convert-cycle phases. These are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts) and auto-zero (1000 to 3000 counts) For signals less than full scale, auto-zero gets the unused portion of reference de-integrate. This makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. For three readings/second, an oscillator frequency of 48kHz would be used. FIGURE 4A To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 331/3kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 100kHz, 662/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz). FIGURE 4B. CLOCK CIRCUITS 6 July 2011, ver.00 KL7107 Component Value Selection Integrating Resistor Reference Voltage Both the buffer amplifier and the integrator have a class A output stage with 100µА of quiescent current. They can supply 4µА of drive current with negligible nonlinearity The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V full scale, 470kΩ is near optimum and similarly a 47kΩ for a 200mV scale. The analog input required to generate full scale output (2000 counts) is: VIN = 2VREF. Thus, for the 200mV and 2V scale, VREF should equal 100mV and 1V, respectively. However, in many applications where the A/D is connected to a transducer, there will exist a scale factor other than unity between the input voltage and the digital reading. For instance, in a weighing system, the designer might like to have a full scale reading when the voltage from the transducer is 0.662V. Instead of dividing the input down to 200mV, the designer should use the input voltage directly and select VREF = 0.341V Suitable values for integrating resistor and capacitor would be 120kΩ and 0.22µF This makes the system slightly quieter and also avoids a divider network on the input. The MTr10 with +5V supplies can accept input signals up to +4V. Another advantage of this system occurs when a digital reading of zero is desired for Integrating Capacitor The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance buildup will not saturate the integrator swing (approximately. 0.3V from either supply). In the NTr10, when the analog COMMON is used as a reference, a nominal +2V full-scale integrator swing is fine. For the MTr10 with +5V supplies and analog COMMON tied to supply ground, a ±3.5V to +4V swing is nominal. For three readings/second (48kHz clock) nominal values for CINT are 0.22µF and 0.10µF, respectively. Of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing. An additional requirement of the integrating capacitor is that it must have a low dielectric absorption to prevent roll-over errors. While other types of capacitors are adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost. VIN ≠ 0. Temperature and weighing systems with a variable fare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or fixed) offset voltage between COMMON and IN LO. Power Supplies The Mtr10 is designed to work from +5V supplies. However, if a negative supply is not available, it can be generated from the clock output with 2 diodes, 2 capacitors, and an inexpensive 1С. Figure 5 shows this application. Auto-Zero Capacitor The size of the auto-zero capacitor has some influence on the noise o In fact, in selected applications no negative supply is required. For 200mV full scale where noise is very important, a 0.47µF capaci The conditions to use a single +5V supply are: recommended. On the 2V scale, a 0.047µF capacitor increases the s 1. The input signal can be referenced to the center of the recovery from overload and is adequate for noise on this scale. common mode range of the converter. Reference Capacitor 2. The signal is less than +1.5V A 0.1µF capacitor gives good results in most applications. 3. An external reference is used. However, where a large common mode voltage exists (i.e., the REF LO pin is not at analog COMMON) and a 200mV scale is used, a larger value is required to prevent roll-over error. Generally 1µF will hold the roll-over error to 0.5 count in this instance. Oscillator Components For all ranges of frequency a 100kΩ resistor is recommended and the capacitor is selected from the equation: MTr10 f = 0.45/RC For 48kHz Clock (3 Readings/sec), C = 100 pF. FIGURE 5. GENERATING NEGATIVE SUPPLY FROM +5V 7 July 2011, ver.00 KL7107 Typical Applications The KL7107 may be used in a wide variety of configurations. The circuits which follow show some of the possibilities, and serve to illustrate the exceptional versatility of these A/D converters. The following application notes contain very useful information on understanding and applying this part and are available from Intersil Corporation. Values shown are for 200 mV full scale, 3 readings/sec. IN LO may be tied IN LO is tied to supply COMMON establishing the correct common mode to either COMMON for inputs floating with respect to supplies, or GND for voltage . If COMMON is not shorted to GND, the input voltage may float single ended inputs. (See discussion under Analog COMMON). with respect to the power supply and COMMON acts as a pre-regulator for the reference. If COMMON is shorted to GND, the input is single ended (referred to supply GND) and the pre-regulator is overridden. FIGURE 7. WITH AN EXTERNAL BAND-GAP REFERENCE (1.2V TYPE) FIGURE 6. USING THE INTERNAL REFERENCE Since low TC zeners have breakdown voltages ~6.8V, diode must be placed across the total supply (10V). As in the case of Figure 7, IN LO may be tied either COMMON or GND FIGURE 9. RECOMMENDED COMPONENT VALUES FOR 2V FULL SCALE FIGURE 8. WITH ZENER DIODE REFERENCE 8 July 2011, ver.00 KL7107 Typical Applications (Continued) An external reference must be used in this application, since the voltage between V+ and V- is insufficient for correct operation of the internal reference. The resistor values within the bridge are determined by the desired sensitivity. FIGURE 10. OPERATED FROM SINGLE +5V FIGURE 11. MEASURENG RATIOMETRIC VALUES OF QUAD LOAD CELL FIGURE 12. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNALS FROM OUTPUT FIGURE 13. DISPLAY BUFFERING FOR INCREASED DRIVE CURRENT 9 July 2011, ver.00 KL7107 Pin Description Pin No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Description Positive supply voltage Activates the D segment Activates the C segment Activates the B segment Activates the A segment Activates the F segment Activates the G segment Activates the E segment Activates the D segment Activates the C segment Activates the B segment Activates the A segment Activates the F segment Activates the E segment Activates the D segment Activates the B segment Activates the F segment Activates the E segment Activates the AB segment No connection Activates the negative polarity display Ground Ground Activates the G segment Activates the A segment Activates the C segment Activates the G segment Negative supply voltage Integrator output Integration resistor connection Pin auto-zero capacitor The analog LOW input is connected to this pin The analog HIGH input is connected to this pin Common Pin CPin C+ Pin REFPin REF+ No connection Display test Oscillator section 3 No connection Oscillator section 2 Oscillator section 1 10 July 2011, ver.00 KL7107 PAKAGE DIMENSION 40-Pin Plastic Dual-in-Line A Aı A2 B B2 C D E E1 e e2 L α Dimension, mm max min min max min max min max min max min max min max min max nom nom min max min max 11 6.35 0.38 3.18 4.95 0.36 0.56 0.77 1.78 0.20 0.38 50.30 53.20 15.24 15.87 12.32 14.73 2.54 15.24 2.92 5.08 0º 10º July 2011, ver.00