1
TC7126
TC7126A
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS
2
FEATURES
GENERAL DESCRIPTION
■
The TC7126A is a 3-1/2 digit CMOS analog-to-digital
converter (ADC) containing all the active components necessary to construct a 0.05% resolution measurement system. Seven-segment decoders, digit and polarity drivers,
voltage reference, and clock circuit are integrated on-chip.
The TC7126A directly drives a liquid crystal display (LCD),
and includes a backplane driver.
A low-cost, high-resolution indicating meter requires
only a display, four resistors, and four capacitors. The
TC7126A's extremely low power drain and 9V battery
operation make it ideal for portable applications.
The TC7126A reduces linearity error to less than 1
count. Roll-over error (the difference in readings for equal
magnitude but opposite polarity input signals) is below ±1
count. High-impedance differential inputs offer 1 pA leakage current and a 1012Ω input impedance. The 15 µVP-P
noise performance guarantees a "rock solid" reading, and
the auto-zero cycle guarantees a zero display reading with
a 0V input.
The TC7126A features a precision, low-drift internal
voltage reference and is functionally identical to the TC7126.
A low-drift external reference is not normally required with
the TC7126A.
■
■
■
■
■
■
■
Low Temperature Drift Internal Reference
TC7126 ....................................... 80 ppm/°C Typ
TC7126A ..................................... 35 ppm/°C Typ
Guaranteed Zero Reading With Zero Input
Low Noise .................................................... 15 µVP-P
High Resolution .............................................. 0.05%
Low Input Leakage Current ...................... 1 pA Typ
10 pA Max
Precision Null Detectors With True Polarity at
Zero
High-Impedance Differential Input
Convenient 9V Battery Operation With
Low Power Dissipation ........................ 500 µW Typ
900 µW Max
TYPICAL APPLICATIONS
■
■
■
■
Thermometry
Bridge Readouts: Strain Gauges, Load Cells, Null
Detectors
Digital Meters and Panel Meters
— Voltage/Current/Ohms/Power, pH
Digital Scales, Process Monitors
TYPICAL OPERATING CIRCUIT
1 MΩ
+
ANALOG
INPUT
–
0.01 µF
31
POL
BP
32 ANALOG
COMMON
28
180 kΩ
0.15 µF
0.33
µF
29
* "A" parts have an improved reference TC
2–19 SEGMENT
22–25 DRIVE
–
30 V IN
VBUFF
V+
MINUS SIGN
BACKPLANE
1
240 kΩ
TC7126
TC7126A
36
REF
10 kΩ
–
35
V REF
27
– 26
VINT
V
OSC2 OSC3 OSC1
39
38 COSC 40
ROSC 50 pF
560 kΩ
+
9V
V+
CAZ
Package Code (see below):
20
21
6
R (reversed pins) or blank (CPL pkg only)
LCD
REF
+
V IN
5
A or blank*
33
C–
REF
4
ORDERING INFORMATION
PART CODE
TC7126X X XXX
0.1 µF
34
C+
3
1 CONVERSION/SEC
Package
Code
Package
Temperature
Range
CKW
CLW
CPL
IPL
44-Pin PQFP
44-Pin PLCC
40-Pin PDIP
40-Pin PDIP (non-A only)
0°C to +70°C
0°C to +70°C
0°C to +70°C
– 25°C to +85°C
7
44-Pin Plastic Quad Flat 44-Pin Plastic Chip
Package Formed Leads
Carrier PLCC
8
AVAILABLE PACKAGES
TO ANALOG COMMON
(PIN 32)
NOTE: Pin numbers refer to 40-pin DIP.
40-Pin Plastic DIP
TC7126/A-8 11/6/96
TELCOM SEMICONDUCTOR, INC.
3-217
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (V+ to V –)......................................... +15V
Analog Input Voltage (Either Input) (Note 1) ........ V+ to V –
Reference Input Voltage (Either Input) ................. V+ to V –
Clock Input ...................................................... TEST to V+
Operating Temperature Range
C Devices .............................................. 0°C to +70°C
I Devices ........................................... – 25°C to +85°C
Storage Temperature Range ................ – 65°C to +150°C
Lead Temperature (Soldering, 10 sec) ................. +300°C
Power Dissipation, (TA ≤ 70°C), (Note 2)
44-Pin PQFP .................................................... 1.00W
44-Pin PLCC .....................................................1.23W
40-Pin Plastic PDIP .......................................... 1.23W
*Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS: VS = +9V, fCLK = 16 kHz, and TA = +25°C, unless otherwise noted.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Zero Input Reading
VIN = 0V
Full Scale = 200 mV
VIN = 0V, 0°C ≤ TA ≤ +70°C
VIN = VREF, VREF = 100 mV
Unit
–000.0
±000.0
+000.0
—
999
0.2
999/1000
1
1000
Full Scale = 200 mV or 2V
Max Deviation From Best Fit
Straight Line
–VIN = +VIN ≈ 200 mV
VIN = 0V, Full Scale = 200 mV
VIN = 0V
VCM = ±1V, VIN = 0V,
Full Scale = 200 mV
VIN = 199 mV, 0°C ≤ TA ≤ +70°C
Ext Ref Temp Coeff = 0 ppm/°C
–1
±0.2
1
Digital
Reading
µV/°C
Digital
Reading
Count
—
—
—
–1
15
1
50
±0.2
—
10
—
1 Count
µVP-P
pA
µV/V
—
1
5
ppm/°C
—
—
—
—
—
—
80
35
—
—
—
75
—
—
ppm/°C
ppm/°C
—
2.7
35
3.05
100
3.35
ppm/°C
V
Input
Zero Reading Drift
Ratiometric Reading
NL
Linearity Error
Roll-Over Error
Noise
Input Leakage Current
Common-Mode Rejection
Ratio
Scale Factor Temperature
Coefficient
eN
IL
CMRR
Analog Common
VCTC
Analog Common
Temperature Coefficient
VC
Analog Common Voltage
250 kΩ Between Common and V +
0°C ≤ TA ≤ +70°C ("C" Devices):
TC7126
TC7126A
– 25°C ≤ TA ≤ +85°C ("I" Device):
TC7126A
250 kΩ Between Common and V+
LCD Drive
VSD
VBD
LCD Segment Drive Voltage
LCD Backplane Drive Voltage
V + to V – = 9V
V+ to V– = 9V
4
4
5
5
6
6
VIN = 0V, V + to V – = 9V (Note 6)
—
55
100
Power Supply
IS
Power Supply Current
VP-P
VP-P
µA
Input voltage may exceed supply voltages when input current is limited to 100 µA.
Dissipation rating assumes device is mounted with all leads soldered to PC board.
Refer to "Differential Input" discussion.
Backplane drive is in-phase with segment drive for "OFF" segment and 180° out-of-phase for "ON" segment. Frequency is 20 times
conversion rate. Average DC component is less than 50 mV.
5. See "Typical Operating Circuit."
6. During auto-zero phase, current is 10–20 µA higher. A 48 kHz oscillator increases current by 8 µA (typical). Common current not
included.
NOTES: 1.
2.
3.
4.
3-218
TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
1
TC7126
TC7126A
OSC 2
OSC 3
TEST
44
43
42
41
40
44 43
–
42
41 40 39
38
V–
OSC 1
1
VINT
NC
2
VBUFF
V+
3
2
CAZ
D1
4
+
+
COMMON
+
VIN
–
VIN
C1
5
VREF
–
VREF
+
C REF
–
C REF
B1
6
VREF
A1
PIN CONFIGURATIONS
37
36
35
34
F1 7
39 VREF
NC 1
33 NC
G1 8
NC 2
32 G
E1 9
+
38 C REF
–
37 C REF
D2 10
36 COMMON
OSC 3 4
30 A 3
C2 11
+
35 VIN
NC 5
29 G 3
34 NC
OSC 2 6
–
33 VIN
OSC 1 7
NC 12
TC7126CLW
TC7126ACLW
(PLCC)
B2 13
A 2 14
32 CAZ
2
TEST 3
31 C 3
28 BP
TC7126CKW
TC7126ACKW
(FLAT PACKAGE)
V+ 8
27 POL
26 AB 4
D1 9
25 E3
1's
21 22
2
OSC2
2
40 V +
REVERSE PIN
CONFIGURATION 39 D1
C1
3
38 OSC 3
OSC 3
3
38 C1
B1
4
5
F1
6
G1
7
37 TEST
+
36 V REF
35 V –
REF
+
34 CREF
–
33 CREF
37 B1
A1
TEST 4
+
V REF
5
–
VREF 6
+
CREF
7
–
CREF
8
ANALOG 9
COMMON
+
V IN
10
V–
IN 11
CAZ 12
D1
E1
8
D2
9
B2 11
A2 12
TC7126CPL
TC7126ACPL
TC7126IPL
TC7126AIPL
32 ANALOG
COMMON
+
31 V IN
30 V –
IN
29 CAZ
E 2 14
28 VBUFF
27 V INT
D3 15
26 V –
B3 16
25 G
2
24 C 3
F3 17
AB4 19
POL 20
(MINUS SIGN)
23 A 3
22 G 3
100's
21 BP
(BACKPLANE)
VBUFF 13
100's
36 A1
35
5
1's
F1
34 G1
33 E 1
6
32 D2
TC7126RCPL
TC7126ARCPL
TC7126RIPL
TC7126ARIPL
31 C2
30 B2
29 A2
28
10's
F2
V INT 14
V – 15
27 E 2
G 2 16
25 B3
C 3 17
24
A 3 18
23 E 3
G 3 19
22 AB4
BP 20
(BACKPLANE)
4
D3
20
E2
19
F2
18
A2
G2
17
1
E 3 18
1000's
15 16
OSC1
1
F2 13
100's
14
40 OSC 1
NORMAL PIN
CONFIGURATION 39 OSC2
V+
C2 10
10's
12 13
B2
28
C2
27
D2
26
E1
25
G1
24
F1
23
A1
21 22
POL
F3
20
C3
23 B3
A3
D 3 17
G3
24 F3
B 1 11
BP
C 1 10
29 V –
NC
30 VINT
AB4
E 2 16
E3
31 VBUFF
B3
F 2 15
18 19
3
7
26 D3
F3
100's
1000's
21 POL
(MINUS SIGN)
8
NC = NO INTERNAL CONNECTION
TELCOM SEMICONDUCTOR, INC.
3-219
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
PIN DESCRIPTION
40-Pin PDIP
Pin Number
Normal
(Reverse)
3-220
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
(40)
(39)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
(20)
(19)
(18)
(17)
(16)
(15)
(14)
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
POL
BP
G3
A3
C3
G2
V–
VINT
28
(13)
VBUFF
29
(12)
CAZ
30
31
32
(11)
(10)
(9)
VIN–
VIN+
ANALOG
COMMON
33
(8)
–
CREF
Description
Positive supply voltage.
Activates the D section of the units display.
Activates the C section of the units display.
Activates the B section of the units display.
Activates the A section of the units display.
Activates the F section of the units display.
Activates the G section of the units display.
Activates the E section of the units display.
Activates the D section of the tens display.
Activates the C section of the tens display.
Activates the B section of the tens display.
Activates the A section of the tens display.
Activates the F section of the tens display.
Activates the E section of the tens display.
Activates the D section of the hundreds display.
Activates the B section of the hundreds display.
Activates the F section of the hundreds display.
Activates the E section of the hundreds display.
Activates both halves of the 1 in the thousands display.
Activates the negative polarity display.
Backplane drive output.
Activates the G section of the hundreds display.
Activates the A section of the hundreds display.
Activates the C section of the hundreds display.
Activates the G section of the tens display.
Negative power supply voltage.
The integrating capacitor should be selected to give the maximum voltage swing
that ensures component tolerance build-up will not allow the integrator output to
saturate. When analog common is used as a reference and the conversion rate is
3 readings per second, a 0.047 µF capacitor may be used. The capacitor must
have a low dielectric constant to prevent roll-over errors. See "Integrating Capacitor" section for additional details.
Integration resistor connection. Use a 180 kΩ resistor for a 200 mV full-scale
range and a 1.8 MΩ resistor for a 2V full-scale range.
The size of the auto-zero capacitor influences system noise. Use a 0.33 µF
capacitor for 200 mV full scale, and a 0.033 µF capacitor for 2V full scale. See
paragraph on auto-zero capacitor for more details.
The low input signal is connected to this pin.
The high input signal is connected to this pin.
This pin is primarily used to set the analog common-mode voltage for battery
operation or in systems where the input signal is referenced to the power supply.
See paragraph on analog common for more details. It also acts as a reference
voltage source.
See pin 34.
TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
1
TC7126
TC7126A
PIN DESCRIPTION (Cont.)
40-Pin PDIP
Pin Number
Normal
(Reverse)
2
Name
34
(7)
+
CREF
35
(6)
(5)
–
VREF
+
VREF
36
(4)
TEST
37
38
40
(3)
(2)
(1)
OSC3
OSC2
OSC1
Description
A 0.1 µF capacitor is used in most applications. If a large common-mode voltage
exists (for example, the VIN– pin is not at analog common), and a 200 mV scale is
used, a 1 µF capacitor is recommended and will hold the roll-over error to 0.5
count.
See pin 36.
The analog input required to generate a full-scale output (1999 counts). Place 100
mV between pins 35 and 36 for 199.9 mV full scale. Place 1V between pins 35
and 36 for 2V full scale. See paragraph on reference voltage.
Lamp test. When pulled HIGH (to V+), all segments will be turned ON and the
display should read –1888. It may also be used as a negative supply for externally-generated decimal points. See paragraph under test for additional information.
See pin 40.
See pin 40.
Pins 40, 39 and 38 make up the oscillator section. For a 48 kHz clock (3 readings
39per second), connect pin 40 to the junction of a 180 kΩ resistor and a 50 pF
capacitor. The 180 kΩ resistor is tied to pin 39 and the 50 pF capacitor is tied to
pin 38.
3
4
GENERAL THEORY OF OPERATION
(All Pin Designations Refer to the 40-Pin DIP)
Dual-Slope Conversion Principles
The TC7126A is a dual-slope, integrating analog-todigital converter. An understanding of the dual-slope conversion technique will aid in following detailed TC7126A
operational theory.
The conventional dual-slope converter measurement
cycle has two distinct phases:
ANALOG
INPUT
SIGNAL
INTEGRATOR
–
+
+
SWITCH
DRIVER
REF
VOLTAGE
5
COMPARATOR
–
PHASE
CONTROL
CONTROL
LOGIC
POLARITY CONTROL
CLOCK
The input signal being converted is integrated for a
fixed time period (tSI), measured by counting clock pulses.
An opposite polarity constant reference voltage is then
integrated until the integrator output voltage returns to
zero. The reference integration time is directly proportional
to the input signal (tRI).
In a simple dual-slope converter, a complete conversion requires the integrator output to "ramp-up" and "rampdown."
A simple mathematical equation relates the input signal,
reference voltage, and integration time:
1
RC
∫0
tSI
VIN(t) dt =
VR tRI
,
RC
TELCOM SEMICONDUCTOR, INC.
INTEGRATOR
OUTPUT
(1) Input signal integration
(2) Reference voltage integration (deintegration)
FIXED
SIGNAL
INTEGRATE
TIME
DISPLAY
6
COUNTER
VIN ' VFULL SCALE
VIN ' 1.2 VFULL SCALE
7
VARIABLE
REFERENCE
INTEGRATE
TIME
Figure 1. Basic Dual-Slope Converter
where:
VR = Reference voltage
tSI = Signal integration time (fixed)
tRI = Reference voltage integration time (variable).
3-221
8
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
analog gates close a feedback loop around the integrator
and comparator. This loop permits comparator offset voltage error compensation. The voltage level established on
CAZ compensates for device offset voltages. The auto-zero
phase residual is typically 10 µV to 15 µV.
The auto-zero cycle length is 1000 to 3000 clock
periods.
NORMAL MODE REJECTION (dB)
30
20
Signal Integration Phase
10
t = MEASUREMENT PERIOD
0
0.1/t
1/t
INPUT FREQUENCY
10/t
Figure 2. Normal-Mode Rejection of Dual-Slope Converter
For a constant VIN:
tRI
VIN = VR t .
SI
The dual-slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as they are
stable during a measurement cycle. Noise immunity is an
inherent benefit. Noise spikes are integrated, or averaged,
to zero during integration periods. Integrating ADCs are
immune to the large conversion errors that plague successive approximation converters in high-noise environments.
Interfering signals with frequency components at multiples
of the averaging period will be attenuated. Integrating ADCs
commonly operate with the signal integration period set to a
multiple of the 50 Hz/60 Hz power line period.
ANALOG SECTION
In addition to the basic integrate and deintegrate dualslope cycles discussed above, the TC7126A design incorporates an auto-zero cycle. This cycle removes buffer
amplifier, integrator, and comparator offset voltage error
terms from the conversion. A true digital zero reading results
without external adjusting potentiometers. A complete conversion consists of three phases:
(1) Auto-zero phase
(2) Signal integrate phase
(3) Reference integrate phase
The auto-zero loop is entered and the internal differential inputs connect to VIN+ and VIN–. The differential input
signal is integrated for a fixed time period. The TC7126A
signal integration period is 1000 clock periods, or counts.
The externally-set clock frequency is 44 before clocking the
internal counters. The integration time period is:
tSI =
4
fOSC
3 1000,
where fOSC = external clock frequency.
The differential input voltage must be within the device
common-mode range when the converter and measured
system share the same power supply common (ground). If
the converter and measured system do not share the same
power supply common, VIN– should be tied to analog common.
Polarity is determined at the end of signal integrate
phase. The sign bit is a true polarity indication, in that signals
less than 1 LSB are correctly determined. This allows
precision null detection limited only by device noise and
auto-zero residual offsets.
Reference Integrate Phase
The third phase is reference integrate, or deintegrate.
VIN– is internally connected to analog common and VIN+ is
connected across the previously-charged reference capacitor. Circuitry within the chip ensures that the capacitor will be
connected with the correct polarity to cause the integrator
output to return to zero. The time required for the output to
return to zero is proportional to the input signal and is
between 0 and 2000 internal clock periods. The digital
reading displayed is:
1000
VIN
VREF
DIGITAL SECTION
Auto-Zero Phase
During the auto-zero phase, the differential input signal
is disconnected from the circuit by opening internal analog
gates. The internal nodes are shorted to analog common
(ground) to establish a zero input condition. Additional
3-222
The TC7126A contains all the segment drivers necessary to directly drive a 3-1/2 digit LCD. An LCD backplane
driver is included. The backplane frequency is the external
clock frequency 4800. For 3 conversions per second the
backplane frequency is 60 Hz with a 5V nominal amplitude.
TELCOM SEMICONDUCTOR, INC.
TELCOM SEMICONDUCTOR, INC.
–
V IN
ANALOG
COMMON
+
V IN
32
31
INT
INT
10
µA
+
C REF
34
CREF
DE (–)
DE
(+)
33
+
–
ZI
V+– 2.8V
+
–
–
V BUFF
C REF
26
–
V
ZI &
AZ
35
–
VREF
AZ & DE (±)
DE (+)
DE
(–)
ZI & AZ
36
+
VREF
+
1
LOW
TEMPCO
VREF
28
V
RINT
TC7126A
SEGMENT
OUTPUT
–
+
27
VINT
CINT
THOUSANDS
TO
DIGITAL
SECTION
ROSC
39
OSC 2
CLOCK
COSC
OSC 3
38
÷4
HUNDREDS
7 SEGMENT
DECODE
VTH
= 1V
CONTROL LOGIC
TENS
DATA LATCH
7 SEGMENT
DECODE
UNITS
7 SEGMENT
DECODE
LCD SEGMENT DRIVERS
LCD
INTERNAL DIGITAL GOUND
fOSC
TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
COMPARATOR
40
OSC 1
AZ
+
–
INTEGRATOR
29
CAZ
INTERNAL DIGITAL GROUND
2 mA
0.5 mA
TYPICAL SEGMENT OUTPUT
+
V
BP
500Ω
6.2V
4200
21
26
1
+
V–
TEST
V
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
1
TC7126
TC7126A
2
3
4
5
6
7
Figure 3. TC7126A Block Diagram
8
3-223
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
When a segment driver is in-phase with the backplane
signal, the segment is OFF. An out-of-phase segment drive
signal causes the segment to be ON, or visible. This AC drive
configuration results in negligible DC voltage across each
LCD segment, ensuring long LCD life. The polarity segment
driver is ON for negative analog inputs. If VIN+ and VIN– are
reversed, this indicator would reverse.
On the TC7126A, when the TEST pin is pulled to V+, all
segments are turned ON. The display reads –1888. During
this mode, LCD segments have a constant DC voltage
impressed. DO NOT LEAVE THE DISPLAY IN THIS MODE
FOR MORE THAN SEVERAL MINUTES; LCDS MAY BE
DESTROYED IF OPERATED WITH DC LEVELS FOR
EXTENDED PERIODS.
The display font and segment drive assignment are
shown in Figure 4.
System Timing
The oscillator frequency is 44 prior to clocking the
internal decade counters. The three-phase measurement
cycle takes a total of 4000 counts (16,000 clock pulses).
The 4000-count cycle is independent of input signal magnitude.
Each phase of the measurement cycle has the following
length:
(1) Auto-zero phase: 1000 to 3000 counts
(4000 to 12,000 clock pulses)
For signals less than full scale, the auto-zero phase
is assigned the unused reference integrate time
period.
(2) Signal integrate:
1000 counts
(4000 clock pulses)
This time period is fixed. The integration period is:
tSI = 4000
1
,
fOSC
where fOSC is the externally-set clock frequency.
(3) Reference integrate: 0 to 2000 counts
(0 to 8000 clock pulses)
The TC7126A is a drop-in replacement for the TC7126
and ICL7126 that offers a greatly improved internal reference temperature coefficient. No external component value
changes are required to upgrade existing designs.
COMPONENT VALUE SELECTION
Auto-Zero Capacitor (CAZ)
The CAZ size has some influence on system noise. A
0.33 µF capacitor is recommended for 200 mV full-scale
applications where 1 LSB is 100 µV. A 0.033 µF capacitor is
adequate for 2V full-scale applications. A Mylar-type dielectric capacitor is adequate.
Reference Voltage Capacitor (CREF)
The reference voltage, used to ramp the integrator
output voltage back to zero during the reference integrate
phase, is stored on CREF. A 0.1 µF capacitor is acceptable
when VREF– is tied to analog common. If a large commonmode voltage exists (VREF– ≠ analog common) and the
application requires a 200 mV full scale, increase CREF to
1 µF. Roll-over error will be held to less than 0.5 count. A
Mylar-type dielectric capacitor is adequate.
Integrating Capacitor (CINT)
CINT should be selected to maximize integrator output
voltage swing without causing output saturation. Due to
the TC7126A's superior analog common temperature coefficient specification, analog common will normally supply the differential voltage reference. For this case, a ±2V
full-scale integrator output swing is satisfactory. For 3
readings per second (fOSC = 48 kHz), a 0.047 µF value is
suggested. For 1 reading per second, 0.15 µF is recommended. If a different oscillator frequency is used, CINT
must be changed in inverse proportion to maintain the
nominal ±2V integrator swing.
An exact expression for CINT is:
(4000)
CINT =
100's
10's
1's
Figure 4. Display Font and Segment Assignment
3-224
1
fOSC
VFS
RINT
,
VINT
DISPLAY FONT
1000's
( )( )
where: fOSC
VFS
RINT
VINT
= Clock frequency at pin 38
= Full-scale input voltage
= Integrating resistor
= Desired full-scale integrator output swing.
At 3 readings per second, a 750Ω resistor should be
placed in series with CINT. This increases accuracy by
compensating for comparator delay. CINT must have low
dielectric absorption to minimize roll-over error. A polypropylene capacitor is recommended.
TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
1
TC7126
TC7126A
Integrating Resistor (RINT)
The input buffer amplifier and integrator are designed
with Class A output stages. The output stage idling current
is 6 µA. The integrator and buffer can supply 1 µA drive
current with negligible linearity errors. RINT is chosen to
remain in the output stage linear drive region, but not so
large that PC board leakage currents induce errors. For a
200 mV full scale, RINT is 180 kΩ. A 2V full scale requires
1.8 MΩ.
input voltage by two, the reference voltage should be set to
200 mV. This permits the transducer input to be used
directly.
The differential reference can also be used where a
digital zero reading is required when VIN is not equal to zero.
This is common in temperature-measuring instrumentation.
A compensating offset voltage can be applied between
analog common and VIN–. The transducer output is connected between VIN+ and analog common.
Component
Value
Nominal Full-Scale Voltage
200 mV
2V
DEVICE PIN FUNCTIONAL DESCRIPTION
CAZ
RINT
CINT
0.33 µF
180 kΩ
0.047 µF
Differential Signal Inputs
NOTE:
0.033 µF
1.8 MΩ
0.047 µF
fOSC = 48 kHz (3 readings per sec).
Oscillator Components
COSC should be 50 pF; ROSC is selected from the
equation:
0.45
fOSC = RC .
For a 48 kHz clock (3 conversions per second), R = 180 kΩ.
Note that fOSC is 44 to generate the TC7126A's internal clock. The backplane drive signal is derived by dividing
fOSC by 800.
To achieve maximum rejection of 60 Hz noise pickup,
the signal integrate period should be a multiple of 60 Hz.
Oscillator frequencies of 240 kHz, 120 kHz, 80 kHz, 60 kHz,
40 kHz, etc. should be selected. For 50 Hz rejection,
oscillator frequencies of 200 kHz, 100 kHz, 66-2/3 kHz, 50
kHz, 40 kHz, etc. would be suitable. Note that 40 kHz (2.5
readings per second) will reject both 50 Hz and 60 Hz.
Reference Voltage Selection
A full-scale reading (2000 counts) requires the input
signal be twice the reference voltage.
Required Full-Scale Voltage*
200 mV
2V
VREF
100 mV
1V
*VFS = 2 VREF.
In some applications, a scale factor other than unity may
exist between a transducer output voltage and the required
digital reading. Assume, for example, a pressure transducer
output for 2000 lb/in.2 is 400 mV. Rather than dividing the
TELCOM SEMICONDUCTOR, INC.
(Pin Numbers Refer to 40-Pin DIP)
VIN+ (Pin 31), VIN– (Pin 30)
The TC7126A is designed with true differential inputs
and accepts input signals within the input stage commonmode voltage range (VCM). Typical range is V+ –1V to V–
+1V. Common-mode voltages are removed from the system
when the TC7126A operates from a battery or floating power
source (isolated from measured system), and VIN– is connected to analog common (VCOM). (See Figure 5.)
In systems where common-mode voltages exist, the
TC7126A's 86 dB common-mode rejection ratio minimizes
error. Common-mode voltages do, however, affect the integrator output level. A worst-case condition exists if a large
positive VCM exists in conjunction with a full-scale negative
differential signal. The negative signal drives the integrator
output positive along with VCM (see Figure 6.) For such
applications, the integrator output swing can be reduced
below the recommended 2V full-scale swing. The integrator
output will swing within 0.3V of V+ or V– without increased
linearity error.
Differential Reference
VREF+ (Pin 36), VREF– (Pin 35)
The reference voltage can be generated anywhere
within the V+ to V– power supply range.
To prevent roll-over type errors being induced by large
common-mode voltages, CREF should be large compared to
stray node capacitance.
The TC7126A offers a significantly improved analog
common temperature coefficient. This potential provides a
very stable voltage, suitable for use as a voltage reference.
The temperature coefficient of analog common is typically
35 ppm/°C for the TC7126A and 80 ppm/°C for the TC7126.
ANALOG COMMON (Pin 32)
The analog common pin is set at a voltage potential
approximately 3V below V+. The potential is guaranteed to
be between 2.7V and 3.35V below V+. Analog common is
tied internally to an N-channel FET capable of sinking
3-225
2
3
4
5
6
7
8
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
SEGMENT
DRIVE
MEASURED
SYSTEM
V+
V–
VBUFF
CAZ VINT
+
VIN
–
VIN
TC7126A
ANALOG –
+
+
COMMON VREF VREF V
GND
LCD
POL BP
OSC1
OSC3
OSC2
V–
V+ V –
GND
POWER
SOURCE
+
9V
Figure 5. Common-Mode Voltage Removed in Battery Operation With VIN = Analog Common
100 µA. This FET will hold the common line at 3V should an
external load attempt to pull the common line toward V+.
Analog common source current is limited to 1 µA. Therefore,
analog common is easily pulled to a more negative voltage
(i.e., below V+ – 3V).
–
The TC7126A connects the internal V+IN and VIN
inputs to analog common during the auto-zero phase. During
–
the reference-integrate phase, VIN
is connected to analog
+
common. If V IN is not externally connected to analog common, a common-mode voltage exists, but is rejected by the
converter's 86 dB common-mode rejection ratio. In battery
–
operation, analog common and VIN
are usually connected,
removing common-mode voltage concerns. In systems where
–
VIN
is connected to power supply ground or to a given
–
voltage, analog common should be connected to VIN
.
The analog common pin serves to set the analog section reference, or common point. The TC7126A is specifically designed to operate from a battery or in any measurement system where input signals are not referenced (float)
INPUT
BUFFER
+
+
CI
RI
–
VIN
–
VI
+
INTEGRATOR
–
VCM
TI
VI =
V CM – VIN
RI CI
Where:
4000
T I = Integration time =
f OSC
C I = Integration capacitor
R I = Integration resistor
[
[
Figure 6. Common-Mode Voltage Reduces Available Integrator
Swing (VCOM ≠ VIN)
3-226
with respect to the TC7126A's power source. The analog
common potential of V+ –3V gives a 7V end of battery life
voltage. The common potential has a 0.001%/% voltage
coefficient and a 15Ω output impedance.
With sufficiently high total supply voltage (V+–V– >7V),
analog common is a very stable potential with excellent
temperature stability (typically 35 ppm/°c). This potential
can be used to generate the TC7126A's reference voltage.
An external voltage reference will be unnecessary in most
cases because of the 35 ppm/°C temperature coefficient.
See "TC7126A Internal Voltage Reference" discussion.
TEST (Pin 37)
The TEST pin potential is 5V less than V+. TEST may be
used as the negative power supply connection for external
CMOS logic. The TEST pin is tied to the internally-generated
negative logic supply through a 500Ω resistor. The TEST pin
load should not be more than 1 mA. See "Digital Section" for
additional information on using TEST as a negative digital
logic supply.
If TEST is pulled HIGH (to V+), all segments plus the
minus sign will be activated. DO NOT OPERATE IN THIS
MODE FOR MORE THAN SEVERAL MINUTES. With
TEST= V+, the LCD segments are impressed with a DC
voltage which will destroy the LCD.
TC7126A Internal Voltage Reference
The TC7126A's analog common voltage temperature
stability has been significantly improved (Figure 7). The "A"
version of the industry-standard TC7126 device allows
users to upgrade old systems and design new systems
without external voltage references. External R and C values do not need to be changed. Figure 10 shows analog
common supplying the necessary voltage reference for the
TC7126A.
TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
1
TC7126
TC7126A
9V
ANALOG COMMON
TEMPERATURE COEFFICIENT (ppm/°C)
200
180
NO
MAXIMUM
SPECIFIED
160
140
TYPICAL
26
1
V–
V+
240 kΩ
120
100
80
TC7126A
NO
GUARANTEED MAXIMUM
SPECIFIED
MAXIMUM
+
VREF
TYPICAL
–
VREF
60
40
36
3
10 kΩ
VREF
TYPICAL
35
ANALOG 32
COMMON
20
TC7126A
ICL7126
ICL7136
0
Figure 7. Analog Common Temperature Coefficient
Several manufacturers supply standard LCDs to interface with the TC7126A 3-1/2 digit analog-to-digital converter.
Manufacturer
Address/Phone
Crystaloid
Electronics
5282 Hudson Dr.,
Hudson, OH 44236
216-655-2429
720 Palomar Avenue
Sunnyvale, CA 94086
408-523-8200
1800 Vernon St., Ste. 2
Roseville, CA 95678
916-783-7878
612 E. Lake St.,
Lake Mills, WI 53551
414-648-2361
AND
VGI, Inc.
Hamlin, Inc.
SET VREF = 1/2 VFULL SCALE
Figure 8. TC7126A Internal Voltage Reference Connection
4
Flat Package
APPLICATIONS INFORMATION
Liquid Crystal Display Sources
*NOTE:
2
+
Representative
Part Numbers*
C5335, H5535,
T5135, SX440
FE 0801,
FE 0203
I1048, I1126
3902, 3933, 3903
Contact LCD manufacturer for full product listing/specifications.
Decimal Point and Annunciator Drive
The TEST pin is connected to the internally-generated
digital logic supply ground through a 500Ω resistor. The
TEST pin may be used as the negative supply for external
CMOS gate segment drivers. LCD annunciators for decimal
points, low battery indication, or function indication may be
added without adding an additional supply. No more than 1
mA should be supplied by the TEST pin: its potential is
approximately 5V below V+.
TELCOM SEMICONDUCTOR, INC.
The TC7126A is available in an epoxy 64-pin formedlead flat package. A test socket for the TC7126ACBQ device
is available:
Part No.
IC 51-42
Manufacturer: Yamaichi
Distribution: Nepenthe Distribution
2471 East Bayshore
Suite 520
Palo Alto, CA 94043
(415) 856-9332
5
Ratiometric Resistance Measurements
The TC7126A's true differential input and differential
reference make ratiometric readings possible. In ratiometric
operation, an unknown resistance is measured with respect
to a known standard resistance. No accurately-defined
reference voltage is needed.
The unknown resistance is put in series with a known
standard and a current passed through the pair. The voltage
developed across the unknown is applied to the input and
the voltage across the known resistor applied to the reference input. If the unknown equals the standard, the display
will read 1000. The displayed reading can be determined
from the following expression:
Displayed reading =
6
7
RUNKNOWN
3 1000.
RSTANDARD
The display will overrange for RUNKNOWN ≥
2 3RSTANDARD.
8
3-227
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
Simple Inverter for Fixed Decimal Point
or Display Annunciator
V+
+
V+
VREF
V–
R STANDARD
V+
REF
TC7126A
TEST
R UNKNOWN
TO LCD
DECIMAL
POINT
BP 21
TC7126A
–
V IN
GND
37
LCD
+
V IN
4049
ANALOG
COMMON
TO
BACKPLANE
Multiple Decimal Point or
Annunciator Driver
Figure 10. Low Parts Count Ratiometric Resistance Measurement
V+
V+
BP
TO LCD
DECIMAL
POINTS
DECIMAL
POINT
SELECT
TC7126A
4030
TEST
GND
Figure 9. Decimal Point and Annunciator Drives
9V
200 mV
C1
2V
0.02
µF
+
1 µF
1 MΩ
VIN
9 MΩ
+
1N4148
1
14
2
13
3
12
10 MΩ
4
900 kΩ
C2
20V
90 kΩ
200V
47 kΩ
1W
10%
6.8 µF
20 kΩ
10%
+
AD636
1
10
6
9
7
8
2.2
µF
29
TC7126A
+
V REF
35
–
V REF
32 ANALOG
COMMON
31
+
V IN
36
10 kΩ
1 MΩ 10%
0.01
µF 30
26
10 kΩ
COM
27
V–
240 kΩ
11
5
26
V+
C1 = 3 pF TO 10 pF, VARIABLE
C2 = 132 pF, VARIABLE
28
40
+
V OUT
38
V–
39
BP
SEGMENT
DRIVE
LCD
Figure 11. 3-1/2 Digit True RMS AC DMM
3-228
TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
1
TC7126
TC7126A
+
160 kΩ
1N4148
SENSOR
300 kΩ
300 kΩ
+
9V
5.6 kΩ
V+
–
VIN
V+
+
VIN
R1
50 kΩ
V–
–
VIN
R1
20 kΩ
+
VIN
0.7%/°C
PTC
TC7126A
+
VREF
R2
50 kΩ
2
160 kΩ
V–
1N4148
9V
R3
TC7126A
+
VREF
R2
20 kΩ
–
VREF
–
VREF
COMMON
COMMON
3
4
Figure 13. Positive Temperature Coefficient Resistor
Temperature Sensor
Figure 12. Temperature Sensor
9V
CONSTANT 5V
2
V+
VOUT
ADJ
REF02
TEMP
6
51 kΩ
R4
5
+
VREF
51 kΩ
50 kΩ
R5
2 –
NC
3
3
TEMPERATURE
DEPENDENT OUTPUT
R2
8
1/2
LM358
+
4
1
V
+
5
–
VREF
+
VIN
TC7126A
–
VIN
VOUT =
1.86V @
+25°C
6
50 kΩ
R1
COMMON
V–
GND
4
7
Figure 14. Integrated Circuit Temperature Sensor
8
TELCOM SEMICONDUCTOR, INC.
3-229