Datasheet

UNISONIC TECHNOLOGIES CO., LTD
UTRS3080
Preliminary
CMOS IC
FAIL-SAFE, 115KBPS, RS-485 /
RS-422 TRANSCEIVERS WITH

DESCRIPTION
SOP-14
The UTC UTRS3080 high-speed transceivers for RS-485/RS-422
communication contain one driver and one receiver. The device
features fail-safe circuitry, which guarantees a logic-high receiver
output when the receiver inputs are open or shorted. This means that
the receiver output will be logic high if all transmitters on a terminated
bus are disabled (high impedance). The UTC UTRS3080 features
reduced slew-rate drivers that minimize EMI and reduce reflections
caused by improperly terminated cables, allowing error-free data
transmission up to 115kbps.
The transceiver typically draws 375µA of supply current when
unloaded or when fully loaded with the drivers disabled.
A device has a 1/8-unit-load receiver input impedance that allows
up to 256 transceivers on the bus.

SOP-8
FEATURES
* True fail-safe receiver while maintaining EIA/TIA-485 compatibility
* Enhanced slew-rate limiting facilitates Error-Free data transmission
* 5.0V single power supply
* 1µA low-current shutdown mode
* Allow up to 256 transceivers on the Bus
* Driver short circuit current limit
* Thermal shutdown for overload protection

ORDERING INFORMATION
Ordering Number
UTRS3080G-S08-R
UTRS3080G-S14-R
www.unisonic.com.tw
Copyright © 2015 Unisonic Technologies Co., Ltd
Package
SOP-8
SOP-14
Packing
Tape Reel
Tape Reel
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UTRS3080
Preliminary
CMOS IC
MARKING

SOP-8

SOP-14
PIN CONFIGURATION
RO
1
8
VCC
RE
2
7
B
DE
3
6
A
DI
4
5
GND
N.C. 1
14 VCC
RO 2
13 N.C.
RE 3
12 A
DE 4
11 B
DI 5
10 Z
GND 6
9
Y
GND 7
8
N.C.
SOP-8

SOP-14
PIN DESCRIPTION
PIN NO.
1, 8, 13
PIN NAME
N.C.
2
RO
3
RE
4
DE
5
DI
6, 7
9
10
11
12
14
GND
Y
Z
B
A
VCC
DESCRIPTION
Not connected. Not internally connected.
Receiver output. When RE is low and if A-B≥-50mV, RO will be high; if A-B≤ -500mV,
RO will be low.
Receiver output enable. Drive RE low to enable RO; RO is high impedance when RE
is high. Drive RE high and DE low to enter low-power shutdown mode.
Driver output enable. Drive DE high to enable driver outputs. These outputs are high
impedance when DE is low. Drive RE high and DE low to enter low-power shutdown
mode.
Driver input. With DE high, a low on DI forces non-inverting output low and inverting
output high. Similarly, a high on DI forces non-inverting output high and inverting output
low.
Ground
Non-inverting driver output
Inverting driver output
Inverting receiver input
Non-inverting receiver input
Positive supply; 4.75V≤VCC≤5.25V
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
Preliminary
CMOS IC
BLOCK DIAGRAM
RD 1
8
VCC
R
14 VCC
N.C. 1
RO 2
RE
DE
2
7
3
6
B
A
DI
4
5
GND
SOP-8
UNISONIC TECHNOLOGIES CO., LTD
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13 N.C.
RE 3
12 A
DE 4
11 B
DI 5
GND 6
D
R
10 Z
D
GND 7
9 Y
8 N.C.
SSOP-14
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Preliminary
CMOS IC
ABSOLUTE MAXIMUM RATING
PARAMETER
SYMBOL
VCC
Supply Voltage
Control Input Voltage ( RE , DE)
Driver Input Voltage
Driver Output Voltage (A, B, Y, Z)
Receiver Input Voltage (A, B)
Receiver Input Voltage, Full Duplex (A, B)
Receiver Output Voltage (RO)
Continuous Power Dissipation
(Derate 8.33mW/°C above +70°C)
RATINGS
+7.0
UNIT
V
-0.3~(VCC+0.3)
V
-0.3~(VCC+0.3)
V
±13
V
±13
V
±25
V
-0.3~(VCC+0.3)
V
SOP-8
471
mW
PD
667
mW
SOP-14
Lead Temperature (Soldering, 10s)
TL
+300
°C
Operating Temperature Ranges
TOPR
-40~+85
°C
Storage Temperature Range
TSTG
-65~+150
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.

DI
DC ELECTRICAL CHARACTERISTICS
(VCC=+5.0V ±5%, TA=TMIN to TMAX, unless otherwise noted. Typical values are at VCC=+5.0V and TA=+25°C) (Note 1)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNIT
DRIVER
Differential Driver Output
VOD1
RT=10kΩ
5.0
V
(No Load)
Fig.1, R=50Ω (RS-422)
1.6
V
Differential Driver Output
VOD2
Fig.1, R=27Ω (RS-485)
1.0
V
Change in Magnitude of
Differential Output Voltage
∆VOD Fig.1, R=50Ω or R=27Ω
0.2
V
(Note 2)
Driver Common-Mode Output
VOC
Fig.1, R=50Ω or R=27Ω
3
V
Voltage
Change In Magnitude of
Common-Mode Voltage
∆VOC Fig.1, R=50Ω or R=27Ω
0.2
V
(Note 2)
Input High Voltage
VIH1
DE, DI, RE
Input Low Voltage
VIL1
DI Input Hysteresis
VHYS
DE, DI, RE
SRL=VCC or Unconnected
SRL Input Current
IIN1
Input Current (A and B)
Full Duplex
IIN4
Output Leakage (Y and Z)
Full Duplex
IO
Driver Short-Circuit Output
Current (Note 4)
VOD1
V
0.8
100
V
mV
DE, DI, RE
±2
µA
VIN=12V
VIN=-7V
VIN=12V
DE=GND, VCC=GND or 5.25V
VIN=-7V
-7V≤VOUT≤VCC
0V≤VOUT≤12V
0V≤VOUT≤VCC
125
-75
125
µA
µA
µA
µA
mA
mA
mA
DE=GND, VCC=GND or 5.25V
UNISONIC TECHNOLOGIES CO., LTD
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2.0
-100
-250
250
±25
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Preliminary
CMOS IC
DC ELECTRICAL CHARACTERISTICS (Cont.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNIT
RECEIVER
Receiver Differential Threshold
VTH
-7V≤VCM≤+12V
-500
-125
50
mV
Voltage
Receiver Input Hysteresis
∆VTH
25
mV
Receiver Output High Voltage
VOH
IO=-4mA, VID=-50mV
VCC-1.5
V
Receiver Output Low Voltage
VOL
IO=4mA, VID=-500mV
0.4
V
Three-State Output Current at
IOZR
0.4V≤VO≤ 2.4V
±1
µA
Receiver
Receiver Input Resistance
RIN
-7V≤VCM≤+12V
96
kΩ
Receiver Output Short-Circuit
IOSR
0V≤VRO≤VCC
±7
±95
mA
Current
SUPPLY CURRENT
No Load,
DE=VCC
430
900
µA
DE=GND
375
600
µA
RE =DI=GND or VCC
Supply Current
ICC
No Load,
DE=VCC
475
1000
µA
DE=GND
420
800
µA
RE =DI=GND or VCC
Supply Current in Shutdown
ISHDN DE=GND, VRE =VCC
1
10
µA
Mode
Notes: 1. All currents into the device are positive; all currents out of the device are negative. All voltages are referred
to device ground unless otherwise noted
2. ∆VOD and ∆VOC are the changes in VOD and VOC, respectively, when the DI input changes state
3. The SRL pin is internally biased to VCC/ 2 by a 100kΩ/100kΩ resistor divider. It is guaranteed to be VCC/ 2
if left unconnected
4. Maximum current level applies to peak current just prior to foldback-current limiting; minimum current level
applies during current limiting
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
Preliminary
CMOS IC
SWITCHING CHARACTERISTICS
(VCC=+5.0V ±5%, TA=TMIN to TMAX, unless otherwise noted. Typical values are at VCC=+5.0V and TA=+25°C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX
tDPLH
2030 2600
Driver Input to Output
Fig.3 and 5, RDIFF=54Ω, CL1=CL2=100pF
tDPHL
2030 2600
Driver Output Skew
-3
±200
tDSKEW Fig.3 and 5, RDIFF=54Ω, CL1=CL2=100pF
| tDPLH - tDPHL |
Driver Rise or Fall Time
tDR, tDF Fig.3 and 5, RDIFF=54Ω, CL1=CL2=100pF
1320 2500
Maximum Data Rate
fMAX
115
Driver Enable to Output High
tDZH
Fig.4 and 6, CL=100pF, S2 Closed
3500
Driver Enable to Output Low
tDZL
Fig.4 and 6, CL=100pF, S1 Closed
3500
Driver Disable Time from Low
tDLZ
Fig.4 and 6, CL=15pF, S1 Closed
100
Driver Disable Time from High
tDHZ
Fig.4 and 6, CL=15pF, S2 Closed
100
tRPLH, Fig.7 and 9, |VID|≥2.0V; Rise and Fall Time
Receiver Input to Output
200 400
tRPHL of VID≤15ns
|tRPLH - tRPHL| Differential
Fig.7 and 9, |VID|≥2.0V; Rise and Fall Time
3
100
tRSKD
Receiver Skew
of VID≤15ns
Receiver Enable to Output Low
tRZL
Fig.2 and 8, CL=100pF, S1 Closed
20
100
Receiver Enable to Output High
tRZH
Fig.2 and 8, CL=100pF, S2 Closed
20
100
Receiver Disable Time from Low
tRLZ
Fig.2 and 8, CL=100pF, S1 Closed
20
300
Receiver Disable Time from
Fig.2 and 8, CL=100pF, S2 Closed
20
300
tRHZ
High
Time to Shutdown
tSHDN Note 1
50
200 600
Driver Enable from Shutdown to
6000
tDZH(SHDN) Fig. 4 and 6, CL=15pF, S2 Closed
Output High
Driver Enable from Shutdown to
6000
tDZL(SHDN) Fig.4 and 6, CL=15pF, S1 Closed
Output Low
Receiver Enable from Shutdown
3500
tRZH(SHDN) Fig.4 and 6, CL=100pF, S2 Closed
to Output High
Receiver Enable from Shutdown
3500
tRZL(SHDN) Fig. 4 and 6, CL=100pF, S1 Closed
to Output Low
UNIT
ns
ns
ns
ns
kbps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: The device is put into shutdown by bringing RE high and DE low. If the enable inputs are in this state for less
than 50ns, the device is guaranteed not to enter shutdown. If the enable inputs are in this state for at least
600ns, the device is guaranteed to have entered shutdown
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
Preliminary
CMOS IC
FUNCTION TABLE
Table 1 TRANSMITTING
INPUTS
RE
X
X
0
1
OUTPUTS
DE
DI
Z
Y
1
1
0
0
1
0
X
X
0
1
High-Z
1
0
High-Z
Shutdown
Table 2 RECEIVING
INPUTS
DE
A-B
RE
0
X
≥-0.05V
0
X
≤-0.5V
0
X
Open/Shorted
1
1
X
1
0
X
X = Don’t care
Shutdown mode, driver and receiver outputs high impedance
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OUTPUT
RO
1
0
1
High-Z
Shutdown
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
Preliminary
CMOS IC
TEST CIRCUIT
Y
TEST POINT
RECEIVER
OUTPUT
R
CRL
VOD
+
15pF
VOC
R
1KΩ
VCC
S1
1KΩ
S2
Z
Fig. 2 Receiver Enable/Disable Timing Test Load
Fig. 1 Driver DC Test Circuit
3V
DE
DI
Y
CL1
VID
OUTPUT
UNDER TEST
VCC
S1
CL
RDIFF
+
500Ω
Z
CL2
S2
Fig. 3 Driver Timing Test Circuit
VOH
RO
Fig. 4 Driver Enable/Disable Timing Test Load
1.5V
1.5V
RE
1.5V
1.5V
tZL(SHDN), tZL
tLZ
VCC
tPHL
A
B
Fig. 7 Receiver Propagation Delays
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RO
1.5V OUTPUT NORMALLY LOW
RO
1.5V
tPLH
Input
-1V
0V
Output
VOL
1V
3V
VOL+0.5V
OUTPUT NORMALLY HIGH
0
tZH(SHDN), tZH
VOH-0.5V
tHZ
Fig. 8 Receiver Enable and Disable Times
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Preliminary

TEST CIRCUIT (Cont.)

TYPICAL APPLICATION CIRCUIT
DE
VCC
4
VCC RE
0.1µF
14
9
DI
5
CMOS IC
D
Y
Rt
10
RO
R
Z
12 A
RO
2
R
Rt
D
11
DI
B
NC
1,8,13
3
6,7 GND
RE
GND
DE
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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