The following document contains information on Cypress products. S6AP412A ASSP Multi-phase 3ch DCDC Converter with I2C Interface and Internal SW FETs Data Sheet (Full Production) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. Publication Number S6AP412A_DS405-00018 CONFIDENTIAL Revision 1.0 Issue Date December 26, 2014 D a t a S h e e t Notice On Data Sheet Designations Spansion. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office. 2 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 S6AP412A ASSP Multi-phase 3ch DCDC converter with I2C interface and internal SW FETs Data Sheet (Full Production) 1. Description S6AP412A contains 2ch buck DC/DC converter and 1ch buck-boost DC/DC converter. One of the buck DC/DC converter is available for Multi-phase method. Multi-phase DC/DC converter is possible to load high current until 4A. S6AP412A can supply the main power line in several systems by using only its chip. The current mode control is adopted for the DC/DC converter, and it is possible to use the small chip inductor with the high switching frequency operation which contains internal switching FETs. S6AP412A contains the output setting resistor and the phase compensation circuit, and contributes to reduce the number of external components and its mount area. Also it contains the CTL input pin which can control the ON/OFF for each 2 DC/DC converter, the Power Good signal output pin and I C communication interface, therefore it is easy to 2 design the power supply sequence. It is possible to tune in the output voltage exactly using the I C communication. 2. Features Operating input voltage range: 2.5V to 5.5V (Maximum rating: 6.5V) Output voltage setting range: DD1*:0.7V to 1.32V (20 mV/step) DD2*:1.2V to 1.95V (50 mV/step) DD3*:2.8V to 3.5V (100 mV/step) Maximum output current: DD1:4A, DD2:1.2A, DD3:0.6A Internal switching FETs, output voltage setting resistor, phase compensation circuit and output discharge resistor (all DC/DC converters) Buck-boost DC/DC converter is seamless to change operation mode Soft start time setting range: 1 ms to 16 ms (approximately 1 ms/step) Switching frequency for the DC/DC converter: 3 MHz 2 Communication interface: I C (ON/OFF, Output voltage, Soft start time) Internal PFM/PWM auto switching mode Each DC/DC converter Power Good function (open drain) Several protection functions: Under voltage lockout (UVLO), Over current protection (OCP), Thermal shut down (TSD) Small package: QFN32 (5mm × 5mm × 0.71mm, 0.5mm pitch) *: DD1,DD2,DD3 : DC/DC converter block 1,2,3 3. Application Network equipment, Factory automation, Security system, Surveillance camera, Electrical music instrument, Multi-function printer, Scanner, Printer, Copy machine, Home appliances ,Data storage (HDD, SSD), Mobile equipment for Li+ battery (1 cell) Publication Number S6AP412A_DS405-00018 Revision 1.0 Issue Date December 26, 2014 This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. CONFIDENTIAL D a t a S h e e t Table of Contents 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 4 CONFIDENTIAL Description ..................................................................................................................................... 3 Features ......................................................................................................................................... 3 Application ...................................................................................................................................... 3 Application Circuit Example ............................................................................................................ 6 Recommended Application Specification ....................................................................................... 7 Pin Configuration ............................................................................................................................ 9 Pin Descriptions............................................................................................................................ 10 Block Diagram .............................................................................................................................. 11 Absolute Maximum Ratings .......................................................................................................... 12 Recommended Operating Conditions........................................................................................... 13 Electrical Characteristics .............................................................................................................. 14 11.1 Reference Control block .................................................................................................... 14 11.2 DD1 ......................................................................................................................... 15 11.3 DD2 ......................................................................................................................... 16 11.4 DD3 ......................................................................................................................... 17 11.5 Digital block ....................................................................................................................... 18 Operation Mode List ..................................................................................................................... 19 State Transition Diagram .............................................................................................................. 20 Turning ON and OFF Sequence (AVCC=CTLMAIN, CTL1, CTL2, CTL3).................................... 21 Turning ON and OFF Sequence (AVCC → CTLMAIN → CTL1 → CTL2 → CTL3) ............... 22 2 Turning ON and OFF Sequence (AVCC → CTLMAIN → I C)................................................... 23 CTL Pin, MODE Pin, ADDSEL Pin Threshold Voltage ................................................................. 24 Protection Operation Sequence ................................................................................................... 25 Operation Condition, Stop Circuit and Release Condition for Protection Circuit ........................... 26 DD Soft Start Operation................................................................................................................ 27 Discharge Operation..................................................................................................................... 28 PG Function ................................................................................................................................. 29 2 I C Interface.................................................................................................................................. 30 2 23.1 Structure of I C Interface ................................................................................................... 30 23.2 Definition of Signal Lines ................................................................................................... 30 23.3 Validity of Data .................................................................................................................. 31 23.4 Definition of Start and Stop Condition ............................................................................... 31 23.5 ACK Signal ........................................................................................................................ 32 2 23.6 I C Interface Input Timing .................................................................................................. 33 23.7 Slave Address ................................................................................................................... 34 2 23.8 Bit Structure of Data on I C Interface ................................................................................ 35 2 Structure of I C Interface and Data............................................................................................... 37 24.1 About DD1 Output Voltage Setting .................................................................................... 38 24.2 About DD2 Output Voltage Setting .................................................................................... 39 24.3 About DD3 Output Voltage Setting .................................................................................... 40 24.4 About Soft Start Time ........................................................................................................ 41 24.5 DC/DC Operation Mode .................................................................................................... 42 24.6 ON/OFF for DC/DC ........................................................................................................... 43 24.7 About Error Monitor ........................................................................................................... 44 24.8 About Power Good Monitor ............................................................................................... 45 I/O Pin Equivalent Circuit Diagram ............................................................................................... 46 Measurement Circuit for Characteristics of General Operation .................................................... 49 Reference Data ............................................................................................................................ 51 Ordering Information..................................................................................................................... 63 Preset Code List ........................................................................................................................... 64 Layout........................................................................................................................................... 65 S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 31. Package Dimensions .................................................................................................................... 66 32. Major Changes ............................................................................................................................. 67 Figures Figure 4-1 Application Circuit ..................................................................................................................... 6 Figure 9-1 Power Dissipation vs. Operation Ambient Temperature .......................................................... 12 Figure 20-1 DD Soft Start ......................................................................................................................... 27 Figure 31-1 Layout example ..................................................................................................................... 65 Tables Table 12-1 Operation Mode List ............................................................................................................... 19 Table 17-1 CTL(*1), MODE, ADDSEL Pin Equivalent Circuit Diagram ..................................................... 24 Table 18-1 Error Detection Sequence ...................................................................................................... 25 Table 24-1 Register map .......................................................................................................................... 37 Table 26-1 Parts list .................................................................................................................................. 50 Table 28-1 Ordering Information ............................................................................................................... 63 December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 5 D a t a S h e e t 4. Application Circuit Example Figure 4-1 Application Circuit 6 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 5. Recommended Application Specification [Input Voltage Range] Input voltage Vin(V) Min Typ Max 2.5 3.3 5.5 VO1 ±1.2% 0.711 0.720 0.729 0.731 0.740 0.749 0.751 0.760 0.769 0.771 0.780 0.789 0.790 0.800 0.810 0.810 0.820 0.830 0.830 0.840 0.850 0.850 0.860 0.870 0.869 0.880 0.891 0.889 0.900 0.911 (*1) (*1) (*1) 0.909 0.920 0.931 0.929 0.940 0.951 0.948 0.960 0.972 0.968 0.980 0.992 0.988 1.000 1.012 (*1) (*1) (*1) 1.008 1.020 1.032 1.028 1.040 1.052 1.047 1.060 1.073 1.067 1.080 1.093 1.087 1.100 1.113 (*1) (*1) (*1) 1.107 1.120 1.133 1.126 1.140 1.154 1.146 1.160 1.174 1.166 1.180 1.194 1.186 1.200 1.214 (*1) (*1) (*1) 1.205 1.220 1.235 1.225 1.240 1.255 1.245 1.260 1.275 1.265 1.280 1.295 1.284 1.300 1.316 1.304 1.320 1.336 December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL Resistance (kΩ) Discharge (ms) Output Soft-start Time Min Switching Mode Current (mA) Limit Current (mA) Max Capacitance (µF) Max 0.708 Inductor (µH) Typ 0.700 Frequency (MHz) Min 0.692 Output Accuracy Symbol Channel DD1 Output Voltage (V) Multi 1 to 16 Phase ms (4800) rectification) Multi Phase C-mode Built-in time of (synchronous 4000 Built-in SWFET At the Buck 3.0 1.0 22 1.0V setting, the details are cf. Contents 17 Remarks (Ta=+25°C) [Output specification] output 5.0 setting resistors Built-in phase compens ation circuit 7 DD2 DD3 VO2 VO3 ±1.2% ±1.8% (*1) (*1) (*1) 1.235 1.250 1.265 1.284 1.300 1.316 1.334 1.350 1.366 Remarks Resistance (kΩ) Discharge (ms) Output Switching Mode (mA) Limit Current Min Soft-start Time Max Capacitance (µF) Max 1.214 Inductor (µH) Typ 1.200 S h e e t frequency (MHz) Min 1.186 Output Output Voltage (V) Current (mA) Accuracy Symbol Channel D a t a (*1) (*1) (*1) 1 to 16 Built-in 1.383 1.400 1.417 ms SWFET 1.433 1.450 1.467 1.482 1.500 1.518 (*1) (*1) (*1) 1.531 1.550 1.569 1.581 1.600 1.619 1.630 1.650 1.670 1.680 1.700 1.729 Built-in Buck 1200 (1500) (synchronous rectification) 3.0 1.0 10 At the output time of setting 1.8V 5.0 setting, C-mode resistors Built-in the details phase 1.720 are cf. compen Contents sation 1.750 1.771 17 circuit 1.778 1.800 1.822 (*1) (*1) (*1) 1.828 1.850 1.872 1.877 1.900 1.923 1.927 1.950 1.973 2.74 2.80 2.86 (*1) (*1) (*1) 1 to 16 Built-in 2.84 2.90 2.96 ms SWFET 2.94 3.00 3.06 (*1) (*1) (*1) 3.04 3.10 3.16 3.14 3.20 3.26 3.23 3.30 3.37 (*1) (*1) (*1) 3.33 3.40 3.43 (*1) Built-in Buck-boost 600 (750) (synchronous rectification) C-mode 3.0 1.0 22 At the output time of setting 3.3V setting, 5.0 resistors Built-in the details phase are cf. compen 3.47 Contents sation 3.50 3.57 17 circuit (*1) (*1) *1: default (It is selectable with the default output voltage) 8 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 6. Pin Configuration (TOP VIEW) (WNT032) December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 9 D a t a S h e e t 7. Pin Descriptions Block DD1 Multi-phase DD2 Buck DD3 Buck-boost CTL I2C Pin Pin Name Number IN1 24 PullI/O Description Unused Unused Unused Unused DD1 DD2 DD3 I2C - GND - - - - AVCC - - - down Resistor I DD1 output voltage feedback DD1 Phase1 output block power PVCC1A 23 - LX1A 22 O DD1 Phase1 inductor connection - Open - - - PG1 28 O DD1 Power Good output - GND - - - PGND1A 21 - DD1 Phase1 output block ground - GND - - - PVCC1B 18 - - AVCC - - - LX1B 19 O DD1 Phase2 inductor connection - Open - - - PGND1B 20 - DD1 Phase2 output block ground - GND - - - IN2 8 I DD2 output voltage feedback - - GND - - PVCC2 5 - DD2 output block power supply - - AVCC - - LX2 6 O DD2 inductor connection - - Open - - PG2 29 O DD2 Power Good output - - GND - - PGND2 7 - DD2 output block ground - - GND - - IN3 31 I DD3 output voltage feedback - - - GND - PVCC3 4 - Power supply for DD3 output block - - - AVCC - supply DD1 Phase2 output block power supply VO3 32 O Output voltage for DD3 - - - GND - LX3-1 3 O DD3 inductor connection1 - - - Open - LX3-2 1 O DD3 inductor connection2 - - - Open - PG3 30 O Output for DD3 Power Good - - - GND - PGND3 2 - Ground for DD3 output block - - - GND - CTLMAIN 25 I Exist - - - - CTL1 9 I DD1 control Exist Open - - - CTL2 10 I DD2 control Exist - Open - - CTL3 11 I DD3 control Exist - - Open - - - - - GND Control for reference voltage output Power supply for I2C DVCC 16 I SCL 14 I Clock for I2C communication - - - - Open SDA 15 I/O Data for I2C communication Exist - - - Open ADDSEL 17 I Switch for slave address - - - - Open AVCC 27 - Power supply for reference voltage - - - - - Exist - - - - communication Select for DC/DC converter Reference MODE 12 I CONFIDENTIAL mode, L=PWM mode, common for all DCDC converter ) control 10 operation mode (H: PFM/PWM VREF18 26 O Output reference voltage - - - - - GND 13 - Ground for reference voltage - - - - - GND EP - Ground for reference voltage - - - - - S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 8. Block Diagram IN1 PVCC1A <<DD1>> VCC:2.5V to 5.5V L Priority A VCC VCC VCC PWM Logic Control ErrAMP ctl1 ICOMP VREF18 A LX1A AST UVLO LV CNV POR SLP CMP DAC PGND1A PG1 mode clk PVCC1B VCC VCC PWM Logic Control ICOMP LV CNV SLP CMP cs1 IN2 scp1 LX1B AST PGND1B xclk PVCC2 <<DD2>> L Priority B VCC VCC ErrAMP ctl2 VREF18 VCC PWM Logic Control ICOMP B LX2 AST UVLO LV CNV POR SLP CMP DAC PGND2 PG2 cs2 IN3 <<DD3>> scp2 mode clk PVCC3 L Priority C VCC VCC VCC ErrAMP ctl3 VREF18 PWM Logic Control ICOMP LX3-1 AST UVLO LV CNV POR SLP CMP DAC C VO3 AST LX3-2 PGND3 PG3 cs3 DVCC mode xclk scp3 VREF18 SCL Logic Control SDA Output Voltage Ajuster CTL1 AVCC ctl1 CTL2 ctl2 CTL3 Common Block Logic Control ctl3 VREF BGR Under Voltage Locked-Out CTLMAIN Thermal Shut Down ADDSEL VREF18 MODE mode scp* (1.8V) Short Circuit Protection (Timer & Latch) Soft Start Control cs* OSC clk CT RT xclk GND December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 11 D a t a S h e e t 9. Absolute Maximum Ratings Parameter Symbol Power supply voltage Terminal voltage LX voltage Permission loss Rating Condition Min Max Unit VVCC1 AVCC,PVCC input voltage -0.3 6.5 V VVCC2 DVCC input voltage -0.3 6.5 V VCTL1 CTL1,CTL 2,CTL3 input voltage -0.3 6.5 V VCTL2 CTLMAIN input voltage -0.3 6.5 V VMODE MODE input voltage -0.3 6.5 V VLOGIC SDA,SCL input voltage -0.3 6.5 V VADD ADDSEL input voltage -0.3 6.5 V VPG PG1, PG2, PG3 drain voltage -0.3 6.5 V VOUT IN1, IN2, IN3 input voltage -0.3 6.5 V VLX LX1, LX2, LX3 voltage -1.0 6.5 V 0 3420 mW PD Ta≤+25°C Thermal resistance (θja): (29.2°C /W(*1)) Maximum junction temperature Tjmax - - +125 °C Storage temperature TSTG - -55 +125 °C *1: When the IC is mounted on 74mm × 74mm four-layer square epoxy board. IC is mounted on a four-layer epoxy board, which terminal bias, and the IC’s thermal pad is connected to the epoxy board. WARNING: 1. Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Figure 9-1 Power Dissipation vs. Operation Ambient Temperature Power dissipation vs. Operation ambient temperature 4000 3500 3000 Pd [mW] 2500 2000 1500 1000 500 0 -40 -20 0 20 40 60 80 100 Temperature[˚C] 12 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 10. Recommended Operating Conditions Parameter Symbol Condition Value Min Typ Max Unit 1. Reference control block Power supply voltage VVCC AVCC 2.5 3.3 5.5 V Output current for reference voltage IREF VREF18 -1 - 0 mA Operating temperature Ta -30 +25 +85 °C - 2. DC/DC channel Power supply voltage VVCC PVCC1, PVCC2, PVCC3 2.5 3.3 5.5 V Input voltage VOUT IN1,IN2 0 - AVCC V Input voltage VOUT IN3 0 - 5.5 V PG input voltage VPG PG1, PG2, PG3 0 - 5.5 V VCTL CTL1, CTL 2, CTL3, MODE 0 - AVCC V 3. Input block Input voltage VMODE CTLMAIN VVCC DVCC 4. I2C communication block Power supply voltage 1.70 - 3.50 V Input voltage VLOGIC SDA,SCL 0 - DVCC V Input voltage VADD ADDSEL 0 - AVCC V WARNING: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. 2. Any use of semiconductor devices will be under their recommended operating condition. 3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. 4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 13 D a t a S h e e t 11. Electrical Characteristics 11.1 Reference Control Block (AVCC = PVCC1A=PVCC1B=PVCC2=PVCC3 = 3.3V, supply, PGND1A=PGND1B=PGND2=PGND3=GND=0V. Ta = +25°C, unless otherwise noted. ) Parameter Symbol 1. Reference voltage VVREF2 VVREF3 VREF18 pin = 0 mA AVCC pin = 2.5V to 5.5V VREF18 pin = 0 mA VREF18 pin = 0 mA to -1 mA 2. Under voltage lockout VTH Hysteresis width VH AVCC rising - 3. Over current protection DD1, DD2, DD3 4. Thermal shut down - 5. Input block (CTL,MODE,CTLMAIN) Input voltage VIH Input voltage VIL ICTLH IMODEH ICTLL IMODEL Input pull-down resistor 1.773 1.800 1.827 V 1.768 1.800 1.832 V 1.768 1.800 1.832 V 2.156 2.20 2.244 V - 0.20(*1) - V 0.9 1 1.1 ms 125(*2) 150 - °C - AVCC V 0 - 0.4 V 2.5 3.3 4.7 µA - - 1 µA - 1(*1) - MΩ - 0 1.0 µA - 30 45 µA - 430 630 µA - 18 27 mA [ TSD ] TTSDH Input current Max [ OCP ] tOCP1 Stop temperature Typ [ VCC UVLO ] Threshold voltage Timer Unit Min [ VREF18 ] VVREF1 Output voltage Value Condition RP [ CTL,MODE,CTLMAIN ] CTL1, CTL2, CTL3,MODE pin AVCC CTLMAIN pin × 0.7 CTL1, CTL2, CTL3,MODE pin CTLMAIN pin CTL1, CTL2, CTL3,MODE pin = 3.3V CTLMAIN pin = 3.3V CTL1, CTL2, CTL3,MODE pin = 0V CTLMAIN pin = 0V CTL1, CTL2, CTL3,MODE pin CTLMAIN pin 6. Consumption current (DC/DC converter block) IVCCS1 IVCCS2 Power supply current CTL1, CTL2, CTL3 pin = 0V CTLMAIN pin = 0V CTL1, CTL2, CTL3 pin = 0V CTLMAIN pin =3.3V DD1,DD2,DD3=ON,MODE=3.3V, IVCC All DD are 0 mA (operation mode: PFM/PWM mode) DD1,DD2,DD3=ON,MODE=0V IVCC All DD are 0 mA (operation mode: Fixed PWM mode) *1: This parameter is not be specified. This should be used as a reference to support designing the circuits. *2: No production tested, ensure by design. 14 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 11.2 DD1 (AVCC = PVCC1A=PVCC1B=PVCC2=PVCC3 = 3.3V, supply, PGND1A=PGND1B=PGND2=PGND3=GND=0V. Ta = +25°C, unless otherwise noted. ) Parameter Symbol Condition Max 0.988 1.000 1.012 V -5 - +5 mV -10 - +10 mV -10 - +15 mV IN1 = 2.0V - 190(*1) - kΩ RPMOS LX1A,1B = -30 mA - 120(*1) - mΩ RNMOS LX1A,1B = 30 mA - 80(*1) - mΩ ILEAK LX1A,1B = 0V -3 - - µA ILEAK LX1A,1B = 3.3V - - 3 µA ILIMIT L=1.0 µH 4900(*2) - - mA IPFM L=1.0 µH - 100(*1) - mA [ DD1 ] Output voltage VOUT Input stability VLINE Load stability VLOAD Load stability VLOAD SW PMOS-Tr on resistance SW NMOS-Tr on resistance SW PMOS-Tr leakage current SW NMOS-Tr Leakage current Over current protection value PFM/PWM mode changeover current Unit Typ 1. DC/DC converter block IN1 input impedance Value Min RIN Discharge resistor RDIS Soft start time Tss Switching frequency fOSC IOUT = -10 mA, Output voltage setting: 1.0V IOUT = -10 mA, PVCC1 = 2.5V to 5.5V IOUT = -1 mA to -4000 mA (Fixed PWM mode) IOUT = -1 mA to -4000 mA (PFM/PWM mode) Soft start time setting: 1 ms - - 5(*1) - kΩ 0.9 1 1.1 ms 2.7 3.0 3.3 MHz *1: This parameter is not be specified. This should be used as a reference to support designing the circuits. *2: No production tested, ensure by design. December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 15 D a t a S h e e t 11.3 DD2 (AVCC = PVCC1A=PVCC1B=PVCC2=PVCC3 = 3.3V, supply, PGND1A=PGND1B=PGND2=PGND3=GND=0V. Ta = +25°C, unless otherwise noted. ) Parameter Symbol Condition Max 1.778 1.800 1.822 V -5 - +5 mV -10 - +10 mV -10 - +20 mV IN2 = 2.0V - 150(*1) - kΩ RPMOS LX2 = -30 mA - 190(*1) - mΩ RNMOS LX2 = 30 mA - 135(*1) - mΩ ILEAK LX2 = 0V -3 - - µA ILEAK LX2 = 3.3V - - 3 μA ILIMIT L=1.0 µH 1500(*2) - - mA IPFM L=1.0 µH - 65(*1) - mA - 5 - kΩ 0.9 1 1.1 ms 2.7 3.0 3.3 MHz [ DD2 ] Output voltage VOUT Input stability VLINE Load stability VLOAD Load stability VLOAD SW PMOS-Tr on resistance SW NMOS-Tr on resistance SW PMOS-Tr leakage current SW NMOS-Tr leakage current Over current protection value PFM/PWM mode changeover current Discharge resistor Unit Typ 2. DC/DC converter block IN2 input impedance Value Min RIN RDIS Soft start time Tss Switching frequency fOSC IOUT = -10 mA, Output voltage setting:1.8V IOUT = -10 mA PVCC2 = 2.5V to 5.5V IOUT = -1mA to -1200 mA (Fixed PWM mode) IOUT = -1 mA to -1200 mA (PFM/PWM mode) Soft start time setting: 1 ms - *1: This parameter is not be specified. This should be used as a reference to support designing the circuits. *2: No production tested, ensure by design. 16 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 11.4 DD3 (AVCC = PVCC1A=PVCC1B=PVCC2=PVCC3 = 3.3V, supply, PGND1A=PGND1B=PGND2=PGND3=GND=0V. Ta = +25°C, unless otherwise noted. ) Parameter Symbol Condition Max 3.241 3.300 3.359 V -5 - +5 mV -10 - +10 mV -10 - +15 mV IN3 = 2.0V - 550(*1) - kΩ RPMOS LX3-1 = -30 mA - 115(*1) - mΩ RNMOS LX3-1 = 30 mA - 140(*1) - mΩ RPMOS LX3-2 = -30 mA - 155(*1) - mΩ RNMOS LX3-2 = 30 mA - 220(*1) - mΩ ILEAK LX3-1 = 0V -3 - - μA ILEAK LX3-1 = 3.3V - - 1 μA ILEAK LX3-2 = 0V -3 - - μA ILEAK LX3-2 = 3.3V - - 1 μA ILIMIT L=1.0 µH 1000(*2) - - mA IPFM L=1.0 µH - 200(*1) - mA [ DD3 ] Output voltage VOUT Input stability VLINE Load stability VLOAD Load stability VLOAD SW PMOS-Tr on resistance SW NMOS-Tr on resistance SW PMOS-Tr on resistance SW NMOS-Tr on resistance SW PMOS-Tr leakage current SW NMOS-Tr leakage current SW PMOS-Tr leakage current SW NMOS-Tr leakage current Over current protection value PFM/PWM mode changeover current RIN Discharge resistor RDIS Soft start time Tss Switching frequency Unit Typ 3. DC/DC converter block IN2 input impedance Value Min IOUT = -10 mA, Output voltage setting: 3.3V IOUT = -10 mA, PVCC3 = 2.5V to 5.5V IOUT = -1 mA to -600 mA (Fixed PWM mode) IOUT = -1 mA to -600 mA (PFM/PWM mode) Soft start time setting:1 ms fOSC - - 5(*1) - kΩ 0.9 1 1.1 ms 2.7 3.0 3.3 MHz *1: This parameter is not be specified. This should be used as a reference to support designing the circuits. *2: No production tested, ensure by design. December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 17 D a t a S h e e t 11.5 Digital Block (AVCC = PVCC1A=PVCC1B=PVCC2=PVCC3 = 3.3V, supply, PGND1A=PGND1B=PGND2=PGND3=GND=0V. Ta = +25°C, unless otherwise noted. ) Parameter Symbol Condition 1. Power Good block Value Min Typ Max Unit [ Power Good ] Output voltage VOL PG1, PG2, PG3 IOL = 1 mA - - 0.4 V Output current IOL PG1, PG2, PG3 1 - - mA Low voltage detection VTH IN1, IN2, IN3 = falling - - V Power on detection VTH IN1, IN2, IN3 = rising - - V DVCC V 2. I2C block Vo ×0.90(*1) Vo ×0.93(*1) [ I2C ] VIH SCL,SDA VIL SCL,SDA DVCC ×0.7 Input voltage IIH Input current IIL SCL,SDA DVCC = 3.3V SCL,SDA DVCC = 3.3V - DVCC 0 - - - 10 µA -10 - - µA ×0.3 V Output voltage VOL SDA IOL = 3 mA - - 0.4 V Output current IOL SDA 3 - - mA - AVCC V 0 - 0.4 V 2.5 3.3 4.7 µA 3. ADDSEL block [ ADDSEL ] Input voltage Input voltage Input current Input pull-down resistor VIH ADDSEL AVCC ×0.7 VIL ADDSEL IADD ADDSEL = 3.3V IADD ADDSEL = 0V - - 1 µA RP ADDSEL - 1(*1) - MΩ *1: This parameter is not be specified. This should be used as a reference to support designing the circuits. 18 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 12. Operation Mode List Table 12-1 Operation Mode List Mode Stand-by Stand-by2 Normal Error Detection L H H H L L H/L(*1) X X CTLMAIN (external) CTL signal Operation Block (external/I2C) CTL1 2 CTL2 (external/I C) L L H/L(*1) CTL3 (external/I2C) L L H/L(*1) X Reference OFF ON ON ON Digital OFF ON ON ON DD1 OFF OFF ON/OFF OFF DD2 OFF OFF ON/OFF OFF DD3 OFF OFF ON/OFF OFF disable enable enable enable I2C communication I2C communication Protection Thermal shut down (TSD) Not available Not available available (*2) operating Over current protection (OCP) Not available Not available available (*2) *1: normal mode means that CTLMAIN pin is "H" level and each DD CTL pin is "H" level *2: This state is after each err detection. Error state will release, when the power supply voltage or CTLMAIN pin will turn off and on. 2 Priority of the External CTL pin and I C Communication CTLMAIN CTL1, CTL2, CTL3 30h Resistor Relevant (External) (External) (I2C) Channel H H 1 ON H H 0 ON H L 1 ON H L 0 OFF L X disable OFF 2 Priority of the External MODE pin and I C Communication MODE 20h Resistor (External) (I2C) H 1 PFM/PWM H 0 PFM/PWM L 1 PFM/PWM L 0 Fixed PWM Operation Mode Notes: − The I C communication is valid after the reference control block and digital block activation setting the external CTLMAIN pin to "H" level. − Please attention below note about ON/OFF control of DD1, DD2, DD3 by I C communication. 2 When each DD control is turned off by I C communication and external CTL pin remains "H" level, DCDC converter keep operating. 2 December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 2 19 D a t a S h e e t 13. State Transition Diagram Stand-by (1) (2) Stand-by 2 (3) (2) (4) General (6) (5) Error detection (1) External CTLMAIN pin is "H" level. (2) External CTLMAIN pin is "L" level. (3) External CTL pin or I2C communication "relevant CH_ON" (4) External CTL pin or I2C communication "relevant CH_OFF" (5) Error detection (TSD, OCP 1 ms continuation) (6) Turning on the power supply again (equal to or less than uvlo_vcc rest voltage) or setting CTLMAIN to "L" level 20 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 14. Turning ON and OFF Sequence (AVCC=CTLMAIN, CTL1, CTL2, CTL3) 2.0V 2.2V AVCC CTLMAIN CTL*(*1) 1.8V VREF18 osc (IC internal signal) uvlo_vcc (IC internal signal) DD1 93% Discharge 93% Discharge 93% Discharge PG1 DD2 PG2 DD3 PG3 UVLO release release to DD* activation UVLO DD(*2) activation Soft-start time Time till start (*3) (*1) Typ : (820)µs Max : TBD µs *1: CTL1, CTL2, CTL3 *2: DD1, DD2, DD3 *3: VREF18 activations depend on the VREF18 pin capacitance. Time in the sequence figure above is applied for the following condition. VREF18 pin capacitance: 1.0µF December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 21 D a t a S h e e t 15. Turning ON and OFF Sequence (AVCC → CTLMAIN → CTL1 → CTL2 → CTL3) AVCC 3.3V CTLMAIN 1.8V VREF18 osc (IC internal signal) uvlo_vcc (IC internal signal) CTL1 93% DD1 Discharge PG1=CTL2 93% Discharge DD2 PG2=CTL3 93% DD3 Discharge PG3 UVLO release to DD*activation activation UVLO release to DD(*1) Time till start (*2) (*1) Typ : (820)µs Max : TBD µs *1: DD1, DD2, DD3 *2: VREF18 activations depend on the VREF18 pin capacitance. Time in the sequence figure above is applied for the following condition. VREF18 pin capacitance: 1.0µF 22 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 16. Turning ON and OFF Sequence (AVCC → CTLMAIN → I2C) AVCC 3.3V CTLMAIN 1.8V VREF18 osc (IC internal signal) uvlo_vcc (IC internal signal) I2C(DD ON/OFF) OFF ON OFF ctl*(*1) DD1 93% Discharge 93% Discharge 93% Discharge PG1 DD2 PG2 DD3 PG3 UVLOrelease releaseto to DD(*2) DD* activation UVLO activation Soft-start time Time till start (*3) (*1) Typ : (820)µs Max : TBD µs *1: CTL1, CTL2, CTL3 *2: DD1, DD2, DD3 *3: VREF18 activations depend on the VREF18 pin capacitance. Time in the sequence figure above is applied for the following condition. VREF18 pin capacitance: 1.0µF December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 23 D a t a S h e e t 17. CTL Pin, MODE Pin, ADDSEL Pin Threshold Voltage The input circuit structure for the CTL(*1) pin is the schmitt trigger style, and the threshold voltage shows the hysteresis characteristics when CTL(*1) OFF to ON and ON to OFF. (See "CTL(*1) pin equivalent circuit diagram" below.) Also, the threshold voltage level depends on the VCC pin voltage. Moreover, make sure to input either the "H" level (>"VCC×0.7"V) or "L" level (<0.4V) to the CTL(*1) and MODE and ADDSEL pin when in use. Table 17-1 CTL(*1), MODE, ADDSEL Pin Equivalent Circuit Diagram AVCC The CTL threshold voltage shows the hysteresis characteristics. ESD protection element CTL*(*1) MODE ADDSEL ESD protection element GND *1: CTLMAIN, CTL1, CTL2, CTL3 24 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 18. Protection Operation Sequence Over Current Protection (DD channel) The DD channel monitors the peak current of FET at any time during the operation. When the DD output becomes the over current state, the output voltage is decreased. Afterward, the timer operation is performed and the output stops after about 1 ms progress. When one of each DD channel stops operation by over current protection, all DD channels stop operation. Thermal Shut Down If the temperature at the junction part reaches +150°C, the thermal shutdown protection circuit turns all channels off. Error Detection Sequence Table 18-1 Error Detection Sequence DD1,DD2,DD3 The whole IC Normal operation Normal operation Over current detection Thermal shutdown protection Voltage drop No 1ms Continue for 1ms? Yes Error detection mode Error signal output (I2C address 40h) Error Detection Mode Release It is necessary to turn the power supply turning on again, or to turn CTLMAIN turning on again to release the error detection mode. December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 25 D a t a S h e e t 19. Operation Condition, Stop Circuit and Release Condition for Protection Circuit Operation Channel Whilst Under Over Current Protection (OCP) Protection Under Voltage Lockout Protection Thermal Shutdown Protection (TSD) (UVLO) Operating condition: Operating condition: Input Operating condition: voltage drop Process during protection After about 1 ms progress in the over current condition Process during protection operation: Process during protection DD1,DD2,DD3 Discharge DD1, DD2, DD3 stop operation: DD1, DD2, DD3 stop Recovery condition: operation: DD1, DD2, DD3 stop Chip temperature increment (1) Power supply reasserted Recovery condition: (2) CTLMAIN reasserted Input voltage rise Recovery condition: (1) Power supply reasserted UVLO operates only when (2) CTLMAIN reasserted CTLMAIN is "H" (at VREF18 output). Only when CTLMAIN is in the "H" state and CTL(*1) is in the "H" state, or when DD(*2) in operating condition by I2C, will operate. Error output - (address 40h) Write "1" when detecting OCP No change Write "1" when detecting TSD Thermal shutdown protection (TSD) operation during over current protection timer operation When the thermal shutdown protection (TSD) operated during the over current protection (OCP) timer operation, the thermal shutdown protection has priority. Operation when releasing under voltage lockout protection (UVLO) − DD1,DD2,DD3 : Activation following the condition for CTL(*1) pin or I2C Note: − 2 When VREF18 decreases at the time of UVLO operation, I C register is reset, and all DD does OFF. It is necessary to let you do ON by CTL(*1) pin and communication again to let DD have ON. *1: CTL1, CTL2, CTL3 *2: DD1, DD2, DD3 26 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 20. DD Soft Start Operation The soft-start operation for DD1, DD2 and DD3 is enabled in order to prevent the rush current during the DD 2 activation. The soft-start time can be controlled by I C. About output voltage changing option, soft start time is showed by follow equation. Tss=Tslp × Vset/Vdef (ms) Tss : soft start time Tslp : slope coefficient of soft start Vset : output voltage setting Vdef : DD1=1.0, DD2=1.8, DD3=3.3 Figure 20-1 DD Soft Start Output voltage2 setting value Output voltage1 setting value Output voltage3 setting value Soft-start time Channel ON/OFF signal (internal signal) t December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 27 D a t a S h e e t 21. Discharge Operation DD Channel When executing the DD OFF operation at the channel ON/OFF signal, the DC/DC smooth capacitance charged for each output voltage is discharged using resistor for discharge which is set in the IC and the output voltage is decreased gradually. However, the discharge time changes depending on the DC/DC converter load current. The discharge time is calculated by the following equation. Discharge time (time till the output becomes 10% without load) toff(s) ≈ 2.3 × R_DIS × COUT (F) Note: − See the table in Electrical Characteristics for the discharge resistor value. IN(*1) A Resistor for discharge R1 PVCC(*2) A Error Amp R2 LX(*3) Cout Reference voltage DAC PGND(*4) Channel ON/OFF Cont. *1: IN1, IN2, IN3 *2: PVCC1, PVCC2, PVCC3 *3: LX1, LX2, LX3 *4: PGND1, PGND2, PGND3 28 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 22. PG Function The following pins for each channel Power Good output are prepared. PG1 It is the pin for DD1 Power Good output. When the output voltage exceeds 93% of the setting value at the DD1 ON mode, "H" is output. Also, when the output voltage becomes equal or lower than 90% of the setting value after the "H" output, "L" is output. "L" is output at the DD1 OFF mode. PG2 It is the pin for DD2 Power Good output. When the output voltage exceeds 93% of the setting value at the DD2 ON mode, "H" is output. Also, when the output voltage becomes equal or lower than 90% of the setting value after the "H" output, "L" is output. "L" is output at the DD2 OFF mode. PG3 It is the pin for DD3 Power Good output. When the output voltage exceeds 93% of the setting value at the DD3 ON mode, "H" is output. Also, when the output voltage becomes equal or lower than 90% of the setting value after the "H" output, "L" is output. "L" is output at the DD3 OFF mode. December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 29 D a t a S h e e t 23. I2C Interface 23.1 Structure of I2C Interface 2 The I C interface executes the data communication in 1 byte (8-bit) units using two signal lines (bus), a SCL (serial clock line) and a SDA (serial data line). This bus is connected to multiple devices; master: device to generate the clock signal and to control the data transfer (CPU and so on) slave: device that an address is specified by a master. This IC is set as the slave and has no function to be the master. Each device is defined due to the communication direction as described below. transmitter: device to send data to bus receiver: device to receive data from bus The IC has the function both transmitter and receiver. SCL SDA transmitter receiver receiver maser slave1 transmitter slave2 The IC defines the followings; Write : data is transmitted from master and the IC receives data Read : The IC transmits data and master receives data. 23.2 Definition of Signal Lines SCL and SDA are connected to the power supply by the pull-up resistor. The output circuit is the open Drain output. When a bus is not used (waiting state), the open "H" is set changing the open Drain to the OFF state. Note: − 2 SCL and SDA pins adopt a different ESD protection system from standard I C specification because of ESD enhancement (see 25. I/O Pin Equivalent Circuit Diagram). When the power supply is in the bus line, do not shut off the power supply for an IC (DVCC). I2C bus line power supply R R Pull Up SCL SDA input Inside of IC 30 CONFIDENTIAL input output S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 23.3 Validity of Data Data has the following characteristics; − change when SCL is the "L" level − valid if the state is kept while SCL is the "H" level. SCL SDA data state data change data state The SDA signal change means the start or stop condition when SCL is the "H" level. 23.4 Definition of Start and Stop Condition The start and stop conditions are output from the master and shows start and stop of communications to the slave. − Start : SDA changes from "H" to "L" when SCL is "H". − Stop : SDA changes from "L" to "H" when SCL is "H". SCL SDA S start condition December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL P stop condition 31 D a t a S h e e t 23.5 ACK Signal This is a signal to confirm the data reception during communication. The receiver replies the ACK signal to show the data reception to a transmitter every time 1 byte (8-bit) of data is received. The ACK signal is sent in 9clk after sending data 8-bit matching to the SCL signal that the master generates. − A transmitter keeps SDA output "open H" in SCL9clk. − A receiver informs the data reception situation to a transmitter outputting the followings in SCL 9 clk; when data was received : SDA output "L" (ACK) when no data was received : SDA output "open H" (NACK) However, if the master is changed to the receiver, ACK is not replied after the last data reception because the bus keeps open stopping the data transmission to the slave transmitter. In this case, the slave transmitter opens the bus (open H) and is set to the stop condition reception waiting state from the master. SCL from master SDA by transmitter SDA by receiver 32 CONFIDENTIAL 1 8 bit0 bit7 9 H hold 10 bit0 NACK ACK S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 23.6 I2C Interface Input Timing (within recommended operating conditions) Value Parameter Symbol SCL=100 kHz SCL=400 kHz Unit Min Max Min Max SCL clock frequency fSCL - 100 - 400 kHz Start condition hold time tHD:start 4.0 - 0.6 - µs Restart condition setup time tSU:start 4.7 - 0.6 - µs Stop condition setup time tSU:stop 4.0 - 0.6 - µs tbuf 4.7 - 1.3 - µs SCL "L" time tLow 4.7 - 1.3 - µs SCL "H" time tHigh 4.0 - 0.6 - µs SCL/SDA rising time tr - 1.0 - 0.3 µs SCL/SDA falling time tf - 0.3 - 0.3 µs Data hold time tHD:data 0.0 - 0.0 - µs Data setup time tSU:data 0.25 - 0.10 - µs Cb - 400 - 400 pF Stop to Start bus open time SCL/SDA capacitor load VIH/VIL level reference 2 Conform to I C bus specifications S tr tf tHigh tLow Sr SCL P tbuf SDA tHD:start tSU:data tHD:data December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL tSU:start tSU:stop 33 D a t a S h e e t 23.7 Slave Address 2 This is a slave address when communicating with the I C interface. The slave address of this IC is set by the first seven bits as shown below. The seventh bit follows the ADDSEL pin and "0"/"1" are variable. The eighth bit is called the least significant bit (LSB) and determines the message direction. The bit "0" shows that information will be written from the master to the slave. The bit "1" shows that the master reads information from the slave. This does not support the general call address. When the ADDSEL pin is in "H" S T A R T slave address 0 1 0 1 1 0 1 MSB R/W LSB A C K S T O P A C K S T O P When the ADDSEL pin is in "L" S T A R T 34 CONFIDENTIAL slave address 0 MSB 1 0 1 1 0 0 R/W LSB S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 23.8 Bit Structure of Data on I2C Interface (1) Writing Data to Register and Reading Data The data line is sent/received in the order from the most significant bit (MSB) to the least significant bit (LSB). S T A R T No. A C K slave address 1 2 3 4 5 6 7 register address 8 1 S 0 1 0 1 1 0 0 W A C K 2 3 4 5 6 7 8 0 0 0 0 0 0 1 0 S A T C O K P data 1 2 3 4 5 6 7 8 a b c d e f g h P register data address 00H 01H 02H 03H 04H : : D07 D06 D05 D04 D03 D02 D01 D00 a b c d e f g h Output the "stop" condition after sending the Write data. : Signal which a master sends, December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL : Signal which this IC sends 35 D a t a S h e e t 2 (2) I C Interface Data Format 2 About I C Communication 1. When a different slave address comes, non-matching ID is informed by not replying ACK after receiving the slave address. 2. All registers write to internal registers in the ACK signal after receiving the 8-bit data of each setting. 3. If a non-existing register address is specified, data is not written to a register. 4. Output the "stop" condition after sending the write data. <Write (W)> S T A R T A C K slave address A C K register address data S A T C O K P S 0 1 0 1 1 0 0 W P When the ADDSEL pin is in "L" Write is allowed per one address. (Sequential writing is not allowed.) Send register address and data as one unit. : Signal which a master sends, : Signal which this IC sends <Read (R)> S T A R T slave address A C K S 0 1 0 1 1 0 0 W When the ADDSEL pin is in "L" register address S T A A C R K T slave address A C K data S 0 1 0 1 1 0 0 R S A T C O K P P When the ADDSEL pin is in "L" Read is allowed per one address. Be sure to perform read by specifying the register addresses. (Sequential reading is not allowed.) : Signal which a master sends, 36 CONFIDENTIAL : Signal which this IC sends S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 24. Structure of I2C Interface and Data Table 24-1 Register Map Data Address Writing Remarks d07 d06 d05 d04 d03 d02 d01 d00 Default Timing 00H 0 0 0 D04 D03 D02 D01 D00 0FH ACK DD1 output voltage setting Output 01H 0 0 0 0 D03 D02 D01 D00 0CH ACK DD2 output voltage setting voltage 02H 0 0 0 0 0 D02 D01 D00 05H ACK DD3 output voltage setting 03H 0 0 0 (*1) (*1) (*1) (*1) (*1) 0FH ACK Unused 10H 0 0 0 0 D03 D02 D01 D00 00H ACK DD1 soft-start time setting 11H 0 0 0 0 D03 D02 D01 D00 00H ACK DD2 soft-start time setting 12H 0 0 0 0 D03 D02 D01 D00 00H ACK DD3 soft-start time setting 13H 0 0 0 0 (*1) (*1) (*1) (*1) 00H ACK Unused Soft start DD DD operation mode setting operation 20H 0 0 0 0 (*1) D02 D01 D00 00H ACK mode "0": Fixed PWM mode, "1":PFM/PWM mode ON/OFF 30H 0 0 0 0 (*1) D02 D01 D00 00H ACK Error 40H 0 0 0 D04 (*1) D02 D01 D00 00H - DD output ON/OFF setting "0":Output OFF / "1": Output ON DD error state monitoring register (read only) "0":Normal / "1": Error detection DD PG state monitoring register PG 50H 0 0 0 0 (*1) D02 D01 D00 00H - (read only) "0": Non-output / "1": output For test EXH - - - - - - - - - - Disabled For test FXH - - - - - - - - - - Disabled *1: Unused register. Write/read is possible, but does not influence IC movement. Note: − Address FXH and address EXH are for test. Do not write/read FXH and EXH. December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 37 D a t a S h e e t 24.1 About DD1 Output Voltage Setting Address 00H DD1 is allocated as resisters for the DC/DC output voltage setting. The DC/DC output voltage setting of DD1 is controlled by writing data to address 00 H. Data S T A R T 0 0 0 D04 D03 D02 MSB D01 D00 LSB A C K S T O P address00H: For DD1 output voltage setting D04 to D00: Set the output voltage DD1 Output Voltage Setting Table Data Output Voltage (V) Data Output Voltage (V) 00H 0.700 10H 1.020 01H 0.720 11H 1.040 02H 0.740 12H 1.060 03H 0.760 13H 1.080 04H 0.780 14H 1.100 (*1) 05H 0.800 15H 1.120 06H 0.820 16H 1.140 07H 0.840 17H 1.160 08H 0.860 18H 1.180 09H 0.880 19H 1.200 (*1) 0AH 0.900 (*1) 1AH 1.220 0BH 0.920 1BH 1.240 0CH 0.940 1CH 1.260 0DH 0.960 1DH 1.280 0EH 0.980 1EH 1.300 0FH 1.000 (*1) 1FH 1.320 *1: Preset value 38 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 24.2 About DD2 Output Voltage Setting Address 01H DD2 is allocated as resisters for the DC/DC output voltage setting. The DC/DC output voltage setting of DD2 is controlled by writing data to address 01 H. Data S T A R T 0 0 0 MSB 0 D03 D02 D01 D00 LSB A C K S T O P address01H: For DD2 output voltage setting D03 to D00: Set the output voltage DD2 Output Voltage Setting Table Data Output Voltage (V) 00H 1.200 (*1) 01H 1.250 02H 1.300 03H 1.350 (*1) 04H 1.400 05H 1.450 06H 1.500 (*1) 07H 1.550 08H 1.600 09H 1.650 0AH 1.700 0BH 1.750 0CH 1.800 (*1) 0DH 1.850 0EH 1.900 0FH 1.950 *1: Preset value December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 39 D a t a S h e e t 24.3 About DD3 Output Voltage Setting Address 02H DD3 is allocated as resisters for the DC/DC output voltage setting. The DC/DC output voltage setting of DD3 is controlled by writing data to address 02 H. Data S T A R T 0 0 0 MSB 0 0 D02 D01 D00 LSB A C K S T O P address02H: For DD3 output voltage setting D02 to D00: Set the output voltage DD3 Output Voltage Setting Table Data Output Voltage (V) 00H 2.80 (*1) 01H 2.90 02H 3.00 (*1) 03H 3.10 04H 3.20 05H 3.30 (*1) 06H 3.40 07H 3.50 (*1) *1: Preset value 40 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 24.4 About Soft Start Time Address 10H to 12H are allocated as registers for the soft start time control. The soft start time control is controlled by writing data to addresses 10 H to 12H. Data S T A R T 0 0 0 0 D03 D02 MSB D01 D00 LSB A C K S T O P address10H: For DD1 soft start time setting address11H: For DD2 soft start time setting address12H: For DD3 soft start time setting D03 to D00: Set the soft start time Tss=Tslp × Vset/Vdef (ms) Tss : soft start time Tslp : slope coefficient of soft start : refer to follow table Vset : output voltage setting Vdef : DD1=1.0, DD2=1.8, DD3=3.3 Soft Start Time Setting Data Tslp Remarks 00H 1.0 DD1,DD2,DD3 (*1) 01H 2.0 02H 3.0 03H 4.0 04H 5.0 05H 6.0 06H 7.0 07H 8.0 08H 9.0 09H 10.0 0AH 11.0 0BH 12.0 0CH 13.0 0DH 14.0 0EH 15.0 0FH 16.0 *1: Preset value December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 41 D a t a S h e e t 24.5 DC/DC Operation Mode Address 20H is allocated as a register for the DC/DC operation mode control. The DC/DC operation mode is controlled by writing data to address 20 H. Data S T A R T 0 0 0 0 D03 D02 D01 MSB D00 LSB A C K S T O P address20H: For DC/DC operation mode setting D01 to D00: Set the DC/DC operation mode Address Bit 20H D00 20H D01 20H D02 20H D03 Description 0: DD1 Fixed PWM (*1) 1: DD1 PFM/PWM 0: DD2 Fixed PWM (*1) 1: DD2 PFM/PWM 0: DD3 Fixed PWM (*1) 1: DD3 PFM/PWM Out of use *1: Preset value 42 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 24.6 ON/OFF for DC/DC Address 30H is allocated as a register for the DC/DC ON/OFF. The DC/DC ON/OFF is controlled by writing data to address 30H. Data S T A R T 0 0 0 0 D03 D02 D01 MSB D00 LSB A C K S T O P address30H: For DC/DC ON/OFF D02 to D00: Set ON/OFF for DC/DC Address Bit 30H D00 30H D01 30H D02 30H D03 Description 0: DD1 output OFF (*1) 1: DD1 output ON 0: DD2 output OFF (*1) 1: DD2 output ON 0: DD3 output OFF (*1) 1: DD3 output ON Out of use *1: Preset value December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 43 D a t a S h e e t 24.7 About Error Monitor Address 40H is allocated as error status monitor of each DC/DC output and thermal shut down. Address 40H is read only resistor. Data S T A R T 0 0 0 D04 D03 D02 D01 MSB D00 LSB A C K S T O P address40H: For error monitor of each DC/DC output and thermal shut down D04 to D00: read only resistor. (Not allowed write resistor) Address Bit 40H D00 40H D01 40H D02 40H D03 40H D04 Description 0: DD1 OCP non detection (*1) 1: DD1 OCP detection 0: DD2 OCP non detection (*1) 1: DD2 OCP detection 0: DD3 OCP non detection (*1) 1: DD3 OCP detection Out of use 0: TSD non detection (*1) 1: TSD detection *1: Preset value 44 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 24.8 About Power Good Monitor Address 50H is allocated as output monitor of each DC/DC output. Address 50H is read only resistor. Data S T A R T 0 0 0 0 D03 D02 D01 MSB D00 LSB A C K S T O P address50H: For output monitor of each DC/DC output. Detection level is over 93% of DCDC output voltage setting. D04 to D00: read only resistor. (Not allowed write resistor) Address Bit 50H D00 50H D01 50H D02 50H D03 Description 0: DD1 non output (*1) 1: DD1 output 0: DD2 non output (*1) 1: DD2 output 0: DD3 non output (*1) 1: DD3 output Out of use *1: Preset value December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 45 D a t a S h e e t 25. I/O Pin Equivalent Circuit Diagram <<AVCC>> AVCC ESD protection element GND <<VREF18>> AVCC VREF18 GND <<IN1,IN2, LX1,LX2, PGND1<PGND2>> AVCC IN* GND IN*: IN1, IN2 LX*: LX1, LX2 PGND*: PGND1, PGND2 46 CONFIDENTIAL LX* PGND* S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t <<PVCC1,PVCC2> AVCC PVCC*: PVCC1, PVCC2 LX*: LX1, LX2 PGND*: PGND1, PGND2 PVCC* LX* PGND* GND <<IN3,PGND3 > IN3 GND PGND3 <<PVCC3,LX3-1,LX3-2,VO3>> AVCC PVCC3 LX3-1 VO3 LX3-2 PGND3 GND December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 47 D a t a S h e e t <<CTL*, ADDSEL, MODE>> <<PG*>> AVCC AVCC PG*: PG1, PG2, PG3 PG* CTL* ADDSEL MODE GND GND CTL*: CTLMAIN, CTL1, CTL2, CTL3 <<SCL>> DVCC DVCC SCL SDA GND 48 CONFIDENTIAL <<SDA>> GND S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 26. Measurement Circuit for Characteristics of General Operation S6AP412A Input Voltage: 2.5V to 5.5V C1 0.1mF C2 4.7mF IN1 AVCC PVCC1A LX1A L1 C7 C8 22mF 22mF 1.0mH DD1:1.0V Io(max):4000mA PGND1A C3 4.7mF PVCC1B LX1B CTL1 L2 1.0mH PGND1B R1 100kW PG1 PG1 C4 4.7mF IN2 PVCC2 LX2 CTL2 L3 C9 22mF 1.0mH DD2:1.80V Io(max):1200mA PGND2 R2 100kW C5 4.7mF PVCC3 PG2 LX3-1 CTL3 L4 1.0mH CTLMAIN 3.3V SCL SDA PG2 LX3-2 DVCC SCL SDA IN3 VO3 MODE ADDSEL VREF18 C10 33mF DD3:3.30V Io(max):600mA PGND3 R3 100kW PG3 PG3 GND C6 1.0mF December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 49 D a t a S h e e t Table 26-1 Parts list Symbol Parts Part number Specifications Vendor L1 Inductor 1276AS-H-1R0M 1.0 µH TOKO L2 Inductor 1276AS-H-1R0M 1.0 µH TOKO L3 Inductor 1276AS-H-1R0M 1.0 µH TOKO L4 Inductor 1276AS-H-1R0M 1.0 µH TOKO C1 Ceramic Capacitor C1608X5R1H104K 0.1 µF TDK C2 Ceramic Capacitor C1608X5R1V475K 4.7 µF TDK C3 Ceramic Capacitor C1608X5R1V475K 4.7 µF TDK C4 Ceramic Capacitor C1608X5R1V475K 4.7 µF TDK C5 Ceramic Capacitor C1608X5R1V475K 4.7 µF TDK C6 Ceramic Capacitor C2012X5R1A336M 1.0 µF TDK C7 Ceramic Capacitor C1608X5R1H105K 22 µF TDK C8 Ceramic Capacitor C1608X5R1H105K 22 µF TDK C9 Ceramic Capacitor C1608X5R1H105K 22 µF TDK C10 Ceramic Capacitor C2012X5R1A336M 33 µF TDK R1 Resistor RR0816P-104-D 100 kΩ SSM R2 Resistor RR0816P-104-D 100 kΩ SSM Resistor RR0816P-104-D 100 kΩ SSM R3 TOKO TDK SSM 50 CONFIDENTIAL : TOKO, INC. : TDK Corporation : SUSUMU CO., LTD. S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 27. Reference Data Inductor and capacitor value refer to section 26. DCDC Convertor Efficiency Data DD1 Input voltage = 3.3V, Vo=1.2V setting 100 100 90 90 80 80 70 70 Efficiency[%] Efficiency[%] Input voltage = 3.3V, Vo = 1.0V setting 60 50 40 30 20 0 0.00001 30 0 0.00001 10 Input voltage = 5.5V, Vo = 1.0V setting 100 100 90 90 80 80 70 70 60 50 40 30 20 0 0.00001 PFM/PWM 0.001 0.1 Load current[A] 10 50 40 30 Fixed PWM PFM/PWM 10 PFM/PWM 0.001 0.1 Load current[A] 60 20 Fixed PWM 10 Fixed PWM Input voltage = 5.5V, Vo = 1.2V setting Efficiency[%] Efficiency[%] 40 10 PFM/PWM 0.001 0.1 Load current[A] 50 20 Fixed PWM 10 60 0 0.00001 10 0.001 0.1 Load current[A] 10 DD2 100 100 90 90 80 80 70 70 60 50 40 30 20 0 0.00001 December 26, 2014, S6AP412A_DS405-00018-1v0-E 50 40 30 10 PFM/PWM 0.001 0.1 Load current[A] 60 20 Fixed PWM 10 CONFIDENTIAL Input voltage = 3.3V, Vo = 1.8V setting Efficiency[%] Efficiency[%] Input Voltage = 3.3V, Vo = 1.5V setting 10 0 0.00001 Fixed PWM PFM/PWM 0.001 0.1 Load current[A] 10 51 D a t a S h e e t DD2 Input Voltage = 5.5V, Vo = 1.8V setting 100 100 90 90 80 80 70 70 Efficiency[%] Efficiency[%] Input voltage = 5.5V, Vo = 1.5V setting 60 50 40 30 20 0 0.00001 40 30 10 PFM/PWM 0.001 0.1 Load current[A] 50 20 Fixed PWM 10 60 0 0.00001 10 Fixed PWM PFM/PWM 0.001 0.1 Load current[A] 10 DD3 100 90 90 80 80 70 70 60 50 40 30 20 10 0 0.00001 52 CONFIDENTIAL Input Voltage = 5.5V, Vo = 3.3V setting 100 Efficiency[%] Efficiency[%] Input voltage = 3.3V, Vo = 3.3V setting 50 40 30 20 Fixed PWM Fixed PWM 10 PFM/PWM 0.001 0.1 Load current[A] 60 10 0 0.00001 PFM/PWM 0.001 0.1 Load current[A] 10 S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t DCDC Convertor Regulation Data DD1 Input voltage = 3.3V, Vo = 1.0V setting Input voltage = 3.3V, Vo=1.2V setting 1.015 1.215 1.010 1.210 Output voltage[V] 1.220 Output voltage[V] 1.020 1.005 1.205 1.000 1.200 0.995 1.195 0.990 Fixed PWM 0.985 PFM/PWM 0.980 0.0 1.0 2.0 3.0 Load current[A] 4.0 Input voltage = 5.5V, Vo = 1.0V setting 1.190 Fixed PWM 1.185 PFM/PWM 1.180 1.215 1.010 1.210 Output voltage[V] 1.220 1.015 Output voltage[V] 1.0 2.0 3.0 Load current[A] 4.0 Input voltage = 5.5V, Vo = 1.2V setting 1.020 1.005 1.205 1.000 1.200 0.995 1.195 0.990 Fixed PWM 0.985 PFM/PWM 0.980 0.0 0.0 1.0 2.0 3.0 Load current[A] 4.0 1.190 Fixed PWM 1.185 PFM/PWM 1.180 0.0 1.0 2.0 3.0 Load current[A] 4.0 DD2 Input Voltage = 3.3V, Vo = 1.5V setting Input voltage = 3.3V, Vo = 1.8V setting 1.815 1.510 1.810 Output voltage[V] 1.820 1.515 Output voltage[V] 1.520 1.505 1.805 1.800 1.500 1.795 1.495 1.490 Fixed PWM 1.485 PFM/PWM 1.480 0.0 0.4 0.8 Load current[A] December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 1.2 1.790 Fixed PWM 1.785 PFM/PWM 1.780 0.0 0.4 0.8 Load current[A] 1.2 53 D a t a S h e e t DD2 Input voltage = 5.5V, Vo = 1.5V setting Input Voltage = 5.5V, Vo = 1.8V setting 1.815 1.510 1.810 Output voltage[V] 1.820 1.515 Output voltage[V] 1.520 1.805 1.505 1.800 1.500 1.795 1.495 1.490 Fixed PWM 1.485 PFM/PWM 1.480 0.0 0.4 0.8 Load current[A] 1.2 1.790 Fixed PWM 1.785 PFM/PWM 1.780 0.0 0.4 0.8 Load current[A] 1.2 DD3 3.320 3.320 3.315 3.315 3.310 3.310 3.305 3.305 3.300 3.300 3.295 3.295 3.290 Fixed PWM 3.285 PFM/PWM 3.280 0.0 0.2 0.4 Load current[A] 54 CONFIDENTIAL Input Voltage = 5.5V, Vo = 3.3V setting Output voltage[V] Output voltage[V] Input voltage = 3.3V, Vo = 3.3V setting 0.6 3.290 Fixed PWM 3.285 PFM/PWM 3.280 0.0 0.2 0.4 0.6 Load current[A] S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t DCDC Convertor Output Ripple Voltage DD1 Input voltage = 3.3V, Vo = 1.0V setting Input voltage = 3.3V, Vo=1.0V setting Load current = 0mA , Fixed PWM Load current = 4000mA, Fixed PWM 10mV/div, 0.5μs/div Input voltage = 5.5V, Vo = 1.0V setting Input voltage = 5.5V, Vo = 1.0V setting Load current = 0mA , Fixed PWM Load current = 4000mA, Fixed PWM 10mV/div, 0.5μs/div 10mV/div, 0.5μs/div Input voltage = 3.3V, Vo = 1.0V setting Input voltage = 3.3V, Vo=1.0V setting Load current = 0mA , PFM/PWM Load current = 4000mA,PFM/PWM 10mV/div, 2ms/div Input voltage = 5.5V, Vo = 1.0V setting Load current = 0mA , PFM/PWM 10mV/div, 2ms/div December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 10mV/div, 0.5μs/div 10mV/div, 0.5μs/div Input voltage = 5.5V, Vo = 1.0V setting Load current = 4000mA,PFM/PWM 10mV/div, 0.5μs/div 55 D a t a S h e e t DD2 Input voltage = 3.3V, Vo = 1.8V setting Input voltage = 3.3V, Vo=1.8V setting Load current = 0mA , Fixed PWM Load current = 1200mA, Fixed PWM 10mV/div, 0.5μs/div Input voltage = 5.5V, Vo = 1.8V setting Input voltage = 5.5V, Vo = 1.8V setting Load current = 0mA , Fixed PWM Load current =1200mA, Fixed PWM 10mV/div, 0.5μs/div Input voltage = 3.3V, Vo=1.8V setting Load current = 0mA , PFM/PWM Load current =1200mA,PFM/PWM 10mV/div, 0.5μs/div Input voltage = 5.5V, Vo = 1.8V setting Input voltage = 5.5V, Vo = 1.8V setting Load current = 0mA , PFM/PWM Load current = 1200mA,PFM/PWM 10mV/div, 2ms/div CONFIDENTIAL 10mV/div, 0.5μs/div Input voltage = 3.3V, Vo = 1.8V setting 10mV/div, 2ms/div 56 10mV/div, 0.5μs/div 10mV/div, 0.5μs/div S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t DD3 Input voltage = 3.3V, Vo = 3.3V setting Input voltage = 3.3V, Vo=3.3V setting Load current = 0mA , Fixed PWM Load current = 600mA, Fixed PWM 10mV/div, 0.5μs/div Input voltage = 5.5V, Vo = 3.3V setting Input voltage = 5.5V, Vo = 3.3V setting Load current = 0mA , Fixed PWM Load current =600mA, Fixed PWM 10mV/div, 0.5μs/div 10mV/div, 0.5μs/div Input voltage = 3.3V, Vo = 3.3V setting Input voltage = 3.3V, Vo=3.3V setting Load current = 0mA , PFM/PWM Load current = 600mA,PFM/PWM 10mV/div, 2ms/div 10mV/div, 0.5μs/div Input voltage = 5.5V, Vo = 1.0V setting Input voltage = 3.3V, Vo =3.3V setting Load current = 0mA , PFM/PWM Load current = 600mA,PFM/PWM 10mV/div, 2ms/div December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 10mV/div, 0.5μs/div 10mV/div, 0.5μs/div 57 D a t a S h e e t DCDC Convertor Enable/Disable DD1(Fixed PWM) Input voltage = 3.3V, Vo = 1.0V setting Input voltage = 3.3V, Vo=1.0V setting Load current = 4000mA, Tss = 1ms setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG1(6V/div) PG1(6V/div) 1.01ms Vo(0.5V/div) Vo(0.5V/div) 200us/div 510ms 200ms/div IIN(1.0A/div) IIN(40mA/div) DD1(PFM/PWM) Input voltage = 3.3V, Vo = 1.0V setting Input voltage = 3.3V, Vo=1.0V setting Load current = 4000mA, Tss = 1ms setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG1(6V/div) PG1(6V/div) 1.01ms Vo(0.5V/div) Vo(0.5V/div) 200us/div 515ms 200ms/div IIN(1.0A/div) IIN(40mA/div) DD2(Fixed PWM) Input voltage = 3.3V, Vo = 1.8V setting Input voltage = 3.3V, Vo=1.8V setting Load current = 1200mA, Tss = 1ms setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG2(6V/div) PG2(6V/div) 1.02ms Vo(1V/div) Vo(1V/div) 200us/div 200ms 50ms/div IIN(500mA/div) IIN(40mA/div) 58 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t DD2(PFM/ PWM) Input voltage = 3.3V, Vo = 1.8V setting Input voltage = 3.3V, Vo=1.8V setting Load current = 1200mA, Tss = 1ms setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG2(6V/div) PG2(6V/div) 1.03ms Vo(1V/div) Vo(1V/div) 200us/div 204ms 50ms/div IIN(500mA/div) IIN(40mA/div) DD3 (Fixed PWM) Input voltage = 3.3V, Vo = 3.3V setting Input voltage = 3.3V, Vo=3.3 V setting Load current = 600mA, Tss = 1ms setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG3(6V/div) PG3(6V/div) 0.99ms Vo(2V/div) 200us/div Vo(2V/div) 270ms 100ms/div IIN(500mA/div) IIN(40mA/div) DD3 (Fixed PWM) Input voltage = 3.3V, Vo = 3.3V setting Input voltage = 3.3V, Vo=3.3 V setting Load current = 600mA, Tss = 1ms setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG3(6V/div) PG3(6V/div) 1.0ms Vo(2V/div) 200us/div Vo(2V/div) 270ms 100ms/div IIN(500mA/div) IIN(40mA/div) December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 59 D a t a S h e e t DCDC Convertor Load Transient DD1(Fixed PWM) Input voltage = 3.3V, Vo = 1.0V setting Input voltage = 3.3V, Vo=1.0V setting Load current = from 0mA to 4000mA per 10us Load current = from 4000mA to 0mA per 10us 82.5mV Vo1(100mV/div) offset：1.000V Vo1(100mV/div) offset：1.000V 82.5mV 10us 10us Io(2.0A/div) Io(2.0A/div) DD1(PFM/PWM) Input voltage = 3.3V, Vo = 1.0V setting Input voltage = 3.3V, Vo=1.0V setting Load current = from 0mA to 4000mA per 10us Load current = from 4000mA to 0mA per 10us Vo1(100mV/div) offset：1.000V 84.1mV Vo1(100mV/div) offset：1.000V 82.5mV 50ms 10us Io(2.0A/div) Io(2.0A/div) DD2(Fixed PWM) Input voltage = 3.3V, Vo = 1.8V setting Input voltage = 3.3V, Vo=1.8V setting Load current = from 0mA to 1200mA per 10us Vo2(50mV/div) offset：1.8V Load current = from 1200mA to 0mA per 10us 54.1mV Vo1(50mV/div) offset：1.8V 54.8mV 10us 10us Io(1.0A/div) 60 CONFIDENTIAL Io(1.0A/div) S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t DD2(PFM/ PWM) Input voltage = 3.3V, Vo = 1.8V setting Input voltage = 3.3V, Vo=1.8V setting Load current = from 0mA to 1200mA per 10us Load current = from 1200mA to 0mA per 10us Vo2(50mV/div) offset：1.8V 57.1mV Vo1(50mV/div) offset：1.8V 54.0mV 10ms 10us Io(1.0A/div) Io(1.0A/div) DD3 (Fixed PWM) Input voltage = 3.3V, Vo = 3.3V setting Input voltage = 3.3V, Vo=3.3 V setting Load current = 600mA, Tss = 1ms setting Load current = 0mA, Tss = 1ms setting Vo3(50mV/div) offset：3.3V 54.7mV Vo3(50mV/div) offset：3.3V 59.5mV 10us 10us Io(500mA/div) Io(500mA/div) DD3 (Fixed PWM) Input voltage = 3.3V, Vo = 3.3V setting Input voltage = 3.3V, Vo=3.3 V setting Load current = 600mA, Tss = 1ms setting Load current = 0mA, Tss = 1ms setting Vo3(50mV/div) offset：3.3V 84mV Vo3(50mV/div) offset：3.3V 83mV 20ms 10us Io(500mA/div) Io(500mA/div) December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 61 D a t a S h e e t DCDC Convertor DVFS Function DD1 (Fixed PWM) Input voltage = 3.3V, Input voltage = 3.3V Vo =from 0.7V to 1.32V setting by I2C Vo =from 1.32V to 0.7V setting by I2C SCL (2V/div) SCL (2V/div) PG (5V/div) PG (5V/div) Vo1 (200mV/div) offset0.7V 62 CONFIDENTIAL 100us Vo1 (200mV/div) offset0.7V 100us S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 28. Ordering Information Table 28-1 Ordering Information Part Number Package Remarks S6AP412A18GN1C000 S6AP412A28GN1C000 S6AP412A38GN1C000 S6AP412A58GN1C000 S6AP412A68GN1C000 S6AP412A78GN1C000 32-pin plastic QFN S6AP412A98GN1C000 (WNT032) S6AP412AA8GN1C000 S6AP412AB8GN1C000 S6AP412AD8GN1C000 S6AP412AE8GN1C000 S6AP412AF8GN1C000 December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL 63 D a t a S h e e t 29. Preset Code List DD1 Output Voltage DD2 Output Voltage DD3 Output Voltage Preset Code Value Preset Code Value Preset Code Value 18 0.90V 1.35V 3.30V 28 0.90V 1.50V 3.30V 38 0.90V 1.80V 3.30V 58 1.00V 1.35V 3.30V 68 1.00V 1.50V 3.30V 78 1.00V 1.80V 3.30V 98 1.10V 1.35V 3.30V A8 1.10V 1.50V 3.30V Preset Code 64 CONFIDENTIAL B8 1.10V 1.80V 3.30V D8 1.20V 1.35V 3.30V E8 1.20V 1.50V 3.30V F8 1.20V 1.80V 3.30V S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 30. Layout Consider the points listed below and do the layout design. − Provide the ground plane as much as possible on the IC mounted face. GND and PGNDx provide the through hole proximal to GND and PGNDx pins of IC, and connect it with GND of internal layer. − Provide the power plane as much as possible to lower impedance of VCC. − Play the most attention to the loop composed of input capacitor (CPVCCx) and SWFET. Input capacitor (CPVCCx) connected with PVCCx should be placed close to the pin as much as possible to make the current loop as small as possible. Also connect the GND pin of the input capacitor with PGNDx. − Output capacitor (CVO3) connected with VO3 should be placed close to the pin as much as possible. Also connect the GND pin of the output capacitor with PGND3. − GND pins of the switching system parts provide the through hole at the proximal place, and connect it with GND of internal layer. − By-pass capacitor (CVREF, CAVCC) connected with VREF and AVCC should be placed close to the pin as much as possible. Also connect the GND pin of the by-pass capacitor with GND of internal layer in the proximal through-hole. − Pull the feedback line to be connected to the INx pin of the IC separately from near the output capacitor pin, whenever possible. Consider the line connected with INx pins to keep away from a switching system parts as much as possible because it is sensitive to the noise. − There is leaked magnetic flux around the inductor or backside of place equipped with inductor. Line and parts sensitive to noise should be considered to be placed away from the inductor (or backside of place equipped with inductor). Switching system parts: Input capacitor(CPVCCx), Inductor(L), Output capacitor(CVOx) Note: − x: Each channel number Figure 30-1 Layout Example Layout example of switching components 1 Layout example of IC CPVCC1A GND PGNDx CPVCCx PVCC1B PGND1B PVCC1A PGND1A CPVCC1B CVREF VREF L Through Hole AVCC CAVCC CVOx GND PVCCx To the LXx pin Output voltage VOx feedback (Top View) Layout example of switching components 2 EP(Exposed Pad) 1pin Surface Layer CPVCC3 PGND2 PVCC2 PVCC3 PGND3 CVO3 Output voltage VO3 feedback VO3 CPVCC2 Inner Layer December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL CVO3 To the LX3-2 pin GND L To the LX3-1 pin PGND3 PVCC3 CPVCC3 GND 65 D a t a S h e e t 31. Package Dimensions 66 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014 D a t a S h e e t 32. Major Changes Page Section Change Results Revision 0.1 - - Initial release - Preliminary → Full production Revision 1.0 50 26. Measurement Circuit for Characteristics of General Operation 63 28. Ordering Information December 26, 2014, S6AP412A_DS405-00018-1v0-E CONFIDENTIAL Revised the Parts number of Component list 1278AS-H-1R0M → 1276AS-H-1R0M Revised the Part number of Ordering Information 67 D a t a S h e e t Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. ® ® ® TM Copyright © 2014 Spansion All rights reserved. Spansion , the Spansion logo, MirrorBit , MirrorBit Eclipse , TM ORNAND and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 68 CONFIDENTIAL S6AP412A_DS405-00018-1v0-E, December 26, 2014