EL5171, EL5371 ® Data Sheet October 30, 2006 FN7307.6 250MHz Differential Twisted-Pair Drivers Features The EL5171 and EL5371 are single and triple bandwidth amplifiers with an output in differential form. They are primarily targeted for applications such as driving twistedpair lines in component video applications. The input signal is single-ended and the outputs are always differential. • Fully differential outputs and feedback On the EL5171 and EL5371, two feedback inputs provide the user with the ability to set the gain of each device (stable at minimum gain of one). For a fixed gain of two, please see EL5170 and EL5370. • Low distortion at 5MHz The output common mode level for each channel is set by the associated VREF pin, which have a -3dB bandwidth of over 50MHz. Generally, these pins are grounded but can be tied to any voltage reference. • Low power - 8mA per channel All outputs are short circuit protected to withstand temporary overload condition. • Twisted-pair driver The EL5171 and EL5371 are specified for operation over the full -40°C to +85°C temperature range. • VGA over twisted-pair • Input range ±2.3V typ. • 250MHz 3dB bandwidth • 800V/µs slew rate • Single 5V or dual ±5V supplies • 90mA maximum output current • Pb-free plus anneal available (RoHS compliant) Applications • Differential line driver • ADSL/HDSL driver Ordering Information PART NUMBER PART MARKING • Single ended to differential amplification TAPE & REEL PACKAGE PKG. DWG. # EL5171IS 5171IS - 8 Ld SO MDP0027 EL5171IS-T7 5171IS 7” 8 Ld SO MDP0027 EL5171IS-T13 5171IS 13” 8 Ld SO MDP0027 EL5171ISZ (See Note) 5171ISZ - 8 Ld SO (Pb-free) MDP0027 EL5171ISZ-T7 (See Note) 5171ISZ 8 Ld SO (Pb-free) MDP0027 8 Ld SO (Pb-free) MDP0027 EL5171ISZ-T13 5171ISZ (See Note) 7” 13” - 28 Ld QSOP MDP0040 EL5371IU-T7 5371IU 7” 28 Ld QSOP MDP0040 EL5371IU-T13 5371IU 13” 28 Ld QSOP MDP0040 EL5371IUZ (See Note) 5371IUZ - 28 Ld QSOP (Pb-free) MDP0040 EL5371IUZ-T7 (See Note) 5371IUZ 7” 28 Ld QSOP (Pb-free) MDP0040 28 Ld QSOP (Pb-free) MDP0040 IN+ 2 REF 3 8 OUT+ + - NC 1 7 VS- INP1 2 6 VS+ INN1 3 5 OUT- REF1 4 28 OUT1 + - 27 FBP1 26 FBN1 25 OUT1B NC 5 24 VSP INP2 6 23 VSN INN2 7 22 OUT2 REF2 8 NC 9 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 EL5371 (28 LD QSOP) TOP VIEW EL5171 (8 LD SO) TOP VIEW FBN 4 5371IU 13” Pinouts FBP 1 EL5371IU EL5371IUZ-T13 5371IUZ (See Note) • Transmission of analog signals in a noisy environment + - 21 FBP2 20 FBN2 INP3 10 19 OUT2B INN3 11 18 OUT3 REF3 12 NC 13 EN 14 + - 17 FBP3 16 FBN3 15 OUT3B CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5171, EL5371 Absolute Maximum Ratings (TA = +25°C) Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA VS+ = +5V, VS- = -5V, TA = 25°C, VIN = 0V, RLD = 1kΩ, RF = 0, RG = OPEN, CLD = 2.7pF, Unless Otherwise Electrical Specifications Specified PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE BW -3dB Bandwidth AV = 1, CLD = 2.7pF 250 MHz AV = 2, RF = 500, CLD = 2.7pF 60 MHz AV = 10, RF = 500, CLD = 2.7pF 10 MHz 50 MHz BW ±0.1dB Bandwidth AV = 1, CLD = 2.7pF SR Slew Rate (EL5171) VOUT = 3VP-P, 20% to 80% 600 800 1000 V/µs Slew Rate (EL5371) VOUT = 3VP-P, 20% to 80% 540 700 1000 V/µs TSTL Settling Time to 0.1% VOUT = 2VP-P TOVR GBWP 10 ns Output Overdrive Recovery Time 20 ns Gain Bandwidth Product 100 MHz AV =1, CLD = 2.7pF 50 MHz VREFBW (-3dB) VREF -3dB Bandwidth VREFSR+ VREF Slew Rate - Rise VOUT = 2VP-P, 20% to 80% 90 V/µs VREFSR- VREF Slew Rate - Fall VOUT = 2VP-P, 20% to 80% 50 V/µs VN Input Voltage Noise at 10kHz 26 nV/√Hz IN Input Current Noise at 10kHz 2 pA/√Hz HD2 Second Harmonic Distortion VOUT = 2VP-P, 5MHz -94 dBc VOUT = 2VP-P, 20MHz -94 dBc VOUT = 2VP-P, 5MHz -77 dBc VOUT = 2VP-P, 20MHz -75 dBc HD3 Third Harmonic Distortion dG Differential Gain at 3.58MHz RL = 300Ω, AV = 2 0.1 % dθ Differential Phase at 3.58MHz RL = 300Ω, AV = 2 0.5 ° eS Channel Separation at f = 1MHz 90 dB INPUT CHARACTERISTICS VOS Input Referred Offset Voltage IIN Input Bias Current (VIN+, VIN-) IREF Input Bias Current (VREF) RIN Differential Input Resistance CIN Differential Input Capacitance DMIR Differential Mode Input Range CMIR+ Common Mode Positive Input Range at VIN+, VIN- CMIR- Common Mode Negative Input Range at VIN+, VIN- Tested only for EL5371 VREFIN + Positive Reference Input Voltage Range (EL5371) 2 Tested only for EL5371 VIN+ = VIN- = 0V ±1.5 ±25 mV -14 -6 -3 µA 0.5 1.3 4 µA 300 kΩ 1 pF ±2.1 ±2.3 3.1 3.4 -4.5 3.5 ±3.8 ±2.5 V V -4.2 V V FN7307.6 October 30, 2006 EL5171, EL5371 VS+ = +5V, VS- = -5V, TA = 25°C, VIN = 0V, RLD = 1kΩ, RF = 0, RG = OPEN, CLD = 2.7pF, Unless Otherwise Electrical Specifications Specified (Continued) PARAMETER DESCRIPTION CONDITIONS VREFIN - Negative Reference Input Voltage Range (EL5371) VREFOS Output Offset Relative to VREF (EL5371) CMRR Input Common Mode Rejection Ratio (EL5371) VIN = ±2.5V Gain Gain Accuracy MIN VIN+ = VIN- = 0V TYP MAX UNIT -3.3 -3 V ±60 ±100 mV 70 82 dB VIN = 1 (EL5171) 0.981 0.996 1.011 V VIN = 1 (EL5371) 0.978 0.993 1.008 V OUTPUT CHARACTERISTICS VOUT Output Voltage Swing RL = 500Ω to GND (EL5171) RL = 500Ω to GND (EL5371) IOUT(Max) ROUT Maximum Output Current ±3.6 ±3.4 V ±3.9 V RL = 10Ω, VIN = ±3.24 (EL5171) ±70 ±90 ±120 mA RL = 10Ω, VIN = ±3.24 (EL5371) ±50 ±70 ±90 mA Output Impedance mΩ 130 SUPPLY VSUPPLY Supply Operating Range IS(ON) Power Supply Current - Per Channel IS(OFF)+ Positive Power Supply Current - Disabled (EL5371) EN pin tied to 4.8V IS(OFF)- Negative Power Supply Current - Disabled (EL5371) PSRR Power Supply Rejection Ratio VS+ to VS- 4.75 6.8 11 V 7.5 8.2 mA 1.7 10 µA -200 -120 µA VS from ±4.5V to ±5.5V (EL5171) 70 84 dB VS from ±4.5V to ±5.5V (EL5371) 65 83 dB ENABLE (EL5371 ONLY) tEN Enable Time 215 ns tDS Disable Time 0.95 µs VIH EN Pin Voltage for Power-Up VIL EN Pin Voltage for Shut-Down IIH-EN EN Pin Input Current High At VEN = 5V IIL-EN EN Pin Input Current Low At VEN = 0V VS+ 1.5 VS+ 0.5 V 122 -10 V 130 -8 µA µA Pin Descriptions EL5171 EL5371 PIN NAME 1 17, 21, 27 FBP1, 2, 3 Feedback from non-inverting output 2 2, 6, 10 INP1, 2, 3 Non-inverting inputs 3 3, 7, 11 INN1, 2, 3 Inverting inputs, note that on EL5171, this pin is also the REF pin 4 16, 20, 26 FBN1, 2, 3 Feedback from inverting output 5 15, 19, 25 OUT1B, 2B, 3B 6 24 VSP Positive supply 7 23 VSN Negative supply 8 18, 22, 28 OUT1, 2, 3 1, 5, 9, 13 NC 4, 8, 12 REF1, 2, 3 14 EN 3 PIN FUNCTION Inverting outputs Non-inverting outputs No connects, grounded for best crosstalk performance Reference input, sets common-mode output voltage ENABLE FN7307.6 October 30, 2006 Connection Diagrams EL5171 RF1 CL1 5pF -5V INP 1 FBP OUT 8 2 INP VSN 7 3 REF VSP 6 4 FBN OUTB 5 OUT RLD 1kΩ RG REF 4 RS1 50Ω RS1 50Ω OUTB RF3 +5V CL2 5pF EL5371 +5V 1 NC OUT1 28 2 INP1 FBP1 27 RF RLD1 1kΩ RG INN1 REF1 INP2 INN2 REF2 3 INN1 FBN1 26 4 REF1 OUT1B 25 5 NC VSP 24 6 INP2 VSN 23 7 INN2 OUT2 22 8 REF2 FBP2 21 RF RF RLD2 1kΩ RG 9 NC INP3 INN3 REF3 RSP1 50Ω RSN1 50Ω RSR1 50Ω RSP2 50Ω RSN2 50Ω RSR2 50Ω RSP3 50Ω RSN3 50Ω RSR3 50Ω RF FBN2 20 10 INP3 OUT2B 19 11 INN3 OUT3 18 12 REF3 FBP3 17 13 NC FBn3 16 14 EN OUT3B 15 RF RG RLD3 1kΩ RF FN7307.6 October 30, 2006 -5V ENABLE EL5171, EL5371 INP1 CL1 5pF CL1B 5pF CL2 5pF CL2B 5pF CL3 5pF CL3B 5pF EL5171, EL5371 Typical Performance Curves AV = 1, RLD = 1kΩ, CLD = 2.7pF RLD = 1kΩ, CLD = 2.7pF 4 4 NORMALIZED MAGNITUDE (dB) 3 MAGNITUDE (dB) 2 1 0 VOP-P = 200mV -1 -2 -3 VOP-P = 1VP-P -4 -5 -6 1M 10M 100M 3 2 1 0 -1 AV = 1 -2 AV = 5 -3 -4 AV = 10 -5 -6 1M 1G 10M FIGURE 1. FREQUENCY RESPONSE AV = 1, RLD = 1kΩ 5 3 4 2 3 1 RLD = 1kΩ 0 RLD = 500Ω -1 -2 RLD = 200Ω MAGNITUDE (dB) NORMINALIZED GAIN (dB) AV = 1, CLD = 2.7pF CLD = 56pF CLD = 34pF 2 CLD = 23pF 1 0 -1 CLD = 9pF -2 CLD = 2.7pF -3 -5 -4 -6 1M 10M 100M -5 1M 1G FREQUENCY (Hz) 9 9 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 10 8 RF = 1kΩ RF = 500Ω 5 4 3 RF = 200Ω 8 7 6 RLD = 1kΩ 5 4 RLD = 500Ω 3 2 RLD = 200Ω 1 1 0 1M 1G AV = 2, RF = 1kΩ, CLD = 2.7pF AV = 2, RLD = 1kΩ, CLD = 2.7pF 6 100M FIGURE 4. FREQUENCY RESPONSE vs CLD 10 7 10M FREQUENCY (Hz) FIGURE 3. FREQUENCY RESPONSE vs RLD 2 1G FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS GAIN 4 -4 100M FREQUENCY (Hz) FREQUENCY (Hz) -3 AV = 2 10M 100M FREQUENCY (Hz) FIGURE 5. FREQUENCY RESPONSE 5 400M 0 1M 10M 100M 400M FREQUENCY (Hz) FIGURE 6. FREQUENCY RESPONSE vs RLD FN7307.6 October 30, 2006 EL5171, EL5371 Typical Performance Curves (Continued) 100 5 4 2 IMPEDENCE (Ω) MAGNITUDE (dB) 3 1 0 -1 -2 10 1 -3 -4 -5 100K 1M 10M 0.1 10K 100M 100K FREQUENCY (Hz) 0 100 -10 90 -20 80 100M 70 -30 -40 PSRR- -50 PSRR+ -60 60 50 40 30 -70 20 -80 10 10K 100K 1M 10M 0 100K 100M 1M FREQUENCY (Hz) 10M 100M 1G FREQUENCY (Hz) FIGURE 9. PSRR vs FREQUENCY FIGURE 10. CMRR vs FREQUENCY -30 1K -40 -50 100 GAIN (dB) VOLTAGE NOISE (nV/√Hz), CURRENT NOISE (pA/√Hz) 10M FIGURE 8. OUTPUT IMPEDANCE vs FREQUENCY CMRR (dB) PSRR (dB) FIGURE 7. FREQUENCY RESPONSE - VREF -90 1K 1M FREQUENCY (Hz) EN 10 CH1 <=> CH2, CH2 <=> CH3 -70 -80 100 1K 10K 100K 1M 10M FREQUENCY (Hz) FIGURE 11. VOLTAGE AND CURRENT NOISE vs FREQUENCY 6 CH1 <=> CH3 -90 IN 1 10 -60 -100 100K 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 12. CHANNEL ISOLATION vs FREQUENCY FN7307.6 October 30, 2006 EL5171, EL5371 Typical Performance Curves (Continued) VS = ±5V, AV = 1, RLD = 1kΩ VS = ±5V, AV = 1, RLD = 1kΩ -50 -50 -55 -55 -60 DISTORTION (dB) DISTORTION (dB) -60 -65 -70 HD3 (f = 20MHz) -75 HD3 (f = 5MHz) -80 -85 HD2 (f -90 H z) (f HD2 -95 -100 = 20M 1 1.5 2 2.5 3 = 3.5 z) HD3 (f = 20MH -70 -75 -80 HD2 (f = 5M -85 z) 5M H 4 HD3 (f = 5MHz) -65 HD2 (f = 20MHz) -90 4.5 -95 1 5 Hz) 2 3 4 VOP-P, DM (V) 5 6 7 8 9 10 VOP-P, DM (V) FIGURE 13. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE FIGURE 14. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE VS = ±5V, AV = 2, VOP-P, DM = 2V VS = ±5V, AV = 1, VOP-P, DM = 1V -40 -50 -55 -65 HD -70 -75 3 (f HD 3 = HD -80 -85 20 M 2 (f HD2 (f -90 (f = 5M Hz ) =2 0M Hz DISTORTION (dB) DISTORTION (dB) -60 Hz ) ) = 5M Hz) 200 300 400 500 600 700 800 900 1000 -70 HD2 (f -80 = 20M H z) HD2 (f = 5MHz) -100 200 300 400 500 600 700 800 900 1000 RLD (Ω) RLD (Ω) FIGURE 15. HARMONIC DISTORTION vs RLD FIGURE 16. HARMONIC DISTORTION vs RLD VS = ±5V, RLD = 1kΩ, VOP-P, DM = 1V for AV = 1, VOP-P, DM = 2V for AV = 2 HD3 (AV = 1) -50 DISTORTION (dB) HD3 (f = 5MHz) -60 -90 -95 -100 100 -40 HD3 (f = 20MHz) -50 -60 -70 H (A V D3 =2 ) 2) HD2 (AV = HD2 (AV = 1) 50mV/DIV -80 -90 -100 0 10 20 30 40 50 60 10ns/DIV FREQUENCY (MHz) FIGURE 17. HARMONIC DISTORTION vs FREQUENCY 7 FIGURE 18. SMALL SIGNAL TRANSIENT RESPONSE FN7307.6 October 30, 2006 EL5171, EL5371 Typical Performance Curves (Continued) M = 100ns, CH1 = 500mV/DIV, CH2 = 5V/DIV 0.5V/DIV CH1 CH2 10ns/DIV 100ns/DIV FIGURE 19. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 20. ENABLED RESPONSE M = 200ns, CH1 = 500mV/DIV, CH2 = 5V/DIV JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 POWER DISSIPATION (W) 1.010W CH1 CH2 1 QSOP28 θJA=99°C/W 0.8 625mW 0.6 0.4 SO8 θJA=160°C/W 0.2 0 0 200ns/DIV 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 21. DISABLED RESPONSE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD POWER DISSIPATION (W) 1.4 1.2 1.266W 1 909mW QSOP28 θJA=79°C/W 0.8 0.6 SO8 θJA=110°C/W 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 23. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 8 FN7307.6 October 30, 2006 EL5171, EL5371 Simplified Schematic VS+ R3 R1 R4 R2 R7 IN+ IN- FBP R8 FBN VB1 OUT+ RCD REF RCD R9 VB2 CC R10 OUTCC R5 R6 VS- Description of Operation and Application Information Product Description The EL5171 and EL5371 are wide bandwidth, low power and single ended to differential output amplifiers. The EL5171 is a single channel differential amplifier. Since the IN- pin and REF pin are tired together internally, the EL5171 can be used as a single ended to differential converter. The EL5371 is a triple channel differential amplifier. The EL5371 have a separate IN- pin and REF pin for each channel. It can be used as single/differential ended to differential converter. The EL5171 and EL5371 are internally compensated for closed loop gain of +1 of greater. Connected in gain of 1 and driving a 1kΩ differential load, the EL5171 and EL5371 have a -3dB bandwidth of 250MHz. Driving a 200Ω differential load at gain of 2, the bandwidth is about 30MHz. The EL5371 is available with a power down feature to reduce the power while the amplifier is disabled. Input, Output, and Supply Voltage Range The EL5171 and EL5371 have been designed to operate with a single supply voltage of 5V to 10V or a split supplies with its total voltage from 5V to 10V. The amplifiers have an input common mode voltage range from -4.5V to 3.4V for ±5V supply. The differential mode input range (DMIR) between the two inputs is from -2.3V to +2.3V. The input voltage range at the REF pin is from -3.3V to 3.8V. If the input common mode or differential mode signal is outside the above-specified ranges, it will cause the output signal distorted. Differential and Common Mode Gain Settings For EL5171, since the IN- pin and REF pin are bounded together as the REF pin in an 8 Ld package, the signal at the REF pin is part of the common mode signal and also part of the differential mode signal. For the true balance differential outputs, the REF pin must be tired to the same bias level as the IN+ pin. For a ±5V supply, just tire the REF pin to GND if the IN+ pin is biased at 0V with a 50Ω or 75Ω termination resistor. For a single supply application, if the IN+ is biased to half of the rail, the REF pin should be biased to half of the rail also. The gain setting for EL5171 is: R F1 + R F2⎞ ⎛ V ODM = V IN + × ⎜ 1 + ----------------------------⎟ RG ⎝ ⎠ 2R F⎞ ⎛ V ODM = V IN + × ⎜ 1 + -----------⎟ RG ⎠ ⎝ V OCM = V REF = 0V Where: • VREF = 0V • RF1 = RF2 = RF EL5371 has a separate IN- pin and REF pin. It can be used as a single/differential ended to differential converter. The voltage applied at REF pin can set the output common mode voltage and the gain is one. The output of the EL5171 and EL5371 can swing from -3.9V to +3.9V at 1kΩ differential load at ±5V supply. As the load resistance becomes lower, the output swing is reduced. 9 FN7307.6 October 30, 2006 EL5171, EL5371 Driving Capacitive Loads and Cables The gain setting for EL5371 is: The EL5171 and EL5371 can drive 50pF differential capacitor in parallel with 1kΩ differential load with less than 5dB of peaking at gain of +1. If less peaking is desired in applications, a small series resistor (usually between 5Ω to 50Ω) can be placed in series with each output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than 1, the gain resistor RG can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. R F1 + R F2⎞ ⎛ V ODM = ( V IN + – V IN - ) × ⎜ 1 + ----------------------------⎟ RG ⎝ ⎠ 2R F⎞ ⎛ V ODM = ( V IN + – V IN - ) × ⎜ 1 + -----------⎟ RG ⎠ ⎝ V OCM = V REF Where: • RF1 = RF2 = RF RF1 FBP VIN+ VIN- V O+ IN+ RG VREF IN- When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. Disable/Power-Down (for EL5371 only) REF V O- FBN RF2 FIGURE 24. Choice of Feedback Resistor and Gain Bandwidth Product For applications that require a gain of +1, no feedback resistor is required. Just short the OUT+ pin to FBP pin and OUT- pin to FBN pin. For gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, RF has some maximum value that should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few Pico farad range in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. The bandwidth of the EL5171 and EL5371 depends on the load and the feedback network. RF and RG appear in parallel with the load for gains other than +1. As this combination gets smaller, the bandwidth falls off. Consequently, RF also has a minimum value that should not be exceeded for optimum bandwidth performance. For gain of +1, RF = 0 is optimum. For the gains other than +1, optimum response is obtained with RF between 500Ω to 1kΩ. The EL5171 and EL5371 have a gain bandwidth product of 100MHz for RLD = 1kΩ. For gains ≥5, its bandwidth can be predicted by the following equation: The EL5371 can be disabled and placed its outputs in a high impedance state. The turn off time is about 0.95µs and the turn on time is about 215ns. When disabled, the amplifier's supply current is reduced to 1.7µA for IS+ and 120µA for IStypically, thereby effectively eliminating the power consumption. The amplifier's power down can be controlled by standard CMOS signal levels at the ENABLE pin. The applied logic signal is relative to VS+ pin. Letting the EN pin float or applying a signal that is less than 1.5V below VS+ will enable the amplifier. The amplifier will be disabled when the signal at EN pin is above VS+ - 0.5V. Output Drive Capability The EL5171 and EL5371 have internal short circuit protection. Its typical short circuit current is ±90mA for EL5171 and ±70mA for EL5371. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds ±60mA. This limit is set by the design of the internal metal interconnections. Power Dissipation With the high output drive capability of the EL5171 and EL5371. It is possible to exceed the 135°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX – T AMAX PD MAX = --------------------------------------------Θ JA Gain × BW = 100MHz 10 FN7307.6 October 30, 2006 EL5171, EL5371 Power Supply Bypassing and Printed Circuit Board Layout Where: • TJMAX = Maximum junction temperature • TAMAX = Maximum ambient temperature • θJA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: ΔV O⎞ ⎛ PD = i × ⎜ V S × I SMAX + V S × ------------⎟ R LD ⎠ ⎝ As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as sort as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. Where: • VS = Total supply voltage • ISMAX = Maximum quiescent supply current per channel • ΔVO = Maximum differential output voltage of the application • RLD = Differential load resistance • ILOAD = Load current • i = Number of channels For good AC performance, parasitic capacitance should be kept to minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. By setting the two PDMAX equations equal to each other, we can solve the output current and RLD to avoid the device overheat. Typical Applications RF FBP 50 TWISTED PAIR IN+ IN+ RT RG IN- EL5171/ EL5371 REF 50 IN- ZO = 100Ω FBN EL5172/ EL5372 VO REF RF RFR RGR FIGURE 25. TWISTED PAIR CABLE RECEIVER 11 FN7307.6 October 30, 2006 EL5171, EL5371 As the signal is transmitted through a cable, the high frequency signal will be attenuated. One way to compensate RF this loss is to boost the high frequency gain at the receiver side. Gain (dB) FBP RT 75 VO+ IN+ RGC RG IN- CL REF VO- FBN RF fL 2R F DC Gain = 1 + ----------RG 1 f L ≅ ------------------------2πR G C C 2R F ( HF )Gain = 1 + -------------------------R G || R GC 1 f H ≅ ----------------------------2πR GC C C fH frequency FIGURE 26. TRANSMIT EQUALIZER NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp 12 FN7307.6 October 30, 2006 EL5171, EL5371 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference N 8 14 16 Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 13 FN7307.6 October 30, 2006 EL5171, EL5371 Quarter Size Outline Plastic Packages Family (QSOP) MDP0040 A QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY D (N/2)+1 N E SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES PIN #1 I.D. MARK E1 1 (N/2) A 0.068 0.068 0.068 Max. - A1 0.006 0.006 0.006 ±0.002 - A2 0.056 0.056 0.056 ±0.004 - b 0.010 0.010 0.010 ±0.002 - c 0.008 0.008 0.008 ±0.001 - D 0.193 0.341 0.390 ±0.004 1, 3 E 0.236 0.236 0.236 ±0.008 - E1 0.154 0.154 0.154 ±0.004 2, 3 e 0.025 0.025 0.025 Basic - L 0.025 0.025 0.025 ±0.009 - L1 0.041 0.041 0.041 Basic - N 16 24 28 Reference - B 0.010 C A B e H C SEATING PLANE 0.007 0.004 C b C A B Rev. E 3/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. L1 A 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. c 4. Dimensioning and tolerancing per ASME Y14.5M-1994. SEE DETAIL "X" 0.010 A2 GAUGE PLANE L A1 4°±4° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN7307.6 October 30, 2006