HD-6402 ® Data Sheet October 31, 2005 CMOS Universal Asynchronous Receiver Transmitter (UART) Features • 8.0MHz Operating Frequency (5962-9052502) The HD-6402 is a CMOS UART for interfacing computers or microprocessors to an asynchronous serial data channel. The receiver converts serial start, data, parity and stop bits. The transmitter converts parallel data into serial form and automatically adds start, parity and stop bits. The data word length can be 5, 6, 7 or 8 bits. Parity may be odd or even. Parity checking and generation can be inhibited. The stop bits may be one or two or one and one-half when transmitting 5-bit code. The HD-6402 can be used in a wide range of applications including modems, printers, peripherals and remote data acquisition systems. Utilizing the Intersil advanced scaled SAJI IV CMOS process permits operation clock frequencies up to 8.0MHz (500K Baud). Power requirements, by comparison, are reduced from 300mW to 10mW. Status logic increases flexibility and simplifies the user interface. Pinout HD-6402 (PDIP, CERDIP) TOP VIEW VCC 1 40 TRC NC 2 39 EPE GND 3 38 CLS1 RRD 4 37 CLS2 RBR8 5 36 SBS RBR7 6 35 PI RBR6 7 34 CRL RBR5 8 33 TBR8 RBR4 9 32 TBR7 RBR3 10 31 TBR6 RBR2 11 30 TBR5 RBR1 12 29 TBR4 PE 13 28 TBR3 FE 14 27 TBR2 OE 15 26 TBR1 SFD 16 25 TRO RRC 17 24 TRE DRR 18 23 TBRL DR 19 22 TBRE RRI 20 21 MR 1 FN2956.3 • 2.0MHz Operating Frequency (HD3-6402R) • Low Power CMOS Design • Programmable Word Length, Stop Bits and Parity • Automatic Data Formatting and Status Generation • Compatible with Industry Standard UARTs • Single +5V Power Supply • CMOS/TTL Compatible Inputs • Pb-Free Plus Anneal Available (RoHS Compliant) Ordering Information TEMP PACKAGE RANGE (°C) 2MHz = 125K BAUD 8MHz = 500K BAUD PKG. DWG. # PDIP -40 to +85 HD3-6402R-9 E40.6 PDIP* (Pb-free) -40 to +85 HD3-6402R-9Z (Note) E40.6 CERDIP SMD# -55 to +125 59629052502MQA F40.6 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2001, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HD-6402 Functional Diagram (32) TBR8 (33) (24) TRE (30) (31) (28) (29) (26) (27) TBR1 TRANSMITTER BUFFER REGISTER (22) TBRE † PARITY LOGIC STOP (23) TBRL TRANSMITTER REGISTER TRANSMITTER TIMING AND CONTROL (40) TRC START MULTIPLEXER (25) TRO (38) CLS1 (37) CLS2 (34) CRL (21) MR (36) SBS (16) SFD (39) EPE (35) PI CONTROL REGISTER (20) RRI (17) RRC MULTIPLEXER RECEIVER TIMING AND CONTROL (18) DRR STOP LOGIC (19) DR † START LOGIC RECEIVER REGISTER PARITY LOGIC RECEIVER BUFFER REGISTER 3-STATE (16) SFD (4) RRD BUFFERS † RBR8 † THESE OUTPUTS ARE THREE-STATE † OE (15) † FE (14) † PE (13) † RBR1 (5) (6) (7) (8) (9) (10) (11) (12) Control Definition CONTROL WORD CHARACTER FORMAT CLS 2 CLS 1 PI EPE SBS START BIT DATA BITS PARITY BIT 0 0 0 0 0 1 5 ODD 1 0 0 0 0 1 1 5 ODD 1.5 0 0 0 1 0 1 5 EVEN 1 0 0 0 1 1 1 5 EVEN 1.5 0 0 1 X 0 1 5 NONE 1 0 0 1 X 1 1 5 NONE 1.5 0 1 0 0 0 1 6 ODD 1 0 1 0 0 1 1 6 ODD 2 0 1 0 1 0 1 6 EVEN 1 0 1 0 1 1 1 6 EVEN 2 0 1 1 X 0 1 6 NONE 1 0 1 1 x 1 1 6 NONE 2 1 0 0 0 0 1 7 ODD 1 1 0 0 0 1 1 7 ODD 2 1 0 0 1 0 1 7 EVEN 1 1 0 0 1 1 1 7 EVEN 2 1 0 1 X 0 1 7 NONE 1 1 0 1 x 1 1 7 NONE 2 1 1 0 0 0 1 8 ODD 1 1 1 0 0 1 1 8 ODD 2 1 1 0 1 0 1 8 EVEN 1 1 1 0 1 1 1 8 EVEN 2 1 1 1 X 0 1 8 NONE 1 1 1 1 x 1 1 8 NONE 2 2 STOP BITS HD-6402 Pin Description PIN TYPE SYMBOL VCC † 1 DESCRIPTION Positive Voltage Supply 2 NC 3 GND Ground RRD A high level on RECEIVER REGISTER DISABLE forces the receiver holding out-puts RBR1-RBR8 to high impedance state. 4 I PIN TYPE SYMBOL DESCRIPTION 24 O TRE A high level on TRANSMITTER REGISTER EMPTY indicates completed transmission of a character including stop bits. 25 O TRO Character data, start data and stop bits appear serially at the TRANSMITTER REGISTER OUTPUT. 26 I TRB1 Character data is loaded into the TRANSMITTER BUFFER REGISTER via inputs TBR1-TBR8. For character formats less than 8 bits the TBR8, 7 and 6 inputs are ignored corresponding to their programmed word length. 27 I TBR2 See Pin 26-TBR1. 28 I TBR3 See Pin 26-TBR1. 29 I TBR4 See Pin 26-TBR1. 30 I TBR5 See Pin 26-TBR1. 31 I TBR6 See Pin 26-TBR1. 32 I TBR7 See Pin 26-TBR1. 33 I TBR8 See Pin 26-TBR1. 34 I CRL A high level on CONTROL REGISTER LOAD loads the control register with the control word. The control word is latched on the falling edge of CRL. CRL may be tied high. No Connection 5 O RBR8 The contents of the RECEIVER BUFFER REGISTER appear on these three-state outputs. Word formats less than 8 characters are right justified to RBR1. 6 O RBR7 See Pin 5-RBR8 7 O RBR6 See Pin 5-RBR8 8 O RBR5 See Pin 5-RBR8 9 O RBR4 See Pin 5-RBR8 10 O RBR3 See Pin 5-RBR8 11 O RBR2 See Pin 5-RBR8 12 O RBR1 See Pin 5-RBR8 13 O PE A high level on PARITY ERROR indicates received parity does not match parity programmed by control bits. When parity is inhibited this output is low. 14 O FE A high level on FRAMING ERROR indicates the first stop bit was invalid. 35 I PI A high level on PARITY INHIBIT inhibits parity generation, parity checking and forces PE output low. 15 O OE A high level on OVERRUN ERROR indicates the data received flag was not cleared before the last character was transferred to the receiver buffer register. 36 I SBS A high level on STOP BIT SELECT selects 1.5 stop bits for 5 character format and 2 stop bits for other lengths. 37 I CLS2 16 I SFD A high level on STATUS FLAGS DISABLE forces the outputs PE, FE, OE, DR, TBRE to a high impedance state. These inputs program the CHARACTER LENGTH SELECTED (CLS1 low CLS2 low 5 bits) (CLS1 high CLS2 low 6 bits) (CLS1 low CLS2 high 7 bits) (CLS1 high CLS2 high 8 bits.) 17 I RRC The Receiver register clock is 16X the receiver data rate. 38 I CLS1 See Pin 37-CLS2. 39 I EPE When PI is low, a high level on EVEN PARITY ENABLE generates and checks even parity. A low level selects odd parity. 40 I TRC The TRANSMITTER REGISTER CLOCK is 16X the transmit data rate. 18 I DRR A low level on DATA RECEIVED RESET clears the data received output DR to a low level. 19 O DR A high level on DATA RECEIVED indicates a character has been received and transferred to the receiver buffer register. 20 I RRI Serial data on RECEIVER REGISTER INPUT is clocked into the receiver register. 21 I MR A high level on MASTER RESET clears PE, FE, OE and DR to a low level and sets the transmitter register empty (TRE) to a high level 18 clock cycles after MR falling edge. MR does not clear the receiver buffer register. This input must be pulsed at least once after power up. The HD-6402 must be master reset after power up. The reset pulse should meet VIH and tMR. Wait 18 clock cycles after the falling edge of MR before beginning operation. 22 O TBRE A high level on TRANSMITTER BUFFER REGISTER EMPTY indicates the transmitter buffer register has transferred its data to the transmitter register and is ready for new data. 23 I TBRL A low level on TRANSMITTER BUFFER REGISTER LOAD transfers data from inputs TBR1TBR8 into the transmitter buffer register. A low to high transition on TBRL initiates data transfer to the transmitter register. If busy, transfer is automatically delayed so that the two characters are transmitted end to end. 3 † A 0.1µF decoupling capacitor from the VCC pin to the GND is recommended. HD-6402 9 8 7 6 5 4 3 2 1 32 33 34 35 36 37 38 39 40 10 11 12 13 14 15 16 17 18 19 20 HD-6402 31 30 29 28 27 26 25 24 23 22 21 Transmitter Operation The rising edge of TBRL clears Transmitter Buffer Register Empty (TBRE). 0 to 1 Clock cycles later, data is transferred to the transmitter register, the Transmitter Register Empty (TRE) pin goes to a low state, TBRE is set high and serial data information is transmitted. The output data is clocked by Transmitter Register Clock (TRC) at a clock rate 16 times the data rate. A second low level pulse on TBRL loads data into the Transmitter Buffer Register (C). Data transfer to the transmitter register is delayed until transmission of the current data is complete (D). Data is automatically transferred to the transmitter register and transmission of that character begins one clock cycle later. The transmitter section accepts parallel data, formats the data and transmits the data in serial form on the Transmitter Register Output (TRO) terminal (See serial data format). Data is loaded from the inputs TBR1-TBR8 into the Transmitter Buffer Register by applying a logic low on the Transmitter Buffer Register Load (TBRL) input (A). Valid data must be present at least tset prior to and thold following the rising edge of TBRL. If words less than 8 bits are used, only the least significant bits are transmitted. The character is right justified, so the least significant bit corresponds to TBR1 (B). 1 TBRL TBRE 1/2 CLOCK 0 TO 1 CLOCK TRE DATA TRO A B C D END OF LAST STOP BIT FIGURE 1. TRANSMITTER TIMING (NOT TO SCALE) Receiver Operation Data is received in serial form at the Receiver Register Input (RRI). When no data is being received, RRI must remain high. The data is clocked through the Receiver Register Clock (RRC). The clock rate is 16 times the data rate. A low level on Data Received Reset (DRR) clears the Data Receiver (DR) line (A). During the first stop bit data is transferred from the Receiver Register to the Receiver Buffer Register (RBR) (B). If the word is less than 8 bits, the unused most significant bits will be a logic low. The output 4 character is right justified to the least significant bit RBR1. A logic high on Overrun Error (OE) indicates overruns. An overrun occurs when DR has not been cleared before the present character was transferred to the RBR. One clock cycle later DR is reset to a logic high, and Framing Error (FE) is evaluated (C). A logic high on FE indicates an invalid stop bit was received, a framing error. A logic high on Parity Error (PE) indicates a parity error. HD-6402 BEGINNING OF FIRST STOP BIT RRI 7 1/2 CLOCK CYCLES RBR1-8, OE, PE DRR DR FE 1 CLOCK CYCLE A B C FIGURE 2. RECEIVER TIMING (NOT TO SCALE) START BIT 5-8 DATA BITS 1, 11/2 OR 2 STOP BITS LSB MSB † PARITY † IF ENABLED FIGURE 3. SERIAL DATA FORMAT Start Bit Detection The receiver uses a 16X clock timing. The start bit could have occurred as much as one clock cycle before it was detected, as indicated by the shaded portion (A). The center of the start bit is defined as clock count 7 1/2. If the receiver clock is a symmetrical square wave, the center of the start bit will be located within ±1/2 clock cycle, ±1/32 bit or 3.125% giving a receiver margin of 46.875%. The receiver begins searching for the next start bit at the center of the first stop bit. CLOCK COUNT 71/2 DEFINED CENTER OF START BIT START A RRI INPUT 71/2 CLOCK CYCLES 81/2 CLOCK CYCLES FIGURE 4. Interfacing with the HD-6402 TRANSMITTER TBR1 TRO TBR8 RECEIVER RB1 RS232 DRIVER RS232 RECEIVER RRI CONTROL DIGITAL SYSTEM CONTROL HD-6402 HD-6402 CONTROL CONTROL RRI RB1 RS232 RECEIVER RS232 DRIVER RB8 RECEIVER TRO TBR1 TBR8 TRANSMITTER FIGURE 5. TYPICAL SERIAL DATA LINK 5 RB8 DIGITAL SYSTEM HD-6402 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage Applied . . . . . GND -0.5V to VCC +0.5V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . .+300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Typical Derating Factor . . . . . . . . . . . 1mA/MHz Increase in ICCOP Thermal Resistance (Typical) θJA θJC CERDIP Package. . . . . . . . . . . . . . . . 50oC/W 12oC/W PDIP Package*. . . . . . . . . . . . . . . . . . 50oC/W N/A Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1643 Gates *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HD3-6402R-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC DC Electrical Specifications VCC = 5.0V ± 10%, TA = -40oC to +85oC (HD3-6402R-9) LIMITS SYMBOL PARAMETER MIN MAX UNITS CONDITIONS VIH Logical ‘‘1’’ Input Voltage 2.0 - V VCC = 5.5V VIL Logical ‘‘0’’ Input Voltage - 0.8 V VCC = 4.5V -1.0 1.0 µA VIN = GND or VCC, VCC = 5.5V II Input Leakage Current VOH Logical ‘‘1’’ Output Voltage 3.0 VCC -0.4 - V IOH = -2.5mA, VCC = 4.5V IOH = -100µA VOL Logical ‘‘0’’ Output Voltage - 0.4 V IOL = +2.5mA, VCC = 4.5V IO Output Leakage Current -1.0 1.0 µA VO = GND or VCC, VCC = 5.5V ICCSB Standby Supply Current - 100 µA VIN = GND or VCC; VCC = 5.5V, Output Open ICCOP Operating Supply Current (See Note) - 2.0 mA VCC = 5.5V, Clock Freq. = 2MHz, VIN = VCC or GND, Outputs Open NOTE: Guaranteed, but not 100% tested Capacitance TA = +25oC LIMIT PARAMETER Input Capacitance Output Capacitance SYMBOL CONDITIONS TYPICAL UNITS CIN Freq. = 1MHz, all measurements are referenced to device GND 25 pF 25 pF COUT AC Electrical Specifications VCC = 5.0V ± 10%, TA = -40oC to +85oC (HD3-6402R-9) LIMITS HD-6402R SYMBOL PARAMETER LIMITS HD-6402B MIN MAX MIN MAX UNITS (1) fCLOCK Clock Frequency D.C. 2.0 D.C. 8.0 MHz (2) tPW Pulse Widths, CRL, DRR, TBRL 150 - 75 - ns (3) tMR Pulse Width MR 150 - 150 - ns (4) tSET Input Data Setup Time 50 - 20 - ns (5) tHOLD Input Data Hold Time 60 - 20 - ns (6) tEN Output Enable Time - 160 - 35 ns 6 CONDITIONS CL = 50pF See Switching Waveform HD-6402 Switching Waveforms CLS1, CLS2, SBS, PI, EPE TBR1 - TBR8 VALID DATA SFD RRD VALID DATA TBRL STATUS OR RBR1 - RBR8 CRL tHOLD (5) (4) tSET tPW (2) (4) tSET tHOLD (5) tEN (6) tPW (2) FIGURE 6. DATA INPUT CYCLE FIGURE 7. CONTROL REGISTER LOAD CYCLE FIGURE 8. STATUS FLAG OUTPUT ENABLE TIME OR DATA OUTPUT ENABLE TIME A.C. Testing Input, Output Waveform INPUT OUTPUT VIH + 20% VIH VOH 1.5V 1.5V VIL - 50% VIL VOL FIGURE 9. NOTE: A.C. Testing: All input signals must switch between VIL - 50% VIL and VIH + 20% VIH. Input rise and fall times are driven at 1ns/V. Test Circuit OUT CL (SEE NOTE) FIGURE 10. NOTE: Includes stray and jig capacitance, CL = 50pF. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7