NB3N65027 D

NB3N65027
3.3V Programmable 3-PLL Clock
Synthesizer with
6 LVTTL/LVCMOS Outputs w/OE
The NB3N65027 is a LVCMOS PLL−synthesized clock generator.
It accepts a 10 MHz to 27 MHz clock or fundamental mode crystal as
the reference source and drives three independent, low noise
phase−locked loops (PLLs).
Control lines ACSx, BCSx and CCS will select their appropriate
bank output frequencies. ACS1 and BCS1 are two−level
LVTTL/LVCMOS inputs, High and Low. ACS0, BCS0 and CCS are
three−level LVCMOS inputs, High, Mid and Low.
The NB3N65027 has three independent LVTTL/LVCMOS output
banks of two outputs each. Banks A and B offer a 1X and a 1/2X
output. Using a 25 MHz crystal, the selectable output frequencies
range from 16 2/3 MHz to 133 1/3 MHz. A 12.5 MHz crystal offers
from 8 1/3 MHz to 66 2/3 MHz. In addition, the NB3N65027 will
generate a buffered reference LVTTL/LVCMOS output, REFOUT,
10 MHz to 27 MHz. See Tables 2 through 9 for the variety of available
output frequencies. The OE pin, when set LOW, will disable the output
drivers to high impedance.
The NB3N65027 operates from a single +3.3 V supply across the
operating temperature range from −40°C to +85°C, and is offered in a
QSOP−20 RoHS compliant package.
The NB3N65027 provides the optimum combination of low cost,
flexibility, and high performance for Network, PCI and SDRAM
applications.
Features
• 12.5 MHz or 25 MHz Fundamental Crystal or Clock
•
•
•
•
•
•
•
•
Input
Six Output Clocks with Selectable Frequencies
Buffered Crystal Reference Output
SDRAM Frequencies of 67, 83, 100, and 133 MHz
LVCMOS with 25 mA Output Drive Capability at TTL
Levels
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MARKING DIAGRAM
3N65027
AWLYWWG
QSOP20
CASE 492AC
3N65027
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Operating Range: VCC = 3.3 V ±10%
QSOP−20 Package, 150 mil
−40°C to +85°C Ambient Operating Temperature
These Devices are Pb−Free and are RoHS Compliant
VDD
CLKA1
PLLA
ACS1
ACS0
PLLB
BCS1
BCS0
CCS
CLKB1
CLKB2
B2
X1/ICLK
PLLC
CLKC1
Clock
Synthesis
and Control
Circuitry
CLKC2
Buffer /
Oscillator
25 or 12.5 MHz
crystal or clock
X2 CLX2
REFOUT
CLX1
GND
Figure 1. Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 2
CLKA2
B2
1
OE (all outputs)
Publication Order Number:
NB3N65027/D
NB3N65027
ACS0
1
20
BCS1
X2
2
19
BCS0
X1/ICLK
3
18
REFOUT
CLKA1
VDD
4
17
ACS1
5
16
VDD
GND
6
15
OE
CLKC1
7
14
GND
CLKC2
8
13
CLKA2
CLKB2
9
12
NC
CLKB1
10
11
CCS
Figure 2. Pinout: QSOP−20 (Top View)
Table 1. PIN DESCRIPTION (Note 1)
Pin Number
Pin Name
Pin Type
1
ACS0
Tri−Level Input
2
X2
Input
Crystal connection. Connect to a fundamental crystal or leave unconnected for a clock
input.
3
X1/ICLK
Input
Crystal or Clock input connection. If a clock input is used, drive it into X1 and leave X2
unconnected.
4
VDD
Power
5
ACS1
Two−Level Input
Pin Description
A Clock Select 0. Selects outputs on CLKA1 and CLKA2 per table on page 3.
Connect to +3.3 V. Must be the same as pin 16.
A Clock Select 1. Selects outputs on CLKA1 and CLKA2 per table on page 3. Internal
pull−up.
6
GND
Power
Connect to ground.
7
CLKC1
Output
Output Clock C1. Depends on setting of CCS per table on page 3.
8
CLKC2
Output
Output Clock C2. Depends on setting of CCS per table on page 3. Same as CLKC1.
9
CLKB2
Output
Output Clock B2. Depends on setting of BCS1, 0 per table on page 3.
10
CLKB1
Output
Output Clock B1. Depends on setting of BCS1, 0 per table on page 3.
11
CCS
Tri−Level Input
Clock C select pin. Selects outputs on CLKC1 and CLKC2 per table on page 3.
12
NC
−
13
CLKA2
Output
No Connect
Output Clock A2. Depends on setting of ACS1, 0 per table on page 3.
14
GND
Power
Connect to ground.
15
OE
Input
16
VDD
Power
Connect to +3.3 V. Must be the same as pin 4.
17
CLKA1
Output
Output Clock A1. Depends on setting of ACS1, 0 per table on page 3.
18
REFOUT
Output
Buffered reference clock output. Same frequency as crystal or clock input.
19
BCS0
Tri−Level Input
20
BCS1
Two−Level Input
Output enable. Tri−states all outputs when low. Internal pull−up.
B Clock Select 0. Selects outputs on CLKB1 and CLKB2 per table on page 3.
B Clock Select 1. Selects outputs on CLKB1 and CLKB2 per table on page 3. Internal
pull−up.
1. All VDD and GND pins must be externally connected to a power supply for proper operation.
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NB3N65027
FOR A 25 MHz FUNDAMENTAL CRYSTAL OR CLOCK INPUT, THE FOLLOWING FOUR TABLES APPLY:
Table 2. A CLOCKS SELECT TABLE (outputs in
MHz)
Table 4. C Clocks Select Table (outputs in MHz)
CCS
CLKC1
CLKC2
ACS1
ACS0
CLKA1
CLKA2
0
125
125
0
0
100
off (low)
M
Test
Test
0
M
Test
Test
1
75
75
0
1
75
off (low)
1
0
33.3333
16.6667
1
M
Test
Test
Table 5. REFERENCE OUTPUT CLOCK FREQUENCY
(in MHz)
1
1
66.6667
33.3333
REFOUT
25
Table 3. B CLOCKS SELECT TABLE (outputs in
MHz)
BCS1
BCS0
CLKB1
CLKB2
0
0
Test
Test
0
M
66.6667
33.3333
0
1
100
50
1
0
83.3333
41.6667
1
M
Test
Test
1
1
133.3333
66.6667
FOR A 12.5 MHz FUNDAMENTAL CRYSTAL OR CLOCK INPUT, THE FOLLOWING FOUR TABLES APPLY:
Table 6. A CLOCKS SELECT TABLE (outputs in
MHz)
ACS1
ACS0
CLKA1
CLKA2
Table 8. C CLOCKS SELECT TABLE (outputs in
MHz)
CCS
CLKC1
CLKC2
0
0
50
off (low)
0
62.5
62.5
0
M
Test
Test
M
Test
Test
0
1
37.5
off (low)
1
37.5
37.5
1
0
16.6667
8.3333
1
M
Test
Test
1
1
33.3333
16.6667
Table 9. REFERENCE OUTPUT CLOCK FREQUENCY
(in MHz)
REFOUT
12.5
Table 7. B CLOCKS SELECT TABLE (outputs in
MHz)
BCS1
BCS0
CLKB1
CLKB2
0
0
Test
Test
0
M
33.3333
16.6667
0
1
50
25
1
0
41.6667
20.8333
1
M
Test
Test
1
1
66.6667
33.3333
0 = connect directly to GND
M = leave unconnected (automatically self biases to VDD/2)
1 = connect directly to VDD
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NB3N65027
Table 10. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
> 2 kV
> 200 V
BCS1, OE
ACS1
430 kW
120 kW
RPU − Internal Input Pull−up Resistor
ZOUT − Nominal Output Impedance
20 W
Moisture Sensitivity (Note 2)
QSOP−20
Flammability Rating
Oxygen Index: 28 to 34
Level 1
UL 94 V−0 @ 0.125 in
Transistor Count
16700
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 11. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Rating
Unit
VDD
Positive Power Supply
GND = 0 V
4.5
V
VIO
All Inputs and Outputs
GND = 0 V
−0.5 to VDD +0.5
V
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
θJA
Thermal Resistance (Junction−to−Ambient) (Note 3)
θJC
Thermal Resistance (Junction−to−Case) (Note 3)
Tsol
Wave Solder Tempearture − Pb−Free
0 lfpm
1 m/s air flow
3 m/s air flow
v 20 sec
−65 to +150
°C
135 typ
93 typ
78 typ
°C/W
°C/W
°C/W
60 typ
°C/W
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB3N65027
Table 12. DC CHARACTERISTICS VDD = 3.3V $10%, GND = 0 V, TA = −40°C to +85°C
Symbol
Characteristic
Min
Typ
Max
Unit
3.0
3.3
3.6
V
40
60
mA
POWER SUPPLY
VDD
Power Supply Voltage; GND = 0 V
IDD
Power Supply Current for VDD (Inputs and Outputs Open)
OUTPUTS
VOH
Output HIGH Voltage; VDD = 3.3V
VOL
Output LOW Voltage;
IOS
Output Short Circuit Current, Each Output
IOH = −25 mA
IOH = −8mA
2.4
VDD – 0.4
V
IOL = 25 mA
0.8
V
mA
±50
X1/CLK INPUT PIN, ONLY
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VDD / 2 + 1
V
VDD / 2 − 1
V
TRI−LEVEL TYPE INPUTS: ACS0, BCS0, CCS
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VDD – 0.5
V
0.5
V
TWO−LEVEL TYPE INPUTS: ACS1, BCS1, OE
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
2.0
V
0.8
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 13. AC CHARACTERISTICS VDD = 3.3V $10%, GND = 0 V, TA = −40°C to +85°C
Symbol
Characteristic
Min
Typ
Max
Unit
fIN
Input Frequency, Crystal or Clock
10
12.5 or 25
27
MHz
tDC
Output Clock Duty Cycle at VDD/2, 15 pF Load
40
50
60
%
0
ppm
1.5
ns
Frequency Error, all clocks, 15 pF Load
tor,, tof
Output Rise/Fall Times; 0.8 V to 2.0 V, 15 pF Load
Absolute Jitter, short−term; variation from mean, 15 pF Load
$120
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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NB3N65027
External Components
Where:
CL = Crystal Spec Load Capacitance
CL1 = X1 Pin Total Load Capacitance
CL2 = X2 Pin Total Load Capacitance
2. If CL = 18 pF, then CL1 = CL2 = 2CL, or 36 pF.
Stray capacitance, CLS1 and CLS2, must be considered and
subtracted from each total load capacitance, CL1 and CL2.
Furthermore:
CL1 = CLX1 + CLS1
CL2 = CLX2 + CLS2
Where:
CLX1 = Load Capacitor Board Component for CL1
CLX2 = Load Capacitor Board Component for CL2
CLS1 = Stray Load Capacitance at X1
CLS2 = Stray Load Capacitance at X2
As an example, for 4 pF of stray capacitance, CLS1 = CLS2
= 4 pF, then, Board Component Capacitors CLX1 = CLX2 =
2CL – CLS(1or2), or 36 pF – 4 pF = 32 pF.
The NB3N65027 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
Decoupling capacitors of 0.01 mF must be connected
between each VDD and GND (pins 4 and 6, pins 16 and 14),
as close to the device as possible. For optimum device
performance, the decoupling capacitor should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50 W trace (a commonly used trace
impedance), place a 33 W resistor in series with the clock
line as close to the clock output pin as possible. The nominal
impedance of the clock output is 20 W.
Crystal Information
The crystal used should be a fundamental mode (do not
use third overtone), parallel resonant. Crystal load
capacitors should be connected from pins X1 to ground and
X2 to ground to optimize the frequency accuracy, See
Figure 1.
A crystal in parallel resonance will require the spec CL as
a balanced loading for each side of the crystal, so CL is
distributed in two equal series load caps, CL1 and CL2. All
stray and additional capacitance must be subtracted from
this total loading.
1. Crystal load capacitance, CL, is:
CL +
ǒ
C L1 @ C L2
Table 14. RECOMMENDED CRYSTAL PARAMETERS
Parameter
Value
Crystal Cut
Fundamental AT Cut
Resonance
Parallel Resonance
Load Capacitance
18 pF
Operating Range
−40 to +85°C
Shunt Capacitance
5 pF Max
Equivalent Series Resistance (ESR)
Correlation Drive Level
Ǔ
50 W Max
1.0 mW Max
C L1 ) C L2
ORDERING INFORMATION
Package
Shipping†
NB3N65027DTG
QSOP20
(Pb−Free)
55 Units / Rail
NB3N65027DTR2G
QSOP20
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB3N65027
PACKAGE DIMENSIONS
QSOP20
CASE 492AC−01
ISSUE O
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH,
PROTRUSIONS, OR GATE BURRS SHALL NOT EX­
CEED 0.005 PER SIDE. DIMENSION E1 DOES NOT
INCLUDE INTERLEAD FLASH OR PROTRUSION. IN­
TERLEAD FLASH OR PROTRUSION SHALL NOT EX­
CEED 0.005 PER SIDE. D AND E1 ARE DETERMINED
AT DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
0.004 C D
D
20
A
L2
D
11
GAUGE
PLANE
SEATING
PLANE
E
E1
C
L
C
DETAIL A
2X
2X 10 TIPS
0.004 C D
1
10
20X
e
B
b
0.007
0.004 C
M
C A-B D
A2
0.004 C
20X
0.008 C D
A1
C
h x 45 _
H
A
SEATING
PLANE
DETAIL A
M
DIM
A
A1
A2
b
c
D
E
E1
e
h
L
L2
M
INCHES
MIN
MAX
---0.069
0.004
0.010
0.049
---0.008
0.012
0.004
0.010
0.341 BSC
0.236 BSC
0.154 BSC
0.025 BSC
0.010
0.020
0.016
0.050
0.010 BSC
0_
8_
MILLIMETERS
MIN
MAX
---1.75
0.10
0.25
1.24
---0.20
0.30
0.10
0.25
8.66 BSC
5.99 BSC
3.91 BSC
0.635 BSC
0.25
0.51
0.41
1.27
0.25 BSC
0_
8_
SOLDERING FOOTPRINT
20X
20X
0.42
1.12
20
11
6.40
1
10
0.635
PITCH
DIMENSIONS: MILLIMETERS
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
NB3N65027/D