CDP1854A/3, CDP1854AC/3 TM High Reliability CMOS Programmable Universal Asynchronous Receiver/Transmitter (UART) March 1997 Features Description • Two Operating Modes - Mode 0 - Functionally Compatible with Industry Types Such as the TR1602A and CDP6402 - Mode 1 - Interfaces Directly with CDP1800 Series Microprocessors without Additional Components The CDP1854A/3 and CDP1854AC/3 are high reliability silicon gate CMOS Universal Asynchronous Receiver/Transmitter (UART) circuits. They are designed to provide the necessary formatting and control for interfacing between serial and parallel data. For example, these UARTs can be used to interface between a peripheral or terminal with serial I/O ports and the 8-bit CDP1800-series microprocessor parallel data bus system. The CDP1854A/3 is capable of full duplex operation, i.e., simultaneous conversion of serial input data to parallel output data and parallel input data to serial output data. • Full or Half-Duplex Operation • Parity, Framing, and Overrun Error Detection • Fully Programmable with Externally Selectable Word Length (5-8 Bits), Parity Inhibit, Even/Odd Parity, and 1, 1-1/2, or 2 Stop Bits Ordering Information PACKAGE TEMP. RANGE 5V/200K BAUD 10V/400K BAUD PKG. NO. -55oC to +125oC CDP1854ACD3 CDP1854ACD3 D40.6 SBDIP The CDP1854A/3 UART can be programmed to operate in one of two modes by using the mode control input. When the mode input is high (MODE = 1), the CDP1854A/3 is directly compatible with the CDP1800 series microprocessor system without additional interface circuitry. When the mode input is low (MODE = 0), the device is functionally compatible with industry standard UARTs such as the TR1602A and CDP6402. It is also pin compatible with these types, except that pin 2 is used for the mode control input. The CDP1854A/3 and the CDP1854AC/3 are functionally identical. The CDP1854A/3 has a recommended operating voltage range of 4V to 10.5V, and the CDP1854AC/3 has a recommended operating voltage range of 4V to 6.5V. Pinouts CDP1854A/3, CDP1854AC/3 (SBDIP) (MODE 0) TOP VIEW VDD 1 MODE (VSS) 2 40 T CLOCK 39 EPE CDP1854A/3, CDP1854AC/3 (SBDIP) (MODE 1) TOP VIEW 40 T CLOCK VDD 1 39 CTS MODE (VDD) 2 VSS 3 38 WLS 1 VSS 3 38 ES RRD 4 37 WLS 2 CS2 4 37 PS1 R BUS 7 5 36 SBS R BUS 7 5 36 NC R BUS 6 6 35 PI R BUS 6 6 35 CS3 R BUS 5 7 34 CRL R BUS 5 7 34 RD/WR R BUS 4 8 33 T BUS 7 R BUS 4 8 33 T BUS 7 R BUS 3 9 32 T BUS 6 R BUS 3 9 32 T BUS 6 R BUS 2 10 31 T BUS 5 R BUS 2 10 31 T BUS 5 R BUS 1 11 30 T BUS 4 R BUS 1 11 30 T BUS 4 R BUS 0 12 29 T BUS 3 R BUS 0 12 29 T BUS 3 PE 13 28 T BUS 2 INT 13 28 T BUS 2 FE 14 27 T BUS 1 FE 14 27 T BUS 1 OE 15 26 T BUS 0 PE/OE 15 26 T BUS 0 SFD 16 25 SD0 RSEL 16 25 SD0 R CLOCK 17 24 TSRE R CLOCK 17 24 RTS DAR 18 23 THRL TPB 18 23 CS1 DA 19 22 THRE DA 19 SDI 20 21 MR 22 THRE SDI 20 21 CLEAR NC = NO CONNECT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1 File Number 1715.2 CDP1854A/3, CDP1854AC/3 Absolute Maximum Ratings Thermal Information DC Supply-Voltage Range, (VDD) (All voltages referenced to VSS terminal) CDP1854A/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +11V CDP1854AC/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5 to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Device Dissipation Per Output Transistor For TA = Full Package-Temperature Range . . . . . . . . . . . 100mW Operating-Temperature Range (TA) Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) SBDIP Package. . . . . . . . . . . . . . . . . . 55 15 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150oC Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC Maximum Lead Temperature (Soldering 10s) At Distance 1/16 ±1/32 inch (1.59 ±0.79mm) . . . . . . . . . . +265oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Static Electrical Specifications CONDITIONS LIMITS -55oC, +25oC VIN (V) VDD (V) MIN MAX MIN MAX UNITS - 0, 5 5 - 500 - 1000 µA - 0, 10 10 - 500 - 1000 µA 0.4 0, 5 5 0.75 - 0.5 - mA 0.5 0, 10 10 1.80 - 1.2 - mA 4.6 0, 5 5 - -0.5 - -0.35 mA 9.5 0, 10 10 - -1.0 - -0.70 mA - 0, 5 5 - 0.1 - 0.2 V - 0, 10 10 - 0.1 - 0.2 V - 0, 5 5 4.9 - 4.9 - V - 0, 10 10 9.9 - 9.8 - V 0.5, 4.5 - 5 - 1.5 - 1.5 V 0.5, 9.5 - 10 - 3 - 3 V 0.5, 4.5 - 5 3.5 - 3.5 - V 0.5, 9.5 - 10 7 - 7 - V - 0, 5 5 - ±1 - ±5 µA - 0, 10 10 - ±1 - ±5 µA 0, 5 0, 5 5 - ±1 - ±10 µA 0, 10 0, 10 10 - ±1 - ±10 µA CIN - - - - 10 - 10 pF COUT - - - - 15 - 15 pF PARAMETER Quiescent Device Current Output Low Drive (Sink) Current Output High Drive (Source) Current Output Voltage Low-Level (Note 1) Output Voltage High Level (Note 1) Input Low Voltage Input High Voltage Input Leakage Current Three-State Output Leakage Current Input Capacitance (Note 1) Output Capacitance (Note 1) +125oC VO (V) IDD IOL IOH VOL VOH VIL VIH IIN IOUT NOTE: 1. Guaranteed but not tested. 2 Specifications CDP1854A/3, CDP1854AC/3 Operating Conditions At TA = Full Package-Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: CONDITIONS LIMITS -55oC, +25oC +125oC VDD (V) MIN MAX MIN MAX UNITS DC Operating Voltage Range - 4 10.5 4 6.5 V Input Voltage Range - VSS VDD VSS VDD V Baud Rate (Receive or Transmit) 5 - 250 - 215 K bits/s 10 - 520 - 430 K bits/s PARAMETER Dynamic Electrical Specifications t R, t F = 15ns, VIH = VDD , VIL = VSS , CL = 100pF, (See Figure 1) LIMITS -55oC, +25oC PARAMETER +125oC VDD (V) MIN MAX MIN MAX UNITS 5 240 - 280 - ns 10 120 - 145 - ns 5 105 - 125 - ns 10 55 - 65 - ns 5 135 - 155 - ns 10 65 - 80 - ns 5 125 - 165 - ns 10 70 - 80 - ns 5 - 425 - 485 ns 10 - 205 - 235 ns 5 - 315 - 380 ns 10 - 155 - 185 ns 5 - 335 - 390 ns 10 - 160 - 190 ns TRANSMITTER TIMING - MODE 1 Clock Period Pulse Width tCC tCL Clock Low Level Clock High Level TPB Propagation Delay Time tCH tTT tCD Clock to Data Start Bit TPB to THRE Clock to THRE tTTH tCTH 3 CDP1854A/3, CDP1854AC/3 Dynamic Electrical Specifications t R, t F = 15ns, VIH = VDD , VIL = VSS , CL = 100pF, (See Figure 2) LIMITS -55oC, +25oC PARAMETER +125oC VDD (V) MIN MAX MIN MAX UNITS 5 240 - 280 - ns 10 120 - 145 - ns 5 105 - 125 - ns 10 55 - 65 - ns 5 135 - 155 - ns 10 65 - 80 - ns 5 125 - 165 - ns 10 70 - 80 - ns 5 105 - 120 - ns 10 65 - 70 - ns 5 - 295 - 340 ns 10 - 150 - 170 ns 5 - 305 - 355 ns 10 - 150 - 170 ns 5 - 305 - 330 ns 10 - 150 - 175 ns 5 - 305 - 330 ns 10 - 150 - 175 ns 5 - 280 - 330 ns 10 - 145 - 165 ns RECEIVER TIMING - MODE 1 Clock Period tCC Pulse Width Clock Low Level Clock High Level TPB tCL tCH tTT Setup Time Data Start Bit to Clock tDC Propagation Delay Time TPB to DATA AVAILABLE Clock to DATA AVAILABLE Clock to Overrun Error Clock to Parity Error Clock to Framing Error tTDA tCDA tCOE tCPE tCFE 4 CDP1854A/3, CDP1854AC/3 TRANSMITTER SHIFT REGISTER LOADED (NOTE 2) TRANSMITTER HOLDING REGISTER LOADED (NOTE 1) tCC tCH T CLOCK 1 tCL 2 3 4 5 6 7 14 15 16 1 2 4 3 tCD WRITE (TPB) (NOTE 3) tTT tCTH tTTH THRE tCD 1ST DATA BIT SDO NOTES: 1. The holding register is loaded on the trailing edge of TPB. 2. The transmitter shift register, if empty, is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + tTC after the trailing edge of TPB and transmission of a start bit occurs 1/2 clock period + tCD later. 3. Write is the overlap of TPB, CS1, and CS3 = 1 and CS3, RD/WR = 0 FIGURE 1. TRANSMITTER TIMING DIAGRAM - MODE 1 CLOCK 7 1/2 SAMPLE tCC tCH R CLOCK CLOCK 7 1/2 LOAD HOLDING REGISTER tCL 1 2 3 4 5 6 7 16 1 2 3 4 5 6 7 8 9 tDC (NOTE 1) START BIT SDI PARITY STOP BIT 1 tCDA tTDA DA READ (NOTE 2) tTT TPB tCOE OE (NOTE 3) tCPE PE (NOTE 3) tCFE FE NOTES: 1. If a start bit occurs at a time less than tDC before a high-to-low transition of the clock, the start bit may not be recognized until the next high-to-low transition of the clock. The start bit may be completely asynchronous with the clock. 2. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0. If a pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding register, the OE signal will come true. 3. OE and PE share terminal 15 and are also available as two separate bits in the status register. FIGURE 2. MODE 1 RECEIVER TIMING DIAGRAM 5 CDP1854A/3, CDP1854AC/3 Dynamic Electrical Specifications t R, t F = 15ns, VIH = VDD , VIL = VSS , CL = 100pF, (See Figure 3) LIMITS -55oC, +25oC PARAMETER +125oC VDD (V) MIN MAX MIN MAX UNITS 5 125 - 165 - ns 10 70 - 80 - ns 5 20 - 10 - ns 10 25 - 25 - ns 5 65 - 75 - ns 10 45 - 50 - ns 5 -10 - -20 - ns 10 5 - 5 - ns 5 95 - 105 - ns 10 55 - 55 - ns CPU INTERFACE - WRITE TIMING - MODE 1 Pulse Width TPB tTT Setup Time RSEL to Write Data to Write tRSW tDW Hold Time RSEL after Write Data after Write tWRS tWD tTT TPB (NOTE 1) tWRS tRSW RSEL tDW T BUS 0T BUS 7 CS3, CS1 (NOTE 1) RD/WR, CS2 (NOTE 1) NOTE: 1. Write is the overlap of TPB, CS1, CS3 = 1 and CS2, RD/WR = 0. FIGURE 3. MODE 1 CPU INTERFACE (WRITE) TIMING DIAGRAM 6 tWD CDP1854A/3, CDP1854AC/3 Dynamic Electrical Specifications t R, t F = 15ns, VIH = VDD , VIL = VSS , CL = 100pF, (See Figure 4) LIMITS -55oC, +25oC PARAMETER +125oC VDD (V) MIN MAX MIN MAX UNITS 5 125 - 165 - ns 10 70 - 80 - ns 5 15 - 0 - ns 10 20 - 10 - ns 5 -10 - -25 - ns 10 5 - 0 - ns 5 - 360 - 420 ns 10 - 165 - 195 ns 5 - 250 - 295 ns 10 - 125 - 145 ns CPU INTERFACE - READ TIMING - MODE 1 Pulse Width TPB tTT Setup Time RSEL to TPB tRST Hold Time RSEL after TPB tTRS Propagation Delay Time Read to Data Valid Time RESEL to Data Valid Time tRDV tRSDV tTT TPB tRST RSEL tRSDV R BUS 0R BUS 7 tRDV RD/WR, CS1, CS3 (NOTE 1) CS2 NOTE: 1. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0. FIGURE 4. MODE 1 CPU INTERFACE (READ) TIMING DIAGRAM 7 tTRS CDP1854A/3, CDP1854AC/3 Dynamic Electrical Specifications t R, t F = 15ns, VIH = VDD , VIL = VSS , CL = 100pF, (See Figure 5) LIMITS PARAMETER -55oC, +25oC +125oC VDD (V) MIN MAX MIN MAX UNITS 5 105 - 125 - ns 10 55 - 65 - ns 5 340 - 385 - ns 10 160 - 175 - ns 5 80 - 85 - ns 10 40 - 60 - ns 5 65 - 65 - ns 10 45 - 45 - ns 5 - 175 - 195 ns 10 - 105 - 115 ns 5 165 - 195 - ns 10 90 - 105 - ns 5 - 185 - 205 ns 10 - 110 - 130 ns 5 165 - 195 - ns 10 90 - 105 - ns INTERFACE TIMING - MODE 0 Pulse Width CRL tCRL MR tMR Setup Time Control Word to CRL tCWC Hold Time Control Word after CRL tCCW Propagation Delay Time SFD High to SOD tSFDH SFD Low to SOD tSFDL RRD High to Receiver Register High Impedance tRRDH RRD Low to Receiver Register Active tRRDL CONTROL INPUT WORD TIMING CONTROL WORD INPUT CONTROL WORD BYTE tCWC tCCW CRL tCRL STATUS OUTPUT TIMING STATUS OUTPUTS tSFDH tSFDL SFD RECEIVER REGISTER DISCONNECT TIMING R BUS 0 R BUS 7 tRRDH tRRDL RRD FIGURE 5. MODE 0 INTERFACE TIMING DIAGRAM 8 CDP1854A/3, CDP1854AC/3 Dynamic Electrical Specifications t R, t F = 15ns, VIH = VDD , VIL = VSS , CL = 100pF, (See Figure 6) LIMITS PARAMETER -55oC, +25oC +125oC VDD (V) MIN MAX MIN MAX UNITS 5 240 - 280 - ns 10 120 - 145 - ns 5 105 - 125 - ns 10 55 - 65 - ns 5 135 - 155 - ns 10 65 - 80 - ns 5 140 - 165 - ns 10 80 - 85 - ns 5 205 - 235 - ns 10 120 - 140 - ns 5 25 - 30 - ns 10 20 - 25 - ns 5 60 - 95 - ns 10 45 - 75 - ns 5 - 435 - 505 ns 10 - 205 - 235 ns 5 - 345 - 420 ns 10 - 175 - 200 ns 5 - 275 - 325 ns 10 - 145 - 165 ns 5 - 345 - 405 ns 10 - 165 - 190 ns TRANSMITTER TIMING - MODE 0 Clock Period tCC Pulse Width Clock Low Level Clock High Level THRL tCL tCH tTHTH Setup Time THRL to Clock Data to THRL tTHC tDT Hold Time Data after THRL tTD Propagation Delay Time Clock to Data Start Bit Clock to THRE THRL to THRE Clock to TSRE tCD tCT tTTHR tTTS 9 CDP1854A/3, CDP1854AC/3 TRANSMITTER HOLDING REGISTER LOADED (NOTE 1) TRANSMITTER SHIFT REGISTER LOADED (NOTE 2) tCC tCH tCL T CLOCK 1 2 3 4 5 6 7 14 15 16 1 2 3 tTHC THRL tTHTH tCD tCD 1ST DATA BIT SDO tTTHR tCT THRE tTTS TSRE tDT T BUS 0 T BUS 7 tTD DATA NOTES: 1. The holding register is loaded on the trailing edge of THRL. 2. The transmitter shift register, if empty, is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + tTHC after the trailing edge of THRL and transmission of a start bit occurs 1/2 clock period + tCD later. FIGURE 6. MODE 0 TRANSMITTER TIMING DIAGRAM CLOCK 7 1/2 SAMPLE tCC tCH R CLOCK CLOCK 7 1/2 LOAD HOLDING REGISTER tCL 1 2 3 4 5 6 7 16 1 2 3 4 5 6 7 8 9 tDC (NOTE 1) SDI START BIT PARITY STOP BIT 1 tCDV R BUS 0 - DATA R BUS 7 DA tDDA tCDA DAR tCOE tDD OE (NOTE 2) tCPE PE tCFE FE NOTES: 1. If a start bit occurs at a time less than tDC before a high-to-low transition of the clock, the start bit may not be recognized until the next high-to-low transition of the clock. The start bit may be completely asynchronous with the clock. 2. If a pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding register, the OE signal will come true. FIGURE 7. MODE 0 RECEIVER TIMING DIAGRAM 10 CDP1854A/3, CDP1854AC/3 Dynamic Electrical Specifications t R, t F = 15ns, VIH = VDD , VIL = VSS , CL = 100pF, (See Figure 7) LIMITS PARAMETER -55oC, +25oC +125oC VDD (V) MIN MAX MIN MAX UNITS 5 240 - 280 - ns 10 120 - 145 - ns 5 105 - 125 - ns 10 55 - 65 - ns 5 135 - 155 - ns 10 65 - 80 - ns 5 75 - 90 - ns 10 45 - 50 - ns 5 105 - 130 - ns 10 65 - 85 - ns 5 - 240 - 280 ns 10 - 130 - 145 ns 5 - 360 - 420 ns 10 - 175 - 195 ns 5 - 320 - 375 ns 10 - 155 - 180 ns 5 - 365 - 415 ns 10 - 170 - 190 ns 5 - 275 - 320 ns 10 - 135 - 155 ns 5 - 270 - 320 ns 10 - 135 - 165 ns RECEIVER TIMING - MODE 0 Clock Period tCC Pulse Width Clock Low Level Clock High Level DATA AVAILABLE RESET tCL tCH tDD Setup Time Data Start Bit to Clock tDC Propagation Delay Time DATA AVAILABLE RESET to Data Available tDDA Clock to Data Valid tCDV Clock to Data Available Clock to Overrun Error Clock to Parity Error Clock to Framing Error tCDA tCOE tCPE tCFE 11 CDP1854A/3, CDP1854AC/3 16 / fCLOCK NEXT DATA WORD 5 - 8 DATA BITS STOP BITS 1, 1-1/2 OR 2 START BIT DATA LSB PARITY BIT DATA MSB FIGURE 8. SERIAL DATA WORD FORMAT Burn-In Circuit VDD VSS 1 40 VDD 2 39 VSS 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 ALL RESISTORS ARE 47kΩ ±20% TYPE VDD TEMPERATURE TIME CDP1854A/3 11 +125oC 160 hrs. CDP1854AC/3 7 +125oC 160 hrs. FIGURE 9. BIAS/STATIC BURN-IN CIRCUIT All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12