HI-546, HI-547, HI-548, HI-549 Data Sheet Single 16 and 8, Differential 8-Channel and 4-Channel CMOS Analog MUXs with Active Overvoltage Protection The HI-546, HI-547, HI-548 and HI-549 are analog multiplexers with active overvoltage protection and guaranteed rON matching. Analog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand constant 70VP-P levels with ±15V supplies. Digital inputs will also sustain continuous faults up to 4V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur. Each input presents 1kΩ of resistance under this condition. These features make the HI-546, HI-547, HI-548 and HI-549 ideal for use in systems where the analog inputs originate from external equipment or separately powered circuitry. All devices are fabricated with 44V Dielectrically Isolated CMOS technology. The HI-546 is a single 16-Channel, the HI-547 is an 8-Channel differential, the HI-548 is a single 8-Channel and the HI-549 is a 4-Channel differential device. If input overvoltage protection is not needed the HI-506/507/508/509 multiplexers are recommended. For further information see Application Notes AN520 and AN521. For MIL-STD-883 compliant parts, request the HI-546/883, HI-547/883, HI-548/883 and HI-549/883 datasheets. 1 June 1999 File Number 3150.2 Features • Analog Overvoltage Protection. . . . . . . . . . . . . . . . . . 70VP-P • No Channel Interaction During Overvoltage • Guaranteed rON Matching • Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . . 44V • Break-Before-Make Switching • Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V • Access Time (Typical) . . . . . . . . . . . . . . . . . . . . . . . 500ns • Standby Power (Typical) . . . . . . . . . . . . . . . . . . . . . 7.5mW Applications • Data Acquisition • Industrial Controls • Telemetry Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. HI1-0546-5 0 to 75 28 Ld CERDIP F28.6 HI1-0546-2 -55 to 125 28 Ld CERDIP F28.6 HI3-0546-5 0 to 75 28 Ld PDIP E28.6 HI4P0546-5 0 to 75 28 Ld PLCC N28.45 HI9P0546-9 -40 to 85 28 Ld SOIC M28.3 HI1-0547-5 0 to 75 28 Ld CERDIP F28.6 HI3-0547-5 0 to 75 28 Ld PDIP E28.6 HI4P0547-5 0 to 75 28 Ld PLCC N28.45 HI9P0547-9 -40 to 85 28 Ld SOIC M28.3 HI1-0548-2 -55 to 125 16 Ld CERDIP F16.3 HI1-0548-5 0 to 75 16 Ld CERDIP F16.3 HI3-0548-5 0 to 75 16 Ld PDIP E16.3 HI4P0548-5 0 to 75 20 Ld PLCC N20.35 HI9P0548-5 0 to 75 16 Ld SOIC M16.15 HI9P0548-9 -40 to 85 16 Ld SOIC M16.15 HI1-0549-2 -55 to 125 16 Ld CERDIP F16.3 HI3-0549-5 0 to 75 16 Ld PDIP E16.3 HI4P0549-5 0 to 75 20 Ld PLCC N20.35 HI9P0549-5 0 to 75 16 Ld SOIC M16.15 HI9P0549-9 -40 to 85 16 Ld SOIC M16.15 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 HI-546, HI-547, HI-548, HI-549 Pinouts HI-546 (CERDIP, PDIP, SOIC) TOP VIEW HI-547 (CERDIP, PDIP, SOIC) TOP VIEW 28 OUT A +VSUPPLY 1 28 OUT +VSUPPLY 1 NC 2 27 -VSUPPLY 27 -VSUPPLY OUT B 2 NC 3 26 IN 8 NC 3 26 IN 8A IN 16 4 25 IN 7 IN 8B 4 25 IN 7A IN 15 5 24 IN 6 IN 7B 5 24 IN 6A IN 14 6 23 IN 5 IN 6B 6 23 IN 5A IN 13 7 22 IN 4 IN 5B 7 22 IN 4A IN 12 8 21 IN 3 IN 4B 8 21 IN 3A IN 11 9 20 IN 2 IN 3B 9 20 IN 2A IN 10 10 19 IN 1 IN 2B 10 19 IN 1A 18 ENABLE IN 1B 11 18 ENABLE IN 9 11 GND 12 17 ADDRESS A0 GND 12 17 ADDRESS A0 VREF 13 16 ADDRESS A1 VREF 13 16 ADDRESS A1 ADDRESS A3 14 15 ADDRESS A2 NC 14 15 ADDRESS A2 NC NC +VSUPPLY OUT -VSUPPLY IN 8 IN 8B NC OUT B +VSUPPLY OUT A -VSUPPLY IN 8A HI-547 (PLCC) TOP VIEW IN 16 HI-546 (PLCC) TOP VIEW 4 3 2 1 28 27 26 4 3 2 1 28 27 26 IN 4B 8 22 IN 4A IN 11 9 21 IN 3 IN 3B 9 21 IN 3A IN 10 10 20 IN 2 IN 2B 10 20 IN 2A IN 9 11 19 IN 1 IN 1B 11 19 IN 1A 12 13 14 15 16 17 18 HI-548 (CERDIP, PDIP, SOIC) TOP VIEW 12 13 14 15 16 17 18 ENABLE 22 IN 4 A0 IN 12 8 A1 23 IN 5A A2 IN 5B 7 NC 23 IN 5 VREF IN 13 7 GND 24 IN 6A ENABLE IN 6B 6 A0 24 IN 6 A1 IN 14 6 A2 25 IN 7A A3 IN 7B 5 GND 25 IN 7 VREF IN 15 5 HI-549 (CERDIP, PDIP, SOIC) TOP VIEW A0 1 16 A1 A0 1 ENABLE 2 15 A2 ENABLE 2 14 GND -VSUPPLY 3 -VSUPPLY 3 16 A1 15 GND 14 +VSUPPLY IN 1 4 13 +VSUPPLY IN 1A 4 13 IN 1B IN 2 5 12 IN 5 IN 2A 5 12 IN 2B IN 3 6 11 IN 6 IN 3A 6 11 IN 3B IN 4 7 10 IN 7 IN 4A 7 10 IN 4B OUT 8 9 IN 8 OUT A 8 2 9 OUT B HI-546, HI-547, HI-548, HI-549 Pinouts (Continued) 10 11 12 13 A1 GND 20 19 18 +VSUPPLY 17 IN 1B 16 NC NC 6 IN 2A 7 15 IN 2B IN 3A 8 14 IN 3B 9 10 11 12 13 IN 4B 9 IN 7 14 IN 6 IN 8 IN 3 8 NC 15 IN 5 OUT IN 2 7 IN 4 16 NC 1 IN 1A 5 17 +V SUPPLY NC 6 2 -VSUPPLY 4 18 GND IN 1 5 3 OUT B -VSUPPLY 4 NC 19 NC 20 A0 A2 1 OUT A A1 2 ENABLE NC 3 IN 4A A0 HI-549 (PLCC) TOP VIEW ENABLE HI-548 (PLCC) TOP VIEW TRUTH TABLE HI-547 (Continued) TRUTH TABLE HI-546 A3 A2 A1 A0 EN “ON” CHANNEL A2 A1 A0 EN “ON” CHANNEL PAIR X X X X L None H L H H 6 L L L L H 1 H H L H 7 L L L H H 2 H H H H 8 L L H L H 3 L L H H H 4 L H L L H 5 L H L H H 6 L H H L H 7 L H H H H 8 H L L L H 9 H L L H H 10 H L H L H 11 H L H H H 12 H H L L H 13 H H L H H 14 H H H L H 15 H H H H H 16 TRUTH TABLE HI-547 A2 A1 A0 EN “ON” CHANNEL PAIR X X X L None L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 3 TRUTH TABLE HI-548 A2 A1 A0 EN “ON” CHANNEL X X X L None L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 TRUTH TABLE HI-549 A1 A0 EN “ON” CHANNEL PAIR X X L None L L H 1 L H H 2 H L H 3 H H H 4 HI-546, HI-547, HI-548, HI-549 Functional Diagrams HI-546 HI-547 OUT 1K IN 1 OUT A 1K IN 1A 1K 1K IN 2 OUT B IN 8A 1K DECODER/ DRIVER IN 1B 1K 1K DECODER/ DRIVER IN 8B IN 16 OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF OVERVOLTAGE CLAMP AND SIGNAL ISOLATION LEVEL SHIFT † DIGITAL INPUT 5V REF LEVEL SHIFT † DIGITAL INPUT † † † † † † † † † VREF A0 A1 A2 EN PROTECTION PROTECTION VREF A0 A1 A2 A3 EN HI-548 HI-549 OUT 1K OUT A 1K IN 1A IN 1 1K 1K OUT B IN 4A IN 2 1K DECODER/ DRIVER IN 1B 1K 1K DECODER/ DRIVER IN 4B IN 8 OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF OVERVOLTAGE CLAMP AND SIGNAL ISOLATION LEVEL SHIFT † DIGITAL INPUT † † † † † DIGITAL INPUT 5V REF LEVEL SHIFT † † † A0 A1 EN PROTECTION PROTECTION A0 4 A1 A2 EN HI-546, HI-547, HI-548, HI-549 Schematic Diagrams ADDRESS DECODER V+ P P P P A0 OR A0 A1 OR A1 P P P N N N N N A2 OR A2 TO P-CHANNEL DEVICE OF THE SWITCH TO N-CHANNEL DEVICE OF THE SWITCH N A3 OR A3 N ENABLE DELETE A3 OR A3 INPUT FOR HI-547, HI-548, HI-549 DELETE A2 OR A2 INPUT FOR HI-549 V- MULTIPLEX SWITCH FROM DECODE OVERVOLTAGE PROTECTION N V+ P R11 1K D6 Q5 D7 D4 D5 N IN N Q6 V- P FROM DECODE 5 OUT HI-546, HI-547, HI-548, HI-549 Schematic Diagrams (Continued) ADDRESS INPUT BUFFER AND LEVEL SHIFTER TTL REFERENCE CIRCUIT V+ R10 R9 Q1 VREF Q4 D3 GND LEVEL SHIFTER V+ OVERVOLTAGE PROTECTION P P P N R2 P P P P R5 V+ D1 LEVEL SHIFTED ADDRESS TO DECODE N N N N R8 N N N V- GND ADD IN 6 P R7 R6 N P R4 R3 D2 R1 200 Ω P V- N HI-546, HI-547, HI-548, HI-549 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +22V V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V Digital Input Voltage (VEN , VA) . . . . . . . . . . . . . (V-) -4V to (V+) +4V Analog Signal (VIN, VOUT). . . . . . . . . . . . . . . (V-) -20V to (V+) +20V or 20mA, Whichever Occurs First Continuous Current, IN or OUT . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, IN or OUT (Pulsed 1ms, 10% Duty Cycle Max) . . 40mA Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) 16 Ld CERDIP Package . . . . . . . . . . . 85 32 28 Ld CERDIP Package . . . . . . . . . . . 55 18 28 Ld PDIP Package . . . . . . . . . . . . . 60 N/A 16 Ld PDIP Package . . . . . . . . . . . . . 90 N/A 28 Ld PLCC Package . . . . . . . . . . . . . 70 N/A 20 Ld PLCC Package . . . . . . . . . . . . . 80 N/A 28 Ld SOIC Package . . . . . . . . . . . . . 75 N/A 16 Ld SOIC Package . . . . . . . . . . . . . 105 N/A Maximum Junction Temperature Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (PLCC, SOIC - Lead Tips Only) Operating Conditions Temperature Ranges HI-546/548/549-2 . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HI-546/547/548/549-5 . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC HI-546/547/548/549-9 . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V; Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section TEST CONDITIONS -2 -5, -9 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS 25 - 0.5 - - 0.5 - µs Full - - 1.0 - - 1.0 µs Break-Before Make Delay, tOPEN 25 25 80 - 25 80 - ns Enable Delay (ON), tON(EN) 25 - 300 500 - 300 - ns Full - - 1000 - - 1000 ns 25 - 300 500 - 300 - ns PARAMETER SWITCHING CHARACTERISTICS Access Time, tA Enable Delay (OFF), tOFF(EN) Full - - 1000 - - 1000 ns To 0.1% 25 - 1.2 - - 1.2 - µs To 0.01% 25 - 3.5 - - 3.5 - µs Note 6 25 50 68 - 50 68 - dB 25 - 10 - - 10 - pF HI-546 25 - 52 - - 52 - pF HI-547 25 - 30 - - 30 - pF HI-548 25 - 25 - - 25 - pF HI-549 25 - 12 - - 12 - pF 25 - 0.1 - - 0.1 - pF Input Low Threshold, TTL Drive, VAL Full - - 0.8 - - 0.8 V Input High Threshold, VAH (Note 8) Full 4.0 - - 4.0 - - V Settling Time Off Isolation Channel Input Capacitance, CS(OFF) Channel Output Capacitance CD(OFF) Input to Output Capacitance, CDS(OFF) DIGITAL INPUT CHARACTERISTICS MOS Drive, VAL (HI-546/547 Only) VREF = 10V 25 - - 0.8 - - 0.8 V MOS Drive, VAH (HI-546/547 Only) VREF = 10V 25 6.0 - - 6.0 - - V Input Leakage Current (High or Low), IA Note 5 Full - - 1.0 - - 1.0 µA 7 HI-546, HI-547, HI-548, HI-549 Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V; Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued) TEST CONDITIONS PARAMETER -2 -5, -9 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS Full -15 - +15 -15 - +15 V 25 - 1.2 1.5 - 1.5 1.8 kΩ Full - 1.5 1.8 - 1.8 2.0 kΩ 25 - - 7.0 - - 7.0 % 25 - 0.03 - - 0.03 - nA Full - - 50 - - 50 nA ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VIN On Resistance, rON Note 2 ∆rON , (Any Two Channels) Off Input Leakage Current, IS(OFF) Off Output Leakage Current, ID(OFF) Note 3 25 - 0.1 - - 0.1 - nA HI-546 Full - - 300 - - 300 nA HI-547 Full - - 200 - - 200 nA HI-548 Full - - 200 - - 200 nA HI-549 Full - - 100 - - 100 nA 25 - 4.0 - - 4.0 - nA Full - - 2.0 - - - µA 25 - 0.1 - - 0.1 - nA HI-546 Full - - 300 - - 300 nA HI-547 Full - - 200 - - 200 nA HI-548 Full - - 200 - - 200 nA HI-549 Full - - 100 - - 100 nA Full - - 50 - - 50 nA Full - 7.5 - - 7.5 - mW ID(OFF) With Input Overvoltage Applied On Channel Leakage Current, ID(ON) Note 3 Note 4 Note 3 Differential Off Output Leakage Current IDIFF (HI-547, HI-549 Only) POWER SUPPLY CHARACTERISTICS Power Dissipation, PD Current, I+ Note 7 Full - 0.5 2.0 - 0.5 2.0 mA Current, I- Note 7 Full - 0.02 1.0 - 0.02 1.0 mA NOTES: ± 2. VOUT = ±10V, IOUT = 100µA. 3. 10nA is the practical lower limit for high speed measurement in the production test environments. 4. Analog Overvoltage = ±33V. 5. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25oC. 6. VEN = 0.8V, RL = 1K, CL = 15pF, VS = 7VRMS , f = 100kHz. 7. VEN , VA = 0V or 4V. 8. To drive from DTL/TTLCircuits, 1kΩ pull-up resistors to +5V supply are recommended. 8 HI-546, HI-547, HI-548, HI-549 Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified 100µA V2 IN OUT VIN rON = V2 100µA FIGURE 1A. ON RESISTANCE TEST CIRCUIT 1.4 1.2 1.1 25oC 1.0 -55oC 0.9 0.8 0.7 0.6 -10 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 -8 -6 -4 -2 0 2 4 6 8 10 5 ANALOG INPUT (V) 6 7 8 9 10 11 12 13 14 SUPPLY VOLTAGE (±V) FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY VOLTAGE FIGURE 1. ON RESISTANCE 100nA LEAKAGE CURRENT 10nA ON LEAKAGE CURRENT ID(ON) OFF OUTPUT CURRENT ID(OFF) +0.8V EN OUT 1nA A ±10V ID(OFF) ± ON RESISTANCE (kΩ) NORMALIZED ON RESISTANCE (REFERRED TO VALUE AT ±15V) 125oC 1.3 10V OFF INPUT LEAKAGE CURRENT IS(OFF) 100pA 10pA 25 50 75 100 TEMPERATURE (oC) 125 FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE 9 FIGURE 2B. ID(OFF) TEST CIRCUIT (NOTE 9) 15 HI-546, HI-547, HI-548, HI-549 Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued) OUT OUT IS(OFF) A +0.8V A EN ± ±10V ID(ON) EN 10V ±10V 10V ± 4V FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 9) FIGURE 2D. ID(ON) TEST CIRCUIT (NOTE 9) NOTE: 10V. (Two measurements per device for ID(OFF): ±10V and ± 9. Two measurements per channel: ±10V and 10V.) ± FIGURE 2. LEAKAGE CURRENTS ANALOG INPUT CURRENT (IIN) 15 5 12 4 9 3 6 2 OUTPUT OFF LEAKAGE CURRENT ID(OFF) 3 1 0 0 15 18 21 24 27 30 33 ANALOG INPUT OVERVOLTAGE (±V) OUTPUT OFF LEAKAGE CURRENT (nA) ANALOG INPUT CURRENT (mA) 18 A IIN A ID(OFF) ±VIN 36 FIGURE 3A. ANALOG INPUT CURRENT AND OUTPUT OFF LEAKAGE CURRENT vs ANALOG INPUT OVER-VOLTAGE FIGURE 3B. TEST CIRCUIT FIGURE 3. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS ±14 -55oC 25oC SWITCH CURRENT (mA) ±12 ±10 125oC ±8 ±6 ±VIN ±4 A ±2 0 0 2 4 6 8 10 12 VOLTAGE ACROSS SWITCH (±V) 14 FIGURE 4A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 4. ON CHANNEL CURRENT 10 FIGURE 4B. TEST CIRCUIT HI-546, HI-547, HI-548, HI-549 Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued) 8 6 V+ IN 1 A3 VSUPPLY = ± 10V 2 A1 IN 2 THRU IN 15 A0 IN 16 EN +4V GND ± 50Ω VA ±10V/±5V HI-546 † A2 VSUPPLY = ± 15V 4 +15V/+10V +ISUPPLY 10V/ 5V OUT V10MΩ A 0 1K 10K 100K 1M 10M TOGGLE FREQUENCY (Hz) ± SUPPLY CURRENT (mA) A 14pF -ISUPPLY -15V/-10V † Similar connection for HI-547/HI-548/HI-549. FIGURE 5A. SUPPLY CURRENT vs TOGGLE FREQUENCY FIGURE 5B. TEST CIRCUIT FIGURE 5. DYNAMIC SUPPLY CURRENT +15V 900 ACCESS TIME (ns) VREF A3 700 A2 50Ω VA 600 A1 V+ IN 1 ±10V IN 2 THRU IN 15 HI-546 † A0 IN 16 ± VREF = OPEN FOR LOGIC HIGH LEVEL < 6V VREF = LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V 800 10V 500 EN +4V GND OUT V- 400 10kΩ 300 3 4 5 6 7 8 9 10 11 LOGIC LEVEL (HIGH) (V) 12 13 14 -15V 15 † Similar connection for HI-547/HI-548/HI-549. FIGURE 6A. ACCESS TIME vs LOGIC LEVEL (HIGH) VAH = 4.0V FIGURE 6B. TEST CIRCUIT VA INPUT 2V/DIV. ADDRESS DRIVE (VA) 50% 0V S1 ON +10V OUTPUT 10% OUTPUT 5V/DIV. -10V S16 ON tA 200ns/DIV. FIGURE 6C. MEASUREMENT POINTS FIGURE 6D. WAVEFORMS FIGURE 6. ACCESS TIME 11 50pF HI-546, HI-547, HI-548, HI-549 Test Circuits and Waveforms A3 TA = 25oC, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued) HI-546 † A2 +5V VAH = 4V IN 1 IN 2 THRU 50Ω VA +4V A1 IN 15 A0 IN 16 EN OUT GND ADDRESS DRIVE (VA) 0V VOUT OUTPUT 50pF 1kΩ 50% 50% tOPEN † Similar connection for HI-547/HI-548/HI-549 FIGURE 7A. TEST CIRCUIT FIGURE 7B. MEASUREMENT POINTS VA INPUT 2V/DIV. S16 ON S1 ON OUTPUT 0.5V/DIV. 100ns/DIV. FIGURE 7C. WAVEFORMS FIGURE 7. BREAK-BEFORE-MAKE DELAY A3 HI-546 † A2 A1 IN 1 +10V IN 2 THRU IN16 ENABLE DRIVE (VA) 0V VOUT 90% OUT EN 50Ω 50% 50% A0 VA VAH = 4V GND 1kΩ OUTPUT 50pF 10% 0V t ON(EN) † Similar connection for HI-547/HI-548/HI-549 FIGURE 8A. TEST CIRCUIT 12 t OFF(EN) FIGURE 8B. MEASUREMENT POINTS HI-546, HI-547, HI-548, HI-549 Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued) ENABLE DRIVE 2V/DIV. DISABLED OUTPUT 2V/DIV. ENABLED (S1 ON) 100ns/DIV. FIGURE 8C. WAVEFORMS FIGURE 8. ENABLE DELAYS 13 HI-546, HI-547, HI-548, HI-549 Die Characteristics DIE DIMENSIONS: PASSIVATION: 83.9 mils x 159 mils Type: Nitride Over Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2kÅ METALLIZATION: Type: CuAl Thickness: 16kÅ ±2kÅ WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 SUBSTRATE POTENTIAL (NOTE): TRANSISTOR COUNT: -VSUPPLY 485 PROCESS: CMOS-DI NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layouts HI-546 EN (18) A0 (17) A1 A2 (16) (15) HI-547 A3 VREF (14) (13) EN (18) GND (12) A0 (17) A1 A2 (16) (15) NC VREF (14) (13) GND (12) IN 1B (11) IN 2B (10) IN 1 (19) IN 9 (11) IN 1A (19) IN 2 (20) IN 10 (10) IN 2A (20) IN 3 (21) IN 11 (9) IN 3A (21) IN 3B (9) IN 4 (22) IN 12 (8) IN 4A (22) IN 4B (8) IN 5 (23) IN 6 (24) IN 13 (7) IN 14 (6) IN 5A (23) IN 6A (24) IN 5B (7) IN 6B (6) IN 7 (25) IN 15 (5) IN 7A (25) IN 7B (5) IN 8 (26) IN 16 (4) IN 8A (26) IN 8B (4) V- (27) OUT (28) +V (1) 14 NC (2) V- (27) OUT A (28) +V (1) OUT B(2) HI-546, HI-547, HI-548, HI-549 Die Characteristics DIE DIMENSIONS: PASSIVATION: 83 mils x 108 mils Type: Nitride Over Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2kÅ METALLIZATION: Type: CuAl Thickness: 16kÅ ±2kÅ WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm SUBSTRATE POTENTIAL (NOTE): TRANSISTOR COUNT: -VSUPPLY 253 PROCESS: CMOS-DI NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layouts HI-548 IN 6 (11) IN 7 IN 8 (10) (9) HI-549 OUT (8) IN 4 IN 3 (7) (6) IN 3B IN 4B OUT B (11) (10) (9) OUT A (8) IN 4A IN 3A (7) (6) IN 5 (12) IN 2 (5) IN 2B (12) IN 2A (5) +V (13) GND (14) IN 1 (4) -V (3) IN 1B (13) +V (14) IN 1A (4) -V (3) A2 (15) A1 (16) A0 (1) EN (2) GND (15) A1 (16) A0 (1) EN (2) All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 15