HI-506, HI-507, HI-508, HI-509 Data Sheet June 1999 File Number 3142.2 Single 16 and 8/Differential 8-Channel and 4-Channel CMOS Analog Multiplexers Features The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS multiplexers each include an array of sixteen and eight analog switches respectively, a digital decoder circuit for channel selection, voltage reference for logic thresholds, and an enable input for device selection when several multiplexers are present. The Dielectric Isolation (DI) process used in fabrication of these devices eliminates the problem of latchup. DI also offers much lower substrate leakage and parasitic capacitance than conventional junction isolated CMOS (see Application Notes AN520 and AN521). • Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . . . ±15V The switching threshold for each digital input is established by an internal +5V reference, providing a guaranteed minimum 2.4V for logic “1” and maximum 0.8V for logic “0”. This allows direct interface without pullup resistors to signals from most logic families: CMOS, TTL, DTL and some PMOS. For protection against transient overvoltage, the digital inputs include a series 200Ω resistor and diode clamp to each supply. • Low ON Resistance . . . . . . . . . . . . . . . . . . . . . . . . . 180Ω • TTL/CMOS Compatible • Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns • Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . . .44V • Break-Before-Make Switching • No Latch-Up • Replaces DG506A/DG506AA and DG507A/DG507AA • Replaces DG508A/DG508AA and DG509A/DG509AA Applications • Data Acquisition Systems • Precision Instrumentation • Demultiplexing • Selector Switch The HI-506 is a single 16-Channel, the HI-507 is an 8-Channel differential, the HI-508 is a single 8-Channel and the HI-509 is a 4-Channel differential multiplexer. Ordering Information If input overvoltages are present, the HI-546/HI-547/HI-548/ HI-549 multiplexers are recommended. HI9P0506-9 -40 to 85 28 Ld SOIC M28.3 HI3-0506-5 0 to 75 28 Ld PDIP E28.6 HI4P0506-5 0 to 75 28 Ld PLCC N28.45 1 PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. HI1-0506-5 0 to 75 28 Ld CERDIP F28.6 HI1-0506-4 -25 to 85 28 Ld CERDIP F28.6 HI1-0506-2 -55 to 125 28 Ld CERDIP F28.6 HI4P0507-5 0 to 75 28 Ld PLCC N28.45 HI3-0507-5 0 to 75 28 Ld PDIP E28.6 HI1-0507-2 -55 to 125 28 Ld CERDIP F28.6 HI1-0508-5 0 to 75 16 Ld CERDIP F16.3 HI3-0508-5 0 to 75 16 Ld PDIP E16.3 HI1-0508-4 -25 to 85 16 Ld CERDIP F16.3 HI1-0508-2 -55 to 125 16 Ld CERDIP F16.3 HI4P0508-5 0 to 75 20 Ld PLCC N20.35 HI9P0508-9 -40 to 85 16 Ld SOIC M16.15 HI9P0508-5 0 to 75 16 Ld SOIC M16.15 HI9P0509-5 0 to 75 16 Ld SOIC M16.15 HI1-0509-4 -25 to 85 16 Ld CERDIP F16.3 HI1-0509-5 0 to 75 16 Ld CERDIP F16.3 HI3-0509-5 0 to 75 16 Ld PDIP E16.3 HI4P0509-5 0 to 75 20 Ld PLCC N20.35 HI1-0509-2 -55 to 125 16 Ld CERDIP F16.3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 HI-506, HI-507, HI-508, HI-509 Pinouts HI-506 (PDIP, CERDIP, SOIC) TOP VIEW HI-507 (PDIP, CERDIP) TOP VIEW 28 OUT +VSUPPLY 1 28 OUT A +VSUPPLY 1 NC 2 27 -VSUPPLY 27 -VSUPPLY OUT B 2 NC 3 26 IN 8 NC 3 26 IN 8A IN 16 4 25 IN 7 IN 8B 4 25 IN 7A IN 15 5 24 IN 6 IN 7B 5 24 IN 6A IN 14 6 23 IN 5 IN 6B 6 23 IN 5A IN 13 7 22 IN 4 IN 5B 7 22 IN 4A IN 12 8 21 IN 3 IN 4B 8 21 IN 3A IN 11 9 20 IN 2 IN 3B 9 20 IN 2A IN 10 10 19 IN 1 IN 2B 10 19 IN 1A 18 ENABLE IN 1B 11 18 ENABLE IN 9 11 GND 12 17 ADDRESS A0 GND 12 17 ADDRESS A0 NC 13 16 ADDRESS A1 NC 13 16 ADDRESS A1 ADDRESS A3 14 15 ADDRESS A2 NC 14 15 ADDRESS A2 26 IN 8A 27 -VSUPPLY IN 8 28 OUT A -VSUPPLY 1 +VSUPPLY OUT 2 OUT B +VSUPPLY 3 NC NC 4 IN 8B NC HI-507 (PLCC) TOP VIEW IN 16 HI-506 (PLCC) TOP VIEW 4 3 2 1 28 27 26 IN 6 IN 6B 6 24 IN 6A IN 13 7 23 IN 5 IN 5B 7 23 IN 5A IN 12 8 22 IN 4 IN 4B 8 22 IN 4A IN 11 9 21 IN 3 IN 3B 9 21 IN 3A IN 10 10 20 IN 2 IN 2B 10 20 IN 2A IN 9 11 19 IN 1 IN 1B 11 19 IN 1A 15 16 17 18 12 13 14 15 2 16 17 18 ENABLE 14 A0 13 A1 12 A2 24 NC 6 NC IN 14 GND IN 7A ENABLE 25 A0 5 A1 IN 7B A2 IN 7 A3 25 NC 5 GND IN 15 HI-506, HI-507, HI-508, HI-509 Pinouts (Continued) HI-508 (PDIP, CERDIP, SOIC) TOP VIEW HI-509 (PDIP, CERDIP, SOIC) TOP VIEW A0 1 16 A1 A0 1 ENABLE 2 15 A2 ENABLE 2 14 GND -VSUPPLY 3 16 A1 15 GND 14 +VSUPPLY -VSUPPLY 3 IN 1 4 13 +VSUPPLY IN 1A 4 13 IN 1B IN 2 5 12 IN 5 IN 2A 5 12 IN 2B IN 3 6 11 IN 6 IN 3A 6 11 IN 3B IN 4 7 10 IN 7 IN 4A 7 10 IN 4B OUT 8 9 IN 8 OUT A 8 A0 NC A1 A2 ENABLE A0 NC A1 GND HI-509 (PLCC) TOP VIEW ENABLE HI-508 (PLCC) TOP VIEW 9 OUT B 3 2 1 20 19 3 2 1 20 19 NC 6 16 NC NC 6 16 NC IN 2 7 15 IN 5 IN 2A 7 15 IN 2B IN 3 8 14 IN 6 IN 3A 8 14 IN 3B 11 12 13 9 10 11 12 13 IN 4B 17 IN 1B OUT B 5 NC IN 1A OUT A 17 +VSUPPLY IN 4A 18 +VSUPPLY IN 7 5 10 4 IN 8 IN 1 9 -VSUPPLY NC 18 GND OUT 4 IN 4 -VSUPPLY 3 HI-506, HI-507, HI-508, HI-509 Truth Tables HI-508 HI-506 A3 A2 A1 A0 EN “ON” CHANNEL A2 A1 A0 EN “ON” CHANNEL X X X X L None X X X L None L L L L H 1 L L L H 1 L L L H H 2 L L H H 2 L L H L H 3 L H L H 3 L L H H H 4 L H H H 4 L H L L H 5 H L L H 5 L H L H H 6 H L H H 6 L H H L H 7 H H L H 7 L H H H H 8 H H H H 8 H L L L H 9 H L L H H 10 A1 A0 EN “ON” CHANNEL PAIR H L H L H 11 X X L None H L H H H 12 L L H 1 H H L L H 13 L H H 2 H H L H H 14 H L H 3 H H H L H 15 H H H 4 H H H H H 16 HI-507 A2 A1 A0 EN “ON” CHANNEL X X X L None L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 4 HI-509 HI-506, HI-507, HI-508, HI-509 Functional Diagrams HI-506 HI-507 IN 1 OUT IN 1A OUT A IN 2 IN 8A DECODER/ DRIVER IN 1B OUT B IN 16 DECODER/ DRIVER IN 8B 5V REF LEVEL SHIFT † DIGITAL INPUT PROTECTION † † † † † A0 A1 A2 A3 EN 5V REF LEVEL SHIFT † DIGITAL INPUT PROTECTION HI-508 † † † † A0 A1 A2 EN HI-509 IN 1 OUT IN 1A OUT A IN 2 IN 4A DECODER/ DRIVER IN 1B OUT B IN 8 DECODER/ DRIVER IN 4B 5V REF † DIGITAL INPUT PROTECTION LEVEL SHIFT † † † † A0 A1 A2 EN 5V REF † DIGITAL 5 INPUT PROTECTION LEVEL SHIFT † † † A0 A1 EN HI-506, HI-507, HI-508, HI-509 Schematic Diagrams ADDRESS DECODER V+ P P P P A0 OR A0 A1 OR A1 P P P N N N N N A2 OR A2 TO P-CHANNEL DEVICE OF THE SWITCH TO N-CHANNEL DEVICE OF THE SWITCH N A3 OR A3 N ENABLE DELETE A3 OR A3 INPUT FOR HI-507, HI-508, HI-509 DELETE A2 OR A2 INPUT FOR HI-509 V- ADDRESS INPUT BUFFER LEVEL SHIFTER V+ P3 P1 P5 A V+ D1 P4 N1 VL VR D2 P6 P7 P8 P9 P10 N6 N7 N8 N9 N10 P2 N4 A 200Ω N5 N2 V- N3 AIN ALL N-CHANNEL BODIES TO VALL P-CHANNEL BODIES TO V+ UNLESS OTHERWISE INDICATED V- TTL REFERENCE CIRCUIT MULTIPLEX SWITCH V+ P15 Q1P Q2P Q3P N18 FROM DECODE Q4P Q5N V+ Q6N VL Q8N R2 16.8K N12 N17 N19 IN P17 Q7P Q11P V- D3 Q10N VR R3 6.8K Q9P N13 N14 N15 P18 P16 Q12N FROM DECODE V- GND 6 OUT HI-506, HI-507, HI-508, HI-509 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +22V V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V Digital Input Voltage (VEN , VA) . . . . . (V-) -4V to (V+) +4V or 20mA, Whichever Occurs First Analog Signal (VIN, VOUT, Note 2) . . . . . . . . . . (V-) -2V to (V+) +2V Continuous Current, In or Out . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, In or Out (Pulsed 1ms, 10% Duty Cycle Max) . 40mA Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) 16 Ld CERDIP Package. . . . . . . . . . . . 85 32 16 Ld SOIC Package . . . . . . . . . . . . . . 115 N/A 16 Ld PDIP Package . . . . . . . . . . . . . . 100 N/A 20 Ld PLCC Package. . . . . . . . . . . . . . 80 N/A 28 Ld CERDIP Package. . . . . . . . . . . . 55 18 28 Ld PDIP Package . . . . . . . . . . . . . . 60 N/A 28 Ld SOIC Package . . . . . . . . . . . . . . 70 N/A 28 Ld PLCC Package. . . . . . . . . . . . . . 70 N/A Maximum Junction Temperature Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC and PLCC - Lead Tips Only) Operating Conditions Temperature Ranges HI-506/507/508/509-2 . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HI-506/508/509-4 . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC HI-506/507/508/509-5 . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC HI-506/508-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. Signals on IN or OUT exceeding V+ or V- are clamped by internal diodes. Limit resulting current to maximum current ratings. If an overvoltage condition is anticipated (analog input exceeds either power supply voltage), the Harris HI-546/HI-547/HI-548/HI-549 multiplexers are recommended. Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V; VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section TEST CONDITIONS -2 -4, -5, -9 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS 25 - 250 500 - 250 - ns Full - - 1000 - - 1000 ns Break-Before-Make Delay, tOPEN 25 25 80 - 25 80 - ns Enable Delay (ON), tON(EN) 25 - 250 500 - 250 - ns Full - - 1000 - - 1000 ns 25 - 250 500 - 250 - ns Full - - 1000 - - 1000 ns To 0.1% 25 - 1.2 - - 1.2 - µs To 0.01% 25 - 2.4 - - 2.4 - µs Settling Time, tS (HI-508 and HI-509) To 0.1% 25 - 360 - - 360 - ns To 0.01% 25 - 600 - - 600 - ns Off Isolation Note 6 25 50 68 - 50 68 - dB 25 - 10 - - 10 - pF HI-506 25 - 52 - - 52 - pF HI-507 25 - 30 - - 30 - pF HI-508 25 - 17 - - 17 - pF HI-509 25 - 12 - - 12 - pF Digital Input Capacitance, CA 25 - 6 - - 6 - pF Input to Output Capacitance, CDS(OFF) 25 - 0.08 - - 0.08 - pF PARAMETER DYNAMIC CHARACTERISTICS Access Time, tA Enable Delay (OFF), tOFF(EN) Settling Time, tS (HI-506 and HI-507) Channel Input Capacitance, CS(OFF) Channel Output Capacitance, CD(OFF) 7 HI-506, HI-507, HI-508, HI-509 Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V; VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued) TEST CONDITIONS -2 -4, -5, -9 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS Input Low Threshold, VAL Full - - 0.8 - - 0.8 V Input High Threshold, VAH Full 2.4 - - 2.4 - - V Full - - 1.0 - - 1.0 µA Full -15 - +15 -15 - +15 V 25 - 180 300 - 180 400 Ω 25 - 5 - - 5 - % 25 - 0.03 - - 0.03 - nA Full - - 50 - - 50 nA 25 - 0.3 - - 0.3 - nA HI-506 Full - - 300 - - 300 nA HI-507 Full - - 200 - - 200 nA HI-508 Full - - 200 - - 200 nA HI-509 Full - - 100 - - 100 nA 25 - 0.3 - - 0.3 - nA HI-506 Full - - 300 - - 300 nA HI-507 Full - - 200 - - 200 nA HI-508 Full - - 200 - - 200 nA HI-509 Full - - 100 - - 100 nA Full - - 50 - - 50 nA PARAMETER DIGITAL INPUT CHARACTERISTICS Input Leakage Current (High or Low), IA Note 5 ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VIN On Resistance, rON Note 3 ∆rON , (Any Two Channels) Off Input Leakage Current, IS(OFF) Off Output Leakage Current, ID(OFF) Note 4 Note 4 On Channel Leakage Current, ID(ON) Note 4 Differential Off Output Leakage Current, IDIFF (HI-507, HI-509 Only) POWER SUPPLY CHARACTERISTICS Current, I+ HI-506/HI-507 Note 7 Full - 1.5 3.0 - 1.5 3.0 mA HI-508/HI-509 Note 7 Full - 1.5 2.4 - 1.5 2.4 mA HI-506/HI-507 Note 7 Full - 0.4 1.0 - 0.4 1.0 mA HI-508/HI-509 Note 7 Full - 0.4 1.0 - 0.4 1.0 mA HI-506/HI-507 Full - - 60 - - 60 mW HI-508/HI-509 Full - - 51 - - 51 mW Current, I- Power Dissipation, PD NOTES: 3. VOUT = ±10V, IOUT = +1mA. 4. 10nA is the practical lower limit for high speed measurement in the production test environment. 5. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25oC. 6. VEN = 0.8V, RL = 1K, CL = 15pF, VS = 7VRMS , f = 100kHz. 7. VEN , VA = 0V or 2.4V. 8 HI-506, HI-507, HI-508, HI-509 Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified 1mA V2 IN OUT VIN rON = V2 1mA FIGURE 1A. TEST CIRCUIT 2.2 NORMALIZED RESISTANCE (REFERRED TO VALUE AT ±15V) ON RESISTANCE (Ω) 400 300 125oC 200 25oC 100 -55oC -55oC TO 125oC VIN = 0V 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0 -15 -10 -5 0 5 ANALOG INPUT (V) 10 15 7 8 9 10 11 12 13 14 SUPPLY VOLTAGE (±V) FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY VOLTAGE FIGURE 1. ON RESISTANCE 100nA OFF OUTPUT LEAKAGE CURRENT ID(OFF) LEAKAGE CURRENT 10nA 0.8V EN ID(ON) OUT 1nA A ±10V ID(OFF) +10V OFF INPUT LEAKAGE CURRENT IS(OFF) 100pA 10pA 25 50 75 100 125 TEMPERATURE (oC) FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE 9 FIGURE 2B. ID(OFF) TEST CIRCUIT (NOTE 8) 15 HI-506, HI-507, HI-508, HI-509 Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified (Continued) OUT OUT IS(OFF) A A 0.8V EN A0 ±10V +10V ±10V ID(ON) EN A1 +10V 2.4V FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 8) FIGURE 2D. ID(ON) TEST CIRCUIT (NOTE 8) FIGURE 2. LEAKAGE CURRENTS NOTE: 8. Two measurements per channel: ±10V and +10V. (Two measurements per device for ID(OFF) ±10V and +10V) 70 SWITCH CURRENT (mA) 60 -55oC 50 25oC 40 125oC 30 20 A ±VIN 10 0 0 2 4 6 8 10 12 VOLTAGE ACROSS SWITCH (±V) 14 16 FIGURE 3A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 3B. TEST CIRCUIT FIGURE 3. ON CHANNEL CURRENT +15V/+10V 8 A +ISUPPLY SUPPLY CURRENT (mA) VSUPPLY = ±15V V+ IN 1 6 A3 A2 4 VA 2 50Ω 3.5V VSUPPLY = ±10V VA A1 IN 2 THRU IN 7/15 A0 IN 8/16 EN HIGH = 3.5V LOW = 0V 50% DUTY CYCLE GND 0 1K 10K 100K TOGGLE FREQUENCY (Hz) 1M 10M † Similar connection for HI-507/HI-508/ HI-509 FIGURE 4A. SUPPLY CURRENT vs TOGGLE FREQUENCY FIGURE 4. DYNAMIC SUPPLY CURRENT 10 ±10V/±5V HI-506 † OUT V- A -ISUPPLY -15V/-10V FIGURE 4B. TEST CIRCUIT +10V/+5V 10 MΩ 14 pF HI-506, HI-507, HI-508, HI-509 Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified (Continued) +15V V+ IN 1 600 ACCESS TIME (ns) A3 A2 50Ω VA 400 A1 IN 2 THRU IN 7/15 HI-506 † A0 +10V IN 16 EN 3.5V GND 200 ±10V OUT V- -15V 0 2 3 4 5 13 LOGIC LEVEL (HIGH) (V) 14 † Similar connection for HI-507/HI-508/ 15 HI-509 FIGURE 5A. ACCESS TIME vs LOGIC LEVEL (HIGH) 3.5V FIGURE 5B. TEST CIRCUIT ADDRESS DRIVE (VA) VA INPUT 2V/DIV. 50% 0V S1 ON +10V OUTPUT 10% OUTPUT 5V/DIV. -10V tA S16 ON 200ns/DIV. FIGURE 5C. MEASUREMENT POINTS FIGURE 5D. WAVEFORMS FIGURE 5. ACCESS TIME +15V V+ A3 A2 VA 50Ω A1 HI-506 † +5V IN 1 IN 2 THRU IN 7/IN 15 IN 8 /16 A0 3.5V VOUT EN GND OUT V- 200Ω -15V † Similar connection for HI-507/HI-508/HI-509 FIGURE 6A. TEST CIRCUIT 11 50pF 10 kΩ 50 pF HI-506, HI-507, HI-508, HI-509 Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified (Continued) 3.5V VA INPUT 2V/DIV. S1 ON ADDRESS DRIVE (VA) 0V S16 ON OUTPUT 1V/DIV. OUTPUT 50% 50% tOPEN 100ns/DIV. FIGURE 6B. MEASUREMENT POINTS FIGURE 6C. WAVEFORMS FIGURE 6. BREAK-BEFORE-MAKE DELAY +15V V+ A3 A2 A1 HI-506 † IN 1 +10V IN 2 THRU IN 7/IN 15 IN 8 /16 A0 VOUT EN VA 50Ω GND OUT V- 50pF 200Ω -15V † Similar connection for HI-507/HI-508/HI-509 FIGURE 7A. TEST CIRCUIT 3.5V ENABLE DRIVE 2V/DIV. 50% ENABLE DRIVE (VA) 50% 0V OUTPUT 90% 10% 0V DISABLED ENABLED (S1 ON) OUTPUT 2V/DIV. tON(EN) tOFF(EN) 100ns/DIV FIGURE 7B. MEASUREMENT POINTS FIGURE 7C. WAVEFORMS FIGURE 7. ENABLE DELAYS 12 HI-506, HI-507, HI-508, HI-509 Typical Performance Curves TA = 25oC, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified 100 (VS), (VD) OFF ISOLATION (dB) INPUT LOGIC THRESHOLD (V) 4 3 2 1 0 6 8 10 12 14 16 POWER SUPPLY VOLTAGE (±V) 18 80 60 RL = 10M 40 0 104 20 105 106 FREQUENCY (Hz) 107 FIGURE 9. OFF ISOLATION vs FREQUENCY 3 POWER SUPPLY CURRENT (mA) 3 POWER SUPPLY CURRENT (mA) VEN = 0V CLOAD = 28pF VS = 7VRMS 20 FIGURE 8. LOGIC THRESHOLD vs POWER SUPPLY VOLTAGE 2 VEN = 2.4V VEN = 0V 1 0 -55 RL = 1K -35 -15 -5 25 45 65 TEMPERATURE (oC) FIGURE 10A. HI-506/HI-507 85 105 125 2 EN = 5V 1 EN = 0V 0 -55 -35 -15 FIGURE 10B. HI-508/HI-509 FIGURE 10. POWER SUPPLY CURRENT vs TEMPERATURE 13 -5 25 45 65 TEMPERATURE (oC) 85 105 125 HI-506, HI-507, HI-508, HI-509 Die Characteristics DIE DIMENSIONS: PASSIVATION: 129 mils x 82 mils Type: Nitride/Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2kÅ METALLIZATION: Type: CuAl Thickness: 16kÅ ±2kÅ WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 SUBSTRATE POTENTIAL (NOTE): TRANSISTOR COUNT: -VSUPPLY 421 PROCESS: CMOS-DI NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layout HI-506 EN A0 A1 A2 HI-507 A3 EN GND A0 A1 A2 NC GND IN 1 IN 9 IN 1A IN 1B IN 2 IN 10 IN 2A IN 2B IN 3 IN 11 IN 3A IN 3B IN 4 IN 12 IN 4A IN 4B IN 5 IN 13 IN 5A IN 5B IN 6 IN 14 IN 6A IN 6B IN 7 IN 15 IN 7A IN 7B IN 8 IN 16 IN 8A IN 8B -V OUT +V 14 NC -V OUT A +V OUT B HI-506, HI-507, HI-508, HI-509 Die Characteristics DIE DIMENSIONS: PASSIVATION: 81.9 mils x 90.2 mils Type: Nitride/Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2kÅ METALLIZATION: Type: CuAl Thickness: 16kÅ ±2kÅ WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 SUBSTRATE POTENTIAL (NOTE): TRANSISTOR COUNT: -VSUPPLY 234 PROCESS: CMOS-DI NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layout HI-508 EN A0 A1 A2 HI-509 GND EN A0 A1 GND +VSUP -VSUP +VSUP IN 1 IN 5 IN 1A IN 1B IN 2 IN 6 IN 2A IN 2B -VSUP IN 3A IN 3 IN 3B IN 7 IN 4 OUT IN 8 15 IN 4A OUT A OUT B IN 4B HI-506, HI-507, HI-508, HI-509 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AE D BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 16 MILLIMETERS e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 8 0.355 10.16 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 10.92 3.81 8 5 6 7 4 9 Rev. 0 12/93 HI-506, HI-507, HI-508, HI-509 Dual-In-Line Plastic Packages (PDIP) E28.6 (JEDEC MS-001-BF ISSUE D) N 28 LEAD NARROW BODY DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 N/2 INCHES -B- -AE D BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 eA A1 eC B 0.010 (0.25) M C L C A B S C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 17 MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.250 - 6.35 4 A1 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.030 0.070 0.77 1.77 8 C 0.008 0.015 D 1.380 1.565 D1 0.005 - 0.13 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.204 0.381 35.1 0.100 BSC - 39.7 5 - 5 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 7 L 0.115 0.200 2.93 N 28 17.78 5.08 28 4 9 Rev. 0 12/93 HI-506, HI-507, HI-508, HI-509 Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) N INDEX AREA H 0.25(0.010) M 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- α e A1 B 0.25(0.010) M 0.10(0.004) C A M B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 18 MAX MILLIMETERS MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 e C MIN 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N α 16 0o 16 8o 0o 7 8o Rev. 0 12/93 HI-506, HI-507, HI-508, HI-509 Small Outline Plastic Packages (SOIC) M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 19 MAX MILLIMETERS MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 e α MIN 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α 28 0o 28 7 8o Rev. 0 12/93 HI-506, HI-507, HI-508, HI-509 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER N20.35 (JEDEC MS-018AA ISSUE A) 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 C L E1 E D2/E2 VIEW “A” A1 A D1 D 0.020 (0.51) MAX 3 PLCS 0.020 (0.51) MIN 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. 20 INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.385 0.395 9.78 10.03 - D1 0.350 0.356 8.89 9.04 3 D2 0.141 0.169 3.59 4.29 4, 5 E 0.385 0.395 9.78 10.03 - E1 0.350 0.356 8.89 9.04 3 E2 0.141 0.169 3.59 4.29 4, 5 N 20 20 6 Rev. 2 11/97 SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE HI-506, HI-507, HI-508, HI-509 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER N28.45 (JEDEC MS-018AB ISSUE A) 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 C L E1 E D2/E2 VIEW “A” A1 A D1 D 0.020 (0.51) MAX 3 PLCS 0.020 (0.51) MIN 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. 21 INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.485 0.495 12.32 12.57 - D1 0.450 0.456 11.43 11.58 3 D2 0.191 0.219 4.86 5.56 4, 5 E 0.485 0.495 12.32 12.57 - E1 0.450 0.456 11.43 11.58 3 E2 0.191 0.219 4.86 5.56 4, 5 N 28 28 6 Rev. 2 11/97 SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE HI-506, HI-507, HI-508, HI-509 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) LEAD FINISH c1 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE -D- -A- BASE METAL E M -Bbbb S C A-B S -C- S1 0.200 - 5.08 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.840 - 21.34 5 E 0.220 0.310 5.59 7.87 5 eA ccc M C A - B S e eA/2 c aaa M C A - B S D S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 22 NOTES - b2 b MAX 0.014 α A A MIN b A L MAX A Q SEATING PLANE MILLIMETERS MIN M (b) D BASE PLANE SYMBOL b1 SECTION A-A D S INCHES (c) e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N 16 16 8 Rev. 0 4/94 HI-506, HI-507, HI-508, HI-509 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A) LEAD FINISH c1 28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE -D- -A- BASE METAL E M -Bbbb S C A-B S -C- S1 0.232 - 5.92 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 1.490 - 37.85 5 E 0.500 0.610 15.49 5 eA ccc M C A - B S e eA/2 c aaa M C A - B S D S D S NOTES - b2 b MAX 0.014 α A A MIN b A L MAX A Q SEATING PLANE MILLIMETERS MIN M (b) D BASE PLANE SYMBOL b1 SECTION A-A D S INCHES (c) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. e 12.70 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N 28 28 8 Rev. 0 4/94 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 23 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029