NSC 74ACT164

74ACT164
Serial-In, Parallel-Out Shift Register
General Description
Features
The 74ACT164 is a high-speed 8-bit serial-in/parallel-out
shift register. Serial data is entered through a 2-input AND
gate synchronous with the Low-to-High transition of the
clock. The device features an asynchronous Master Reset
which clears the register, setting all outputs Low independent of the clock.
Y
Logic Symbol
Connection Diagram
Y
Outputs source/sink 24 mA
’ACT has TTL-compatible inputs
Pin Assignment
for SOIC
TL/F/11553 – 1
Pin Names
A, B
CP
MR
Q0 – Q7
Description
TL/F/11553 – 2
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active Low)
Outputs
FACTTM is a trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/11553
RRD-B30M75/Printed in U. S. A.
74ACT164 Serial-In, Parallel-Out Shift Register
November 1993
Functional Description
Function Table
The 74ACT164 is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight
stages. Data is entered serially through one of two inputs (A
or B); either of these inputs can be used as an active High
Enable for data entry through the other input. An unused
input must be tied High.
Each Low-to-High transition on the Clock (CP) input shifts
data one place to the right and enters into Q0 the logical
AND of the two data inputs (A # B) that existed before the
rising clock edge. A Low level on the Master Reset (MR)
input overrides all other inputs and clears the register asynchronously, forcing all Q outputs Low.
Operating
Mode
MR
Inputs
A
B
Q0
Outputs
Q1 –Q7
Reset (Clear)
L
X
X
L
L–L
Shift
H
H
H
H
L
L
H
H
L
H
L
H
L
L
L
H
Q0 –Q6
Q0 –Q6
Q0 –Q6
Q0 –Q6
H e High Voltage Levels
L e Low Voltage Levels
X e Immaterial
Q e Lower case letters indicate the state of the referenced input or
output one setup time prior to the Low-to-High clock transition.
Logic Diagram
TL/F/11553 – 3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI e b0.5V
VI e VCC a 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO e b0.5V
VO e VCC a 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
SOIC
Supply Voltage (VCC)
’ACT
Input Voltage (VI)
b 0.5V to a 7.0V
4.5V to 5.5V
0V to VCC
0V to VCC
Output Voltage (VO)
Operating Temperature (TA)
74ACT
b 20 mA
a 20 mA
b 0.5V to VCC a 0.5V
b 40§ C to a 85§ C
Minimum Input Edge Rate (DV/Dt)
’ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
b 20 mA
a 20 mA
b 0.5V to VCC a 0.5V
125 mV/ns
g 50 mA
g 50 mA
b 65§ C to a 150§ C
140§ C
Note 1: Absolute maximum ratings are values beyond which damage to the
device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT TM circuits outside databook specifications.
DC Characteristics for ’ACT Family Devices
Symbol
Parameter
VCC
(V)
74ACT
74ACT
TA e a 25§ C
TA e
b 40§ C to a 85§ C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
VOUT e 0.1V
or VCC b 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
VOUT e 0.1V
or VCC b 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
V
3.86
4.86
3.76
4.76
V
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.44
0.44
V
g 0.1
g 1.0
mA
VI e VCC, GND
1.5
mA
VI e VCC b 2.1V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
IIN
Maximum Input
Leakage Current
5.5
ICCT
Maximum ICC/Input
5.5
IOLD
² Minimum Dynamic
Output Current
IOHD
ICC
Maximum Quiescent
Supply Current
0.001
0.001
0.6
IOUT e b50 mA
*VIN e VIL or VIH
b 24 mA
IOH
b 24 mA
IOUT e 50 mA
*VIN e VIL or VIH
24 mA
IOL
24 mA
5.5
75
mA
VOLD e 1.65V Max
5.5
b 75
mA
VOHD e 3.85V Min
40.0
mA
VIN e VCC
or GND
5.5
4.0
*All outputs loaded; thresholds on input associated with output under test.
² Maximum test duration 2.0 ms, one output loaded at a time.
3
AC Electrical Characteristics
Symbol
Parameter
VCC*
(V)
Min
74ACT
74ACT
TA e a 25§ C
CL e 50 pF
TA e b40§ C
to a 85§ C
CL e 50 pF
Typ
Max
Min
Units
Max
fmax
Maximum Clock
Frequency
5.0
100
tPLH
Propagation Delay
CP to Qn
5.0
1.0
6.0
11.5
1.0
12.5
ns
tPHL
Propagation Delay
CP to Qn
5.0
1.0
6.0
11.5
1.0
12.5
ns
tPHL
Propagation Delay
MR to Qn
5.0
1.0
6.0
13.0
1.0
14.5
ns
80
MHz
*Voltage Range 5.0 is 5.0V g 0.5V
AC Operating Requirements
Symbol
Parameter
VCC*
(V)
74ACT
74ACT
TA e a 25§ C
CL e 50 pF
TA e b40§ C
to a 85§ C
CL e 50 pF
Typ
Guaranteed Minimum
Units
tS
Set-Up Time, HIGH or LOW
A or B to CP
5.0
0.5
7.0
8.0
ns
tH
Hold Time, HIGH or LOW
CP to A or B
5.0
0.0
1.5
1.5
ns
tW
Pulse Width, HIGH or LOW
CP to MR
5.0
0.5
7.0
8.0
ns
tREC
Recovery Time
MR to CP
5.0
0.5
2.0
2.0
ns
*Voltage Range 5.0 is 5.0V g 0.5V
Capacitance
Parameter
Typ
Units
Conditions
CIN
Symbol
Input Capacitance
4.5
pF
VCC e OPEN
CPD
Power Dissipation
Capacitance
45.0
pF
VCC e 5.0V
4
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74ACT
164
S
C
X
Temperature Range Family
74ACT e Commercial TTL-Compatible
Special Variations
X e Devices Shipped in 13× reels
Device Type
Temperature Range
C e Commercial (b40§ C to a 85 § C)
Package Code
S e Small Outline Package (SOIC)
5
74ACT164 Serial-In, Parallel-Out Shift Register
Physical Dimensions inches (millimeters)
14-Lead Small Outline Integrated Circuit (S)
NS Package Number M14A
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