Vishay Semiconductors Reliability The requirements concerning quality and reliability of products are always increasing. It is not sufficient to only deliver fault–free parts. In addition, it must be ensured that the delivered goods serve their purpose safely and failure free, i.e. reliably. From the delivery of the device up to its use in a final product, there are some occasions where the device or the final product may fail despite testing and outgoing inspection. In principle, this sequence is valid for all components of a product. For these reasons, the negative consequences of a failure, which become more serious and expensive the later they occur, are obvious. The manufacturer is therefore interested in supplying products with the lowest possible D AOQ (Average Outgoing Quality) value D EFR (Early Failure Rate) value D LFR (Long-term Failure Rate) value Average Outgoing Quality (AOQ) Long-Term Failure Rate (LFR) LFR shows the failure rate during the operational period of the devices. This period is of particular interest to the manufacturer of the final product. Based on the LFR value, estimations concerning long-term failure rate, reliability and a device’s or module’s usage life may be derived. The usage life time is normally the period of constant failure rate. All failures occuring during this period are random. Within this period the failure rate is: l+ S Sum of failures 1 hours (Quantity Time to failure) The measure of l is FIT (Failures In Time = number of failures in 109 device hours). Example A sample of 500 semiconductor devices is tested in a operating life test (dynamic electric operation). The devices operate for a period of 10,000 hours. Failures: 1 failure after 1000 h 1 failure after 2000 h All outgoing products are sampled after 100% testing. This is known as “Average Outgoing Quality” (AOQ). The results of this inspection are recorded in ppm (parts per million) using the method defined in JEDEC 16. The failure rate may be calculated from this sample by Early Failure Rate (EFR) l+ EFR is an estimate (in ppm) of the number of early failures related to the number of devices used. Early failures are normally those which occur within the first 300 to 1000 hours. Essentially, this period of time covers the guarantee period of the finished unit. Low EFR values are therefore very important to the device user. The early life failure rate is heavily influenced by complexity. Consequently, ‘designing-in’ of better quality during the development and design phase, as well as optimized process control during manufacturing, significantly reduces the EFR value. Normally, the early failure rate should not be significantly higher than the random failure rate. EFR is given in ppm (parts per million). Document Number 80116 02-02 l+ 1000 ) 1 1 2 2000 ) 498 2 1 + 4.01 4983000 h 1 10000 h 10–7 1 h This is a l-value of 400 FIT, or this sample has a failure rate of 0.04% / 1000 h on average. l Early Failures EFR Operating Period LFR Wear Out Failures t 95 11401 Figure 4. Bath tub curve www.vishay.com 1 Vishay Semiconductors Confidence Level The failure rate l calculated from the sample is an estimate of the unknown failure rate of the lot. The interval of the failure rate (confidence interval) may be calculated, depending on the confidence level and sample size. The following is valid: D The larger the sample size, the narrower the confidence interval. D The lower the confidence level of the statement, the narrower the confidence interval. The confidence level applicable to the failure rate of the whole lot when using the estimated value of l is derived from the k2-distribution. In practice, only the upper limit of the confidence interval (the maximum average failure rate) is used. Therefore: l max + k2ń2 (r; P A) in 1 n t h LFR + k 2ń2 (r; PA) n t 1 r: Number of failures PA: Confidence level n: Sample size t: Time in hours n t: Device hours 10 9 in [FIT] 10 –7 1 h This means that the failure rate of the lot does not exceed 0.0618% / 1000 h (618 FIT) with a probability of 60%. If a confidence level of 90% is chosen from the table 15 : k2/2 (r = 2; PA = 90%) = 5.3 l max + 5.3 + 1.06 4983000 Document Number 80116 02-02 Number of Failures 0 1 2 3 4 5 6 7 8 9 10 Confidence Level 50% 0.60 1.68 2.67 3.67 4.67 5.67 6.67 7.67 8.67 9.67 10.67 60% 0.93 2.00 3.08 4.17 5.24 6.25 7.27 8.33 9.35 10.42 11.42 90% 2.31 3.89 5.30 6.70 8.00 9.25 10.55 11.75 13.00 14.20 15.40 95% 2.96 4.67 6.21 7.69 9.09 10.42 11.76 13.16 14.30 15.63 16.95 Operating Life Tests Number of devices tested: n = 50 Number of failures (positive qualification): c = 0 Test time: t = 2000 hours PA = 60% k2/2 (0; 60%) = 0.93 For the above example from table 15: k2/2 (r=2; PA = 60%) = 3.08 n t = 4983000 h 3.08 + 6.18 4983000 Table 15. Confidence level: The k2/2 for l are taken from table 15. l max + This means that the failure rate of the lot does not exceed 0.106% / 1000 h (1060 FIT) with a probability of 90%. 10 –6 1 h l max + 50 0.93 + 9.3 2000 10–6 1 h This means, that the failure rate of the lot does not exceed 0.93% / 1000 h (9300 FIT) with a probability of 60%. This example demonstrates that it is only possible to verify LFR values of 9300 FIT with a confidence level of 60% in a normal qualification tests (50 devices, 2000 h). To obtain LFR values which meet today’s requirements (t50 FIT), the following conditions have to be fulfilled: D Very long test periods D Large quantities of devices D Accelerated testing (e.g. higher temperature) www.vishay.com 2 Vishay Semiconductors Mean Time to Failure (MTTF) For systems which can not be repaired and whose devices must be changed, e.g. semiconductors, the following is valid: Power dissipation of the device PV = 100 mW MTTF + 1 l MTTF is the average fault-free operating period per a monitored (time) unit. Thermal resistance junction/environment RthJA = 300 K/W Accelerating Stress Tests The system temperature / junction temperature results from: Innovation cycles in the field of semiconductors are becoming shorter and shorter. This means that products must be brought to the market quicker. At the same time, expectations concerning the quality and reliability of the products have become higher. Manufacturers of semiconductors must therefore assure long operating periods with high reliability but in a short time. Sample stress testing is the most commonly used way of assuring this. The rule of Arrhenius describes this temperaturedependent change of the failure rate. ƪ ǒ e E A k l(T 2) + l(T 1) 1 1 – T1 T2 Ǔƫ TJ = TA + RthJA TJ = 70°C + 300 K/W Operation in the field at an ambient temperature of 50°C and at an average power dissipation of 80 mW is utilized. This results in a junction temperature in operation of TJ = 74°C. The activation energy used for opto components is EA = 0.8 eV. The resulting acceleration factor is: AF + Junction temperature real operation T1 in Kelvin Junction temperature stress test T2 in Kelvin Failure rate real operation l (T1) Failure rate stress test l (T2) ƪ ǒ E A k 1 1 – T1 T2 Ǔƫ Example The following conditions apply to an operating life stress test: Environmental temperature during stress test TA = 70°C Document Number 80116 02-02 l(373K) +e l(347K) ƪ E A k 1 1 Ǔ ǒ347K – ƫ 373K AF [ 6.5 This signifies that, regarding this example, the failure rate is lower by a factor of 6.5 compared to the stress test. Other accelerating stress tests may be: The acceleration factor is described by the exponential function as being: l(T 2) AF + +e l(T 1) 100 mW TJ = 100°C Boltzmann’s constant k = 8.63 10–5 eV/K Activation energy EA in eV PV D Humidity (except displays type TDS.) TA = 85°C RH = 85% D Temperature cycling Temperature interval as specified The tests are carried out according to the requirements of appropriate IEC–standards (see also chapter ‘Qualification and Release’). www.vishay.com 3 Vishay Semiconductors Activation Energy Degradation of IREDs There are some conditions which need to be fulfilled in order to use Arrhenius’ method: The diagrams in figure 6 and figure 7 are based on electrical life tests, calculated with Ea = 0.8 eV at Tj = 25°C. D The validity of Arrhenius’ rule has to be verified. D ‘Failure-specific’ activation energies must be determined. Values often used for different device groups are: Opto components 0.8 eV Bipolar ICs 0.7 eV MOS ICs 0.6 eV Transistors 0.7 eV Diodes 0.7 eV By using this method, it is possible to provide long–term predictions for the actual operation of semiconductors even with relatively short test periods. IF=50mA 8 Degradation ( % ) These conditions may be verified by a series of tests. Today, this procedure is generally accepted and used as a basis for estimating operating life. The values of activation energies can be determined by experiments for different failure mechanisms. 10 6 4 2 0 103 104 105 Time (h) 94 8169 Figure 6. Average degradation of TSUS 5. 20 1000 IF=50mA 0.8 eV 0.6 eV 100 0.5 eV 15 Degradation ( % ) Acceleration factor 0.7 eV 10 10 5 100 1 55 125 75 95 115 135 Junction Temperature (°C) 0 103 150 155 105 Time (h) 95 11369 Figure 5. Acceleration factor for different activation energies normalized to Tj = 55°C Document Number 80116 02-02 94 8170 104 Figure 7. Average degradation of TSHA 5. www.vishay.com 4