ISL43240 ® Data Sheet April 2003 Low-Voltage, Single and Dual Supply, Quad SPDT, High Performance Analog Switches Features The Intersil ISL43240 device is a CMOS, precision, quad SPDT analog switches designed to operate from a single +2V to +12V supply or from a ±2V to ±6V supply. Targeted applications include battery powered equipment that benefit from the devices’ low power consumption (5µW), low leakage currents (5nA max), and fast switching speeds (tON = 52ns, tOFF = 40ns). A 5Ω maximum RON flatness ensures signal fidelity, while channel-to-channel mismatch is guaranteed to be less than 2Ω. • Four Separately Controlled SPDT Switches • Fully Specified for 10% Tolerances at VS = ±5V and V+ = 12V, 5V and 3.3V The ISL43240 is a quad single-pole / double-throw (SPDT) device and can be used as a quad SPDT, a quad 2:1 multiplexer, a single 4:1 multiplexer, or a dual 2-channel differential multiplexer. Table 1 summarizes the performance of this family. TABLE 1. FEATURES AT A GLANCE CONFIGURATION QUAD SPDT ±4.5V RON 18Ω ±4.5V tON/tOFF 52ns/40ns 10.8V RON 14Ω 10.8V tON/tOFF 40ns/27ns 4.5V RON 30Ω 4.5V tON/tOFF 64ns/29ns 3V RON 51Ω 3V tON/tOFF Packages 120ns/50ns 20 Ld SSOP, 20 Ld QFN 4x4 FN6036.1 • ON Resistance (RON) . . . . . . . . . . . . . . . . . . . . . . . . 18Ω • RON Matching Between Channels. . . . . . . . . . . . . . . . . . <1Ω • Low Charge Injection . . . . . . . . . . . . . . . . . . . . . . 5pC (Max) • Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . . .<5µW • Low Off Leakage Current (Max at 85oC) . . . . . . . . . 2.5nA • Fast Switching Action - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns • Guaranteed Break-Before-Make • Minimum 2000V ESD Protection per Method 3015.7 • TTL, CMOS Compatible Applications • Battery Powered, Handheld, and Portable Equipment - Barcode Scanners - Laptops, Notebooks, Palmtops • Communications Systems - Radios - XDSL and PBX / PABX - RF “Tee” Switches - Base Stations • Test Equipment - Medical Ultrasound - Electrocardiograph - ATE • Audio and Video Switching • General Purpose Circuits - +3V/+5V DACs and ADCs - Digital Filters - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • AN557 “Recommended Test Procedures for Analog Switches” 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL43240 (Note 1) COM1 3 18 COM4 NC1 4 17 NC4 V- 5 IN1 IN4 NO4 20 IN4 19 NO4 NO1 IN1 1 NO1 2 ISL43240 (QFN) TOP VIEW N.C. ISL43240 (SSOP) TOP VIEW 20 19 18 17 16 COM1 1 15 COM4 NC1 2 14 NC4 V- 3 13 V+ 16 V+ GND 4 12 NC3 13 COM3 NC2 5 11 COM3 COM2 8 NO2 9 12 NO3 IN2 10 11 IN3 6 7 8 9 10 NO3 14 NC3 IN2 NC2 7 NO2 15 N.C. COM2 GND 6 IN3 Pinouts NOTE: 1. Switches Shown for Logic “0” Input. Truth Table Ordering Information ISL43240 ISL43240 LOGIC NO SW NC SW 0 OFF ON 1 ON OFF NOTE: Logic “0” ≤ 0.8V. Logic “1” ≥ 2.4V. Pin Descriptions PIN FUNCTION V+ Positive Power Supply Input V- Negative Power Supply Input. Connect to GND for Single Supply Configurations. GND Ground Connection IN Digital Control Input COM Analog Switch Common Pin NO Analog Switch Normally Open Pin NC Analog Switch Normally Closed Pin N.C. No Internal Connection 2 PART NO. (BRAND) TEMP. RANGE (oC) PACKAGE PKG. NO. ISL43240IA -40 to 85 20 Ld SSOP M20.209 ISL43240IA-T -40 to 85 20 Ld SSOP Tape and Reel M20.209 ISL43240IR -40 to 85 20 Ld QFN L20.4x4 ISL43240IR-T -40 to 85 20 Ld QFN Tape and Reel L20.4x4 ISL43240 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V All Other Pins (Note 2) . . . . . . . . . . . . . ((V-) - 0.3V) to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current, IN, NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . 100mA ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . .>2kV Thermal Resistance (Typical) θJA (oC/W) 20 Ld SSOP Package (Note 3) . . . . . . . . . . . . . . . . 150 20 Ld QFN Package (Note 4). . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Moisture Sensitivity (See Technical Brief TB363) All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Storage Temperature Range. . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SSOP - Lead Tips Only) Operating Conditions Temperature Range ISL43240IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. Signals on NC, NO, COM, or IN exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. Electrical Specifications: ±5V Supply PARAMETER Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) (NOTE 5) MIN Full V- - V+ V 25 - 18 25 Ω TYP (NOTE 5) MAX UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON VS = ±4.5V, ICOM = 10mA, VNO or VNC = ±3.5V, See Figure 5 Full - - 30 Ω RON Matching Between Channels, ∆RON VS = ±4.5V, ICOM = 10mA, VNO or VNC = ±3V 25 - 0.5 2 Ω RON Flatness, RFLAT(ON) VS = ±4.5V, ICOM = 10mA, VNO or VNC = 0V, ±3V, Note 7 NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = +4.5V, Note 6 COM ON Leakage Current, ICOM(ON) VS = ±5.5V, VCOM = VNO or VNC = ±4.5V, Note 6 Full - - 4 Ω 25 - - 5 Ω Full - - 5 Ω 25 -0.2 - 0.2 nA Full -2.5 - 2.5 nA 25 -0.4 - 0.4 nA Full -5 - 5 nA Input Voltage High, VINH Full 2.4 1.6 - V Input Voltage Low, VINL Full - 1.5 0.8 V VS = ±5.5V, VIN = 0V or V+ Full -1 - 1 µA VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 25 - 52 65 ns Full - - 75 ns 25 - 40 50 ns DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 Break-Before-Make Time Delay, tD VS = ±5.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 3 Full - - 55 ns Full 10 19 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - - 5 pC NO OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 30 - pF OFF Isolation 25 - 71 - dB Crosstalk, Note 8 RL = 50Ω, CL = 15pF, f = 1MHz, VNO or VNC = 1VRMS, See Figures 4 and 6 25 - -92 - dB Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz 25 - 59 - dB 3 ISL43240 Electrical Specifications: ±5V Supply PARAMETER Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (oC) (NOTE 5) MIN Full ±2 - ±6 V 25 -1 0.01 1 µA TYP (NOTE 5) MAX UNITS POWER SUPPLY CHARACTERISTICS Power Supply Range VS = ±5.5V, VIN = 0V or V+, Switch On or Off Positive Supply Current, I+ Negative Supply Current, I- Full -1 - 1 µA 25 -1 0.01 1 µA Full -1 - 1 µA NOTES: 5. VIN = Input voltage to perform proper function. 6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25oC. 8. Flatness is defined as the delta between the maximum and minimum RON values over the specified voltage range. 9. Between any two switches. Electrical Specifications: 5V Supply PARAMETER Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN (NOTE 5) Full 0 - V+ V 25 - 30 40 Ω Full - - 50 Ω Ω TYP MAX (NOTE 5) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V, See Figure 5 RON Matching Between Channels, ∆RON V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3V RON Flatness, RFLAT(ON) V+ = 5.5V, ICOM = 1.0mA, VNO or VNC = 1V, 2V, 3V, Note 7 NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V, Note 6 COM ON Leakage Current, ICOM(ON) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 1V, 4.5V Note 6 25 - 0.5 3 Full - - 4 Ω 25 - 4.4 6 Ω Full - - 8 Ω 25 -0.2 - 0.2 nA Full -2.5 - 2.5 nA 25 -0.4 - 0.4 nA Full -5 - 5 nA Input Voltage High, VINH Full 2.4 1.5 - V Input Voltage Low, VINL Full - 1.4 0.8 V V+ = 5.5V, VIN = 0V or V+ Full -1 - 1 µA V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 25 - 64 80 ns Full - - 90 ns 25 - 29 40 ns DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 Full - - 45 ns Break-Before-Make Time Delay, tD V+ = 5.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 3 Full 15 39 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 1.2 2 pC NO OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 30 - pF OFF Isolation 25 - 71 - dB Crosstalk, Note 8 RL = 50Ω, CL = 15pF, f = 1MHz, VNO or VNC = 1VRMS, See Figures 4 and 6 25 - -92 - dB Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz 25 - 59 - dB 4 ISL43240 Electrical Specifications: 5V Supply PARAMETER Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (oC) MIN (NOTE 5) TYP MAX (NOTE 5) UNITS POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 5.5V, V- = 0V, VIN = 0V or V+, Switch On or Off Negative Supply Current, I- Electrical Specifications: 3.3V Supply PARAMETER 25 -1 0.01 1 µA Full -1 - 1 µA 25 -1 0.01 1 µA Full -1 - 1 µA Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN (NOTE 5) Full 0 - V+ V 25 - 51 60 Ω Full - - 70 Ω TYP MAX (NOTE 5) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V, See Figure 5 RON Matching Between Channels, ∆RON V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V RON Flatness, RFLAT(ON) V+ = 3V, ICOM = 1.0mA, VNO or VNC = 0.5V, 1.5V, Note 7 NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 3V, 1V, Note 6 COM ON Leakage Current, ICOM(ON) V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 1V, 3V, Note 6 25 - 0.5 3 Ω Full - - 4 Ω 25 - 12 17 Ω Full - - 17 Ω 25 -0.2 - 0.2 nA Full -2.5 - 2.5 nA 25 -0.4 - 0.4 nA Full -5 - 5 nA Input Voltage High, VINH Full 2.4 1.0 - V Input Voltage Low, VINL Full - 0.9 0.8 V V+ = 3.6V, VIN = 0V or V+ Full -1 - 1 µA V+ = 3.0V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 25 - 120 138 ns Full - - 160 ns 25 - 50 60 ns DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF V+ = 3.0V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 Full - - 65 ns Break-Before-Make Time Delay, tD V+ = 3.6V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 3 Full 30 60 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 1 2 pC NO OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 30 - pF OFF Isolation 25 - 71 - dB Crosstalk, Note 8 RL = 50Ω, CL = 15pF, f = 1MHz, VNO or VNC = 1VRMS, See Figures 4 and 6 25 - -92 - dB Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz 25 - 59 - dB POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 3.6V, V- = 0V, VIN = 0V or V+, Switch On or Off Negative Supply Current, I- 5 25 -1 0.01 1 µA Full -1 - 1 µA 25 -1 0.01 1 µA Full -1 - 1 µA ISL43240 Electrical Specifications: 12V Supply PARAMETER Test Conditions: V+ = +10.8V to +13.2V, V- = GND = 0V, VINH = 3.0V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN (NOTE 6) Full 0 - V+ V 25 - 14 20 Ω TYP MAX (NOTE 6) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 9V, See Figure 5 Full - - 30 Ω RON Matching Between Channels, ∆RON V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 9V 25 - 0.3 2 Ω Full - - 4 Ω RON Flatness, RFLAT(ON) V+ = 13.2V, ICOM = 1.0mA, VNO or VNC = 3V, 6V, 9V, Note 7 Ω NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 13V, VCOM = 1V, 12V, VNO or VNC = 12V, 1V, Note 6 COM ON Leakage Current, ICOM(ON) V+ = 13V, VCOM = 1V, 12V, VNO or VNC = 1V, 12V Note 6 25 - 1.7 2 Full - - 3 Ω 25 -0.2 - 0.2 nA Full -2.5 - 2.5 nA 25 -0.4 - 0.4 nA Full -5 - 5 nA Full 3.0 2.8 - V DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH Input Voltage Low, VINL Input Current, IINH, IINL Full - 2.2 0.8 V V+ = 13.2V, VIN = 0V or V+ Full -1 - 1 µA V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 25 - 40 50 ns Full - - 83 ns V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 25 - 27 35 ns Full - - 40 ns DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD V+ = 13.2V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 3 Full 5 20 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 12 14 pC NO OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 30 - pF OFF Isolation RL = 50Ω, CL = 15pF, f = 1MHz, VNO or VNC = 1VRMS, See Figures 4 and 6 25 - 71 - dB Crosstalk, Note 8 25 - -92 - dB Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz 25 - 59 - dB 25 -1 0.01 1 µA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 13V, VIN = 0V or V+, Switch On or Off Negative Supply Current, I- 6 Full -1 - 1 µA 25 -1 0.01 1 µA Full -1 - 1 µA ISL43240 Test Circuits and Waveforms tr < 20ns tf < 20ns 3V LOGIC INPUT 50% V+ C VNC 0V tON NC tON VNO SWITCH OUTPUT 75% SWITCH INPUTS CL 35pF RL 300Ω GND 25% tOFF VOUT IN 75% 25% VNC COM NO VOUT VNO C C LOGIC INPUT tOFF V- Logic input waveform is inverted for switches that have the opposite logic sense. C Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------------R L + R ( ON ) FIGURE 1A. MEASUREMENT POINTS FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES V+ SWITCH OUTPUT VOUT ∆VOUT RG C COM VOUT NO or NC 3V LOGIC INPUT ON ON VG OFF GND IN CL 0V C Q = ∆VOUT x CL V- Logic input waveform is inverted for switches that have the opposite logic sense. LOGIC INPUT Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2. CHARGE INJECTION V+ 3V C C LOGIC INPUT VNX 0V NO VOUT COM NC SWITCH OUTPUT VOUT 80% LOGIC INPUT 0V tD RL 300Ω IN GND Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE TIME 7 FIGURE 3B. TEST CIRCUIT CL 35pF ISL43240 Test Circuits and Waveforms (Continued) V+ V+ C C RON = V1/1mA SIGNAL GENERATOR NO or NC NO or NC VNX 0V or 2.4V IN 1mA COM ANALYZER 0.8V or 2.4V IN V1 COM GND GND RL C C V- V- Repeat test for all switches. Repeat test for all switches. FIGURE 5. RON TEST CIRCUIT FIGURE 4. OFF ISOLATION TEST CIRCUIT V+ V+ C SIGNAL GENERATOR NO1 or NC1 50Ω COM1 NO or NC IN1 IN 0V or 2.4V IN2 0V or 2.4V COM2 ANALYZER NO CONNECTION NO2 or NC2 GND 0V or 2.4V IMPEDANCE ANALYZER COM GND RL C V- FIGURE 6. CROSSTALK TEST CIRCUIT Detailed Description The ISL43240 quad analog switches offer precise switching capability from a bipolar ±2V to ±6V or a single 2V to 12V supply with low on-resistance (18Ω) and high speed operation (tON = 52ns, tOFF = 40ns). The devices are especially well suited for portable battery powered equipment thanks to the low operating supply voltage (2V), low power consumption (5µW), low leakage currents (5nA max). High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. Supply Sequencing And Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to V- (see 8 V- FIGURE 7. CAPACITANCE TEST CIRCUIT Figure 8). To prevent forward biasing these diodes, V+ and V- must be applied before any input signals, and input signal voltages must remain between V+ and V-. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above V-. ISL43240 The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTECTION DIODE V+ High-Frequency Performance OPTIONAL PROTECTION RESISTOR INX VNO or NC VCOM VOPTIONAL PROTECTION DIODE FIGURE 8. OVERVOLTAGE PROTECTION Power-Supply Considerations The ISL43240 construction is typical of most CMOS analog switches, in that they have three supply pins: V+, V-, and GND. V+ and V- drive the internal CMOS switches and set their analog voltage limits, so there are no connections between the analog signal path and GND. Unlike switches with a 13V maximum supply voltage, the ISL43240 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies (±6V or 12V single supply), as well as room for overshoot and noise spikes. This family of switches performs equally well when operated with bipolar or single voltage supplies. The minimum recommended supply voltage is 2V or ±2V. It is important to note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched V+ and V- signals to drive the analog switch gate terminals. Logic-Level Thresholds V+ and GND power the internal logic stages, so V- has no affect on logic thresholds. This switch family is TTL compatible (0.8V and 2.4V) over a V+ supply range of 2.5V to 10V (see Figure 17). At 12V the VIH level is about 2.8V. For best results with a 12V supply, use a logic family the provides a VOH greater than 3V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails (see Figure 18). Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. The 9 ISL43240 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0V to V+). For example driving the device with 3V logic (0V to 3V) while operating with dual or single 5V supplies the device draws only 10µA of current (see Figure 18 for VIN = 3V). Similiar devices of competitors can draw 8 times this amount of current. In 50Ω systems, signal response is reasonably flat even past 200MHz (see Figure 19). Figure 19 also illustrates that the frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch’s input to its output. Off Isolation is the resistance to this feedthrough, while Crosstalk indicates the amount of feedthrough from one switch to another. Figure 20 details the high Off Isolation and Crosstalk rejection provided by this switch. At 10MHz, off isolation is about 50dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and V-. One of these diodes conducts if any analog signal exceeds V+ or V-. Virtually all the analog leakage current comes from the ESD diodes to V+ or V-. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or V- and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and V- pins constitutes the analog-signalpath leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and GND. ISL43240 Typical Performance Curves TA = 25oC, Unless Otherwise Specified 25 70 VCOM = (V+) - 1V ICOM = 1mA 25oC -40oC 85oC 25oC 25oC -40oC 4 5 6 7 8 V+ (V) 9 10 11 12 13 45 ICOM = 1mA VS = ±2V 85oC 35 -40oC 85oC V+ = 5V 25 25oC V- = 0V 20 -40oC 85oC V+ = 12V 25oC V- = 0V -40oC 0 1 2 3 4 5 6 7 VCOM (V) 8 9 10 11 12 15 25oC 30 10 25 V+ = 12V -40oC 20 35 VS = ±3V 85oC 25 25oC 20 VS = ±5V -40oC 15 10 25 20 V+ = 3V 0 VS = ±5V 85oC 25oC V+ = 5V 5 Q (pC) 30 RON (Ω) 25oC 30 ICOM = 1mA V- = 0V FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE FIGURE 9. ON RESISTANCE vs POSITIVE SUPPLY VOLTAGE 40 40 15 20 18 16 14 12 10 8 V- = 0V 3 85oC 30 -40oC 2 50 20 35 V- = -3V 85oC V+ = 3V 60 RON (Ω) RON (Ω) 15 10 35 30 25 20 15 10 200 150 125 100 75 50 25 0 V- = -5V 85oC 20 -5 15 -40oC 10 -10 5 -5 -4 -3 -2 -1 0 1 2 3 4 -5 5 -2.5 0 VCOM (V) 2.5 5 VCOM (V) 7.5 10 12.5 FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE 50 300 VCOM = (V+) - 1V VCOM = (V+) - 1V V- = 0V V- = 0V 250 40 tOFF (ns) tON (ns) 200 85oC 150 25oC 85oC 30 25oC 100 20 -40oC -40oC 50 0 10 2 3 4 5 6 7 8 9 10 11 12 V+ (V) FIGURE 13. TURN - ON TIME vs POSITIVE SUPPLY VOLTAGE 10 2 3 4 5 6 7 8 9 10 11 12 V+ (V) FIGURE 14. TURN - OFF TIME vs POSITIVE SUPPLY VOLTAGE ISL43240 Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued) 150 300 -40oC 250 200 -40oC VCOM = (V+) - 1V V- = -5V 100 25oC 150 25oC 100 tOFF (ns) tON (ns) -40oC 0 250 V- = -3V 200 100 0 300 50 150 2 50 3 4 5 6 7 V+ (V) 8 9 10 11 3.0 VINH 2 4 5 6 7 V+ (V) 8 9 10 11 12 70 V- = -5V to 0V V+ = +5V 60 85oC 2.0 3 FIGURE 16. TURN - OFF TIME vs POSITIVE SUPPLY VOLTAGE -40oC 25oC 2.5 85oC 0 12 FIGURE 15. TURN - ON TIME vs POSITIVE SUPPLY VOLTAGE 1.5 50 1.0 V- = 0V to -5V I+CC (µA) 0.5 3.0 VINL -40oC 2.5 25oC 2.0 40 30 20 1.5 10 1.0 85oC V- = 0V to -5V 0.5 2 3 4 6 5 7 8 V+ (V) 9 10 11 12 0 0 13 0.5 1 1.5 2 2.5 3 3.5 4 4.5 FIGURE 17. DIGITAL SWITCHING POINT vs POSITIVE SUPPLY VOLTAGE FIGURE 18. POSITIVE SUPPLY CURRENT vs DIGITAL INPUT VOLTAGE -10 VS = ±2V or V+ = 5V (VIN = 4VP-P) 0 VS = ±5V (VIN = 5VP-P) GAIN VS = ±2V (VIN = 4VP-P) V+ = 5V (VIN = 4VP-P) VS = ±5V (VIN = 5VP-P) V+ = 2.7V (VIN = 2VP-P) 45 90 135 180 RL = 50Ω 1 10 100 FREQUENCY (MHz) FIGURE 19. FREQUENCY RESPONSE 11 600 PHASE (DEGREES) 0 CROSSTALK (dB) -3 PHASE 10 V+ = 3V to 12V or -20 VS = ±2V to ±5V RL = 50Ω -30 V+ = 2.7V (VIN = 2VP-P) 3 5 VIN (V) 20 30 -40 40 -50 50 -60 60 ISOLATION -70 70 -80 80 CROSSTALK -90 90 ALL HOSTILE CROSSTALK -100 -110 1k 100 10k 100k 1M 10M 110 100M 500M FREQUENCY (Hz) FIGURE 20. CROSSTALK AND OFF ISOLATION OFF ISOLATION (dB) VINH AND VINL (V) 25oC 100 85oC -40oC 0 V- = -3V -40oC 200 25oC 85oC -40oC 250 -40oC 150 NORMALIZED GAIN (dB) 25oC 50 85oC 50 VCOM = (V+) - 1V V- = -5V 25oC ISL43240 Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued) Die Characteristics V+ = 3V to 12V or VS = ±2V to ±5V RL = 50Ω 0 SUBSTRATE POTENTIAL (POWERED UP): V- VIN = 1VP-P TRANSISTOR COUNT: PSRR (dB) 10 ISL43240: 418 20 PROCESS: 30 Si Gate CMOS -PSRR, SWITCH ON 40 50 60 +PSRR, SWITCH ON 70 0.3 1 10 100 FREQUENCY (MHz) FIGURE 21. ±PSRR vs FREQUENCY 12 1000 ISL43240 Shrink Small Outline Plastic Packages (SSOP) M20.209 (JEDEC MO-150-AE ISSUE B) N 20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E -B1 2 3 0.25 0.010 SEATING PLANE -A- SYMBOL GAUGE PLANE A D -C- α e C 0.10(0.004) C A M B S MILLIMETERS MIN MAX NOTES A 0.068 0.078 1.73 1.99 0.002 0.008’ 0.05 0.21 A2 0.066 0.070’ 1.68 1.78 B 0.010’ 0.015 0.25 0.38 C 0.004 0.008 0.09 0.20’ D 0.278 0.289 7.07 7.33 3 E 0.205 0.212 5.20’ 5.38 4 0.026 BSC 0.301 0.311 7.65 7.90’ L 0.025 0.037 0.63 0.95 8 deg. 0 deg. N 20 0 deg. 9 0.65 BSC H α NOTES: MAX A1 e A2 A1 B 0.25(0.010) M L MIN 6 20 7 8 deg. Rev. 3 11/02 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 13 ISL43240 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L20.4x4 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VGGD-1 ISSUE C) MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A 0.80 0.90 1.00 - A1 - - 0.05 - A2 - - 1.00 A3 b 0.18 D 0.23 9 0.30 5, 8 4.00 BSC D1 D2 9 0.20 REF - 3.75 BSC 1.95 2.10 9 2.25 7, 8 E 4.00 BSC - E1 3.75 BSC 9 E2 1.95 e 2.10 2.25 7, 8 0.50 BSC - k 0.25 - - - L 0.35 0.60 0.75 8 L1 - - 0.15 10 N 20 Nd 2 5 3 Ne 5 5 3 P - - 0.60 9 θ - - 12 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14