ISL6521 ® Data Sheet February 8, 2005 PWM Buck DC-DC and Triple Linear Power Controller Features The ISL6521 provides the power control and protection for four output voltages in low-voltage, high-performance applications. The IC integrates a voltage-mode PWM controller and three linear controllers, as well as monitoring and protection functions into a 16-lead SOIC package. The PWM controller is intended to regulate the low voltage supply that requires the greatest amount of current (usually the core voltage for the FPGA, ASIC, or processor) with a synchronous rectified buck converter. The linears are intended to regulate other system voltages, such as I/O (input/output) and memory circuits. Both the switching regulator and linear voltage reference provide ±2% of static regulation over line, load, and temperature ranges. All outputs are user-adjustable by means of an external resistor divider. All linear controllers can supply up to 120mA with no external pass devices. Employing bipolar NPNs for the pass transistors, the linear regulators can achieve output currents of 3A or higher with proper device selection. The ISL6521 monitors all the output voltages. The PWM controller’s adjustable overcurrent function monitors the output current by using the voltage drop across the upper MOSFET’s rDS(ON). The linear regulator outputs are monitored via the FB pins for undervoltage events. Ordering Information PART NUMBER TEMP. RANGE (°C) • Provides 4 Regulated Voltages - Switching Regulator 20A Capable - Three Linear Regulators - Capable of 120mA - Capable of up to 3A with an External Transistor • Externally Resistor-Adjustable Outputs • Simple Single-Loop Control Design - Voltage-Mode PWM Control • Fast PWM Converter Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Ratio • Excellent Output Voltage Regulation - All Outputs: ±2% Over Temperature • Overcurrent Fault Monitors - Switching Regulator Does Not Require Extra Current Sensing Element, Uses MOSFET’s rDS(ON) • Small Converter Size - 300kHz Constant Frequency Operation - Small External Component Count • Commercial and Industrial Temperature Range Support • Pb-free Available (RoHS Compliant) Applications PACKAGE PKG. DWG. # ISL6521CBZ (Note) 0 to 70 16 Ld SOIC (Pb-free) M16.15 ISL6521CBZ-T (Note) 0 to 70 16 Ld SOIC (Pb-free) M16.15 ISL6521IBZ (Note) -40 to 85 16 Ld SOIC (Pb-free) M16.15 ISL6521IBZ-T (Note) -40 to 85 16 Ld SOIC (Pb-free) M16.15 ISL6521EVAL1 Evaluation Board NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. • FPGA and PowerPC™-based boards • General purpose, low voltage power supplies Related Literature • Technical Support Document AG0001, “Power Management Application Guide for Xilinx FPGAs” • Technical Support Document AG0002, “Power Management Application Guide for Altera FPGAs” • Technical Support Document AG0005, “Power Management Application Guide for Actel FPGAs” Pinout ISL6521 (SOIC) TOP VIEW DRIVE2 1 FB2 2 FB 3 16 FB3 15 DRIVE3 14 FB4 COMP 4 13 DRIVE4 GND 5 12 OCSET PHASE 6 1 FN9148.2 11 VCC BOOT 7 10 LGATE UGATE 8 9 PGND CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. Block Diagram OCSET FB3 VCC VCC 2 EA3 + - EA4 DRIVE4 40µA + DRIVE3 POWER-ON RESET (POR) - x 0.70 + - UV3 + - + UV4 0.8V BOOT INHIBIT/SOFT-START + UGATE - DRIVE2 DRIVE1 SOFT-START AND FAULT LOGIC ++ EA2 OCC -- + - FB2 UV2 + + - EA1 - PWM PHASE GATE CONTROL COMP1 VCC LGATE GND OSCILLATOR SYNC DRIVE FB COMP PGND ISL6521 FB4 ISL6521 Typical Applications High Output Current PWM Converter With Simple Triple Linears Regulators LIN +5V + VOUT2 2.5V 120mA CIN VCC BOOT DRIVE2 + CBOOT FB2 COUT2 Rs2 OCSET Rp2 UGATE VOUT3 1.8V 120mA Q1 DRIVE3 + ISL6521 FB3 COUT3 Rs3 LGATE VOUT1 1.5V LOUT1 PHASE + Q2 CR1 PGND COUT1 Rp3 FB VOUT4 3.3V 120mA Rs1 COMP DRIVE4 + FB4 COUT4 Rs4 Rp4 Rp1 GND High Output Current PWM Converter and Auxiliary 3.3V Linear Regulator LIN +5V + VOUT2 2.5V 120mA CIN VCC BOOT DRIVE2 + CBOOT FB2 COUT2 Rs2 OCSET Rp2 UGATE VOUT3 1.8V 120mA Q1 PHASE DRIVE3 + ISL6521 FB3 COUT3 Rs3 LGATE Q2 PGND Rp3 FB +5V COMP VOUT4 3.3V 3A Rs1 DRIVE4 Q3 FB4 + Rs4 COUT4 3 Rp4 GND Rp1 VOUT1 1.5V LOUT1 + CR1 COUT1 ISL6521 Absolute Maximum Ratings Thermal Information UGATE, BOOT. . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V VCC, PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V DRIVE, LGATE, all other pins . . . . . . . . GND - 0.3V to VCC + 0.3V Thermal Resistance (Typical, Note 1) θJA (°C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (SOIC - Lead Tips Only) Operating Conditions Supply Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10% Ambient Temperature Range ISL6521CBZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C ISL6521IBZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C Junction Temperature Range. . . . . . . . . . . . . . . . . . -40°C to 125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Operating Conditions: VCC = 5V, TA = 0°C to 70°C, Unless Otherwise Noted. Typical specifications are at TA = 25°C. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 5 - mA Rising VCC Threshold 4.25 - 4.51 V Falling VCC Threshold 3.74 - 4.0 V ISL6521CBZ 275 300 325 kHz ISL6521IBZ (-40°C to 85°C) 250 300 350 kHz VCC SUPPLY CURRENT Nominal Supply Current ICC UGATE, LGATE, and DRIVEx Open POWER-ON RESET OSCILLATOR AND SOFT-START Free Running Frequency FOSC Ramp Amplitude ∆VOSC - 1.5 - VP-P Soft-Start Interval TSS 6.25 6.83 7.40 ms REFERENCE VOLTAGE Reference Voltage (All Regulators) VREF All Outputs Voltage Regulation 0.780 0.800 0.820 V ISL6521CBZ -2.0 - +2.0 % ISL6521IBZ (-40°C to 85°C) -2.5 - +2.5 % VCC > 4.5V 100 120 - mA - 70 - % - 80 - dB 15 - - MHz COMP = 10pF - 6 - V/µs LINEAR REGULATORS (OUT2, OUT3, AND OUT4) Output Drive Current (All Linears) Undervoltage Level (VFB/VREF) VUV SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER DC Gain Gain-Bandwidth Product GBWP Slew Rate SR PWM CONTROLLER GATE DRIVERS UGATE Source IUGATE VCC = 5V, VUGATE = 2.5V - -1 - A UGATE Sink IUGATE VUGATE-PHASE = 2.5V - 1 - A LGATE Source ILGATE VCC = 5V, VLGATE = 2.5V - -1 - A LGATE Sink ILGATE VLGATE = 2.5V - 2 - A IOCSET ISL6521CBZ 34 40 46 µA 31.5 40 48 µA PROTECTION OCSET Current Source ISL6521IBZ (-40°C to 85°C) 4 ISL6521 Functional Pin Descriptions VCC (Pin 11) Provide a well decoupled 5V bias supply for the IC to this pin. This pin also provides the gate bias charge for the lower MOSFET controlled by the PWM section of the IC, as well as the drive current for the linear regulators. The voltage at this pin is monitored for Power-On Reset (POR) purposes. GND (Pin 5) Signal ground for the controller. All voltage levels are measured with respect to this pin. PGND (Pin 9) This is the power ground connection. Tie the source of the lower MOSFET of the synchronous PWM converter to this pin. BOOT (Pin 7) Floating bootstrap supply pin for the upper gate drive. The bootstrap capacitor provides the necessary charge to turn and hold the upper MOSFET on. Connect a suitable capacitor (0.47µF recommended) from this pin to PHASE. DRIVE2, 3, 4 (Pins 1, 15, 13) Connect these pins to the point of load or to the base terminals of external bipolar NPN transistors. These pins are each capable of providing 120mA of load current or drive current for the pass transistors. FB2, 3, 4 (Pins 2, 16, 14) Connect the output of the corresponding linear regulators to these pins through properly sized resistor dividers. The voltage at these pins is regulated to 0.8V. These pins are also monitored for undervoltage events. Quickly pulling and holding any of these pins above 1.25V (using diode-coupled logic devices) shuts off the respective regulators. Releasing these pins from the pull-up voltage initiates a soft-start sequence on the respective regulator. Description Operation The voltage at this pin is monitored for power-on reset (POR) purposes and pulling this pin below 1.25V with an open drain/collector device will shut down the switching controller. The ISL6521 monitors and precisely controls one synchronous PWM converter and three configurable linear regulators from a +5V bias input. The PWM controller is designed to regulate the core voltage of an embedded processor or simple down conversion for high current applications. The PWM controller drives two MOSFETs (Q1 and Q2) in a synchronous-rectified buck converter configuration and regulates the output voltage to a level programmed by a resistor divider. The linear controllers are designed to regulate three additional system voltages. Typically, these include any I/O, memory, or clock voltages that might be required. All three linear controllers support up to 120mA of load current without external pass devices or higher currents with external NPN bipolar transistors. PHASE (Pin 6) Initialization Connect this pin to the source of the PWM converter upper MOSFET. This pin is used to monitor the voltage drop across the upper MOSFET for overcurrent protection. The ISL6521 automatically initializes upon receipt of input power. The Power-On Reset (POR) function continually monitors the input bias supply voltage. The POR monitors the bias voltage at the VCC pin. The POR function initiates soft-start operation after the bias supply voltage exceeds its POR threshold. OCSET (Pin 12) Connect a resistor from this pin to the drain of the upper PWM MOSFET. This resistor, an internal 40µA current source (typical), and the upper MOSFET’s on-resistance set the converter overcurrent trip point. An overcurrent trip cycles the soft-start function. UGATE (Pin 8) Connect UGATE pin to the PWM converter’s upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. LGATE (Pin 10) This pin provides the gate drive for the synchronous rectifier lower MOSFET. Connect LGATE to the gate of the lower MOSFET. COMP and FB (Pins 4, 3) COMP and FB are the available external pins of the PWM converter error amplifier. The FB pin is the inverting input of the error amplifier. Similarly, the COMP pin is the error amplifier output. These pins are used to compensate the voltage-mode control feedback loop of the synchronous PWM converter. 5 Soft-Start The POR function initiates the soft-start sequence. The PWM error amplifier reference input is clamped to a level proportional to the soft-start voltage. As the soft-start voltage slews up, the PWM comparator generates PHASE pulses of increasing width that charge the output capacitor(s). Similarly, all linear regulators’ reference inputs are clamped to a voltage proportional to the soft-start voltage. The rampup of the internal soft-start function provides a controlled output voltage rise. Figure 1 shows the soft-start sequence for a typical application. At T0 the +5V bias voltage starts to ramp up crossing the 4.5V POR threshold at time T1. On the PWM section, the oscillator’s triangular waveform is compared to ISL6521 the clamped error amplifier output voltage. As the internal soft-start voltage increases, the pulse-width on the PHASE pin increases to reach its steady-state duty cycle at time T2. Also at time T2, the error amplifier references of the linear controllers, ramp to their final value bringing all outputs within regulation limits. three soft-start periods, the fourth cycle initiates a ramp-up of this linear output at time T3. One soft-start period after T3, the linear output is within regulation limits. UV glitches less than 1µs (typically) in duration are ignored. VOUT4 (3.3V) VOUT3 (1.8V) +5V VOUT1 (1.5V) VOUT2 (2.5V) VOUT4 (3.3V) 0V (0.5V/DIV.) 0V VOUT2 (2.5V) (1V/DIV) SOFT-START FUNCTION VOUT3 (1.8V) VOUT1 (1.5V) UV MONITORING VOUT1 INACTIVE ACTIVE 0V (0.5V/DIV) T0 T1 VOUT2 T2 TIME FIGURE 1. SOFT-START INTERVAL T0 T1 TIME T2 T3 T4 FIGURE 2. OVERCURRENT/UNDERVOLTAGE PROTECTION RESPONSE Overcurrent Protection All outputs are protected against excessive overcurrents. The PWM controller uses the upper MOSFET’s on-resistance, rDS(ON) to monitor the current for protection against a shorted output. All linear controllers monitor their respective FB pins for undervoltage events to protect against excessive currents. A sustained overload (undervoltage on linears or overcurrent on the PWM) on any output results in an independent shutdown of the respective output, followed by subsequent individual re-start attempts performed at an interval equivalent to 3 soft-start intervals. Figure 2 describes the protection feature. At time T0, an overcurrent event sensed across the switching regulator’s upper MOSFET (rDS(ON) sensing) triggers a shutdown of the VOUT1 output. As a result, its internal soft-start initiates a number of soft-start cycles. After a three-cycle wait, the fourth soft-start initiates a ramp-up attempt of the failed output, at time T2, bringing the output in regulation at time T4. To exemplify a UV event on one of the linears, at time T1, the clock regulator (VOUT2) is also subjected to an overcurrent event, resulting in a UV condition. Similarly, after 6 Overcurrent protection is performed on the synchronous switching regulator on a cycle-by-cycle basis. OC monitoring is active as long as the regulator is operational. Since the overcurrent protection on the linear regulators is performed through undervoltage monitoring at the feedback pins (FB2, FB3, and FB4), this feature is activated approximately 25% into the soft-start interval (see Figure 2). A resistor (ROCSET) programs the overcurrent trip level for the PWM converter. As shown in Figure 3, the internal 40µA current sink (IOCSET) develops a voltage across ROCSET (VSET) that is referenced to VIN . The DRIVE signal enables the overcurrent comparator (OCC). When the voltage across the upper MOSFET (VDS(ON)) exceeds VSET, the overcurrent comparator trips to set the overcurrent latch. Both VSET and VDS(ON) are referenced to VIN and a small capacitor across ROCSET helps VOCSET track the variations of VIN due to MOSFET switching. The overcurrent function will trip at a peak inductor current (IPEAK) determined by: I OCSET × R OCSET I PEAK = --------------------------------------------------r DS ( ON ) ISL6521 The OC trip point varies with MOSFET’s rDS(ON) temperature variations. To avoid overcurrent tripping in the normal operating load range, determine the ROCSET resistor from the equation above with: 1. The maximum rDS(ON) at the highest junction temperature. 2. The minimum IOCSET from the specification table. 3. Determine IPEAK for IPEAK > IOUT(MAX) + (∆I) / 2, where ∆I is the output inductor ripple current. OVERCURRENT TRIP: V >V DS SET i ¥r >I ¥R D DS ( ON ) OCSET OCSET VIN = +5V ROCSET OCSET IOCSET 40µA VSET + UGATE OC + To ensure the parallel combination of the feedback resistors equals a certain chosen value, RFB, use the following equations: R S × V FB R P = -------------------------------- , where V OUT – V FB VOUT - the desired output voltage, V = V –V PHASE IN DS V = V –V OCSET IN SET GATE CONTROL PWM + VDS(ON) PHASE - OCC RS × RP --------------------- < 5kΩ RS + RP V OUT R S = ---------------- × R FB V FB iD VCC DRIVE Output voltage selection on the linear regulators is set by means of external resistor dividers as shown in Figure 4. The two resistors used to set the voltage on each of the three linear regulators have to meet the following criteria: their value while in a parallel connection has to be less than 5kΩ, or otherwise said, the following relationship has to be met: VFB - feedback (reference) voltage, 0.8V. Application Guidelines FIGURE 3. OVERCURRENT DETECTION For an equation for the ripple current see the section under component guidelines titled ‘Output Inductor Selection’. Output Voltage Selection The output voltage of the PWM converter can be resistorprogrammed to any level between VIN and 0.8V. However, since the value of RS1 is affecting the values of the rest of the compensation components, it is advisable its value is kept between 2kΩ and 5kΩ. +5VIN DRIVE3 Q3 VOUT3 FB3 COUT3 + RS3 RP3 VOUT4 COUT4 ISL6521 DRIVE4 + FB4 RS4 RP4 Soft-Start Interval The soft-start function controls the output voltages rate of rise to limit the current surge at start-up. The soft-start function is integrated on the chip and the soft-start interval is fixed. PWM Controller Feedback Compensation The PWM controller uses voltage-mode control for output regulation. This section highlights the design consideration for a PWM voltage-mode controller. Apply the methods and considerations only to the PWM controller. Figure 5 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the reference voltage level, 0.8V. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A . This function is dominated by a DC Gain, given by VIN/VOSC , and shaped by the output filter, with a double pole break frequency at FLC and a zero at FESR . Modulator Break Frequency Equations R S V OUT = 0.8 × 1 + -------- R P 1 F LC = ---------------------------------------2π × L O × C O FIGURE 4. ADJUSTING THE OUTPUT VOLTAGE OF ANY OF THE FOUR REGULATORS (OUTPUTS 3 AND 4 PICTURED) 7 1 F ESR = ----------------------------------------2π × ESR × C O The compensation network consists of the error amplifier (internal to the ISL6521) and the impedance networks ZIN ISL6521 VIN DRIVER1 OSC PWM COMP LO SYNC DRIVER + ∆ VOSC PHASE CO + ESR (PARASITIC) ZFB VE/A VOUT ZIN + 0.8V ERROR AMP DETAILED COMPENSATION COMPONENTS ZFB C2 C1 VOUT ZIN C3 R2 R3 Figure 6 shows an asymptotic plot of the DC-DC converter’s gain vs. frequency. The actual Modulator Gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown in Figure 5. Using the above guidelines should yield a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 6 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. RS1 COMP FB + ISL6521 FZ1 RP1 FZ2 FP1 FP2 100 OPEN LOOP ERROR AMP GAIN V IN 20 log ------------ V PP 80 0.8V FIGURE 5. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN and ZFB . The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network’s poles, zeros and gain to the components (R1 , R2 , R3 , C1 , C2 , and C3) in Figure 5. Use these guidelines for locating the poles and zeros of the compensation network: GAIN (dB) 60 40 COMPENSATION GAIN 20 0 -20 R2 20 log ------------- R S1 -40 MODULATOR GAIN -60 10 100 FLC 1K CLOSED LOOP GAIN FESR 10K 100K 1M 10M FREQUENCY (Hz) FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN 1. Pick Gain (R2/R1) for desired converter bandwidth 2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC) Individual Output Disable 3. Place 2ND Zero at Filter’s Double Pole 4. Place 1ST Pole at the ESR Zero The PWM and linear controllers can independently be shutdown. 5. Place 2ND Pole at Half the Switching Frequency To disable the switching regulator, use an open-drain or open-collector device capable of pulling the OCSET pin (with the attached ROCSET pull-up) below 1.25V. To minimize the possibility of OC trips at levels different than predicted, a COCSET capacitor with a value of an order of magnitude larger than the output capacitance of the pull-down device, has to be used in parallel with ROCSET (1nF recommended). Upon turn-off of the pull-down device, the switching regulator undergoes a soft-start cycle. 6. Check Gain against Error Amplifier’s Open-Loop Gain 7. Estimate Phase Margin - Repeat if Necessary Compensation Break Frequency Equations 1 F Z1 = ----------------------------------2π × R 2 × C1 1 F Z2 = --------------------------------------------------------2π × ( R S1 + R3 ) × C3 1 F P1 = ------------------------------------------------------C1 × C2 2π × R 2 × ---------------------- C1 + C2 1 F P2 = ----------------------------------2π × R 3 × C3 8 To disable a particular linear controller, pull and hold the respective FB pin above a typical threshold of 1.25V. One way to achieve this task is by using a logic gate coupled ISL6521 Layout Considerations MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. Careful component layout and printed circuit design minimizes the voltage spikes in the converter. Consider, as an example, the turnoff transition of the upper PWM MOSFET. Prior to turn-off, the upper MOSFET was carrying the full load current. During the turn-off, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET or Schottky diode. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. There are two sets of critical components in a DC-DC converter using an ISL6521 controller. The switching power components are the most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bypass current. The power components and the controller IC should be placed first. Locate the input capacitors, especially the highfrequency ceramic decoupling capacitors, close to the power switches. Locate the output inductor and output capacitors 9 LIN +5VIN CIN + +12V CVCC VCC GND OCSET ROCSET Q1 LOUT UGATE VOUT2 VOUT1 PHASE + COUT2 DRIVE2 Q3 VOUT3 + COCSET LGATE COUT1 Q2 + CR1 VOUT4 ISL6521 COUT3 DRIVE3 DRIVE4 Q4 PGND LOAD If the collector voltage to a linear regulator pass transistor (Q3, Q4, or Q5 shown in Figure 7) is lost, the respective regulator has to be shut down by pulling high its FB pin. This measure is necessary in order to avoid possible damage to the ISL6521 as a result of overheating. Overheating can occur in such situations due to sheer power dissipation inside the chip’s linear drivers. A multi-layer printed circuit board is recommended. Figure 7 shows the connections of the critical components in the converter. Note that the capacitors CIN and COUT each can represent numerous physical capacitors. Dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the PHASE nodes, but do not unnecessarily oversize these particular islands. Since the PHASE nodes are subjected to very high dv/dt voltages, the stray capacitor formed between these islands and the surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal wiring. The wiring traces from the control IC to the MOSFET gate and source should be sized to carry 2A peak currents. Q5 + COUT4 LOAD Important Note When Using External Pass Devices The critical small signal components include the bypass capacitor for VCC and the feedback resistors . Locate these components close to their connecting pins on the control IC. LOAD RS × RP 2kΩ < ---------------------- < 5kΩ RS + RP between the MOSFETs and the load. Locate the PWM controller close to the MOSFETs. LOAD through a small-signal diode. The diode should be placed as close to the FB pin as possible to minimize stray capacitance to this pin. Upon turn-off of the pull-up device, the respective output undergoes a soft-start cycle, bringing the output within regulation limits. On regulators implementing this feature, the parallel combination of the feedback resistors has to be sufficiently high to allow ease of driving from the external device. Considering the other restriction applying to the upper range of this resistor combination (see ‘Output Voltage Selection’ paragraph), it is recommended the values of the feedback resistors on the linear regulator output meet the following constraint: +3.3VIN KEY ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT OR POWER PLANE LAYER VIA CONNECTION TO GROUND PLANE FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS ISL6521 Component Selection Guidelines Output Capacitor Selection The output capacitors for each output have unique requirements. In general, the output capacitors should be selected to meet the dynamic load regulation requirements. Additionally, the PWM converters require an output capacitor to filter the current ripple. The load transient for some embedded processors requires high quality capacitors to supply the high slew rate (di/dt) current demands. PWM Output Capacitors High performance embedded processors can produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient current and slow the load rate-ofchange seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR determines the output ripple voltage and the initial voltage drop following a high slew-rate transient’s edge. An aluminum electrolytic capacitor’s ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. Linear Output Capacitors The output capacitors for the linear regulators provide dynamic load current. The linear controllers use dominant pole compensation integrated into the error amplifier and are insensitive to output capacitor selection. Output capacitors should be selected for transient load regulation. PWM Output Inductor Selection The PWM converter requires an output inductor. The output inductor is selected to meet the output voltage ripple requirements and sets the converter’s response time to a load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations: 10 V IN – V OUT V OUT ∆I = -------------------------------- × ---------------FS × L V IN ∆V OUT = ∆I × ESR Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values increase the converter’s response time to a load transient. One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6521 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time interval required to slew the inductor current from an initial current value to the post-transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: L O × I TRAN t RISE = ------------------------------V IN – V OUT L O × I TRAN t FALL = -----------------------------V OUT where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Input Capacitor Selection The important parameters for the bulk input capacitors are the voltage rating and the RMS current rating. For reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 of the summation of the DC load current. Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use ceramic capacitance for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedances. For a through-hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. ISL6521 Transistors Selection/Considerations The ISL6521 can employ up to 5 external transistors. Two N-channel MOSFETs are used in the synchronous-rectified buck topology of PWM converter. The linear controllers can each drive an NPN bipolar transistor as a pass element. All these transistors should be selected based upon rDS(ON) , current gain, saturation voltages, gate/base supply requirements, and thermal management considerations. PWM MOSFET Selection and Considerations In high-current PWM applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. These losses are distributed between the upper and lower MOSFETs according to duty factor (see the equations below). The conduction losses are the main component of power dissipation for the lower MOSFETs. Only the upper MOSFET has significant switching losses, since the lower device turns on and off into near zero voltage. The equations below assume linear voltage-current transitions and do not model power loss due to the reverserecovery of the lower MOSFET’s body diode. The gatecharge losses are dissipated by the ISL6521 and don't heat the MOSFETs. However, large gate-charge increases the switching time, tSW which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. 2 I O × r DS ( ON ) × V OUT I O × V IN × t SW × F S P UPPER = ----------------------------------------------------------- + ---------------------------------------------------V IN 2 2 I O × r DS ( ON ) × ( V IN – V OUT ) P LOWER = -------------------------------------------------------------------------------V IN Given the reduced available gate bias voltage (5V) logiclevel or sub-logic-level transistors have to be used for both N-MOSFETs. Caution should be exercised with devices exhibiting very low VGS(ON) characteristics, as the low gate threshold could be conducive to some shoot-through (due to the Miller effect), in spite of the counteracting circuitry present aboard the ISL6521. 11 +5V OR LESS +5V VCC BOOT + CBOOT ISL6521 UGATE Q1 PHASE NOTE: VGS ≈ VCC -0.5V VCC - + LGATE Q2 CR1 PGND NOTE: VGS ≈ VCC GND FIGURE 8. MOSFET GATE BIAS Rectifier CR1 is a clamp that catches the negative inductor swing during the dead time between the turn off of the lower MOSFET and the turn on of the upper MOSFET. The diode must be a Schottky type to prevent the lossy parasitic MOSFET body diode from conducting. It is acceptable to omit the diode and let the body diode of the lower MOSFET clamp the negative inductor swing, providing the body diode is fast enough to avoid excessive negative voltage swings at the PHASE pin. The diode's rated reverse breakdown voltage must be greater than the maximum input voltage. Linear Controller Transistor Selection The main criteria for selection of transistors for the linear regulators is package selection for efficient removal of heat. The power dissipated in a linear regulator is: P LINEAR = I O × ( V IN – V OUT ) Select a package and heatsink that maintains the junction temperature below the rating with a the maximum expected ambient temperature. If bipolar NPN transistors have to be used with the linear controllers, insure the current gain at the given operating VCE is sufficiently large to provide the desired maximum output load current when the base is fed with the minimum driver output current. ISL6521 ISL6521 DC-DC Converter Application Circuit Figure 9 shows a power management application circuit for powering an embedded processor. The circuit provides the processor core voltage (VCORE), the I/O voltage (VI/O), the clock voltage (VCLOCK), and memory voltage (VMEMORY) from a single +5V supply. A component selection table provides the recommended component values at various load current steps. Intersil’s portfolio of multiple output controllers continues to expand with new selections to better fit our customer’s needs. Refer to our website for updated information: www.intersil.com +5V C1 C7 0.1µF D1 MA732 VCC ISL6521 Q3 FB2 + C11 10µF R6 12.7kΩ C8 BOOT OCSET LINEAR REGULATOR VI/O 2.5V DRIVE2 R5 C3 0.47µF UGATE Q1 C12 10µF C9 100µF R8 18.2kΩ SWITCHING REGULATOR FB3 LINEAR REGULATOR DRIVE3 R9 5.9kΩ Q2 FB4 C14 + R11 C13 + C10 10µF 2.0kΩ FB C5 COMP R1 C14 R12 R2 LINEAR REGULATOR + DRIVE4 Q4 VMEMORY C4 PGND C6 +5V VCORE 1.5V LOUT PHASE R7 5.9kΩ LGATE VCLOCK 3.3V C2 1µF + R3 2.26kΩ R10 GND FIGURE 9. POWER SUPPLY APPLICATION CIRCUIT FOR AN EMBEDDED PROCESSOR Component Selection Table ICC_INT LOUT Q1 Q2 Q3 C1 C4 5A 7.5µH Pulse P1172.103 IRF7910 IRF7910 FZT649 (1A or less) 1 x 1000µF 10MBZ1000M 10x12.5 1 x 1200µF 6.3MBZ1200M 8x16 10A 4.8µH Sumida CDEP134 IRF7460 IRF7476 2SD1802 (3A or less) 2 x 1000µF 10MBZ1000M 10x12.5 2 x 1800µF 6.3MBZ1800M 10x16 15A 1.6µH Sumida CDEP134 IRF7821 IRF7832 2SD1802 (3A or less) 2 x 1800µF 10MBZ1800M 10x20 2 x 3300µF 6.3MBZ3300M 10x23 20A 0.5µH Pulse PG0006.601 2x IRF7821 2x IRF7832 2SD1802 (3A or less) 3 x 1500µF 10MBZ1500M 10x16 3 x 3300µF 6.3MBZ3300M10x23 12 ISL6521 Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INCHES INDEX AREA H 0.25(0.010) M B M SYMBOL E -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- e B 0.25(0.010) M C 0.10(0.004) C A M B S MILLIMETERS MAX MIN MAX NOTES A 0.053 0.069 1.35 1.75 - A1 0.004 0.010 0.10 0.25 - B 0.014 0.019 0.35 0.49 9 C 0.007 0.010 0.19 0.25 - D 0.386 0.394 9.80 10.00 3 E 0.150 0.157 3.80 4.00 4 e µα A1 MIN 0.050 BSC 1.27 BSC - H 0.228 0.244 5.80 6.20 - h 0.010 0.020 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α 16 0o 16 7 8o Rev. 1 02/02 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 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