ISL6528 ® Data Sheet December 28, 2004 Dual Regulator - Standard Buck PWM and Linear Power Controller FN9038.3 Features The ISL6528 provides the power control and protection for two output voltages in high-performance graphics cards and other embedded processor applications. The dual-output controller drives an N-Channel MOSFET in a standard buck topology and a NPN pass transistor in a linear configuration. The ISL6528 provides both a regulated high current, low voltage supply and an independent, lower current supply integrated in an 8-lead SOIC package. The controller is ideal for graphics card applications where both graphics processing unit (GPU) and memory supplies are required. • Pb-Free Available (RoHS Compliant) • Provides two regulated voltages - One standard buck PWM - One linear controller • Small converter size - 600kHz constant frequency operation - Small external component count • Excellent output voltage regulation - Both outputs: ±2% over temperature • Single 5V bias and bootstrap supply The standard buck converter is a simple, single feedback loop, voltage-mode control with fast transient response. Both the switching regulator and linear regulator provide a maximum static regulation tolerance of ±2% over line, load, and temperature ranges. Each output is user-adjustable by means of external resistors. • Output voltage range: 0.8V to 3.3V An integrated soft-start feature brings both supplies into regulation in a controlled manner. Each output is monitored via the FB pins for undervoltage events. If either output drops below 52.5% of the internal reference voltage, both regulators are shutdown. • Linear controller drives bipolar linear pass transistor Ordering Information • Graphics–GPU and memory supplies PART NUMBER TEMP. RANGE (oC) ISL6528CB ISL6528CB-T ISL6528CBZ (See Note) 0 to 70 PACKAGE 8 Ld SOIC PKG. DWG. # M8.15 8Ld SOIC Tape and Reel 0 to 70 8 Ld SOIC (Pb-free) ISL6528CBZ-T (See Note) 8Ld SOIC Tape and Reel (Pb-free) ISL6528EVAL1 Evaluation Board M8.15 • Simple single-loop voltage-mode PWM control design • Fast PWM converter transient response - High-bandwidth error amplifier - Full 0–100% duty ratio • Fully-adjustable outputs • Undervoltage fault monitoring on both outputs Applications • ASIC power supplies • Embedded processor and I/O supplies • DSP supplies Related Literature • Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinout ISL6528 (SOIC) TOP VIEW GND 1 8 UGATE VCC 2 7 BOOT DRIVE2 3 6 COMP FB2 4 1 5 FB CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Block Diagram VCC 2 POWER-ON 1.28V RESET (POR) SHUTDOWN FB2 EA2 BOOT RESTART SOFTSTART AND FAULT LOGIC DRIVE1 UGATE DRIVE2 INHIBIT SOFT-START INHIBIT SOFT-START PWM UV2 EA1 COMP1 UV1 GND OSCILLATOR FB COMP ISL6528 INHIBIT/SOFT-START 0.42V 0.80V VOLTAGE REFERENCE FN9038.3 December 28, 2004 ISL6528 Simplified Power System Diagram +5V +3.3V Q1 Q2 LINEAR CONTROLLER VOUT2 VOUT1 PWM CONTROLLER + D1 + ISL6528 Typical Application +5V +3.3V CIN D2 + CBP VCC BOOT VOUT2 DRIVE2 Q2 2.5V FB2 CBOOT UGATE + Q1 VOUT1 LOUT COUT2 1.5V PHASE ISL6528 D1 + COUT1 FB COMP GND 3 FN9038.3 December 28, 2004 ISL6528 Absolute Maximum Ratings Thermal Information UGATE, BOOT. . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to +10V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to +7V FB, DRIVE2, FB2, COMP, . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 Thermal Resistance (Typical, Note 1) Operating Conditions θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Supply Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10% Supply Voltage to drain of upper MOSFET . . . . . . . . . +3.3V ±10% Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams, and Typical Application Schematic PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 2 3.7 6.5 mA Rising VCC Threshold 4.25 4.4 4.50 V Falling VCC Threshold 3.75 3.8 4.00 V FOSC 550 600 650 kHz Ramp Amplitude ∆VOSC - 1.5 - VP-P Soft-Start Interval TSS 3.10 3.42 3.75 ms VREF .784 0.800 .816 V -2.00 - +2.00 % - 80 - dB GBWP 15 - - MHz Slew Rate SR - 6 - V/µs Undervoltage Level (VFB/VREF) VUV 48.13 52.5 56.88 % VCC SUPPLY CURRENT Nominal Supply Current ICC UGATE and DRIVE2 Open POWER-ON RESET OSCILLATOR AND SOFT-START Free Running Frequency REFERENCE VOLTAGE Reference Voltage System Accuracy PWM CONTROLLER ERROR AMPLIFIER DC Gain Gain-Bandwidth Product PWM CONTROLLER GATE DRIVER UGATE Source Impedance RUGATE VCC = 5V, VUGATE = 2.5V - 2.75 5.0 Ω UGATE Sink Impedance RUGATE VUGATE-PHASE = 2.5V - 3.0 5.0 Ω 100 120 - mA LINEAR REGULATOR ERROR AMPLIFIER Output Drive Current VCC > 4.5V Overvoltage Level (VFB2/VREF) VOV 150.0 160.0 175.0 % Undervoltage Level (VFB2/VREF) VUV 48.13 52.5 56.88 % 4 FN9038.3 December 28, 2004 ISL6528 Functional Pin Descriptions Description Operation Overview GND 1 8 UGATE VCC 2 7 BOOT DRIVE2 3 6 COMP 5 FB FB2 4 GND (Pin 1) Signal ground for the IC. All voltage levels are measured with respect to this pin. Place via close to pin to minimize impedance path to ground plane. VCC (Pin 2) Provide a well decoupled 5V bias supply for the IC to this pin. The voltage at this pin is monitored for Power-On Reset (POR) purposes. DRIVE2 (Pin 3) Connect this pin to the base terminal of an external bipolar NPN transistor. This pin provides the base current drive for the linear regulator pass transistor. FB2 (Pin 4) Connect the output of the linear regulator to this pin through a properly sized resistor divider. The voltage at this pin is regulated to 0.8V. This pin is also monitored for undervoltage events. Pulling and holding FB2 above 1.25V shuts down both regulators. Releasing FB2 initiates soft-start on both regulators. FB (Pin 5) and COMP (Pin 6) FB and COMP are the available external pins of the error amplifier. The FB pin is the inverting input of the error amplifier and the COMP pin is the error amplifier output. These pins are used to compensate the voltage-mode control feedback loop of the standard buck converter. BOOT (Pin 7) Connect a suitable capacitor (0.47µF recommended) from this pin to the source terminal of the upper MOSFET (PHASE node). This bootstrap capacitor supplies the UGATE driver the energy necessary to turn and hold the upper MOSFET on. The absolute maximum voltage on BOOT must be kept below 10V. This can be met with a 5V VCC and 3.3V drain supply to the upper MOSFET. UGATE (Pin 8) Connect UGATE to the upper MOSFET gate. This pin provides the gate drive for the MOSFET. 5 The ISL6528 monitors and precisely controls two output voltage levels. Refer to the Block Diagram, Simplified Power System Diagram, and Typical Application Schematic on pp. 2–3. The controller is intended for use in graphics card or embedded processor applications with 3.3V and 5V bias input available. The IC integrates both a standard buck PWM controller and a linear controller. The PWM controller is designed to regulate the high current GPU voltage (VOUT1). The PWM controller drives a single N-Channel MOSFET (Q1) in a standard buck converter configuration and regulates the output voltage to a level programmed by a resistor divider. The linear controller is designed to regulate the lower current local memory voltage (VOUT2) through an external NPN pass transistor. Initialization The ISL6528 automatically initializes upon application of input power. Special sequencing of the input supplies is not necessary. The POR function continually monitors the input bias supply voltage at the VCC pin. The POR function initiates soft-start operation after the 5V bias supply voltage exceeds its POR threshold. Soft-Start The POR function initiates the digital soft-start sequence. Both the linear regulator error amplifier and PWM error amplifier reference inputs are forced to track a voltage level proportional to the soft-start voltage. As the soft-start voltage slews up, the PWM comparator regulates the output relative to the tracked soft-start voltage slowly charging the output capacitor(s). Simultaneously, the linear output follows the smooth ramp of the soft-start function into normal regulation. Figure 1 shows the soft-start sequence for a typical application. At T0, the +5V VCC bias voltage starts to ramp followed by the 3.3V input supply. Once the voltage on VCC crosses the 4.4V POR threshold at time T1, both outputs begin their soft-start sequence. The triangle waveform from the PWM oscillator is compared to the rising error amplifier output voltage. As the error amplifier voltage increases, the pulse-width on the UGATE pin increases to reach its steady-state duty cycle at time T2. The error amplifier reference of the linear controller also rises relative to the soft-start reference. The resulting soft ramp on DRIVE2 brings VOUT2 within regulation limits by time T2. Undervoltage Protection The FB and FB2 pins are monitored during converter operation by two separate undervoltage (UV) comparators. If the FB voltage drops below 52.5% of the reference voltage (0.42V), a fault signal is generated. The internal fault logic FN9038.3 December 28, 2004 ISL6528 +5V (VCC) VOUT2 (2.5V) VOUT1 (1.5V) +3.3V (UPPER FET DRAIN) Delay Interval 0V 0V (1V/DIV) (0.5V/DIV) VOUT2 (2.5V) VOUT2 (2.5V) Internal Soft-Start Function VOUT1 (1.5V) Delay Interval 0V 0V (0.5V/DIV) T0 T2 T1 TIME FIGURE 1. SOFT-START INTERVAL shuts down both regulators simultaneously when the fault signal triggers a restart. Figure 2 illustrates the protection feature responding to an UV event on VOUT1. At time T0, VOUT1 has dropped below 52.5% of the nominal output voltage. Both outputs are quickly shut down and the internal soft-start function begins producing soft-start ramps. The delay interval, T0 to T3, seen by the output is equivalent to three soft-start cycles. After a short delay interval of 10.5ms, the fourth internal softstart cycle initiates a normal soft-start ramp of the output, at time T3. Both outputs are brought back into regulation by time T4, as long as the UV event has cleared. Had the cause of the UV still been present after the delay interval, the UV protection circuitry becomes active approximately 875µs into the soft-start interval. A fault signal could then be generated and the outputs once again shutdown. The resulting hiccup mode style of protection would continue to repeat indefinitely. Output Voltage Selection The output voltage of the PWM converter can be programmed to any level between VIN (i.e. +3.3V) and the internal reference, 0.8V. An external resistor divider is used to scale the output voltage relative to the reference voltage and feed it back to the inverting input of the error amplifier, see Figure 3. However, since the value of R1 affects the values of the rest of the compensation components, it is advisable to keep its value less than 5kΩ. Depending on the T0 T1 T2 TIME T3 T4 FIGURE 2. UNDERVOLTAGE PROTECTION RESPONSE value chosen for R1, R4 can be calculated based on the following equation: R1 × 0.8V R4 = -------------------------------------V OUT1 – 0.8V (EQ. 1) If the output voltage desired is 0.8V, simply route VOUT1 back to the FB pin through R1, but do not populate R4. +5V D2 VCC BOOT +3.3V C4 LOUT VOUT1 COUT1 UGATE Q1 ISL6528 + D1 FB R3 C2 R1 COMP C3 R2 C1 R4 FIGURE 3. OUTPUT VOLTAGE SELECTION OF THE PWM 6 FN9038.3 December 28, 2004 ISL6528 PHASE voltage is then smoothed by the output filter, LOUT and COUT, to produce a DC voltage level. +3.3VIN DRIVE2 Q2 VOUT2 COUT2 FB2 R5 + ISL6528 R6 R5 V OUT2 = 0.8 × 1 + -------- R6 The modulator transfer function is defined as VOUT/VE/A . The internal PWM comparator and driver circuits equate to a DC gain block dominated by the supply voltage, VIN, divided by the peak-to-peak magnitude of the triangle wave, ∆VOSC. The output filter components, LOUT and COUT, shape the overall modulator small-signal transfer function by contributing a double pole break frequency at FLC and a zero at FESR . Modulator Break Frequency Equations FIGURE 4. OUTPUT VOLTAGE SELECTION OF THE LINEAR The linear regulator output voltage is also set by means of an external resistor divider as shown in Figure 4. The two resistors used to set the output voltage should not exceed a parallel equivalent value, referred to as RFB, of 5kΩ. This restriction is due to the manner of implementation of the softstart function. The following relationship must be met: R5 × R6 R FB = ---------------------- < 5kΩ R5 + R6 (EQ. 2) To ensure the parallel combination of the feedback resistors meets this criteria, choose a target value for RFB of less than 5kΩ and then apply the following equations: V OUT2 R5 = ------------------- × R FB V REF (EQ. 3) R5 × V REF R6 = ---------------------------------------V OUT2 – V REF (EQ. 4) 1 F LC = ---------------------------------------2π × L O × C O (EQ. 5) 1 F ESR = ----------------------------------------2π × ESR × CO (EQ. 6) The compensation network consists of the error amplifier and the impedance networks ZIN and ZFB . They provide the link between the modulator transfer function and a controllable closed loop transfer function of VOUT/VREF. The goal of component selection for the compensation network is to provide a loop gain with high 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. VIN DRIVER OSC PWM COMP - ∆ VOSC PWM Controller Feedback Compensation A simplified representation of the voltage-mode control loop used for output regulation by the standard buck converter is shown in Figure 5. The output voltage, VOUT, is fed back to the negative input of the error amplifier which is regulated to the reference voltage level, VREF. The error amplifier output, VE/A, is compared with the triangle wave produced by the oscillator, VOSC, to provide a pulse-width modulated (PWM) signal from the PWM comparator. This signal is then used to switch the MOSFET and produce a PWM waveform with an amplitude of VIN at the PHASE node. The square-wave 7 + VOUT CO + ESR (PARASITIC) ZFB VE/A Pulling and holding the FB2 pin above a typical threshold of 1.28V will shutdown both regulators. Upon release of the FB2 pin, the regulators enter into a soft-start cycle which brings both outputs back into regulation. PHASE + where VOUT2 is the desired linear regulator output voltage and VREF is the internal reference voltage, 0.8V. For an output voltage of 0.8V, simply populate R5 with a value less than 5kΩ and do not populate R6. Converter Shutdown LOUT ZIN VREF ERROR AMP DETAILED COMPENSATION COMPONENTS ZFB C2 C1 VOUT ZIN C3 R2 R3 R1 COMP FB + ISL6528 0.8V FIGURE 5. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN FN9038.3 December 28, 2004 ISL6528 Compensation Break Frequency Equations Poles: 1 F P1 = ------------------------------------------------------C1 × C2 2π × R 2 × ---------------------- C1 + C2 1 F P2 = ----------------------------------2π × R 3 × C3 (EQ. 8) (EQ. 9) Application Guidelines Zeros: 1 F Z1 = ----------------------------------2π × R 2 × C1 (EQ. 10) 1 F Z2 = ------------------------------------------------------2π × ( R1 + R3 ) × C3 (EQ. 11) Follow this procedure for selecting compensation components by locating the poles and zeros of the compensation network: 1. Set the loop gain (R2/R1) to provide a converter bandwidth of one quarter of the switching frequency. 2. Place the first compensation zero, FZ1, below the output filter double pole (~75% FLC). 3. Position the second compensation zero, FZ2, at the output filter double pole, FLC. 4. Locate the first compensation pole, FP1, at the output filter ESR zero, FESR. 5. Position the second compensation pole at half the converter switching frequency, FSW. 6. Check gain against error amplifier’s open-loop gain. 7. Estimate phase margin; repeat if necessary. 8. FZ1 FZ2 FP1 FP2 100 OPEN LOOP ERROR AMP GAIN V IN 20 log ------------------ V OSC 80 GAIN (dB) 60 40 COMPENSATION GAIN 20 0 -20 R2 20 log --------- R1 -40 MODULATOR GAIN -60 10 The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45°. Include worst case component variations when determining phase margin. 100 FLC 1K LOOP GAIN FESR 10K 100K 1M 10M FREQUENCY (Hz) FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN Figure 6 shows an asymptotic plot of the DC-DC converter’s gain vs. frequency. The actual modulator gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown in Figure 6. Using the above procedure should yield a compensation gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. 8 Layout Considerations Layout is very important in high frequency switching converter design. With power devices switching efficiently at 600kHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. Careful component layout and printed circuit board design minimizes the voltage spikes in the converters. As an example, consider the turn-off transition of the PWM MOSFET. Prior to turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is picked up by the lower Schottky diode. Any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide traces minimizes the magnitude of voltage spikes. There are two sets of critical components in a DC-DC converter using the ISL6528. The switching components are the most critical because they switch large amounts of energy, and therefore tend to generate large amounts of noise. Next are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling. A multi-layer printed circuit board is recommended. Figure 7 shows the connections of the critical components in the converter. Note that capacitors CIN and COUT could each represent numerous physical capacitors. Dedicate one solid layer, usually a middle layer of the PC board, for a ground plane and make all critical component ground connections through vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminal to the output inductor short. The power plane should support the input and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase node. Use the remaining printed circuit layers for small signal wiring. The wiring traces from the UGATE pin to the MOSFET gate should be kept short and wide enough to easily handle the 1A of drive current. The switching components should be placed close to the ISL6528 first. Minimize the length of the connections between the input capacitors, CIN, and the power switches FN9038.3 December 28, 2004 ISL6528 PWM REGULATOR OUTPUT CAPACITORS +3.3 VIN Modern digital ICs can produce high transient load slew rates. High frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. The bulk filter capacitor selection is generally determined by the effective series resistance (ESR) and voltage rating requirements rather than actual capacitance requirements. +5 VCC VCC GND CIN CBP D2 BOOT CBOOT Q1 PHASE ISL6528 COMP LOUT D1 C2 VOUT1 LOAD UGATE COUT1 C1 R2 R1 FB C3 R3 R4 +3.3 VIN Q2 DRIVE2 R5 FB2 COUT2 LOAD R6 VOUT2 KEY ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT PLANE LAYER VIA CONNECTION TO GROUND PLANE FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS by placing them nearby. Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as possible. Position the output inductor and output capacitors between the upper MOSFET and lower diode and the load. The critical small signal components include any bypass capacitors, feedback components, and compensation components. Position the bypass capacitor, CBP, close to the VCC pin with a via directly to the ground plane. Place the PWM converter compensation components close to the FB and COMP pins. The feedback resistors for both regulators should also be located as close as possible to the relevant FB pin with vias tied straight to the ground plane as required. Component Selection Guidelines Output Capacitor Selection Output capacitors are required to filter the output and supply the load transient current. The filtering requirements are a function of switching frequency and output current ripple. The load transient requirements are a function of the transient load current slew rate (di/dt) and magnitude. These requirements are generally met with a mix of capacitors and careful layout. 9 High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Specialized low-ESR capacitors intended for switchingregulator applications are recommended for the bulk capacitors. The bulk capacitor’s ESR determines the output ripple voltage and the initial voltage drop following a high slew-rate transient edge. Aluminum electrolytic, tantalum, and special polymer capacitor ESR values are related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. LINEAR REGULATOR OUTPUT CAPACITORS The output capacitors for the linear regulator provide dynamic load current. The linear controller uses dominant pole compensation integrated into the error amplifier and is relatively insensitive to output capacitor selection. Output capacitors should be selected for transient load regulation. PWM Output Inductor Selection The PWM converter requires an output inductor. The output inductor is selected to meet the output voltage ripple requirements and sets the converter response time to a load transient. The inductor value determines the converter’s ripple current and the ripple voltage is also a function of the ripple current. The ripple voltage and current are approximated by the following equations: V IN – V OUT V OUT ∆I = -------------------------------- × ---------------V IN FS × L (EQ. 11) ∆V OUT = ∆I × ESR (EQ. 12) Increasing the value of inductance reduces the output ripple current and voltage ripple. However, increasing the FN9038.3 December 28, 2004 ISL6528 inductance value will slow the converter response time to a load transient. One of the parameters limiting the converter’s response to a load transient is the time required to slew the inductor current. Given a sufficiently fast control loop design, the ISL6528 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time interval required to slew the inductor current from an initial current value to the final current level. During this interval the difference between the inductor current and the load current must be supplied by the output capacitor(s). Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: L O × I TRAN t RISE = ------------------------------V IN – V OUT (EQ. 13) L O × I TRAN t FALL = -----------------------------V OUT (EQ. 14) where ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a +3.3V input source, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Input Capacitor Selection The important parameters for the bulk input capacitors are the voltage rating and the RMS current rating. For reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 of the summation of the DC load current. Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use ceramic capacitance for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedances. Connect them directly to ground with a via placed very close to the ceramic capacitor footprint. 10 For a through-hole design, several aluminum electrolytic capacitors may be needed. For surface mount designs, tantalum or special polymer capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. Transistor Selection/Considerations The ISL6528 requires two external transistors. One Nchannel MOSFET is used as the upper switch in a standard buck topology PWM converter. The linear controller drives an NPN bipolar transistor as a pass element. The transistors should be selected based upon rDS(ON) , current gain, saturation voltages, gate/base supply requirements, and thermal management considerations. UPPER MOSFET SWITCH SELECTION In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses account for a large portion of the power dissipation of the MOSFET. Switching losses also contribute to the overall MOSFET power loss. P Conduction ≅ I o2 × r DS ( on ) × D 1 P Switching ≅ --- I o × V IN × t SW × F SW 2 (EQ. 15) (EQ. 16) where Io is the maximum load current, D is the duty cycle of the converter (defined as VO/VIN), tSW is the switching interval, and FSW is the PWM switching frequency. These equations assume linear voltage-current transitions and are approximations. The gate-charge losses are dissipated by the ISL6528 and do not heat the MOSFET. However, large gate-charge increases the switching interval, tSW, which increases the upper MOSFET switching losses. Ensure that the MOSFET is within its maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature, air flow, and load current requirements. Given the reduced available gate bias voltage (5V) a logiclevel transistor is recommended for the upper switch. Close attention to layout guidelines should be exercised with devices exhibiting very low VGS(on) characteristics, as the low gate threshold could lead to some shoot-through despite counteracting circuitry present aboard the ISL6528. NPN PASS TRANSISTOR SELECTION A bipolar NPN transistor must be used with the linear controller. Insure the current gain at the given operating VCE is sufficiently large to provide the desired maximum output FN9038.3 December 28, 2004 ISL6528 load current when the base is fed with the minimum driver output current. The main criteria for selection of the linear regulator pass transistor is package selection for efficient removal of heat. Select a package and heatsink that maintains the junction temperature below the rating with a maximum expected ambient temperature. +5V +3.3V D2 CBOOT VCC BOOT The power dissipated in a linear regulator is: P LINEAR ≅ I O × ( V IN – V OUT ) PHASE (EQ. 17) where IO is the maximum output current and VOUT is the nominal output voltage of the linear regulator. Diode Selection (D1) Rectifier D1 conducts when MOSFET Q1 is off. The diode should be a Schottky type for low power losses. The power dissipation in the Schottky rectifier is approximated by: P CONDUCTION ≅ I O × V f × ( 1 – D ) (EQ. 18) where IO is the maximum output current of the PWM converter, Vf is the Schottky forward voltage drop, and D is the duty cycle of the converter (defined as VO/VIN). In addition to power dissipation, package selection and heatsink requirements are the main design trade-offs in choosing a Schottky rectifier. Since the three factors are interrelated, the selection process is an iterative procedure. The maximum junction temperature of the rectifier must remain below the manufacturer’s specified value, typically 125°C. By using the package thermal resistance specification and the Schottky power dissipation equation, the junction temperature of the rectifier can be estimated. Be sure to use the available airflow and ambient temperature to determine the junction temperature rise. Bootstrap Component Selection External bootstrap components, a diode and capacitor, are required to provide sufficient gate enhancement to the MOSFET. The internal MOSFET gate driver is supplied by the external bootstrap circuitry as shown in Figure 8. The boot capacitor, CBOOT, develops a floating supply voltage referenced to the PHASE pin. This supply is refreshed each cycle, when D1 conducts, to a voltage of VCC less the boot diode drop, VD2, plus the voltage rise across D1. Just after the PWM switching cycle begins and the charge transfer from the bootstrap capacitor to the gate capacitance is complete, the voltage on the bootstrap capacitor is at its lowest point during the switching cycle. The charge lost on the bootstrap capacitor will be equal to the charge transferred to the equivalent gate-source capacitance of the MOSFET as shown in Equation 19. Q GATE = C BOOT × ( V BOOT1 – V BOOT2 ) 11 Q1 UGATE D1 ISL6528 FIGURE 8. UPPER GATE DRIVE where QGATE is the maximum total gate charge of the MOSFET, CBOOT is the bootstrap capacitance, VBOOT1 is the bootstrap voltage immediately before turn-on, and VBOOT2 is the bootstrap voltage immediately after turn-on. The bootstrap capacitor begins its refresh cycle when the gate drive begins to turn off the MOSFET. A refresh cycle ends when the MOSFET is turned on again, which varies depending on the switching frequency and duty cycle. The minimum bootstrap capacitance can be calculated by rearranging Equation 19 and solving for CBOOT. Q GATE C BOOT ≥ ----------------------------------------------------V BOOT1 – V (EQ. 20) BOOT2 Typical gate charge values for MOSFETs considered in these types of applications range from 20–100nC. Since the voltage drop across D2 is offset by the voltage drop across D1, VBOOT1 is simply VCC (+5V). A good rule is to keep the voltage drop across the bootstrap capacitor no greater than 1V during the on-time of the MOSFET. Initial calculations with VBOOT2 no less than 4V will quickly help narrow the bootstrap capacitor range. For example, consider a MOSFET is chosen with a maximum gate charge, Qg, of 100nC. Limiting the voltage drop across the bootstrap capacitor to 1V results in a value of no less than 0.1µF. The tolerance of the ceramic capacitor should also be considered when selecting the final bootstrap capacitance value. A fast recovery diode is recommended when selecting a bootstrap diode to reduce the impact of reverse recovery charge loss. Otherwise, the recovery charge, QRR, would have to be added to the gate charge of the MOSFET and taken into consideration when calculating the minimum bootstrap capacitance. Employing a Schottky diode over a standard diode will also increase the gate drive voltage available to enhance the MOSFET. (EQ. 19) FN9038.3 December 28, 2004 ISL6528 ISL6528 Converter Application Circuit Figure 9 shows a typical DC-DC converter circuit for a graphics card application. Additional information on this circuit can be obtained by referencing application note AN9982. +3.3V C7 330µF C6 330µF C8 1µF D2 +5V BAT54 C5 1µF C4 0.1µF UGATE GND VCC Q2 DRIVE2 FB2 VOUT2 (1A) R5 BOOT COMP 1.71µH D1 R2 39.2kΩ R6 C12 470µF 5.36kΩ C9,C10 2x470µF FB C1 150pF 11.3kΩ C14 1µF ISL6528 VOUT1 (6A) L1 Q1 C11 1µF C2 1500pF R1 2.32kΩ C1 R4 R2 2.67kΩ 0.018µF 30.9Ω Q1 Q2 L1 D1 FDS6690A FZT649 ETQ-P6F1R8BFA B520C-13 Fairchild Fairchild Panasonic Diode Inc. FIGURE 9. POWER SUPPLY APPLICATION CIRCUIT FOR A GRAPHICS CONTROLLER 12 FN9038.3 December 28, 2004 ISL6528 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N INDEX AREA 0.25(0.010) M H 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- µα e A1 B 0.25(0.010) M C C A M B S 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. MILLIMETERS MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N NOTES: MAX A1 e 0.10(0.004) MIN α 8 0o 8 7 8o Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN9038.3 December 28, 2004