DUAL DMOS FULL-BRIDGE DRIVER ADVANCE INFORMATION (Subject to change without notice) May 2, 2000 NO CONNECTION 1 LOGIC GROUND 24 LOGIC SUPPLY 2 23 PWM2 S10 3 22 S20 OUT1A 4 21 OUT2A LOAD SUPPLY1 5 20 LOAD SUPPLY2 GROUND 6 GROUND 7 SENSE1 8 OUT1B 99 S11 10 PWM1 11 CP1 12 NC VDD VBB2 LOGIC LOGIC VBB1 Data Sheet 29319.32 3971 Designed to interface between external PWM control logic and inductive loads such as relays, solenoids, dc motors, or stepper motors, each full bridge can operate with output currents to ±2.5 A and operating voltages to 50 V. Low rDS(on) DMOS output drivers provide low power dissipation during PWM operation. Internal charge pump circuitry is used to create a boosted voltage to fully enhance the high-side DMOS switches. t c u d o ly r P On d e e c u it n ren n e f o e c s rR i D o F CHARGE PUMP 19 GROUND 18 GROUND 17 SENSE2 16 OUT2B 15 S21 14 VCP 13 CP2 Dwg. PP-069-2 Three TTL-compatible logic-input terminals per bridge allow flexibility in configuring PWM control. Internal circuit protection includes thermal shutdown with hysteresis, and crossover-current protection. Special power -up sequencing is not required. The A3971SLB is supplied in a 24-lead plastic SOIC with a copper batwing tab. The power tab is at ground potential and needs no electrical isolation. ABSOLUTE MAXIMUM RATINGS at TA = +25°C Load Supply Voltage, VBB ................ 50 V Output Current, IOUT Transient (<500 ns) ................... ±5 A Logic Supply Voltage, VDD ............................................ 7.0 V Sense Voltage, VSENSE ...................... 0.5 V Logic Input Voltage Range, VIN .................. -0.3 V to VDD + 0.3 V High-Side Gate Voltage ........... VBB + 8 V Package Power Dissipation, PD ............................................. 2.2 W Operating Temperature Range, TA ............................. -20°C to +85°C Junction Temperature, TJ ............. +150°C Storage Temperature Range, TS ........................... -55°C to +150°C FEATURES ■ ±2.5 A Load Current Capability per Bridge ■ Parallel Outputs for 5 A Load-Current Capability ■ Low rDS(on) Outputs Typically 325 mΩ source, 175 mΩ sink ■ Synchronous Rectification via Control Logic ■ Internal Undervoltage Monitor ■ Crossover-Current Protection ■ Source Connections for External Current Sensing ■ Thermal Shutdown Circuitry Output duty cycle, ambient temperature, and heat sinking may limit current rating. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150 °C. Always order by complete part number: A3971SLB . 3971 DUAL DMOS FULL-BRIDGE DRIVER FUNCTIONAL BLOCK DIAGRAM 0.22 µF/100 V LOGIC SUPPLY CP2 13 VDD 24 CP1 12 V REF VOLTAGE REFERENCE CHARGE PUMP LOW SIDE SUPPLY 14 20 V CP LOAD SUPPLY 0.22 µF 50 V V BB2 DMOS H-BRIDGE V CP UVLO & THERMAL SHUTDOWN 21 16 OUT 2A OUT 2B S10 3 S11 10 PWM1 11 BRIDGE 1 CONTROL LOGIC 17 SENSE2 RS , CS (OPTIONAL) GATE DRIVE DMOS H-BRIDGE 5 V BB1 S20 22 S 21 15 PWM2 23 BRIDGE 2 CONTROL LOGIC 4 9 LGND OUT1A OUT1B SENSE1 2 RS , CS (OPTIONAL) 8 6 7 18 19 GROUND Dwg. FP-050 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2000, 2002 Allegro MicroSystems, Inc. 3971 DUAL DMOS FULL-BRIDGE DRIVER ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V (unless otherwise noted). Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Load Supply Voltage Range VBB Operating 10 — 50 V Logic Supply Voltage Range VDD Operating 4.5 5.0 5.5 V Load Supply Current IBB Operating, each supply, no load — — 3.0 mA Logic Supply Current IDD Operating — — 5.0 mA IDSS VOUT = VBB — <1.0 20 µA VOUT = 0 V — <-1.0 -20 mA High-side switch, IOUT = -2.5 A — 325 375 mΩ Low-side switch, IOUT = 2.5 A — 175 200 mΩ Source diode, IF = 2.5 A — 1.2 — V Sink diode, IF = 2.5 A — 1.0 — V C = 0.22 µF, reference VBB 6.0 6.5 7.0 V VIN(0) — — 0.8 V VIN(1) 2.0 — — V Output Drivers Output Leakage Current Output ON Resistance Body Diode Forward Voltage High-Side Gate Voltage rDS(on) VF VCP Control Logic Logic Input Voltage Logic Input Current Propagation Delay Time Thermal Shutdown Temperature Thermal Shutdown Hysteresis IIN(0) VIN = 0 V — <1.0 -5.0 µA IIN(1) VIN = 5.0 V — 20 50 µA tPD 50% to 90%: PWM change to source off — 50 — ns PWM change to sink off — 60 — ns PWM change to source on — 565 — ns PWM change to sink on — 665 — ns Disable to source on — 150 — ns Disable to sink on — 250 — ns TJ — 165 — °C ∆TJ — 15 — °C 3.9 4.15 4.4 V — 0.15 — V UVLO Threshold VUVLO UVLO Hysteresis ∆VUVLO Increasing VDD NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal. www.allegromicro.com 3971 DUAL DMOS FULL-BRIDGE DRIVER Logic Truth Table PWMx Sx0 Sx1 OUTxA OUTxB Function X 0 0 Z Z Disable 0 0 1 L H Forward 0 1 0 H L Reverse 0 1 1 L L Synchronous 1 0 1 L L Rectification/ 1 1 1 L L Slow Decay 1 1 0 L L Chop Terminal List Terminal 1 2 3 4 5 6, 7 8 9 10 11 12 13 14 15 16 17 18, 19 20 21 22 23 24 Name NC LGND S10 OUT1A VBB1 GND SENSE1 OUT1B S11 PWM1 CP1 CP2 VCP S21 OUT2B SENSE2 GND VBB2 OUT2A S20 PWM2 VDD Description No (Internal) connection Logic ground Control input, bridge 1 Output A, bridge 1 Load supply voltage, bridge 1 Ground Sense resistor, bridge 1 Output B, bridge 1 Control input, bridge 1 Control input, bridge 1 Charge-pump capacitor Charge-pump capacitor Reservoir capacitor Control input, bridge 2 Output B, bridge 2 Sense resistor, bridge 2 Ground Load supply voltage, bridge 2 Output A, bridge 2 Control input, bridge 2 Control input, bridge 2 Logic supply voltage 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3971 DUAL DMOS FULL-BRIDGE DRIVER Functional Description NC VDD 24 2 23 3 22 4 21 5 20 15–50 V 15–50 V 19 7 18 8 17 99 16 10 15 11 14 12 CHARGE PUMP 47 µF VBB2 LOGIC VBB1 LOGIC 47 µF 6 0.22 µF Thermal protection. Circuitry turns off all drivers when the junction temperature reaches 165°C, typically. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15°C. +5 V 1 0.22 µF Current Sensing. If external current-sensing circuitry is used, the sense resistor should have an independent ground return to the ground terminal of the device. Due to current transients during switching, a 0.1 µF capacitor should be connected from the sense terminal to the batwing tab connection of the package. This capacitor reduces voltage swings at the terminal due to the fast di/dt, which in turn ensures that the sink driver gate-source voltage stays within the safe operating area. Allegro MicroSystems recommends a value of RS given by: RS = 0.5/ITRIP max. PWM CONTROL Protection Circuitry. In the event of a fault due to excessive junction temperature, or low voltage on VCP or VDD, the outputs of the device are disabled until the fault condition is removed. Parallel Operation. For high-power applications, the two DMOS full bridges in the A3971 may be connected in parallel as shown below. The current will be shared equally in each full bridge due to the positive temperature coefficient of the DMOS rDS(on). + Control Logic. Each bridge is controlled by three TTLcompatible inputs. The inputs are resistively pulled to ground (via 250 kΩ). A crossover-delay circuit protects the outputs from a shoot-thru condition when going from a forward or reverse on state to synchronous rectification/ slow decay chop (both sink drivers on). If the logic is in the DISABLE state and changes to an on state the 415 ns crossover delay does not occur. Layout. The printed wiring board should use a heavy ground plane. For optimum electrical and thermal performance, the driver should be soldered directly onto the board. If external current sensing is used, the ground side of RS should have an individual path to the ground terminal(s) of the device. This path should be as short as is possible physically and should not have any other components connected to it. The load supply terminal should be decoupled with an electrolytic capacitor ( >47 µF is recommended) placed as close to the device as is possible. + Charge Pump. The DMOS output stage requires a charge pump to bring the high-side gate-source voltage approximately 8 V above the VBB supply. Two external components are required, a pumping capacitor connected between CP1 and CP2 and a reservoir capacitor connected between VBB and VCP. Ceramic 0.22 µF capacitors are recommended. 13 Dwg. EP-069 www.allegromicro.com 3971 DUAL DMOS FULL-BRIDGE DRIVER Dimensions in Inches (for reference only) 24 13 0.0125 0.0091 0.419 0.394 0.2992 0.2914 0.050 0.016 0.020 0.013 1 2 0.050 3 0.6141 0.5985 BSC 0° TO 8° 0.0926 0.1043 Dwg. MA-008-24A in 0.0040 MIN. NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative 3. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3971 DUAL DMOS FULL-BRIDGE DRIVER Dimensions in Millimeters (controlling dimensions) 24 13 0.32 0.23 10.65 10.00 7.60 7.40 1.27 0.40 0.51 0.33 1 2 1.27 3 15.60 15.20 BSC 0° TO 8° 2.65 2.35 0.10 MIN. NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative 3. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. www.allegromicro.com Dwg. MA-008-24A mm 3971 DUAL DMOS FULL-BRIDGE DRIVER The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000