A6800/A6801: DABiC-5 Latched Sink Drivers

A6800 and A6801
DABiC-5 Latched Sink Drivers
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: November 1, 2010
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, refer to your Allegro sales representative.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A6800 and A6801
DABiC-5 Latched Sink Drivers
Features and Benefits
Description
▪ 3.3 to 5 V logic supply range
▪ Up to 10 MHz data input rate
▪ High-voltage, high-current outputs
▪ Darlington current-sink outputs, with improved low-saturation
voltages
▪ CMOS, TTL compatible inputs
▪ Output transient protection
▪ Internal pull-down resistors
▪ Low-power CMOS latches
The A6800 and A6801 latched-input BiMOS ICs merge
high-current, high-voltage outputs with CMOS logic. The
CMOS input section consists of 4 or 8 data (D type) latches
with associated common CLEAR, STROBE, and OUTPUT
ENABLE circuitry. The power outputs are bipolar NPN
Darlingtons. This merged technology provides versatile,
flexible interface. These BiMOS power interface ICs greatly
benefit the simplification of computer or microprocessor I/O. The A6800 ICs each contain four latched drivers.
A6801 ICs contain eight latched drivers.
The CMOS inputs are compatible with standard CMOS
circuits. TTL circuits may mandate the addition of input
pull-up resistors. The bipolar Darlington outputs are suitable
for directly driving many peripheral/power loads: relays,
lamps, solenoids, small DC motors, and so forth.
Packages
A6800
14-pin SOICN
(L package)
All devices have open-collector outputs and integral diodes
for inductive load transient suppression. The output transistors are capable of sinking 600 mA and can withstand at
least 50 V in the off state. Because of limitations on package
power dissipation, the simultaneous operation of all drivers at maximum rated current can only be accomplished
by a reduction in duty cycle. Outputs may be paralleled for
higher load current capability.
A6801
28-pin PLCC
(EP package)
Continued on the next page…
Approximate scale 1:1
Functional Block Diagram
C OMMON
S UP P LY
V DD
OUT N
IN N
S T R OB E
G R OUND
C LE AR
OUT P UT E NAB LE
T Y P IC AL MOS LAT C H
C OMMON MOS C ONT R OL
26180.110J
T Y P IC AL B IP OLAR DR IV E
A6800 and
A6801
DABiC-5 Latched Sink Drivers
Description (continued)
The A6800SL is furnished in a surface-mountable SOIC, and the
A6801SEP in a 28-lead PLCC. These devices are lead (Pb) free,
with 100% matte tin plated leadframes.
Applications include:
▪ Relays
▪ Lamps
▪ Solenoids
▪ Small DC motors
Selection Guide
Part Number
Package
Packing
A6800SLTR-T
14-pin SOIC
2500 per reel
A6801SEPTR-T
28-pin PLCC
800 per reel
Absolute Maximum Ratings*
Characteristic
Symbol
Rating
Units
50
V
VDD
7
V
VIN
–0.3 to VDD + 0.3
V
IC
600
mA
Output Voltage
VCE
Supply Voltage
Input Voltage Range
Continuous Collector Current
Notes
Operating Ambient Temperature
TA
–20 to 85
ºC
Maximum Junction Temperature
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Storage Temperature
Range S
*Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to
extremely high static-electrical charges.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A6800 and
A6801
DABiC-5 Latched Sink Drivers
Allowable Power Dissipation
2.5
28-LEAD PLCC, RQJA = 68oC/W
PACKAGE POWER DISSIPATION (W)
2.0
1.5
1.0
0.5
14-LEAD SOIC, RQJA = 120oC/W
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (ºC)
Typical Input Circuit
VDD
IN
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A6800 and
A6801
DABiC-5 Latched Sink Drivers
ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage VDD = 3.0 to 5.5 V
VDD = 3.3 V
Characteristic
Min.
Typ.
Typ.
Max.
Units
VOUT = 50 V
–
–
10
–
–
10
μA
IOUT = 350 mA, L = 3 mH
35
–
–
35
–
–
V
IOUT = 100 mA
–
0.8
1.0
–
0.8
1.0
V
IOUT = 200 mA
–
0.9
1.1
–
0.9
1.1
V
Symbol
Output Leakage Current
ICEX
Output Sustaining Voltage
VCE(SUS)
Collector-Emitter Saturation
Voltage
VCE(SAT)
Test Conditions
IOUT = 350 mA (See note 2)
Input Voltage
Input Resistance
Logic Supply Current
VDD = 5 V
Max. Min.
–
1.0
1.3
–
1.0
1.3
V
VIN(1)
2.2
–
–
3.3
–
–
V
VIN(0)
–
–
1.1
–
–
1.7
V
RIN
50
–
–
50
–
–
kΩ
mA
IDD(1)
One output on, IOUT = 100 mA
–
–
1.0
–
–
1.0
IDD(0)
All outputs off
–
130
150
–
130
150
μA
Clamp Diode Leakage Current
Ir
Vr = 50 V
–
–
50
–
–
50
μA
Clamp Diode Forward Voltage
Vf
If = 350 mA
–
–
2.0
–
–
2.0
V
Output Fall Time
tf
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
80
–
–
80
–
ns
Output Rise Time
tr
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
100
–
–
100
–
ns
1
Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic 1.
2
Because of limitations on package power dissipation, the simultaneous operation of multiple drivers can only be accomplished by reduction in duty cycle.
Truth Table
OUT N
OUT P UT
IN N
S T R OB E
CLE AR
E NA B L E
t-1
t
0
1
X
X
X
X
1
1
X
X
0
0
0
0
1
X
0
0
0
0
X
1
0
0
X
X
X
X
ON
OF F
OF F
ON
OF F
OF F
ON
OF F
X = irrelevant
t-1 = previous output s tate
t = pres ent output s tate
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A6800 and
A6801
DABiC-5 Latched Sink Drivers
Timing Requirements and Specifications
(Logic Levels are VDD and Ground)
CLEAR
G
STROBE
A
C
B
B
C
C
A
H
B
H
INN
D
E
E
F
OUTN
HIGH = ALL OUTPUTS DISABLED (OFF)
OUTPUT ENABLE
50%
t en(BQ)
tr
tf
t dis(BQ)
OUT N
Key
DATA
10%
90%
50%
Description
Time (ns)
A
Minimum data active time before Strobe enabled (Data Set-Up Time)
25
B
Minimum data active time after Strobe disabled (Data Hold Time)
25
C
Minimum Strobe pulse width
50
D
Maximum time between Strobe activation and transition from output on to output off*
500
E
Maximum time between Strobe activation and transition from output off to output on*
500
F
Maximum time between Clear activation and transition from output on to output off*
500
G
Minimum Clear pulse width
50
H
Minimum data pulse width
100
tdis(BQ)
Output Enable to output off delay*
500
ten(BQ)
Output Enable to output on delay*
500
*Conditions for output transition testing are: VCC = 50 V, VDD = 5 V, R1 = 500 Ω, C1 ≤ 30 pF.
NOTE: Information present at an input is transferred
to its latch when the STROBE is high. A high CLEAR
input will set all latches to the output off condition
regardless of the data or STROBE input levels. A high
OUTPUT ENABLE will set all outputs to the off contdition, regardless of any other input conditions. When
the OUTPUT ENABLE is low, the outputs depend on
the state of their respective latches.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A6800 and
A6801
DABiC-5 Latched Sink Drivers
A6800 L Package
1
14
OUTPUT
ENABLE
STROBE
2
VDD 13
SUPPLY
IN 1
3
12
OUT 1
IN 2
4
11
OUT 2
IN 3
5
10
OUT 3
IN 4
6
9
OUT 4
ROUND
7
8
COMMON
LATCHES
CLEAR
28 OUTPUT
ENABLE
26
V DD
NC
1
C
27 SUPPLY
2
ST
NC
OE
4
3
NC
CLEAR
STROBE
A6801 EP Package
25
OUT1
6
24
OUT 2
IN 3
7
23
OUT 3
IN 4
8
22
OUT4
IN 5
9
LATCHES
5
IN 2
IN1
21 OUT 5
16
OUT8
15
GROUND
LAMP DIODE
COMMON
IN 8
18
OUT7
K
19
17 NC
IN 7 11
14 NC
OUT 6
13 NC
20
12
IN 6 10
Dwg. PP-037
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A6800 and
A6801
DABiC-5 Latched Sink Drivers
TYPICAL APPLICATION
UNIPOLAR STEPPER-MOTOR DRIVE
+30 V
OUTPUT ENABLE (ACTIVE LOW)
CLEAR
IN 1
M¾
IN 2
IN 3
IN 4
1
14
2
V DD 13
3
12
4
5
LATCHES
STROBE
V DD
OUT 1
OUT 2
11
OUT 3
10
OUT 4
6
9
7
8
A6800SL
+30 V
Dwg. No. B-1537
UNIPOLAR WAVE DRIVE
STROBE
UNIPOLAR 2-PHASE DRIVE
STROBE
IN 1
IN 1
IN 2
IN 2
IN 3
IN 3
IN 4
IN 4
OUT 1
OUT 1
OUT 2
OUT 2
OUT 3
OUT 3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A6800 and
A6801
DABiC-5 Latched Sink Drivers
Package EP (A6801) 28-pin PLCC
12.45±0.13
11.51±0.08
2
1
0.51
28
A
12.45±0.13
5.21±0.36
11.51±0.08
5.21±0.36
0.51 MIN
0.74±0.08
+0.20
4.37 –0.18
28X
0.10 C
SEATING
PLANE
C
0.43±0.10
1.27
5.21±0.36
5.21±0.36
For Reference Only
(reference JEDEC MS-018 AB)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A6800 and
A6801
DABiC-5 Latched Sink Drivers
Package L (A6800) 14-pin SOICN
9.90 ±0.10
4° ±4
14
1.27
0.65
0.21 ±0.04
3.90 ±0.10
6.00 ±0.20
A
1
+0.43
0.84 –0.44
2
0.25
14X
SEATING
PLANE
0.10 C
0.41 ±0.10
5.60
1.27
C
1.75
B PCB Layout Reference View
SEATING PLANE
GAUGE PLANE
1.75 MAX
+0.07
0.18 –0.08
For Reference Only
Dimensions in millimeters
(reference JEDEC MS-012 AB)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Reference pad layout (reference IPC SOIC127P600X175-14M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Copyright ©2003-2010, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9