The following document contains information on Cypress products. FUJITSU SEMICONDUCTOR CM71-10111-6E CONTROLLER MANUAL FR60 32-BIT MICROCONTROLLER MB91307 Series HARDWARE MANUAL FR60 32-BIT MICROCONTROLLER MB91307 Series HARDWARE MANUAL FUJITSU LIMITED PREFACE ■ Objectives and Intended Reader Thank you for using Fujitsu semiconductor products. The MB91307 series is a standard single-chip microcontroller that has a 32-bit highperformance RISC CPU as well as built-in I/O resources and bus control mechanisms for embedded controller that requires high-performance and high-speed CPU processing. Although the MB91307 series basically uses external bus access to support a vast address space accessed by a 32-bit CPU, it has a 1 KB instruction cache memory and large-capacity RAM to increase the speed at which the CPU executes instructions. The MB91307 series is most suitable for embedded applications, such as DVD players, navigation systems, high-performance fax machines, and printer controllers, that require a high level of CPU processing power. The MB91307 series is one of the FR60 of microcontrollers, which are based on the FR30/40 family of CPUs. It has enhanced bus access and is optimized for high-speed use. This manual is intended for engineers who will develop products using the MB91307 series and describes the functions and operations of the MB91307 series. Read this manual thoroughly. For more information on instructions, see the "Instructions Manual". ■ Trademarks FR, which is an abbreviation of FUJITSU RISC controller, is a product of Fujitsu Limited. The names of other systems and products appearing in this manual are the trademarks of their respective companies or organizations. In this manual, the symbols TM or ® are not always used. ■ License Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. i ■ Structure of This Manual This manual consists of the following 15 chapters and an appendix. CHAPTER 1 "OVERVIEW" This chapter provides basic information required to understand the MB91307 series, and covers features, a block diagram, and functions. CHAPTER 2 "HANDLING THE DEVICE" This chapter provides precautions on handling the MB91307 series. CHAPTER 3 "CPU AND CONTROL UNITS" This chapter provides basic information required to understand the functions of the MB91307 series. It covers architecture, specifications, and instructions. CHAPTER 4 "EXTERNAL BUS INTERFACE" The external bus interface controller controls the interfaces with the internal bus for chips and with external memory and I/O devices. This chapter explains each function of the external bus interface and its operation. CHAPTER 5 "I/O PORT" This chapter describes the I/O ports and the configuration and functions of registers. CHAPTER 6 "16-BIT RELOAD TIMER" This chapter describes the 16-bit reload timer, the configuration and functions of registers, and 16-bit reload timer operation. CHAPTER 7 "U-TIMER" This chapter describes the U-TIMER, the configuration and functions of registers, and UTIMER operation. CHAPTER 8 "EXTERNAL INTERRUPT AND NMI CONTROLLER" This chapter describes the external interrupt and NMI controller, the configuration and functions of registers, and operation of the external interrupt and NMI controller. CHAPTER 9 "DELAYED INTERRUPT MODULE" This chapter describes the functions and operation of the delayed interrupt module. CHAPTER 10 "INTERRUPT CONTROLLER" This chapter describes the interrupt controller, the configuration and functions of registers, and interrupt controller operation. It also presents an example of using the hold request cancellation request function. CHAPTER 11 "A/D CONVERTER" This chapter describes the A/D converter, the configuration and functions of registers, and A/ D converter operation. CHAPTER 12 "UART" This chapter describes the UART, the configuration and functions of registers, and UART operation. CHAPTER 13 "I2C INTERFACE" This chapter describes the I2C interface, the configuration and functions of registers, and I2C interface operation. ii CHAPTER 14 "DMA CONTROLLER (DMAC)" This chapter describes the DMA controller (DMAC), the configuration and functions of registers, and DMAC operation. CHAPTER 15 "BIT SEARCH MODULE" This chapter describes the bit search module, the configuration and functions of registers, and bit search module operation. APPENDIX This appendix consists of the following parts: I/O map, interrupt vector, pin states in the CPU state, notes on using a little endian area, and instruction lists. The appendix contains detailed information that could not be included in the main text and reference material for programming. • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Copyright ©2001-2006 FUJITSU LIMITED All right reserved iii How To Read This Manual ■ Terms Used in This Manual The following defines principal terms used in this manual. Term Meaning I-bus 32 bit bus for internal instructions. In the FR family, which is based on an internal Harvard architecture, independent buses are used for instructions and data. A bus converter is connected to the I-bus. D-bus Internal 32-bit data bus. An internal resource is connected to the D-bus. F-bus Internal instructions and data are multiplexed on a Princeton bus. The F-bus is connected to the I-bus and D-bus via a switch. The F-bus is connected to built-in resources such as ROM and RAM. X-bus External interface bus. The X-bus is connected to the external interface module. Data and instructions are multiplexed on an external bus. R-bus Internal 16-bit data bus. The R-bus is connected to the F-bus via an adapter. An I-O, clock generator, and interrupt controller are connected to the R-bus. Since addresses and data are multiplexed on an R-bus that is 16 bits wide, more than one cycle is required for the CPU to access these resources. E-unit Execution unit for operations. CLKP System clock. Clock generated by the clock generator for each of the internal resources connected to the R-bus. This clock has the same frequency as the source oscillation at its maximum, but becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, or 1/16 (or 1/2, 1/4, 1/6, or 1/32) frequency clock as determined by the divide-by rate specified by the P3 to P0 bits in the clock generator DIVR0 register. CLKB System clock. Operating clock for the CPU and each of the other resources connected to a bus other than the R-bus and X-bus. This clock has the same frequency as the source oscillation at its maximum, but becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, or 1/16 (or 1/2, 1/4, 1/6, or 1/32) frequency clock as determined by the divided-by rate specified by the B3 to B0 bits in the clock generator DIVR0 register. CLKT System clock. Operating clock for the external resources connected to the Xbus. This clock has the same frequency as the source oscillation at its maximum, but becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, or 1/16 (or 1/2, 1/4, 1/6, or 1/32) frequency clock as determined by the divided-by rate specified by the T3 to T0 bits in the clock generator DIVR1 register. iv CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 CHAPTER 2 2.1 2.2 OVERVIEW ................................................................................................... 1 Features of the MB91307 Series ........................................................................................................ 2 Block Diagram .................................................................................................................................... 6 External Dimensions ........................................................................................................................... 7 Pin Layout ........................................................................................................................................... 8 List of Pin Functions ......................................................................................................................... 10 Input-output Circuit Forms ................................................................................................................ 18 HANDLING THE DEVICE .......................................................................... 23 Precautions on Handling the Device ................................................................................................. 24 Precautions on Handling Power Supplies ......................................................................................... 33 CHAPTER 3 CPU AND CONTROL UNITS ..................................................................... 35 3.1 Memory Space .................................................................................................................................. 3.2 Internal Architecture .......................................................................................................................... 3.3 Instruction Cache .............................................................................................................................. 3.3.1 Configuration of the Instruction Cache ........................................................................................ 3.3.2 Configuration of the Control Registers ........................................................................................ 3.3.3 Instruction Cache Statuses and Settings ..................................................................................... 3.3.4 Setting Up the Instruction Cache Before Use .............................................................................. 3.4 Dedicated Registers ......................................................................................................................... 3.4.1 Program Status (PS) Register ..................................................................................................... 3.5 General-Purpose Registers .............................................................................................................. 3.6 Data Structure ................................................................................................................................... 3.7 Word Alignment ................................................................................................................................ 3.8 Memory Map ..................................................................................................................................... 3.9 Branch Instructions ........................................................................................................................... 3.9.1 Operation of Branch Instructions with Delay Slot ........................................................................ 3.9.2 Operation of Branch Instruction without Delay Slot ..................................................................... 3.10 EIT (Exception, Interrupt, and Trap) ................................................................................................. 3.10.1 EIT Interrupt Levels ..................................................................................................................... 3.10.2 Interrupt Control Register (ICR) ................................................................................................... 3.10.3 System Stack Pointer (SSP) ........................................................................................................ 3.10.4 Table Base Register (TBR) ......................................................................................................... 3.10.5 Multiple EIT Processing ............................................................................................................... 3.10.6 EIT Operations ............................................................................................................................ 3.11 Reset (Device Initialization) .............................................................................................................. 3.11.1 Reset Levels ................................................................................................................................ 3.11.2 Reset Sources ............................................................................................................................. 3.11.3 Reset Sequence .......................................................................................................................... 3.11.4 Oscillation Stabilization Wait Time .............................................................................................. 3.11.5 Reset Operation Modes ............................................................................................................... 3.12 Clock Generation Control ................................................................................................................. v 36 40 45 46 49 52 54 57 60 64 65 66 67 68 69 72 73 74 76 77 78 82 84 88 89 90 92 94 96 98 3.12.1 PLL Controls ................................................................................................................................ 99 3.12.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time .................................................... 101 3.12.3 Clock Distribution ....................................................................................................................... 104 3.12.4 Clock Division ............................................................................................................................ 106 3.12.5 Block Diagram of Clock Generation Controller .......................................................................... 107 3.12.6 Register of Clock Generation Controller .................................................................................... 108 3.12.7 Peripheral Circuits of Clock Controller ....................................................................................... 127 3.13 Device State Control ....................................................................................................................... 130 3.13.1 Device States and State Transitions ......................................................................................... 131 3.13.2 Low-power Modes ..................................................................................................................... 134 3.14 Operating Modes ............................................................................................................................ 139 CHAPTER 4 EXTERNAL BUS INTERFACE ................................................................ 143 4.1 Overview of the External Bus Interface .......................................................................................... 4.2 External Bus Interface Registers .................................................................................................... 4.2.1 Area Select Registers 0 to 7(ASR0 to ASR7) ............................................................................ 4.2.2 Area Configuration Registers 0 to 7 (ACR0 to ACR7) ............................................................... 4.2.3 Area Wait Register (AWR0 to AWR7) ....................................................................................... 4.2.4 I/O Wait Registers for DMAC (IOWR0 to IOWR2) ..................................................................... 4.2.5 Chip Select Enable Register (CSER) ........................................................................................ 4.2.6 Cache Enable Register (CHER) ................................................................................................ 4.2.7 Pin/Timing Control Register (TCR) ............................................................................................ 4.3 Setting Example of the Chip Select Area ........................................................................................ 4.4 Endian and Bus Access .................................................................................................................. 4.4.1 Big Endian Bus Access ............................................................................................................. 4.4.2 Little Endian Bus Access ........................................................................................................... 4.4.3 Comparison of Big Endian and Little Endian External Access .................................................. 4.5 Operation of the Ordinary bus interface .......................................................................................... 4.5.1 Basic Timing .............................................................................................................................. 4.5.2 Operation of WE + Byte Control Type ....................................................................................... 4.5.3 Read → Write Operation ........................................................................................................... 4.5.4 Write → Write Operation ............................................................................................................ 4.5.5 Auto-Wait Cycle ......................................................................................................................... 4.5.6 External Wait Cycle ................................................................................................................... 4.5.7 Synchronous Write Enable Output ............................................................................................ 4.5.8 CS Delay Setting ....................................................................................................................... 4.5.9 CS → RD/WE Setup and RD/WE → CS Hold Setting ............................................................... 4.5.10 DMA Fly-By Transfer (I/O → Memory) ...................................................................................... 4.5.11 DMA Fly-By Transfer (Memory → I/O) ...................................................................................... 4.6 Burst Access Operation .................................................................................................................. 4.7 Address/data Multiplex Interface .................................................................................................... 4.8 Prefetch Operation .......................................................................................................................... 4.9 DMA Access Operation .................................................................................................................. 4.9.1 DMA Fly-By Transfer (I/O → Memory) ...................................................................................... 4.9.2 DMA Fly-By Transfer (Memory → I/O) ...................................................................................... 4.9.3 2-Cycle Transfer (Internal RAM → External I/O, RAM) ............................................................. 4.9.4 2-Cycle Transfer (External → I/O) ............................................................................................. vi 144 149 150 152 158 165 168 170 171 174 175 177 182 187 193 194 195 197 198 199 200 201 203 204 205 206 207 209 212 215 216 218 220 221 4.9.5 2-Cycle Transfer (I/O → External) ............................................................................................. 4.10 Bus Arbitration ................................................................................................................................ 4.11 Procedure for Setting a Register .................................................................................................... 4.12 Notes on Using the External Bus Interface ..................................................................................... CHAPTER 5 5.1 5.2 16-BIT RELOAD TIMER ........................................................................... 239 Overview of the 16-bit Reload Timer .............................................................................................. 16-bit Reload Timer Registers ........................................................................................................ Control Status Register (TMCSR) ............................................................................................. 16-bit Timer Register (TMR) ...................................................................................................... 16-bit Reload Register (TMRLR) ............................................................................................... 16-bit Reload Timer Operation ....................................................................................................... Operating States of the Counter ..................................................................................................... Precautions on Using the 16-bit Reload Timer ............................................................................... CHAPTER 7 7.1 7.2 7.3 I/O PORT .................................................................................................. 227 Overview of the I/O Port ................................................................................................................. 228 I/O Port Registers ........................................................................................................................... 230 CHAPTER 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.3 6.4 6.5 240 241 242 245 246 247 252 253 U-TIMER ................................................................................................... 255 Overview of the U-TIMER ............................................................................................................... 256 U-TIMER Registers ......................................................................................................................... 257 U-TIMER Operation ........................................................................................................................ 261 CHAPTER 8 EXTERNAL INTERRUPT AND NMI CONTROLLER ............................... 263 8.1 Overview of the External Interrupt and NMI Controller ................................................................... 8.2 External Interrupt and NMI Controller Registers ............................................................................. 8.2.1 Interrupt Enable Register (ENIR) ............................................................................................... 8.2.2 External Interrupt Source Register (EIRR) ................................................................................ 8.2.3 External Interrupt Request Level Setting Register (ELVR) ........................................................ 8.3 Operation of the External Interrupt and NMI Controller .................................................................. CHAPTER 9 9.1 9.2 9.3 222 223 225 226 264 265 266 267 268 269 DELAYED INTERRUPT MODULE ........................................................... 273 Overview of the Delayed Interrupt Module ..................................................................................... 274 Delayed Interrupt Module Registers ............................................................................................... 275 Operation of the Delayed Interrupt Module ..................................................................................... 276 CHAPTER 10 INTERRUPT CONTROLLER ................................................................... 277 10.1 Overview of the Interrupt Controller ................................................................................................ 10.2 Interrupt Controller Registers .......................................................................................................... 10.2.1 Interrupt Control Register (ICR) ................................................................................................. 10.2.2 Hold Request Cancellation Request Level Setting Register (HRCL) ........................................ 10.3 Interrupt Controller Operation ......................................................................................................... 10.4 Example of Using the Hold Request Cancellation Request Function (HRCR) ............................... vii 278 280 282 284 285 291 CHAPTER 11 A/D CONVERTER .................................................................................... 293 11.1 Overview of the A/D Converter ....................................................................................................... 11.2 A/D Converter Registers ................................................................................................................. 11.2.1 A/D Control Status Register (ADCS) ......................................................................................... 11.2.2 Data Register (ADCR) ............................................................................................................... 11.3 A/D Converter Operation ................................................................................................................ 11.4 Conversion Data Protection Function ............................................................................................. 11.5 Precautions on the Using A/D Converter ........................................................................................ 294 296 297 302 303 305 307 CHAPTER 12 UART ........................................................................................................ 309 12.1 Overview of the UART .................................................................................................................... 12.2 UART Registers .............................................................................................................................. 12.2.1 Serial Mode Register (SMR) ...................................................................................................... 12.2.2 Serial Control Register (SCR) ................................................................................................... 12.2.3 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) ................................... 12.2.4 Serial Status Register (SSR) ..................................................................................................... 12.2.5 DRCL Register .......................................................................................................................... 12.3 UART Operation ............................................................................................................................. 12.3.1 Asynchronous (Start-stop Synchronization) Mode .................................................................... 12.3.2 CLK Synchronous Mode ............................................................................................................ 12.3.3 Occurrence of Interrupts and Timing for Setting Flags .............................................................. 12.4 Example of Using the UART ........................................................................................................... 12.5 Example of Setting U-TIMER Baud Rates and Reload Values ...................................................... 310 312 313 315 318 319 322 323 325 327 329 332 334 CHAPTER 13 I2C INTERFACE ....................................................................................... 335 13.1 Overview of the I2C Interface .......................................................................................................... 13.2 I2C Interface Registers ................................................................................................................... 13.2.1 Bus Status Register (IBSR) ....................................................................................................... 13.2.2 Bus Control Register (IBCR) ..................................................................................................... 13.2.3 Clock Control Register (ICCR) .................................................................................................. 13.2.4 10-bit Slave Address Register (ITBA) ........................................................................................ 13.2.5 10-bit Slave Address Mask Register (ITMK) ............................................................................. 13.2.6 7-bit Slave Address Register (ISBA) ......................................................................................... 13.2.7 7-bit Slave Address Mask Register (ISMK) ............................................................................... 13.2.8 Data Register (IADR) ................................................................................................................. 13.2.9 Clock Disable Register (IDBL) ................................................................................................... 13.3 I2C Interface Operation ................................................................................................................... 13.4 Operation Flowcharts ...................................................................................................................... 336 338 340 343 350 352 353 355 356 357 358 359 364 CHAPTER 14 DMA CONTROLLER (DMAC) .................................................................. 367 14.1 Overview of the DMA Controller (DMAC) ....................................................................................... 14.2 DMA Controller (DMAC) Registers ................................................................................................. 14.2.1 Control/Status Registers A (DMACA0 to DMACA4) .................................................................. 14.2.2 Control/Status Registers B (DMACB0 to DMACB4) .................................................................. 14.2.3 Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to DMASA4/DMADA0 to DMADA4).......................................................................... 14.2.4 DMAC All-Channel Control Register (DMACR) ......................................................................... viii 368 370 372 377 383 385 14.2.5 Other Functions ......................................................................................................................... 14.3 DMA Controller (DMAC) Operation ................................................................................................ 14.3.1 Setting a Transfer Request ........................................................................................................ 14.3.2 Transfer Sequence .................................................................................................................... 14.3.3 General Aspects of DMA Transfer ............................................................................................. 14.3.4 Addressing Mode ....................................................................................................................... 14.3.5 Data Types ................................................................................................................................ 14.3.6 Transfer Count Control .............................................................................................................. 14.3.7 CPU Control .............................................................................................................................. 14.3.8 Hold Arbitration .......................................................................................................................... 14.3.9 Operation from Starting to End/Stopping ................................................................................... 14.3.10 DMAC Interrupt Control ............................................................................................................. 14.3.11 Channel Selection and Control .................................................................................................. 14.3.12 Supplement on External Pin and Internal Operation Timing ..................................................... 14.4 Operation Flowcharts ...................................................................................................................... 14.5 Data Bus ......................................................................................................................................... 14.6 DMA External Interface ................................................................................................................... 14.6.1 Examples of DMA External Interface Operation (Simplified Waveforms) .................................. 14.6.2 Input Timing of the DREQx Pin ................................................................................................. 14.6.3 FR30 Compatible Mode of DACK(DEOP) ................................................................................. 387 388 391 392 396 398 399 400 401 402 403 407 408 410 414 417 420 421 423 425 CHAPTER 15 BIT SEARCH MODULE ........................................................................... 427 15.1 15.2 15.3 Overview of the Bit Search Module ................................................................................................ 428 Bit Search Module Registers .......................................................................................................... 429 Bit Search Module Operation .......................................................................................................... 431 APPENDIX ......................................................................................................................... 435 APPENDIX A I/O MAP ............................................................................................................................... APPENDIX B INTERRUPT VECTOR ........................................................................................................ APPENDIX C PIN STATE IN EACH CPU STATE ...................................................................................... APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA .................................................................... D.1 C Compiler (fcc911) ....................................................................................................................... D.2 Assembler (fasm911) ..................................................................................................................... D.3 Linker (flnk911) .............................................................................................................................. D.4 Debugger (sim911, eml911, mon911) ............................................................................................ APPENDIX E INSTRUCTION LISTS ......................................................................................................... E.1 How to Read the Instruction Lists .................................................................................................. E.2 FR Family Instruction Lists ............................................................................................................. 436 446 450 457 458 461 463 464 465 466 470 INDEX................................................................................................................................... 487 ix x Main changes in this edition Page Changes (For details, refer to main body.) 24 A sentence is added to ❍ Quartz oscillation circuit 25 ❍ Bit search module is changed (BSDC registers → BDSC registers) 26 ❍ Low power consumption mode is changed 28 ❍ RD/WD-CS hold extension cycle is changed (RD/WR-CS → RD/WD-CS) 29 ❍ DMA transfer source selection (MB91306R/307R only) is added 32 ❍ Operand break is added 33 ■ Processing of Source Oscillation Input after Power-on is changed (wait → wait time) 38 Figure 3.1-4 Address Map Immediately After a Reset is Cleared is changed (0004_0000H → 0000_0400H) 38 ❍ Immediately after a reset is cleared is changed (000F_FFF8H and 001F_FFFCH → 001F_FFF8H and 001F_FFFCH) 39 Figure 3.1-5 Address Map of Initialization Step is changed (Internal RAM → Built-in RAM) 49 Lead of 3.3.2 Configuration of the Control Registers is changed (instruction cache register (ICHCR) → instruction cache control register (ICHCR)) 49 Figure 3.3-3 Configuration of the Cache Size Register (ISIZE) Bits is changed (Control Register (ISIZE) → Cache Size Register (ISIZE)) 57 Lead of 3.4 Dedicated Registers is changed (table base register (TBC) → table base register (TBR)) 74 Table 3.10-1 EIT Interrupt Levels is changed (rows of Interrupt source, Remarks are added) 75 ■ I Flag is changed (Bit 4 → CCR Bit 4) 79 to 81 Table 3.10-4 Vector Table is changed (RN row is deleted) 84 ■ Operation of User Interrupt/NMI is changed (3. Mask and do → 3. Mask but do) 89 A sentence is added to ❍ Items initialized in a settings initialization reset (INIT) 98 ❍ Self-induced oscillation mode (X0/X1 pin input) is changed (main Plus → main PLL) 108 The explanation for state0 of [Bit 15] INIT (INITialize reset occurred) is changed (INIT → No INIT) 109 [Bit 12] ERST (External ReSeT occurred) is changed (reset(INIT) → reset(RST)) 111 [Bit 6] SLEEP (SLEEP mode) is changed (Bit 6 (SLEEP bit) → Bit 7 (STOP bit)) (this bit(STOP) → Bit 7(STOP)) 111 [Bit 5] HIZ (HIZ mode) is changed (initialized to 0 → initialized to "1") 113 Note: is changed 115 Note: is deleted 128 [Suspending the watchdog timer (automatic postponement)] is changed 133 ■ Operation Initialization Reset (RST) State is changed (are stopped and but are deleted) xi Page Changes (For details, refer to main body.) 138 ❍ Normal and synchronous reset operations is changed (standby → reset) 148 Figure 4.1-2 List of External Bus Interface Registers is changed (IOWR2 → IOWR1) (CSER → CHER) (CSER → Reserved) 149 ■ Register Types is changed ( • Mode register (MODR) is deleted) 153 Note: is added 163 [Bits 17/1] W01 (CS → RD/WE Setup Extension Cycle) is changed (external clock MCLK → external memory clock MCLK) 165 4.2.4 I/O Wait Registers for DMAC (IOWR0 to IOWR2) is changed (DMAC (IOWR0-3) → DMAC (IOWR0 to IOWR2)) 165 ■ Configuration of the I/O Wait Registers for DMAC (IOWR0-3) is changed (IOWR0-3 → IOWR0 to IOWR2) 165 Figure 4.2-4 Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR2) is changed (IOWR0-3 → IOWR0 to IOWR2) (Bit configuration figure of IOWR3 bit is deleted) (0000 0688H → 0000 0678H) (0000 0689H → 0000 0679H) (0000 068aH → 0000 067AH) 165, 166 ■ Functions of Bits in the I/O Wait Registers for DMAC (IOWR0 to IOWR2) is changed (Descriptions of bit7,bit6,bit5,bit4 are deleted) (channels 0-3 → channels 0 to 2) (RYE3 is deleted) (HLD3 is deleted) 172 [Bits 3, 2] OHT1, OHT0 (Output hold delay selection) is changed (external clock → external memory clock) 179 Figure 4.4-13 Relationship between Internal Register and External Data Bus for Byte Access is changed (Halfword access → Byte access) 196 • Set write recovery cycle to "1" or more is changed 214 ❍ Reading from the prefetch buffer is changed (up to 16 bits → up to 16 bytes) 215 • 2-cycle transfer (internal RAM → external I/O, RAM) is changed (I/O → external I/O) 216 Figure 4.9-1 Timing Chart for DMA Fly-By Transfer (I/O → Memory) is changed (The explanation of *1 is added) (The explanation of *2 is added) 218 Figure 4.9-2 Timing chart for DMA Fly-By Transfer (Memory → I/O) is changed (The explanation of *1 is added) (The explanation of *2 is added) 218, 219 ■ DMA Fly-By Transfer (Memory -> I/O) is changed (IOWR0-3 → IOWR0 to IOWR2) 220 Figure 4.9-3 Timing Chart for 2-cycle Transfer (Internal RAM → External I/O, RAM) is changed (The explanation of Basic cycle is added) 221 Figure 4.9-4 Timing Chart for 2-Cycle Transfer (External → I/O) is changed (The explanation of Basic cycle is added) xii Page Changes (For details, refer to main body.) 222 Figure 4.9-5 Timing Chart for 2-Cycle Transfer (I/O → External) is changed (The explanation of Basic cycle is added) 224 Figure 4.10-2 Timing Chart for Acquiring the Bus Right is changed (Read → Write) 225 A sentence is added to 2. and 4. of ■ Procedure for Setting a Register 228 Figure 5.1-1 Basic Block Diagram of the I/O Port is changed (Peripheral output → Peripheral input) 229 ❍ Port output mode (PFR=0 & DDR=1) is changed (Port input → Port output) 229 ❍ Peripheral output mode (PFR=1 & DDR=x) is changed (Port input → Peripheral output) 229 The item of • in Notes: is deleted 230 ■ Configuration of the Port Data Registers (PDR) is changed (PDR0-PDRP → PDR2 to PDRJ) (PFR6-PFRO → PFR6 to PFRJ) (The item of • is deleted) 233, 237 Table 5.2-1 Functions of the Port Function Registers (PFR) is changed (*1 is deleted) (The explanation of *1 is deleted) 246 Lead of 6.2.3 16-bit Reload Register (TMRLR) is changed (Be sure to read → Be sure to write) 247 Figure 6.3-1 Startup and Operations of the Counter is changed (Reload load → Reload data) 251 A sentence is added to ■ Other Operation 259 [Bit 2] CLKS (clock select) is changed (* is deleted) (The explanation of * is deleted) 265 Figure 8.2-1 List of External Interrupt and NMI Controller Registers is changed (External Interrupt → List of External) 269 Procedures are added to ■ Operating Procedure for an External Interrupt 270 "The terms of ■ External Interrupt Request Level are changed (Source Holding Circuit → External Interrupt Source Register) (Source F/F → External interrupt source register)" 270 ■ NMI is changed (NMIC pin → NMI pin) 285 to 288 Table 10.3-1 Relationship Between Interrupt Sources, Interrupt Numbers, and Interrupt Levels is changed (RN line is deleted) 290 ■ Clearing an Interrupt Source is deleted 295 Figure 11.1-1 Block Diagram of the A/D Converter is changed (AD control register (ADCS) → A/D control status register (ADCS)) 296 Figure 11.2-1 A/D Converter Registers is changed (Control data register (ADCS) → A/D control status register (ADCS)) 298 Table 11.2-1 Settings of A/D Conversion Start Causes is changed (timer → reload timer) 301 Note: is added 302 The address in Figure 11.2-3 Bit Configuration of the Data Register (ADCR) is changed (000038H → 000078H) xiii Page Changes (For details, refer to main body.) 302 The initial value indicated in Figure 11.2-3 Bit Configuration of the Data Register (ADCR) is changed (0 → X) 339 Figure 13.2-1 I2C Interface Registers is changed (Data register(IDAR) → Data register(IADR)) 341 [Bit 3] TRX (Transferring Data) is changed (mask interrupt status → master interrupt status) 345 A sentence is added to Note: 358 Note: is added to ■ Clock Disable Register (IDBL) 368 ❍ Channel priority rotation is changed 373 [Bit 30] PAUS (PAUSe)*: Temporary stop instruction is changed 374 * and explanation are added to Table 14.2-1 Settings for Transfer Request Sources 391 The item of • is added to Notes: in ■ Built-in Peripheral Request 394 ❍ Demand transfer fly-by transfer is changed (External area → All 32-bit areas specifiable) 398 Notes: is changed (the description for the items related to the end code → "Table 14.2-6 End Codes" for details) 403 A sentence is added to ■ Transfer Request Acceptance and Transfer 405 ❍ Transfer stop requests from peripheral circuits is changed (the specifications for each peripheral circuit → "12.2.5 DRCL Register") 413 ■ AC Characteristics of DMAC is changed (DMAC → DMAC on the Data sheet) 437 Access unit of HRCL in Table A-1 I/O Map is changed 438, 439 485 Registers in Table A-1 I/O Map are changed (DMACB0 → DMACB1) (DMACB0 → DMACB2) (DMACB0 → DMACB3) (DMACB0 → DMACB4) (ICHRC → ICHCR) Note: is added to Table E.2-19 Resource Instructions xiv CHAPTER 1 OVERVIEW This chapter provides basic information required to understand the MB91307 series, and covers features, a block diagram, and functions. 1.1 Features of the MB91307 Series 1.2 Block Diagram 1.3 External Dimensions 1.4 Pin Layout 1.5 List of Pin Functions 1.6 Input-output Circuit Forms 1 CHAPTER 1 OVERVIEW 1.1 Features of the MB91307 Series The MB91307 series is a standard single-chip microcontroller that has a 32-bit highperformance RISC CPU as well as built-in I/O resources and bus control mechanisms for embedded controller requiring high-performance and high-speed CPU processing. Although the MB91307 series basically uses external bus access to support a vast address space accessed by a 32-bit CPU, it has a 1 KB instruction cache memory and large-capacity RAM to increase the speed at which the CPU executes instructions. The MB91307 series is most suitable for embedded applications, such as DVD players, navigation systems, high-performance fax machines, and printer controllers, that require a high level of CPU processing power. This model is an FR60 model that is based on the FR30/40 of CPUs. It has enhanced bus access and is optimized for high-speed use. ■ FR CPU • 32-bit RISC, load/store architecture, five pipelines • Operating frequency of 66 MHz [PLL used, original oscillation at 16.5 MHz] • 16-bit fixed-length instructions (basic instructions), one instruction per cycle • Memory-to-memory transfer, bit processing, instructions, including barrel shift, etc.-instructions appropriate for embedded applications • Function entry and exit instructions, multi load/store instructions--instructions compatible with high-level languages • Register interlock function to facilitate assembly-language coding • Built-in multiplier/instruction-level support • Signed 32-bit multiplication: 5 cycles • Signed 16-bit multiplication: 3 cycles • Interrupts (saving of PC and PS): 6 cycles, 16 priority levels • Harvard architecture enabling simultaneous execution of both program access and data access • 4-word queues in the CPU provided to add an instruction prefetch function • Vast 4 GB memory space that can be accessed linearly ■ Bus Interface 2 • Maximum operating frequency of 33 MHz • 25-bit addresses can be fully output (32 MB space) • 8- and 16-bit data output • Prefetch buffer installed • Unused data and address pins can be used as general-purpose I/O ports. • Totally independent 8-area chip select output that can be defined at a minimum of 64 KB CHAPTER 1 OVERVIEW • Support of interfaces for various memory modules • SRAM, ROM/Flash • Page-mode Flash ROM, page-mode ROM interfaces • Burst-mode Flash ROM (a burst length of 1, 2, 4, or 8 can be selected) • Basic bus cycle: 2 cycles • Automatic wait cycle generator that can be programmed for each area and can insert waits • External wait cycles due to RDY input • Supports fly-by DMA transfer that enables independent I/O wait control ■ Built-in RAM • 128 KB (MB91307B/R), 64 KB (MB91306R) RAM installed • Built-in RAM can be used as instruction RAM if instruction codes, instead of data, are written to it ■ Instruction Cache • Capacity of 1 KB • 2 way set associative • 4 words (16 bytes) per set • Lock function allows programs to stay resident • A part of the instruction cache not in use can be used as RAM ■ DMAC (DMA Controller) • 5 channels (3 channels for external to external) • 3 transfer sources (external pins, internal peripherals, software) • Addressing mode with 32-bit full address specifications (increase, decrease, fixed) • Transfer modes (demand transfer, burst transfer, step transfer, block transfer) • Fly-by transfer supported (three channels between external I/O and external memory) • Transfer data size that can be selected from 8, 16, and 32 bits ■ Bit Search Module (Used by REALOS) • Searches for the position of the first bit varying between 1 and 0 in the MSB of a word ■ Reload Timer (including One Channel for REALOS) • 16-bit timer; 3 channels • Internal clock that can be selected from those resulting from frequency divided by 2, 8, and 32 3 CHAPTER 1 OVERVIEW ■ UART • Full-duplex double buffer • 3 channels • Parity or no parity can be selected. • Either asynchronous (start-stop synchronization) or CLK synchronous communication can be selected. • Built-in timer for dedicated baud rates • An external clock can be used as the transfer clock • Plentiful error detection functions (parity, frame, overrun) ■ I2C Interface • Master/slave transmission and reception • Clock synchronization function • Transfer direction detection function • Bus error detection function • Supports standard mode (Max 100 Kbps) and high-speed mode (Max 400 Kbps). • Arbitration function • Slave address/general call address detection function • Start condition repetitious occurrence and detection function • 10-bit/7-bit slave address ■ Interrupt Controller • Total of 9 external interrupts (one unmaskable pin (NMI) and eight regular interrupt pins (INT7 to INT0)) • Interrupts from internal peripherals • Priority level can be defined as programmable (16 levels) except for the unmaskable pin • Can be used for wake-up during stop ■ A/D Converter • 10-bit resolution, 4 channels • Sequential comparison and conversion type (conversion time: about 5.4 µs: CLKP = 33MHz) • Conversion modes (single-shot conversion mode, successive conversion mode) • Causes of startup (software, external triggers, timer output signals) ■ Other Interval Timers 4 • 16-bit timer: 3 channels (U-TIMER) • Watchdog timer CHAPTER 1 OVERVIEW ■ I/O Ports • Maximum of 69 ports ■ Other Features • Has a built-in oscillation circuit as a clock source for which PLL multiplication can be selected. • INIT is provided as a reset pin. • Additionally, a watchdog timer reset and software resets are provided. • Stop mode and sleep mode supported as low-power modes • Gear function • Built-in time base timer • Packages • • • LQFP-120 (FPT-120P-M21): MB91307B MB91306R, and MB91307R • PGA135: MB91V307R (evaluation product common to MB91307B MB91306R, and MB91307R) CMOS technology • 0.25 µm: MB91307B and MB91V307R • 0.18 µm: MB91306R and MB91307R Power voltages • MB91307B and MB91V307R: 3.3 V -0.3 V to +0.3 V (built-in regulator: 3.3 V → 2.5 V) • MB91306R and MB91307R: 3.3 V -0.3 V to +0.3 V, 1.8 V -0.15 V to +0.15 V (two power supplies) ■ MB91307 Series MB91307B MB91306R/MB91307R Process CMOS 0.25µm CMOS 0.18µm Power voltage 3.3 V -0.3 V to +0.3 V Single power supply with built-in debooster 3.3 V -0.3 V to +0.3 V, 1.8 V -0.15 V to +0.15 V Two power supplies Hardware standby function Supported Not supported 5 CHAPTER 1 OVERVIEW 1.2 Block Diagram Figure 1.2-1 is a block diagram of the MB91307 series. ■ Block Diagram Figure 1.2-1 Block Diagram FR CPU Core 32 32 I$ 1KB Bit search Bus converter RAM * DMAC5ch 32 32 ↔ 16 adapter External memory I/F 16 Clock control UART 3ch U-TIMER 3ch I2C 1ch Interrupt controller External interrupt *: Built-in RAM 6 Reload timer 3ch 128KB: MB91307B/R 64KB: MB91306R A/D 4ch Port CHAPTER 1 OVERVIEW 1.3 External Dimensions The MB91307 series is available in one type of package. ■ Dimensions of the FPT-120P-M21 Figure 1.3-1 Dimensions of the FPT-120P-M21 7 CHAPTER 1 OVERVIEW 1.4 Pin Layout This section shows the pin layout of the MB91307 series. ■ Pin Layout of the MB91307B Figure 1.4-1 is a diagram of the pin layout of the MB91307B. 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 PA2/CS2 PA1/CS1 CS0 PB7/IORD PB6/IOWR VCC X0 X1 VSS PB5/DEOP1 PB4/DACK1 PB3/DREQ1 PB2/DEOP0 PB1/DACK0 PB0/DREQ0 MD2 MD1 MD0 PG2/DEOP2 PG1/DACK2 PG0/DREQ2 PH7/SCL PH6/SDA PH5/TOT2 PH4/TOT1 * PH3/TOT0 * VSS PH2/SC2 PH1/SO2 PH0/SI2 Figure 1.4-1 Pin Layout of the MB91307B 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 MB91307B (TOP VIEW) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P26/D22 P27/D23 D24 D25 D26 D27 D28 D29 D30 D31 VSS A00 A01 A02 A03 A04 A05 A06 A07 VCC A08 A09 A10 A11 A12 A13 A14 A15 VSS P60/A16 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PA3/CS3 PA4/CS4 PA5/CS5 C PA6/CS6 PA7/CS7 P80/RDY P81/BGRNT P82/BRQ RD UUB/WR0 P85/ULB/WR1 NMI HST VSS INIT P90/SYSCLK P91 P92/MCLK P93 P94/LBA/AS P95/BAA P96 P97/WE P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 * : "L" output initially and upon reset. 8 PI5/SC1 PI4/SO1 PI3/SI1 PI2/SC0 PI1/SO0 PI0/SI0 VCC PJ7/INT7/ATG PJ6/INT6/TIN2 PJ5/INT5/TIN1 PJ4/INT4/TIN0 PJ3/INT3 PJ2/INT2 PJ1/INT1 PJ0/INT0 AN3 AN2 AN1 AN0 AVSS/AVRL AVRH AVCC A24/P70 A23/P67 A22/P66 A21/P65 A20/P64 A19/P63 A18/P62 A17/P61 CHAPTER 1 OVERVIEW ■ Pin Layout of the MB91307R 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 PA2/CS2 PA1/CS1 CS0 PB7/IORD PB6/IOWR VCC X0 X1 VSS PB5/DEOP1 PB4/DACK1 PB3/DREQ1 PB2/DEOP0 PB1/DACK0 PB0/DREQ0 MD2 MD1 MD0 PG2/DEOP2 PG1/DACK2 PG0/DREQ2 PH7/SCL PH6/SDA PH5/TOT2 PH4/TOT1 * PH3/TOT0 * VSS PH2/SC2 PH1/SO2 PH0/SI2 Figure 1.4-2 Pin Layout of the MB91306R/MB91307R MB91306R MB91307R (TOP VIEW) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PI5/SC1 PI4/SO1 PI3/SI1 PI2/SC0 PI1/SO0 PI0/SI0 VCC PJ7/INT7/ATG PJ6/INT6/TIN2 PJ5/INT5/TIN1 PJ4/INT4/TIN0 PJ3/INT3 PJ2/INT2 PJ1/INT1 PJ0/INT0 AN3 AN2 AN1 AN0 AVSS/AVRL AVRH AVCC A24/P70 A23/P67 A22/P66 A21/P65 A20/P64 A19/P63 A18/P62 A17/P61 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 P26/D22 P27/D23 D24 D25 D26 D27 D28 D29 D30 D31 VSS A00 A01 A02 A03 A04 A05 A06 A07 VCC A08 A09 A10 A11 A12 A13 A14 A15 VSS P60/A16 PA3/CS3 PA4/CS4 PA5/CS5 VCCI PA6/CS6 PA7/CS7 P80/RDY P81/BGRNT P82/BRQ RD UUB/WR0 P85/ULB/WR1 NMI VCCI VSS INIT P90/SYSCLK P91 P92/MCLK P93 P94/LBA/AS P95/BAA P96 P97/WE P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 * : "L" output initially and upon reset. Note: Vcc : 3.3V power supply pin VccI : 1.8V power supply pin 9 CHAPTER 1 OVERVIEW 1.5 List of Pin Functions This section describes the pin functions of the MB91307 series. ■ Description of Pin Functions Table 1.5-1 lists the pin of the MB91307 series and their functions. Table 1.5-1 Pin Function Table (1/8) Pin number 85 to 92 Pin name D16 to D23 I/O circuit form C P20 to P27 Bits 16 to 23 of the external data bus. Enabled only in external bus 16-bit mode. Can be used as a port in external bus 8-bit mode. 93 to 100 D24 to D31 C Bits 24 to 31 of the external data bus 102 to 109 A00 to A07 F Bits 0 to 7 of the external address output 111 to 118 A08 to A15 F Bits 8 to 15 of the external address output 120,1 to 7 8 12 to 15 16 to 19 A16 to A23 P60 to P67 A24 P70 AN0 to AN3 INT0 to INT3 F F D I PJ0 to PJ3 20 to 22 PJ4 to PJ6 Can be used as a port according to the setting. Bit 24 of the external address output Can be used as a port according to the setting. Analog input pin for A/D converter [INT0 to INT3] External interrupt input. Since this input is used whenever the corresponding external interrupt is enabled, it can be used at any time. Output by other functions must be stopped unless it is absolutely required. [TIN0 to TIN2] Reload timer input. Since this input is used whenever the corresponding timer input is enabled, it can be used at any time. Output by other functions must be stopped unless it is absolutely required. I INT4 to INT6 Bits 16 to 23 of the external address output [PJ0 to PJ3] General-purpose input-output port TIN0 to TIN2 10 Function [INT4 to INT6] External interrupt input. Since this input is used whenever the corresponding external interrupt is enabled, it can be used at any time. Output by other functions must be stopped unless it is absolutely required. [PJ4 to PJ6] General-purpose input-output port CHAPTER 1 OVERVIEW Table 1.5-1 Pin Function Table (2/8) Pin number Pin name I/O circuit form [ATG] A/D converter external trigger input. Since this input is used whenever it is selected as the cause of A/D start-up, it can be used at any time. Output by other functions must be stopped unless it is absolutely required. ATG I INT7 [INT7] External interrupt input. Since this input is used whenever the corresponding external interrupt is enabled, it can be used at any time. Output by other functions must be stopped unless it is absolutely required. PJ7 [PJ7] General-purpose input-output port SI0 [SI0] UART0 data input. Since this input is used whenever UART0 is performing an input operation, it can be used at any time. Output by other functions must be stopped unless it is absolutely required. 23 25 [PI0] General-purpose input-output port SO0 [SO0] UART0 data output. This function is enabled when the UART0 data output specification is enabled. F PI1 [PI1] General-purpose input-output port. This function is enabled when the UART0 data output function is disabled. SC0 [SC0] UART0 clock input-output. Clock output is enabled when the UART0 clock output specification is enabled. 27 29 F PI2 [PI2] General-purpose input-output port. This function is enabled when the UART0 clock output function is disabled. SI1 [SI1] UART1 data input. Since this input is used whenever UART1 is performing an input operation, it can be used at any time. Output by other functions must be stopped unless it is absolutely required. F PI3 [PI3] General-purpose input-output port SO1 [SO1] UART1 data output. This function is enabled when the UART1 data output specification is enabled. F PI4 [PI4] General-purpose input-output port. This function is enabled when the UART1 data output function is disabled. SC1 [SC1] UART1clock input-output. Clock output is enabled when the UART1 clock output specification is enabled. 30 31 F PI0 26 28 Function F PI5 [PI5] General-purpose input-output port. This function is enabled when the UART1 clock output function is disabled SI2 [SI2] UART2 data input. Since this input is used whenever UART2 is performing an input operation, it can be used at any time. Output by other functions must be stopped unless it is absolutely required. PH0 F [PH0] General-purpose input-output port 11 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Function Table (3/8) Pin number Pin name I/O circuit form SO2 F 32 [PH1] General-purpose input-output port. This function is enabled when the UART2 data output function is disabled. SC2 [SC2] UART2clock input-output. Clock output is enabled when the UART2 clock output specification is enabled. F PH2 TOT0 35 C PH3 TOT1 36 C PH4 38 39 TOT2 C [TOT0] Timer output port. This function is enabled when timer output is enabled. [PH3] General-purpose input-output port. This pin is set to L output upon reset. [TOT1] Timer output port. This function is enabled when timer output is enabled. [PH4] General-purpose input-output port. This pin is set to L output upon reset. [TOT2] Timer output port. This function is enabled when timer output is enabled. [PH5] General-purpose input-output port SDA [SDA] Input-output pin for the I2C bus. This function is enabled when I2C is enabled. The port output must be set to Hi-Z to use the I2C bus. This pin is an open-drain pin when the I2C bus is being used. Q PH6 [PH6] General-purpose input-output port SCL [SCL] Input-output pin for the I2C bus. This function is enabled when I2C is enabled. The port output must be set to Hi-Z to use the I2C bus. This pin is an open-drain pin when the I2C bus is being used. Q DREQ2 [PH7] General-purpose input-output port F PG0 41 F PG1 [DREQ2] DMA external transfer request input. Since this input is used whenever this pin is selected as the cause of DMA startup, it can be used at any time. Output by other functions must be stopped unless it is absolutely required. [PG0] General-purpose input-output port DACK2 12 [PH2] General-purpose input-output port. This function is enabled when the UART2 clock output function is disabled PH5 PH7 40 [SO2] UART2 data output. This function is enabled when the UART2 data output specification is enabled. PH1 33 37 Function [DACK2] DMA external transfer request acceptance output. This function is enabled when the DMA transfer request acceptance output specification is enabled. [PG1] General-purpose input-output port. This function is enabled when the DMA transfer request acceptance output specification is disabled. CHAPTER 1 OVERVIEW Table 1.5-1 Pin Function Table (4/8) Pin number 42 Pin name I/O circuit form DEOP2 [DEOP2] DMA external transfer completion output. This function is enabled when the DMA external transfer completion output specification is enabled. DSTP2 [DSTP2] DMA external transfer halt input. This function is enabled when the DMA external transfer halt input specification is enabled. F [PG2] General-purpose input-output port. This function is enabled when the DMA external transfer completion output specification and the external transfer halt input specification are disabled. PG2 43 to 45 46 MD2 to MD0 DREQ0 G F PB0 47 F PB1 49 Mode pins 2 to 0. Configure these pins to define the basic operating mode. Connect them to VCC or VSS. [DREQ0] DMA external transfer request input. Since this input is used whenever this pin is selected as the cause of DMA start-up, it can be used at any time. Output by other functions must be stopped unless it is absolutely required. [PB0] General-purpose input-output port DACK0 48 Function [DACK0]DMA external transfer request acceptance output. This function is enabled when the DMA transfer request acceptance output specification is enabled. [PB1] General-purpose input-output port. This function is enabled when the DMA transfer request acceptance output specification is disabled. DEOP0 [DEOP0] DMA external transfer completion output. This function is enabled when the DMA external transfer completion output specification is enabled. DSTP0 [DSTP0] DMA external transfer halt input. This function is enabled when the DMA external transfer halt input specification is enabled. F PB2 [PB2] General-purpose input-output port. This function is enabled when the DMA external transfer completion output specification and the external transfer halt input specification are disabled. DREQ1 [DREQ1] DMA external transfer request input. Since this input is used whenever this pin is selected as the cause of DMA startup, it can be used at any time. Output by other functions must be stopped unless it is absolutely required. PB3 F [PB3] General-purpose input-output port 13 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Function Table (5/8) Pin number Pin name I/O circuit form DACK1 50 F PB4 51 [DACK1] DMA external transfer request acceptance output. This function is enabled when the DMA transfer request acceptance output specification is enabled. [PB4] General-purpose input-output port. This function is enabled when the DMA transfer request acceptance output specification is disabled. DEOP1 [DEOP1] DMA external transfer completion output. This function is enabled when the DMA external transfer completion output specification is enabled. DSTP1 [DSTP1] DMA external transfer halt input. This function is enabled when the DMA external transfer halt input specification is enabled. F [PB5] General-purpose input-output port. This function is enabled when the DMA external transfer completion output specification and the external transfer halt input specification are disabled. PB5 53 X1 54 X0 A IOWR F 56 PB6 IORD F 57 Clock (oscillation) output Clock (oscillation) input [IOWR] Write strobe output used during DMA fly-by transfer. This function is enabled when the DMA fly-by transfer write strobe output specification is enabled. [PB6] General-purpose input-output port. This function is enabled when the DMA fly-by transfer write strobe output specification is disabled. [IORD] Read strobe output used during DMA fly-by transfer. This function is enabled when the DMA fly-by transfer read strobe output specification is enabled. PB7 [PB7] General-purpose input-output port. This function is enabled when the DMA fly-by transfer read strobe output specification is disabled. CS0 [CS0] Chip Select 1 output. This function is enabled when the Chip Select 0 output specification is enabled. F 58 PA1 [PA1] General-purpose input-output port. This function is enabled when the Chip Select 1 output specification is disabled. CS1 [CS1] Chip Select 1 output. This function is enabled when the Chip Select 1 output specification is enabled. F 59 PA1 14 Function [PA1] General-purpose input-output port. This function is enabled when the Chip Select 1 output specification is disabled. CHAPTER 1 OVERVIEW Table 1.5-1 Pin Function Table (6/8) Pin number Pin name I/O circuit form CS2 F 60 Function [CS2] Chip Select 2 output. This function is enabled when the Chip Select 2 output specification is enabled. PA2 [PA2] General-purpose input-output port. This function is enabled when the Chip Select 2 output specification is disabled. CS3 [CS3] Chip Select 3 output. This function is enabled when the Chip Select 3 output specification is enabled. F 61 PA3 [PA3] General-purpose input-output port. This function is enabled when the Chip Select 3 output specification is disabled. CS4 [CS4] Chip Select 4 output. This function is enabled when the Chip Select 4 output specification is enabled. F 62 PA4 [PA4] General-purpose input-output port. This function is enabled when the Chip Select 4 output specification is disabled. CS5 [CS5] Chip Select 5 output. This function is enabled when the Chip Select 5 output specification is enabled. F 63 PA5 [PA5] General-purpose input-output port. This function is enabled when the Chip Select 5 output specification is disabled. C - (MB91307B) [C] Bypass capacitor pin for built-in regulator. See the "CHAPTER 2 HANDLING THE DEVICE". VCCI - (MB91306R, MB91307R) Internal power supply pin (1.8 V power supply) 64 CS6 F 65 [CS6] Chip Select 6 output. This function is enabled when the Chip Select 6 output specification is enabled. PA6 [PA6] General-purpose input-output port. This function is enabled when the Chip Select 6 output specification is disabled. CS7 [CS7] Chip Select 7 output. This function is enabled when the Chip Select 7 output specification is enabled. F 66 PA7 [PA7] General-purpose input-output port. This function is enabled when the Chip Select 7 output specification is disabled. RDY [RDY] External ready input. This function is enabled if the external ready input specification is enabled. 67 C P80 BGRNT F 68 P81 [P80] General-purpose input-output port. This function is enabled if the external ready input specification is disabled. [BGRNT] External bus open acceptance output. Set to L output if an external bus is opened. Enabled if the output specification is enabled. [P81] General-purpose input-output port. This function is enabled if the external bus open acceptance specification is disabled. 15 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Function Table (7/8) Pin number Pin name I/O circuit form [BRQ] External bus open request input. Enter 1 to open an external bus. Enabled if the input specification is enabled. BRQ 69 P [P82] General-purpose input-output port. This function is enabled if the external bus open request specification is disabled. M External bus read strobe output F External bus write strobe output [UUB] High-order bits of 16-bit SRAM input-output mask enable bits. Enabled if the external bus is set to SRAM. (WE/P97 is the write strobe.) P82 70 RD 71 WR0 UUB 72 WR1 ULB P85 F External bus write strobe output [ULB] High-order bits of 16-bit SRAM input-output mask enable bits. Enabled if the external bus is set to SRAM. (WE/P97 is the write strobe.) 73 NMI H NMI request input HST H (MB91307B) Hardware standby input VCCI - (MB91307R) Internal power supply pin (1.8 V power supply) INIT B External reset input F [SYSCLK] System clock output. This function is enabled if the system clock output specification is enabled. The same clock as the external bus operating frequency is output. Clock output is stopped in stop and hardware standby mode. 74 76 SYSCLK 77 [P90] General-purpose input-output port. This function is enabled when the system clock output specification is disabled. P90 78 P91 F [P91] General-purpose input-output port. F [MCLK] Clock output for memory Clock output is stopped in sleep, stop and hardware standby mode. MCLK 79 [P92] General-purpose input-output port. This function is enabled when the clock output specification is disabled. P92 80 P93 F 81 LBA P94 [P93] General-purpose input-output port. [AS] Address strobe output. This function is enabled when the address strobe output specification is enabled. AS 16 Function F [LBA] Burst FlashROM address load output. This function is enabled when the address load output specification is enabled. [P94] General-purpose input-output port. This function is enabled when the address load output and address strobe output specifications are disabled. CHAPTER 1 OVERVIEW Table 1.5-1 Pin Function Table (8/8) Pin number Pin name I/O circuit form BAA - 82 P95 83 P96 F WE - 84 P97 Function [BAA] Burst FlashROM address advance output. This function is enabled when the address advance output specification is enabled. [P95] General-purpose input-output port. This function is enabled when the address advance output and column address strobe output specifications are disabled. [P96] General-purpose input-output port. This function is enabled when the column address strobe output specification is disabled. [WE] Write strobe output for 16-bit SRAM. This function is enabled when the write strobe output specification is enabled. [P97] General-purpose input-output port. This function is enabled when the write strobe output specification is disabled. 9 AVCC - Power supply for A/D converter 10 AVRH - Power supply for A/D converter 11 AVSS/ AVRL - Power supply for A/D converter (GND) 24,55,110 VCC - Power supply pin (3.3 series) 34,52,75,101 VSS - Power supply pin (GND) 17 CHAPTER 1 OVERVIEW 1.6 Input-output Circuit Forms This section describes the input-output circuit forms. ■ Input-output Circuit Types Table 1.6-1 Input-output Circuit Types (1/4) Classification Circuit type X1 A Remarks • Oscillation feedback resistor: About 1 MΩ • CMOS hysteresis input with pull-up resistors (25 kΩ) • CMOS level input-output with standby control Clock input XO Standby control B Digital input Digital input C Digital output Digital input Standby control 18 CHAPTER 1 OVERVIEW Table 1.6-1 Input-output Circuit Types (2/4) Classification Circuit type Remarks • Analog input with switches • CMOS level output CMOS level hysteresis input with standby control • CMOS level input without standby control • CMOS level hysteresis input without standby control D Analog input Control Digital output F Digital output Digital input Standby control G Digital input H Digital input 19 CHAPTER 1 OVERVIEW Table 1.6-1 Input-output Circuit Types (3/4) Classification Circuit type Remarks • • CMOS level output CMOS level hysteresis input without standby control • CMOS level output • CMOS level input-output with standby control with pull-down resistors (25 kΩ) Digital output I Digital output Digital input Digital output M Digital output Digital output Digital output P CONTROL Digital input Standby control 20 CHAPTER 1 OVERVIEW Table 1.6-1 Input-output Circuit Types (4/4) Classification Circuit type Remarks • Open-drain output CMOS level hysteresis input with standby control Open-drain control Q Digital output Digital input Standby control 21 CHAPTER 1 OVERVIEW 22 CHAPTER 2 HANDLING THE DEVICE This chapter provides precautions on handling the MB91307 series. 2.1 Precautions on Handling the Device 2.2 Precautions on Handling Power Supplies 23 CHAPTER 2 HANDLING THE DEVICE 2.1 Precautions on Handling the Device This section contains information on preventing a latch up and on the handling of pins. ■ Preventing a Latch up A latch up can occur if, on a CMOS IC, a voltage higher than VCC or a voltage lower than VSS is applied to an input or output pin or a voltage higher than the rating is applied between VCC and VSS. A latch up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the maximum rating. ■ Handling of Pins The following are precautions on treating various pins and on quartz oscillation circuits. ❍ Unused input pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pull-up or pull-down resistor. ❍ Power supply pins If more than one VCC or VSS pin exists, those that must be kept at the same potential are designed to be connected to one other inside the device to prevent malfunctions such as latch up. Be sure to connect the pins to a power supply and ground external to the device to minimize undesired electromagnetic radiation, prevent strobe signal malfunctions due to an increase in ground level, and conform to the total output current rating. Given consideration to connecting the current supply source to VCC or VSS of the device at the lowest impedance possible. It is also recommended that a ceramic capacitor of around 0.1 µF be connected between VCC and VSS at circuit points close to the device as a bypass capacitor. ❍ Mode pins (MD0 to MD2) These pins must be directly connected to VCC or VSS when they are used. Keep the pattern length between a mode pin on a printed circuit board and VCC or VSS as short as possible so that they can be connected at a low impedance. ❍ Quartz oscillation circuit Noise near the X0 or X1 pin may cause the device to malfunction. Design printed circuit boards so that X0, X1, the quartz oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as near to one another as possible. It is strongly recommended that printed circuit board artwork that surrounds the X0 and X1 pins with ground be used to increase the expectation of stable operation. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. ❍ Treatment of NC pins Any pins marked "NC" (not connected) must be left open. 24 CHAPTER 2 HANDLING THE DEVICE ❍ External clock When using an external clock, in general supply it to the X0 pin while also supplying a reversephase clock to the X1 pin simultaneously. If you also use STOP mode (oscillation stop mode), use an external resistor of about 1 kΩ to be inserted, since the X1 pin stops with H level output in STOP mode and collision between the outputs must be prevented. The following figure shows an example of using an external clock. Figure 2.1-1 Example of using an External Clock (Normal Case) X0 X1 MB91307 series [Insert a resistor for the X1 pin if STOP mode (oscillation stop mode) is used.] For the maximum input frequency, see the data sheet. ❍ Notes on during operation of PLL clock mode If the PLL clock mode is selected, the microcontroller attempt to be working with the selfoscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. ❍ Precaution on using ports 6 and 7 If one of P60/A15 to P70/A24, which are shared for output of external bus interface addresses, is used as a port, a grid voltage is applied to the port instantaneously when the status of another address output pin is changed. Therefore, add resistors or capacitors to those ports to prevent application of the grid voltage. ■ Precautions on Use ❍ Clock controller Reserve an oscillation stabilization wait time when an L-level signal is input to INIT. ❍ Bit search module Only word access is allowed for the BSD0, BSD1, and BSDC registers. ❍ Prefetch When allowing prefetch from an area that has been set as a little endian area, limit access to the area to word access (i.e., access in units of 32 bits). The area cannot be accessed correctly by byte or half-word accesses. ❍ External-bus setting This model guarantees use of an external 33 MHz bus. Because the external bus function is designed to support 66 MHz for future requirements, the initial value of the clock rate for the external bus is the same as that of the base clock (decided by the set value of PLL). If you set the base clock to 66 MHz with the initial value set for DIVR1 (external bus base clock 25 CHAPTER 2 HANDLING THE DEVICE division register), the clock for the external bus is set to 66 MHz. To change the base clock, first change the base clock setting so that the external bus clock does not exceed 33 MHz. ❍ MCLK and SYSCLK MCLK is stopped in sleep and stop modes, and SYSCLK is stopped only in stop mode. Use MCLK and SYSCLK appropriately according to the purpose of use. ❍ I2C I/O pin The SDA and SCL pins of this model are designed as pseudo open-drain pins for which the P-ch transistor is turned off to prevent the H-level output. Therefore, the circuit format of the pins has a diode connected on the VCC side. Adjust the communication voltage to the voltage of the 3.3 V power supply of this model. (Pull up the voltage to the voltage of the 3.3 V power supply.) ❍ Switching the function of a common port Use the port function register (PFR) to switch the function of a pin which also serves as a port. However, use an external bus setting to switch the function of a bus pin. ❍ Pull-up resistor control If a pull-up resistor is connected to a pin to be used as an external bus pin, the AC ratings cannot be guaranteed. Even a port that already has a pull-up resistor is invalid in stop mode (Hi-Z = 1) and hardware standby mode. ❍ I/O port access Only byte accesses are allowed to I/O ports. ❍ Low power consumption mode • Use the following sequences after using the synchronous standby mode (TBCR: Set by time base counter control register bit8 SYNCS bit) when putting in the standby mode. (LDI (LDI STB LDUB LDUB NOP NOP NOP NOP NOP #value_of_standby, R0) #_STCR, R12) R0, @12) // Writing in standby control register (STCR) @R12, R0 // STCR lead for synchronous standby @R12, R0 // Dummy re-lead of STCR // five NOPs for timing adjustment • Do not do the following when the monitor debugger is used. - Set the break point to the above-mentioned instruction row. - Execute the step for the above-mentioned instruction row. ❍ Executing instructions on RAM • If instruction codes are placed in RAM, they should not be placed in the last 8 address bytes 0005__FFF8H to 0005_FFFFH. (Instruction code prohibited area) ❍ Current at power-on (for the MB91V307B and MB91V307R only) About 300 mA of power supply current flows when the power is turned on with INIT set to 0. 26 CHAPTER 2 HANDLING THE DEVICE Set INIT to "1" to stop the overcurrent flowing. After that, the overcurrent will not flow even if INIT is set to "0". ❍ Watchdog timer function The watchdog timer function of this model monitors whether a program holds over a reset within a specified time. It also resets the CPU if the reset is not held over because of uncontrollable program operation. After the watchdog timer function is enabled, it keeps operating until a reset occurs. The watchdog timer function usually holds over CPU reset automatically when program execution by the CPU stops. For the relevant exception conditions, see the section explaining the watchdog timer function. The reset by the watchdog timer function might not occur if the above status is caused by uncontrollable system operation. If it might occur, a reset (INIT) request must be input from the external INIT pin. ■ Limitations ❍ Little endian Do not set a prefetch-enabled area as a little endian area. If a prefetch-enabled area is set as a little endian area, the area cannot be accessed correctly. ❍ Terminal and timing control register (TCR) (0x00000683) The terminal and timing control register (TCR) is a write-only register. Therefore, do not access TCR with a bit manipulation instruction. If you intend to disable sharing of the bus by writing "0" to Bit 7 (BREN bit) of TCR when the bit is "1", be sure to follow the procedure below. If the procedure is not followed, the device may hang up. 1. Write "0" to Bit 2 (BRQE bit) of the port 8 function register (PFR8). 2. Write "0" to Bit 7 (BREN bit) of TCR. ❍ RD/WD-CS hold extension cycle Assume that use of the RD/WD-CS hold extension cycle is specified (Bit 0 of AWR is 1) for an area for which the normal memory/IO access type is set (the TYPE3 to TYPE0 bits of ACR are 0xxx). Even in this case, the hold extension cycle might not be inserted when the operation and settings are specified in a specific combination. The hold extension cycle will not be inserted when the following conditions are met: • Use of the RD/WD-CS hold extension cycle is specified. (Bit 0 [W00 bit] of AWR is "1".) • A normal memory/IO access type is set for the area. (Bits 3 to 0 [TYPE3 to TYPE0 bits] of ACR are "0xxx".) Note: The MB91307 series allows only this type to be set. • Disuse of the address-CS delay cycle is specified. (Bit 2 [W02 bit] of AWR is "0".) • A setting (recovery enabled) other than 0 cycle is made for the write recovery cycle. (Bits 5 and 4 [W05 and W04 bits] of AWR are other than "00".) (Example: First word writing to an external bus 16-bit area) 27 CHAPTER 2 HANDLING THE DEVICE • If an access is made to write data larger than the bus width to the relevant area under the above conditions, the RD/WD-CS hold extension cycle is not inserted in any cycle other than the last cycle to write divisions of the data. Therefore, the hold time becomes insufficient. *: This problem does not occur in the read cycle. To use this function, make either of the following settings: • Specify the use of the address-CS delay cycle. (Set "1" for Bit 2 [W02 bit] of AWR.) • Specify 0 cycle for the write recovery cycle. (Set "00" for Bits 5 and 4 [W05 and W04 bits] of AWR.) ❍ Signed DIVIDE statement (DIV0S) When the instruction immediately before the instruction of DIV0S is an instruction by which the memory access is done, a correct calculation result might not be obtained. This is generated under the following conditions. • When the instruction performs memory accesses just before a DIVOS instruction. Note: Instructions that performs relevant memory accesses (a total of 58 instructions) ST Ri, @- R15 STB Ri, @Rj STB Ri, @ (R14, disp8) LDUH @ (R13, Rj), Ri DMOVH @dir9, R13 LDUH @ (R14, disp9), Ri ANDH Rj, @Ri EORB Rj, @Ri DMOVB @R13+, @dir8 DMOVB @dir8, @R13+ ST Rs, @- R15 STB Ri, @ (R13, Rj) LDUB @Rj, Ri LDUB @ (R13, Rj), Ri DMOVB @dir8, R13 LDUB @ (R14, disp8), Ri ANDB Rj, @Ri DMOV @R13+, @dir10 DMOV @dir10, @R13+ DMOV @R15+, @dir10 ST PS, @- R15 DMOVB R13, @dir8 LD @ (R13, Rj), Ri DMOV @dir10, R13 LD @ (R14, disp10), Ri AND Rj, @Ri ORB Rj, @Ri DMOVH @R13+, @dir9 DMOVH @dir9, @R13+ DMOV @dir10, @- R15 • When full trace mode is specified as trace mode and the DIVOS and DIV1 instructions are not 4-byte aligned. • Even if the DIVOS and DIV1 instructions are 4-byte aligned, perform a D-bus DMA transfer or specify the full trace mode as trace mode if a breakpoint is set in the DIV1 instruction. Avoid this notes as follows: - Do not place an instruction that performs memory access before a DIVOS instruction. - Do not perform a DMA transfer to the D-bus or set full trace mode as trace made when a DIVOS instruction is specified. To output the code for avoiding above (1) condition, specify "-@div0s 1" as the compiler option. SOFTUNE compiler: 28 • In case of using the SOFTUNE V3: after the SOFTUNE compiler V30L07R07 • In case of using the SOFTUNE V5: after the SOFTUNE compiler V50L04 • In case of using the SOFTUNE V6: after the SOFTUNE compiler V60L01 CHAPTER 2 HANDLING THE DEVICE ❍ DMA demand transfer In sleep mode, demand transfer is executed only once and processing does not go further. During normal operation, the efficiency of demand transfers may seem to be lowered. This action occurs only in demand transfers (it does not occur in DREQ edge detection mode or the like). This is occurred in the following cases: • A demand transfer by DMAC is performed in sleep mode. - After a demand transfer is performed once, processing does not go further although DREQ is input successively. - A subsequent transfer is started if the device is released from sleep mode and an external bus operation other than a DMA transfer occurs. • A demand transfer by DMAC is performed during normal operation. - After a demand transfer is performed once, a subsequent transfer is not performed until an external bus access other than a DMA transfer occurs. - A demand transfer does not progress while there is no external bus access because cache hitting is performed continuously or internal ROM operation continues. • A subsequent demand transfer is not started even if an external bus access for prefetching occurs. Avoid this notes as follows: • Do not perform a demand transfer by DMAC in sleep mode. • Do not use sleep mode during a demand transfer by DMAC. ❍ DMA transfer source selection (MB91306R/307R only) When the following sources are set as DMA transfer source selection, the start source is not cleared. Be sure not to use these sources. IS4 to 0 bits in DMA control/status registers DMACA0 to 4 (transfer source selection) • 10110 External interrupt 0 • 10111 External interrupt 1 • 11000 Reload timer 0 • 11001 Reload timer 1 • 11010 Reload timer 2 • 11011 External interrupt 2 • 11100 External interrupt 3 • 11101 External interrupt 4 • 11110 External interrupt 5 ❍ RMW instructions using R15 If one of the instructions listed below is executed, the value of SSP or USP* is not used as the value of R15 and, as a result, an incorrect value is written to memory. Therefore, the compiler does not generate the following instructions: AND OR R15,@Rj R15,@Rj ANDH ORH R15,@Rj R15,@Rj ANDB ORB R15,@Rj R15,@Rj 29 CHAPTER 2 HANDLING THE DEVICE EOR R15,@Rj XCHB @Rj,R15 EORH R15,@Rj EORB R15,@Rj *: R15 is an insubstantial register. If R15 is accessed by a program, SSP or USP is accessed according to the state of the S flag of the PS register. Avoid this notes as follows: • When programming any of the above 10 instructions by an assembler, specify a generalpurpose register in place of R15. ❍ Notes of PS register Since some instructions process the PS register first, interrupt processing routines can lead to breaks during debugging or updating of the PS register flag due to the following exceptions. Whichever the case, the program is designed to reprocess correctly after returning from EIT to ensure that operation before and after EIT conforms to specifications. 1 The following operations may occur when (a) user interrupt/NMI is received, (b) step execution is performed, (c) break occurs in a data event or emulator menu in an immediately preceding DIVOU/DIVOS instruction. (1) D0 and D1 flag precede and are renewed. (2) EIT processing routine (user interruption, NMI or emulator) is executed. (3) After returning from EIT, DIVOU/DIVOS instructions are executed and the D0 and D1 flags are updated to the same value as (1). 2 When each ORCCR/STILM/MOV Ri and PS instruction is executed to permit interrupting with the user interruption and the NMI factor generated, the following operations are done. (1) The PS register precedes and is updated. (2) EIT processing routine (user interruption or NMI) is executed. (3) After returning from EIT, the above instructions are executed and the PS register is updated to the same value as (1). ❍ Note of I-bus memory Do not do the data access to the control register and RAM of the instruction cache immediately before the instruction of RETI. ■ Notes about debugger ❍ Step execution of RETI instruction If the RETI instruction is executed in steps in an environment in which interrupts occur often, the relevant interrupt processing routine alone is executed repeatedly. As a result, the main routine and the programs at low interrupt levels are not executed. (For example, if the time base timer interrupt is enabled, step execution of the RETI instruction always breaks at the top of the time base timer routine.) Disable the relevant interrupt when debugging of the relevant interrupt processing routine becomes unnecessary. Otherwise, avoid step execution of the RETI instruction. ❍ Break function 1. If the address of a current system stack pointer or an area that includes a stack pointer is specified as an object address of a hardware break (including an event break), a break occurs after one instruction is executed. The break occurs although the relevant user program does not include an actual data access instruction. To avoid this problem, do not set the (word) access to an area that includes the address of a system stack pointer as a 30 CHAPTER 2 HANDLING THE DEVICE target of a hardware break (including an event break). 2. If an instruction that causes a wait is executed between an instruction to read a branch destination address from memory and a branch instruction, an instruction alignment error occurs at a point where an instruction alignment error cannot occur originally. Then, an ICE break (CPU error break) occurs, and execution of instructions stops. Furthermore, even if an instruction break is set for the branch destination address at the point where the above error occurs, a break might not occur. Example: LD LD CALL @R1,R0 @R2,R3 @R0 ; read F-bus RAM ; read F-bus RAM ; An incorrect alignment error may occur or a break might not occur. To avoid the incorrect alignment error as described above, turn off the alignment error function in debugger function setup. To perform the instruction break correctly, do not specify use of a hardware break, but specify use of a software break in debugger function setup. ❍ Trace mode If the trace mode for debugging is set to full trace mode, which uses internal FIFO memory as the output buffer, the current may increase or DMA access to the D bus may be lost. This is occurred if: • A DMA transfer to the D bus or standby mode occurs in full trace mode. Use internal trace mode to avoid this note. ❍ Alignment error (emulator debugger) Assume that instruction alignment error break is enabled and an instruction that causes a wait is executed between an instruction to read a branch destination address from memory and a branch instruction. Under these conditions, an instruction alignment error occurs at a point where an instruction alignment error cannot occur originally, an ICE break occurs, and execution of instructions stops. Then, a message indicating an unknown break factor or a CPU error break is output. Furthermore, even if an instruction break is set for the branch destination address at the point where the above error occurs, a break might not occur. This problem occurs if the following three types of instructions are executed successively: (1) LD or DMOV instructions causing a wait (reading a branch destination address) LD @Rj,Ri LD @(R13,Rj)Ri LD @(R14,disp10),Ri LD @R15+,Ri DMOV @dir10,R13 LDUH @Rj,RI LDUH @(R13,Rj),Ri LDUH @(R14,disp9),Ri LD @R15+,Rs DMOVH @dir9,R13 LDUB @(R13,Rj),Ri LDUB @(R14,disp8),Ri LD @R15+,PS DMOVB @dir8,R13 (2) Instructions causing a wait (reading F-bus RAM or external memory) (3) Branch instructions such as JMP @Ri, JMP: D @Ri, CALL @Ri, CALL: D @Ri, RET, and RET: D Example: LD@R1,R0 ;read F-bus RAM LD@R2,R3 ;read F-bus RAM CALL @R0 Avoid this notes as follows: Assume that instruction alignment error break is enabled and an instruction that causes a wait is executed between an instruction to read a branch destination address from memory and a 31 CHAPTER 2 HANDLING THE DEVICE branch instruction. Under these conditions, an instruction alignment error occurs at a point where an instruction alignment error cannot occur originally, an ICE break occurs, and execution of instructions stops. Then, a message indicating an unknown break factor or a CPU error break is output. Furthermore, even if an instruction break is set for the branch destination address at the point where the above error occurs, a break might not occur. To avoid this problem, proceed as follows: - To avoid the incorrect alignment error as described above, turn off the alignment error function in debugger function setup. - To perform the instruction break correctly, set the break point in an address other than the branch destination address. ❍ Concurrent occurrence of a software break (INTE instruction) and user interrupt or NMI If an INTE instruction and a user interrupt (including a user NMI) are accepted concurrently, the following problems occur in the emulator debugger: • The emulator debugger stops, indicating a point other than the break point set by the user. (It stops, indicating the top of the relevant user interrupt or NMI processing routine.) • After it has stopped, the emulator debugger does not correctly execute processing. If this problem occurs, use a hardware break in place of a software break. If you use a monitor debugger, avoid setting a break at the relevant point. ❍ Operand break A stack pointer in an area set as operand break of DSU causes a malfunction. Do not use access to an area that contains a system stack pointer for a data event break. 32 CHAPTER 2 HANDLING THE DEVICE 2.2 Precautions on Handling Power Supplies This section provides precautions on power supplies with regard to pin handling and processing when power is turned on. ■ Processing after Power-on Immediately after power-on, be sure to apply a reset that initializes settings (INIT) from the INIT pin. To provide for an oscillation stabilization wait immediately after power-on, continue to input the L level to the INIT pin as long as the oscillation stabilization wait time required by the oscillating circuit. (Initialization by INIT from the INIT pin sets the oscillation stabilization wait time to the minimum value.) ■ Processing of Source Oscillation Input after Power-on After power-on, be sure to input a clock until the oscillation stabilization wait time is canceled. ■ Hardware Standby after Power-on (MB91307B, MB91V307B only) If a hardware standby request occurs immediately after power-on, the reset that initializes settings (INIT) from the INIT pin takes precedence. If the device then enters the hardware standby status after the reset (INIT) from the INIT pin is cleared, the oscillation stabilization wait time is initialized at the maximum value. After the hardware standby request is cleared, the oscillation stabilization wait time is set to the maximum value (MB91307R dose not have a hardware standby function). ■ Built-in DC-DC Regulator (MB91307B, MB91V307B only) This model has a built-in regulator. Supply 3.3 V to the VCC pin and insert a bypass capacitor of about 0.1 µF at the C pin for the regulator. The A/D converter needs separate 3.3 V power supply. 3.3V VCC C AVCC AVRH AVSS/AVRL VSS 0.1 F GND 33 CHAPTER 2 HANDLING THE DEVICE ■ Precautions on turning on and off the power supplies (MB91306R, MB91307R only) Precautions on turning on and off VCCI (internal 1.8 V power supply) and VCC (external 3.3 V power supply) Do not apply VCC (external power supply) alone to the device continuously (for one minute or more) while VCCI (internal power supply) is off. Doing so may cause a problem with the LSI reliability. When VCC (external power supply) is restored from the off state to the on state, the internal circuit status might not be able to be retained, because of the influence of power supply noise. At power-on: VCCI (internal power supply) → VCC (external power supply) → signals At power-off: Signals → VCC (external power supply) → VCCI (internal power supply) ■ Precautions on Using STOP Mode The built-in regulator of this model stops in STOP mode. If the internal leakage current (ICCH) increases in STOP mode or a malfunction due to noise or a power supply failure stops the regulator during normal operation, the internal 2.5 V power supply may drop below the voltage that assures operation. Therefore, to use STOP mode using the built-in regulator, supplement external power so that the 3.3 V power supply does not drop. If a drop does occur, you can input a reset to restart the built-in regulator. When restarting the built-in regulator, set the oscillation stabilization wait time reset to the "L" level. 3.3V VCC 2.4K 7.6K GND 34 C 0.1 F VSS CHAPTER 3 CPU AND CONTROL UNITS This chapter provides basic information required to understand the functions of the MB91307 series. It covers architecture, specifications, and instructions. 3.1 Memory Space 3.2 Internal Architecture 3.3 Instruction Cache 3.4 Dedicated Registers 3.5 General-Purpose Registers 3.6 Data Structure 3.7 Word Alignment 3.8 Memory Map 3.9 Branch Instructions 3.10 EIT (Exception, Interrupt, and Trap) 3.11 Reset (Device Initialization) 3.12 Clock Generation Control 3.13 Device State Control 3.14 Operating Modes 35 CHAPTER 3 CPU AND CONTROL UNITS 3.1 Memory Space The MB91307 series has a logical address space of 4 GB (232 addresses), which the CPU accesses linearly. ■ Memory Map Figure 3.1-1 shows the memory space of the MB91307 series. Figure 3.1-1 Memory Map MB91307B/R MB91306R Internal-ROM/ external-bus mode Internal-ROM/ external-bus mode MB91307B/R MB91306R External-bus mode 0000 0000H 0000 0000H I/O I/O I/O 0000 0400H 0000 0400H I/O I/O I/O 0001 0000H 0004 0000H 0006 0000H See the I/O map. 0001 0000H Access prohibited 0005 0000H Direct addressing area Built-in RAM 128 KB Access prohibited Access prohibited Access prohibited 0004 0000H Built-in RAM 64 KB Access prohibited External area 0006 0000H 0010 0000H 0010 0000H External area External area External area FFFF FFFFH ❍ Direct addressing area The areas in the address space listed below are used for input-output. These areas called the direct addressing area. The address of an operand can be directly specified in an instruction. The size of the direct addressing area varies according to the size of data to be accessed: 36 • Byte data access: 000H to 0FFH • Halfword data access: 000H to 1FFH • Word data access: 000H to 3FFH CHAPTER 3 CPU AND CONTROL UNITS ■ Built-in RAM Area in the Memory Space The MB91307 series has 128 KB built-in RAM. To enable this RAM, you must set the mode vector value for internal-ROM/external-bus mode (ROMA=1). The following are precautions on using the MB91307 series: • The reset vector is fixed at 000F_FFFCH. • For the MB91307 series, the 128 KB RAM area is located at 0004_0000H to 0005_FFFFH. Access to the area from 0006_0000H to 000F_FFFFH is prohibited. • To use the RAM, set the mode vector for internal-ROM/external-bus mode. Although the built-in RAM area can be used in internal-ROM/external-bus mode, the vector area 000F_FFxxH becomes the internal area and external access is disabled. Use the RAM area as described below. • When you place instruction codes in the RAM, do not place any in the last eight address bytes from 0005_FFFF8H to 0005_FFFFH (area where instruction codes prohibited). Figure 3.1-2 shows the memory maps after a reset is cleared and after the mode is set. The built-in RAM area is enabled after the mode is set. Figure 3.1-2 Locations within Built-in RAM Area After a mode is set: Internal-ROM/external-bus mode After a reset is cleared 0000 0000H MB91306R I/O Direct addressing area I/O I/O I/O See the I/O map. I/O I/O Access prohibited Access prohibited 0000 0400H 0001 0000H MB91307B/R Access prohibited 0004 0000H 0005 0000H External area Built-in RAM 128KB External area Access prohibited External area External area 0006 0000H Built-in RAM 64KB Access prohibited 0010 0000H External area FFFF FFFFH 37 CHAPTER 3 CPU AND CONTROL UNITS ■ Initializing a User Program This section uses an example to describe use of the built-in RAM. As using MB91306R, only built-in RAM area size is different from other setting of product. ❍ Hardware design conditions Figure 3.1-3 Connecting Hardware MB91307 series Ordinary design CS0 External ROM A19-1 • A 1 MB ROM is assumed to be located at 0010_0000H. Use a linker to place a program here (The following description applies also for other addresses as well). • Since addresses from A19 to A1 (1MB) are connected to the ROM, use CS0 for any addresses higher than these. • Set the mode pins (MD2, MD1, and MD0) in external-ROM mode vectors. • Write a reset vector at 001F_FFFCH. Similarly, write a mode vector at 001F_FFF8H ❍ Immediately after a reset is cleared Figure 3.1-4 Address Map Immediately After a Reset is Cleared 0000_0000H MB91307 series 0000_0400H CS0 External ROM External ROM FFFF_FFFFH A 1 MB space in ROM is seen repetitiously on the address map. • 38 Immediately after a reset is cleared, the CPU usually tries to fetch a mode vector from 000F_FFF8H and a reset vector from 000F_FFFCH. However, the CPU actually tries to fetch them externally because the settings are for external-ROM mode vectors. Since the external space is seen as a repetition of the 1 MB external ROM because of the initial CS0 value, the CPU fetches the mode vector and the reset vector stored at 001F_FFF8H and 001F_FFFCH in external ROM. CHAPTER 3 CPU AND CONTROL UNITS • The linker places the branch destination at 001X_XXXXH. Program execution continues from this location. ❍ User program initialization step Figure 3.1-5 Address Map of Initialization Step 0000_0000H MB91307 series 0004_0000H 0006_0000H CS0 External ROM Internal RAM 0010_0000H External ROM 001F_FFFFH FFFF_FFFFH A 1 MB space in ROM matches 1 MB on the address map. Set the interrupt table (TBR) at 001F_FFXXH and then perform the initialization procedure. 1. During this process, also set the chip select. At the same time, set so that the CS0 address at 001X_XXXXH is enabled. Since the CS0 decode result does not change before and after the setting, the CPU continues to execute the program in external ROM. 2. If necessary, initialize the ROM contents. 3. Thus the initialization is completed and Application Program can be executed. 39 CHAPTER 3 CPU AND CONTROL UNITS 3.2 Internal Architecture The MB91307 series is a high-performance core based on RISC architecture and advanced instructions for embedded applications. ■ Features ❍ RISC architecture used Basic instruction: One instruction per cycle ❍ 32-bit architecture General-purpose register: 32 bits × 16 ❍ 4 GB linear memory space ❍ Multiplier installed • 32-bit by 32-bit multiplication: 5 cycles • 16-bit by 16-bit multiplication: 3 cycles ❍ Enhanced interrupt processing function • Quick response speed: 6 cycles • Support of multiple interrupts • Level mask function: 16 levels ❍ Enhanced instructions for I/O operations • Memory-to-memory transfer instruction • Bit-processing instructions ❍ Efficient code Basic instruction word length: 16 bits ❍ Low-power consumption Sleep and stop modes ❍ Gear function 40 CHAPTER 3 CPU AND CONTROL UNITS ■ Internal Architecture The MB91307 series CPU uses the Harvard architecture, which has separate buses for instructions and data. An on-chip instruction cache is connected to the instruction bus (I-bus). A 32-bit/16-bit bus converter is connected to the bus (F-bus), providing an interface between the CPU and peripheral resources. A Harvard/Princeton bus converter is connected to both the Ibus and D-bus, providing an interface between the CUP and bus controllers. Figure 3.2-1 shows connections in the internal architecture. Figure 3.2-1 Internal Architecture FRex CPU D-bus Instruction cache I-bus I address 32 I data 32 D address D data Harvard 32 Princeton bus converter 32 F address 32 F data 32 RAM 32 bit 16 bit Bus converter R-bus 16 Peripheral resources F-bus Bus controllers 41 CHAPTER 3 CPU AND CONTROL UNITS ❍ CPU The CPU is a compact implementation of the 32-bit RISC MB91307 series architecture. Five instruction pipe lines are used to execute one instruction per cycle. A pipeline consists of the following stages: • Instruction fetch (IF): Outputs an instruction address to fetch an instruction. • Instruction decode (ID): Decodes a fetched instruction. Also reads a register. • Execution (EX): Executes an arithmetic operation. • Memory access (MA): Performs a load or store access to memory. • Write-back (WB): Writes an operation result (or loaded memory data) to a register Figure 3.2-2 Instruction Pipelines CLK Instruction 1 WB Instruction 2 MA WB Instruction 3 EX MA WB Instruction 4 ID EX MA WB Instruction 5 IF ID EX MA WB IF ID EX MA Instruction 6 WB Instructions are never executed randomly. If Instruction A enters a pipeline before Instruction B, it always reaches the write-back stage before Instruction B. In general, one instruction is executed per cycle. However, multiple cycles are required to execute a load/store instruction with a memory wait, a branch instruction without a delay slot, or a multiple-cycle instruction. The execution of instructions slows down if the instructions are not supplied fast enough. ❍ Instruction cache The existence of an on-chip instruction cache enables the construction of a high-performance system without added costs for high-speed external memory and the related control logic. The instruction cache can supply instructions to the CPU even when the external bus is slow. For details of instruction cache, see Section "3.3 Instruction Cache". ❍ 32-bit/16-bit bus converter The 32-bit/16-bit bus converter provides an interface between the F-bus accessed with 32-bit width and the R-bus accessed with 16-bit width and enables data access from the CPU to builtin peripheral circuits. If the CPU performs one 32-bit access to the R-bus, the 32-bit/16-bit bus converter translates the access into two 16-bit accesses. Some of the built-in peripheral circuits have limitations on the access width. 42 CHAPTER 3 CPU AND CONTROL UNITS ❍ Harvard/Princeton bus converter The Harvard/Princeton bus converter coordinates instruction and data accesses of the CPU to provide a smooth interface between it and external buses. The CPU has a Harvard architecture with separate buses for instructions and data. On the other hand, the bus controller that performs control of external buses has a Princeton architecture with a single bus. The Harvard/Princeton bus converter assigns priorities to instruction and data accesses from the CPU to control accesses to the bus controller. This function allows the order of external bus accesses to be permanently optimized. ■ Overview of Instructions The MB91307 series supports the general RISC instructions as well as logical operation, bit manipulation, and direct addressing instructions optimized for embedded applications. Each instruction is 16 bits long (some instructions 32 and 48 bits long), resulting in superior efficiency of memory use. For a list of instruction sets, see the appendix. An instruction set is classified into the following function groups: • Arithmetic operation • Load and store • Branch • Logical operation and bit manipulation • Direct addressing • Other ❍ Arithmetic operation Arithmetic operation instructions include standard arithmetic operation instructions (addition, subtraction, and comparison) and shift instructions (logical shift and arithmetic shift). The addition and subtraction instructions include an operation with carries for use with multiple-wordlength operations and an operation that does not change flag values, a convenience in address calculations. Furthermore, 32-bit-by-32-bit and 16-bit-by-16-bit multiplication instructions and a 32-bit-by-32bit step division instruction are provided. Additionally, an immediate data transfer instruction that sets immediate data in a register and a register-to-register transfer instruction are provided. An arithmetic operation instruction is executed using the general-purpose registers and the multiplication and division registers in the CPU. ❍ Load and store Load and store instructions read and write to external memory. They are also used to read and write to a peripheral circuit (I/O) on the chip. Load and store instructions have three access lengths: byte, halfword, and word. In addition to indirect memory addressing via general registers, indirect memory addressing via registers with displacements and via registers with register incrementing or decrementing are provided for some instructions. ❍ Branch The branch group includes branch, call, interrupt, and return instructions. Some branch instructions have delay slots while others do not. These may be optimized according to the application. For more information about the branch instructions, see Section "3.9 Branch Instructions". 43 CHAPTER 3 CPU AND CONTROL UNITS ❍ Logical operation and bit manipulation Logical operation instructions perform the AND, OR, and EOR logical operations between general-purpose registers or a general-purpose register and memory (and I/O). Bit manipulation instructions directly manipulate the contents of memory (and I/O). They access memory using general register indirect addressing. ❍ Direct addressing Direct addressing instructions are used for access between an I/O and a general-purpose register or between an I/O and the memory. High-speed and high-efficiency access can be achieved since an I/O address is directly specified in an instruction instead of using register indirect addressing. Indirect memory addressing via registers with register incrementing or decrementing are provided for some instructions. ❍ Other types of instructions Other types of instructions include instructions that provide flag setting, stack manipulation, sign/ zero extension, and other functions in the PS register. Also, function entry and exit instructions that support high-level languages and register multi-load/store instructions are provided. 44 CHAPTER 3 CPU AND CONTROL UNITS 3.3 Instruction Cache This section describes the instruction cache in detail. ■ Overview The instruction cache is temporary storage memory. When low-speed external memory accesses an instruction code, the instruction cache internally stores the code already accessed once time to increase the access speed for subsequent uses. The instruction cache data RAM enables software-based direct read access and write access when RAM mode is set. To turn the instruction cache on and then off, be sure to use the subroutine described in the precautions in Section "3.3.4 Setting Up the Instruction Cache Before Use". ■ Area That Can Be Cached in the Instruction Cache • The instruction cache can cache only the external bus space. • If external memory is updated during DMA transfer, it does not become consistent with the contents of the instruction cache. To maintain consistency in this case, flush the instruction cache. • Each of the chip select areas can be set as a non-cache area, in which case there is a penalty of one more cycle than when the cache is turned off. (See "CHAPTER 4 EXTERNAL BUS INTERFACE".) 45 CHAPTER 3 CPU AND CONTROL UNITS 3.3.1 Configuration of the Instruction Cache This section describes the configuration of the instruction cache. ■ Overview of Specifications The following is an overview of the instruction cache specifications: • FR basic instruction length: 2 bytes • Block layout method: 2-way set associative • Block: One way consists of 32 blocks. One block consists of 16 bytes (= 4 sub blocks). One sub block consists of 4 bytes (= 1 bus access unit) ■ Configuration of Instruction Cache Figure 3.3-1 shows the configuration of the instruction cache. Figure 3.3-1 Configuration of Instruction Cache 4 bytes Way 1 4 bytes 4 bytes 4 bytes 4 bytes 13 12 11 11 Cache tag Subblock 3 Subblock 2 Subblock 1 Subblock 0 Block 0 Cache tag Subblock 3 Subblock 2 Subblock 1 Subblock 0 Block 31 Cache tag Subblock 3 Subblock 2 Subblock 1 Subblock 0 Block 0 Cache tag Subblock 3 Subblock 2 Subblock 1 Subblock 0 Block 31 32 blocks Way 2 32 blocks 46 CHAPTER 3 CPU AND CONTROL UNITS ■ Instruction Cache Tags Figure 3.3-2 shows the configuration of the instruction cache tags. Figure 3.3-2 Configuration of Instruction Cache Tags Way 1 31 09 Address tag 07 08 Blank 06 SBV3 SBV2 05 04 03 02 01 SBV1 SBV0 TAGV Empty LRU Subblock valid 00 ETLK TAG valid LRU Entry lock Way 2 31 09 Address tag 07 08 Blank 06 SBV3 SBV2 05 04 03 SBV1 SBV0 TAGV Subblock valid 02 01 Empty 00 ETLK TAG valid Entry lock The following describes the functions of the instruction cache tag bits. [Bits 31 to 9] Address tag In the address tag, the high-order 23 bits of the memory address of an instruction cached in a corresponding block are stored. The instruction data stored in Sub block k of Block i has Memory Address IA, which is calculated as IA = address-tag × 211 + i × 24 + k × 22 The address tag is used to check the matching of an instruction address requested for the access by the CPU. Based on the result of the tag check, one of the following operations occurs: • If the requested instruction data exists in the cache (hit) The data is transferred from the cache to the CPU within the cycle. • If the requested instruction data does not exist in the cache (miss) The data acquired via external access is acquired by the CPU and the cache simultaneously. 47 CHAPTER 3 CPU AND CONTROL UNITS [Bits 7 to 4] Sub block valid If SBV*=1, the instruction data at the address indicated by the tag has been entered in the corresponding sub block. Normally, two instructions can be stored in a sub block (except for a immediate data transfer instruction). [Bit 3] TAG valid bit Indicates whether the address tag value is valid. If this bit is "0", the block becomes invalid regardless of the sub block valid bit (when flushed). [Bit 1] LRU (only for Way 1) Exists only in the instruction cache tag of Way 1. Indicates whether, in a selected set, the entry last accessed was Way 1 or Way 2. Indicates that the last accessed entry of the set belongs to Way 1 if LRU=1 or Way 2 if LRU=0. [Bit 0] Entry lock Locks into the cache all the entries in the block corresponding to the tag. The entries are locked if ETLK=1 (there is no updating) if a cache miss occurs. However, invalid sub blocks are updated. If, for both Ways 1 and 2, a cache miss occurs while the entries are locked, one cycle required for the cache miss decision is lost and then external memory is accessed. Note: Do neither control register of the instruction cache nor the data access to RAM of the instruction cache immediately before the instruction of RETI. 48 CHAPTER 3 CPU AND CONTROL UNITS 3.3.2 Configuration of the Control Registers Control registers include the cache size register (ISIZE) and the instruction cache control register (ICHCR). This section describes the functions of these registers. ■ Configuration of Cache Size Register (ISIZE) Figure 3.3-3 shows the configuration of the cache size register (ISIZE) bits. Figure 3.3-3 Configuration of the Cache Size Register (ISIZE) Bits bit 00000307H 7 - 6 - 5 - 4 - 3 - 2 - 1 0 SIZE1 SIZE0 R/W R/W Initial value ------00B The following describes the functions of the cache size register (ISIZE) bits. [Bits 1, 0] SIZE1, SIZE0 These bits set the capacity of the instruction cache. Depending on the setting, the cache size, IRAM capacity, and address map used in RAM mode vary as shown in Figure 3.3-4. If you have changed the cache capacity, be sure to flush the cache and unlock the entries before turning on the cache. Table 3.3-1 Cache Size Registers SIZE1 SIZE0 Capacity 0 0 1KB 0 1 Setting prohibited 1 0 Setting prohibited 1 1 Setting prohibited 49 CHAPTER 3 CPU AND CONTROL UNITS Figure 3.3-4 Address Map of CACHE-3 RAM Address 00010000 00010200 00010400 00010600 00010800 Cache 1K RAM off Cache 1K RAM on TAG0 - 00014000 00014200 00014400 00014600 00014800 TAG1 00018000 00018200 00018400 00018600 00018800 way0 $RAM0 0001C000 0001C200 0001C400 0001C600 0001C800 way1 $RAM1 00020000 TAG RAM 00010000 00010004 00010008 0001000C 00010010 00010014 $RAM <- Entry at 00x address 00012000 <- Mirror of 00x 00012004 00012008 0001200C <- Entry at 01x address 00012010 <- Mirror of 01x 00012014 Instruction at 000 address (SBV0) Instruction at 004 address (SBV1) Instruction at 008 address (SBV2) Instruction at 00C address (SBV3) Instruction at 010 address (SBV0) Instruction at 014 address (SBV1) Instruction at 018 address (SBV2) Instruction at 01C address (SBV3) 00010020 ■ Instruction Cache Control Register (ICHCR) The instruction cache control register (ICHCR: I-CacHe Control Register) controls instruction cache operation. Writing to the ICHCR does not affect the cache operation of an instruction fetched during the subsequent three cycles. Figure 3.3-5 shows the configuration of the instruction cache control register. Figure 3.3-5 Configuration of Instruction Cache Control Register (ICHCR) bits bit 000003E7H 50 7 RAM R/W 6 - 5 4 3 2 1 0 GBLK ALFL EOLK ELKR FLSH ENAB R/W R/W R/W R/W R/W R/W Initial value 0-000000B CHAPTER 3 CPU AND CONTROL UNITS The following describes the functions of the instruction cache control register (ICHCR) bits. [Bit 7] RAM (RAM mode) If this bit is "1", RAM mode is set. In RAM mode, set the ENAB bit to "0" to turn off the instruction cache. [Bit 5] GBLK (Global lock) This bit locks all the current entries to the instruction cache. If a miss occurs when GBLK=1, a valid entry in the instruction cache is not updated. However, invalid subblocks are updated. The instruction data fetch operation at this time is the same as when the entries are not locked. [Bit 4] ALFL (Autolock fail) This bit (ALFL) is set to "1" if locking is attempted on an entry that is already locked. If, during entry autolock, an entry update is attempted on an entry that is already locked, no new entry is locked in the instruction cache regardless of what the user intends. Reference this bit for debugging of a program or similar purpose. Clear this bit by writing "0" to it. [Bit 3] EOLK (Entry autolock) This bit either enables or disables an autolock setting on an entry in the instruction cache. An entry accessed if this bit (EOLK) is "1" (only if a miss occurs) is locked when the hardware sets the entry lock bit in the instruction cache tag to "1". After this point, a locked entry is not subject to update when an instruction cache miss occurs. However, invalid subblocks are updated. To ensure that an entry is locked, flush the cache and set this bit. [Bit 2] ELKR (Entry lock clear) This bit specifies clearing of the entry lock bit in all the instruction cache tags. In the cycle following the one in which this bit (ELKR) is set to "1", the entry lock bit in all the cache tags is cleared to "0". However, the content of this bit is held only for one clock cycle and the bit is cleared to "0" in the second and later clock cycles. [Bit 1] FLSH (Flush) This bit specifies flushing of the instruction cache. Set this bit (FLSH) to "1" to flush the instruction cache. However, the content of this bit is held only for one clock cycle and the bit is cleared to "0" in the second and later clock cycles. [Bit 0] ENAB (Enable) This bit either enables or disables the instruction cache. If this bit (ENAB) is "0", the instruction cache is disabled and an instruction access from the CPU becomes external directly without going through the instruction cache. In the disabled state, the contents of the instruction cache are maintained. 51 CHAPTER 3 CPU AND CONTROL UNITS 3.3.3 Instruction Cache Statuses and Settings This section describes the state of the instruction cache in each operating modes and how to set up the instruction cache. ■ Instruction Cache Status in Each Operating Mode Table 3.3-2 shows the state of the instruction cache in each operating mode. The disable and flush states are encountered if a bit manipulation or similar instruction has changed only the related bit. Table 3.3-2 Status of Instruction Cache in Each Operating Mode Just after reset Disable Contents undefined Previous state maintained Not rewritable while disabled Previous state maintained Address tag Contents undefined Previous state maintained Not rewritable while disabled Previous state maintained Subblock valid bit Contents undefined Previous state maintained Not rewritable while disabled Previous state maintained LRU Contents undefined Previous state maintained Not rewritable while disabled Previous state maintained Entry lock bit Contents undefined Previous state maintained Not rewritable while disabled Entry lock cleared TAG valid bit Contents undefined Previous state maintained Flushable while disabled All entries invalid Normal mode Previous state maintained Flushable while disabled Previous state maintained Global lock Unlocked Previous state maintained Rewritable while disabled Previous state maintained Autolock fail No fail Previous state maintained Rewritable while disabled Previous state maintained Entry autolock Unlocked Previous state maintained Rewritable while disabled Previous state maintained Entry lock clear No clearing Previous state maintained Rewritable while disabled Previous state maintained Enable Disabled Disabled Previous state maintained Flush Not flushed Previous state maintained Rewritable while disabled Flushed in the cycle following memory access Returned to 0 thereafter Cache memory Tag RAM Control register 52 Flush CHAPTER 3 CPU AND CONTROL UNITS ■ Updating Entries in the Instruction Cache Entries in the instruction cache are updated as shown in Table 3.3-3. Table 3.3-3 Updating of Entries in the Instruction Cache Unlock Hit Miss Lock Not updated Not updated Loads the memory and updates the contents of entries in the instruction cache. Not updated for a tag miss. Updated for subblock invalid. 53 CHAPTER 3 CPU AND CONTROL UNITS 3.3.4 Setting Up the Instruction Cache Before Use This section describes how to set up the instruction cache before it is used. ■ Setup Procedure Before using the instruction cache, set it up as follows: ❍ Initialization Before the instruction cache is used, it must be cleared. Set the FLSH and ELKR bits of the register to "1" to delete past data. ldi #0x000003e7, r0 // I-Cache control register address ldi #0B00000110, r1 // FLSH bit (Bit 1) // ELKR bit (Bit 2) stb r1, @r0 // Write to the register This initializes the instruction cache. ❍ Enabling the instruction cache (ON) To enable the instruction cache, set the ENAB bit to "1". Ldi #0x000003e7, r0 // I-Cache control register address Ldi #0B00000001, r1 // ENAB bit (Bit 0) Stb r1, @r0 // Write to the register Any subsequent instruction access is loaded into the instruction cache. The instruction cache can be enabled at the same time it is initialized. 54 Ldi #0x000003e7, r0 // I-Cache control register address Ldi #0B00000111, r1 // ENAB bit (Bit 0) // FLSH bit (Bit 1) // ELKR bit (Bit 2) stb r1, @r0 // Write to the register CHAPTER 3 CPU AND CONTROL UNITS ❍ Disabling the instruction cache (OFF) To disable the instruction cache, set the ENAB bit to "0". Ldi #0x000003e7, r0 // I-Cache control register address Ldi #0B00000000, r1 // ENAB bit (Bit 0) Stb r1, @r0 // Write to the register In this state maintained (which is the same as after reset), the instruction cache virtually does not exist and thus does nothing. It may be a good idea to turn off the instruction cache if overhead seems to be a problem. ❍ Locking the complete contents of the cache Lock the instruction cache so that all the instructions it contains are removed, leaving nothing in it. Set the GBLK bit of the register to "1". Also set the ENAB bit to "1", since otherwise the instruction cache is turned off and no locked instructions in the instruction cache are used. Ldi #0x000003e7, r0 // I-Cache control register address Ldi #0B00100001, r1 // ENAB bit (Bit 0) // GBLK bit (Bit 5) stb r1, @r0 // Write to the register 55 CHAPTER 3 CPU AND CONTROL UNITS ❍ Locking a specific instruction to the instruction cache To lock a specific group of instructions (subroutines, etc.) to the instruction cache, set the EOLK bit to "1" before executing the instructions. A locked instruction is accessed as if it is in highspeed internal ROM. Ldi #0x000003e7, r0 // I-Cache control register address Ldi #0B00001001, r1 // ENAB bit (Bit 0) // EOLK bit (Bit 3) stb r1, @r0 // Write to the register Depending on the number of memory waits, this bit becomes valid with the next or a later instruction following the stb instruction. When locking of the group of instructions is completed, set the EOLK bit to 0. Ldi #0x000003e7, r0 // I-Cache control register address Ldi #0B00000001, r1 // ENAB bit (Bit 0) // EOLK bit (Bit 3) stb r1, @r0 // Write to the register ❍ Clearing an instruction cache lock Clear the lock information for an instruction locked with the EOLK bit described above. Ldi #0x000003e7, r0 // I-Cache control register address Ldi #0B00000000, r1 // Cache disable Stb r1, @r0 // Write to the register Ldi #0B00000000, r1 // ELKR bit (Bit 2) Stb r1, @r0 // Write to the register Only the lock information is cleared. Locked instructions are replaced sequentially with new instructions depending on the state maintained of the LRU bit. 56 CHAPTER 3 CPU AND CONTROL UNITS 3.4 Dedicated Registers Use the dedicated registers for specific purposes. A program counter (PC), program status (PS), table base register (TBR), return pointer (RP), system stack pointer (SSP), user stack pointer (USP), and multiply and divide registers (MDH/MDL) are provided. ■ List of Dedicated Registers A register consists of 32 bits. Figure 3.4-1 shows the dedicated registers. Figure 3.4-1 Dedicated Registers Program counter PC Program status PS Table base register TBR Return pointer RP System stack pointer SSP User stack pointer USP Multiply and divide registers MDH MDL - ILM - SCR CCR ■ Program Counter (PC) This section describes the functions of the program counter (PC: Program Counter). The program counter (PC) consists of 32 bits as shown below: 31 PC 0 [Initial value] XXXXXXXXH The program counter indicates the address of the instruction being executed. If the PC is updated when an instruction is executed, Bit 0 is set to "0". Bit 0 can be set to "1" only if an odd-number address is specified as the branch address. If Bit 0 is set to "1", however, Bit 0 is invalid and an instruction must be placed at the address that is a multiple of "2". The initial value upon reset is undefined. 57 CHAPTER 3 CPU AND CONTROL UNITS ■ Table Base Register (TBR) This section describes the functions of the table base register (TBR: Table Base Register). The table base register (TBR) consists of 32 bits as shown below: 31 0 TBR [Initial value] 000FFC00H The table base register holds the first address of the vector table to be used during EIT processing. The initial value upon reset is 000FFC00H. ■ Return Pointer (RP) This section describes the functions of the return pointer (RP: Return Pointer). The return pointer (RP) consists of 32 bits as shown below: 31 0 RP [Initial value] XXXXXXXXH The return pointer holds the return address from a subroutine. When the CALL instruction is executed, the value of the PC is transferred to the RP. When the RET instruction is executed, the contents of the RP are transferred to the PC. The initial value upon reset is undefined. ■ System Stack Pointer (SSP) This section describes the functions of the system stack pointer (SSP: System Stack Pointer). The system stack pointer (SSP) consists of 32 bits as shown below: 31 SSP 0 [Initial value] 00000000H The SSP is the system stack pointer. This register is used as an R15 general-purpose register if the S flag of the condition code register (CCR) is "0". The SSP can also be specified explicitly. This register is also used as a stack pointer that specifies a stack on which the contents of the PS and PC are to be saved if an EIT occurs. The initial value upon reset is 00000000H. 58 CHAPTER 3 CPU AND CONTROL UNITS ■ User Stack Pointer (USP) This section describes the functions of the user stack pointer (USP: User Stack Pointer). The user stack pointer (USP) consists of 32 bits as shown below: 31 0 USP [Initial value] XXXXXXXXH The USP is the user stack pointer. This register is used as an R15 general-purpose register if the S flag of the condition code register (CCR) is "1". The USP can also be specified explicitly. The initial value upon reset is undefined. This register cannot be used by the RETI instruction. ■ Multiply and Divide Registers (MDH/MDL) This section describes the functions of the multiply and divide registers (MDH/MDL: Multiply & Divide register). The multiply and divide registers (MDH/MDL) consist of 32 bits as shown below: 31 0 MDH MDL MDH and MDL are the multiply and divide registers. Each register is 32 bits long. The initial value upon reset is undefined. ❍ Functions when multiplication is executed For a 32-bit-by-32-bit multiplication, the 64-bit-long operation result is stored in the multiply and divide registers as follows: • MDH: High-order 32 bits • MDL: Low-order 32 bits For a 16-bit-by-16-bit multiplication, the result is stored in one of the multiply and divide registers as follows: • MDH: Undefined • MDL: 32-bit result ❍ Functions when division is executed When a calculation is started, the dividend is stored in MDL. When any of the DIV0S/DIV0U, DIV1, DIV2, DIV3, and DIV4S instructions is executed to perform division, the result is stored in MDH and MDL as follows: • MDH: Remainder • MDL: Quotient 59 CHAPTER 3 CPU AND CONTROL UNITS 3.4.1 Program Status (PS) Register The program status register (PS: Program Status) holds the program status. The PS register consists of three parts: ILM, SCR, and CCR. All undefined bits are reserved. During reading, 0 is always read. Writing is disabled. ■ Program Status (PS) Register The program status (PS) register consists of the condition code register (CCR), system condition code register (SCR), and interrupt level mask (ILM) register. Bit location 31 20 16 10 8 7 SCR ILM 0 CCR ❍ Condition code register (CCR) The condition code register (CCR: Condition Code Register) has the following configuration: bit 7 - 6 - 5 S 4 I 3 N 2 Z 1 V 0 C [Initial value] --00XXXXB The following describes the functions of these bits. [Bit 5] S (Stack flag) This bit specifies the stack pointer to be used as general-purpose register R15. The settings of this bit are shown in the following table. Value Description 0 The system stack pointer (SSP) is used as general-purpose register R15. When an EIT occurs, this bit is automatically set to "0". Note that a value saved on the stack is the value before it is cleared. 1 The user stack pointer (USP) is used as general-purpose register R15. This bit is cleared to "0" by a reset. Set this bit to "0" when the RETI instruction is executed. 60 CHAPTER 3 CPU AND CONTROL UNITS [Bit 4] I (Interrupt enable flag) This bit enables or disables a user interrupt request. The settings of this bit are shown in the following table. Value Description 0 User interrupts disabled. When the INT instruction is executed, this bit is cleared to "0". Note that a value saved on the stack is the value before it is cleared. 1 User interrupts enabled. The mask processing of a user interrupt request is controlled by the value held by the ILM register. This bit is cleared to "0" by a reset. [Bit 3] N (Negative flag) This bit indicates the sign used when the operation result is handled as an integer expressed as the two’s complement. The settings of this bit are shown in the following table. Value Description 0 Indicates that the operation result is a positive value. 1 Indicates that the operation result is a negative value. The initial state of this bit upon reset is undefined. [Bit 2] Z (Zero flag) This bit indicates whether the operation result is "0". The settings of this bit are shown in the following table. Value Description 0 Indicates that the operation result is not "0". 1 Indicates that the operation result is "0". The initial state of this bit upon reset is undefined. [Bit 1] V (Overflow flag) This bit indicates whether an overflow has occurred as a result of the operation when the operand used in the operation is handled as an integer expressed as the two’s complement. The settings of this bit are shown in the following table. Value Description 0 Indicates that no overflow has occurred as a result of the operation. 1 Indicates that an overflow has occurred as a result of the operation. The initial state of this bit upon reset is undefined. 61 CHAPTER 3 CPU AND CONTROL UNITS [Bit 0] C (Carry flag) This bit indicates whether a carry or a borrow has occurred from the highest bit in the operation. The settings of this bit are shown in the following table. Value Description 0 Indicates that no carry or borrow has occurred. 1 Indicates that a carry or borrow has occurred. The initial state of this bit upon reset is undefined. ❍ System condition code register (SCR) The system condition code register (SCR: System Condition code Register) has the following configuration: 10 D1 9 D0 8 T [Initial value] XX0B The following describes the functions of the system condition code register (SCR) bits. [Bits 10, 9] D1, D0 (Step division flag) These bits hold the intermediate data obtained when step division is executed. Do not change these bits while division processing is being executed. To perform other processing while executing a step division, save and restore the value of the PS register to ensure that the step division is restarted. The initial state of this bit upon reset is undefined. To set these bits, execute the DIV0S instruction with the dividend and the divisor to be referenced. To forcibly clear these bits, execute the DIV0U instruction. [Bit 8] T (Step trace trap flag) This bit specifies whether the step trace trap is to be enabled. The settings of this bit are shown in the following table. Value Description 0 The step trace trap is disabled. 1 The step trace trap is enabled. With this setting, all the user NMI and user interrupts are prohibited. This bit is initialized to "0" by a reset. The step trace trap function is used by an emulator. When an emulator is used, this function cannot be used in a user program. 62 CHAPTER 3 CPU AND CONTROL UNITS ❍ Interrupt level mask (ILM) register The interrupt level mask (ILM) register has the following configuration: 20 ILM4 19 ILM3 18 ILM2 17 ILM1 16 ILM0 [Initial value] 01111B The interrupt level mask (ILM) register holds an interrupt level mask value. The value held in ILM register is used as a level mask. The CPU accepts only interrupt requests sent to it with an interrupt level higher than the level indicated by the ILM. The highest level is 0 (00000B) and the lowest level is 31 (11111B). Values that can be set by a program have a limit. If the original value is between 16 and 31, the new value must be between 16 and 31. If an instruction that sets a value between 0 and 15 is executed, the specified value plus 16 is transferred. If the original value is between 0 and 15, an arbitrary value between 0 and 31 may be set. This register is initialized to 15 (01111B) by a reset. ❍ Notes Since some instructions process the PS register first, interrupt processing routines can lead to breaks during debugging or updating of the PS register flag due to the following exceptions. Whichever the case, the program is designed to reprocess correctly after returning from EIT to ensure that operation before and after EIT conforms to specifications. 1 The following operations may occur when (a) user interrupt/NMI is received, (b) step execution is performed, (c) break occurs in a data event or emulator menu in an immediately preceding DIVOU/DIVOS instruction. (1) D0 and D1 flag precede and are renewed. (2) EIT processing routine (user interruption, NMI or emulator) is executed. (3) After returning from EIT, DIVOU/DIVOS instructions are executed and the D0 and D1 flags are updated to the same value as (1). 2 When each ORCCR/STILM/MOV Ri and PS instruction is executed to permit interrupting with the user interruption and the NMI factor generated, the following operations are done. (1) The PS register precedes and is updated. (2) EIT processing routine (user interruption or NMI) is executed. (3) After returning from EIT, the above instructions are executed and the PS register is updated to the same value as (1). 63 CHAPTER 3 CPU AND CONTROL UNITS 3.5 General-Purpose Registers Registers R0 to R15 are general-purpose registers. These registers are used as an accumulator in an operation or a pointer in a memory access. ■ General-purpose Registers Figure 3.5-1 shows the configuration of the general-purpose registers. Figure 3.5-1 Configuration of General-purpose Registers 32-bit R0 R1 ... ... R12 R13 R14 R15 ... ... AC FP SP Initial value XXXX XXXXH ... ... ... ... ... XXXX XXXXH 0000 0000H Of these 16 registers, the following are intended for special applications and therefore enhanced instructions are provided for them: • R13: Virtual accumulator • R14: Frame pointer • R15: Stack pointer The initial value upon reset is undefined for R0 through R14 and is 00000000H (SSP value) for R15. 64 CHAPTER 3 CPU AND CONTROL UNITS 3.6 Data Structure The MB91307 series uses the following two data ordering methods: • Bit ordering • Byte ordering ■ Bit Ordering The MB91307 series uses the little endian method for bit ordering. Figure 3.6-1 shows the bit configuration in bit ordering. Figure 3.6-1 Bit Configuration in Bit Ordering bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSB LSB ■ Byte Ordering The MB91307 series uses the big endian method for byte ordering. Figure 3.6-2 shows the configuration of byte ordering. Figure 3.6-2 Configuration of Byte Ordering Memory MSB bit 31 23 15 7 LSB 0 10101010 11001100 11111111 00010001 bit 7 Address n 0 10101010 Address (n+1) 11001100 Address (n+2) 11111111 Address (n+3) 00010001 65 CHAPTER 3 CPU AND CONTROL UNITS 3.7 Word Alignment Since instructions and data are accessed in byte units, the addresses at which they are placed depend on the instruction length or the data width. ■ Program Access A program for the MB91307 series must be placed at an address that is a multiple of "2". Bit 0 of the program counter (PC) is set to "0" if the PC is updated when an instruction is executed. Bit 0 can be set to "1" only if an odd-number address is specified as the branch address. If Bit 0 is set to "1", however, Bit 0 is invalid and an instruction must be placed at the address that is a multiple of "2". No odd-number address exception exists. ■ Data Access If data in the MB91307 series is accessed, forced alignment is applied to the address based on the width. • Word access: An address must be a multiple of "4". (The lowest-order 2 bits are forcibly set to "00".) • Halfword access: An address must be a multiple of "2". (The lowest-order bit is forcibly set to "0".) • Byte access: - During word or halfword data access, some of the bits in the result of calculating an effective address are forcibly set to "0". For example, in @(R13, Ri) addressing mode, the register before addition is used without change in the calculation (even if the lowest-order bit is "1") and the low-order bits are masked. A register before calculation is not masked. [Example] LD @(R13, R2), R0 R13 00002222H R2 00000003H +) 66 Addition result 00002225H Lower 2 bits forcibly masked Address pin 00002224H CHAPTER 3 CPU AND CONTROL UNITS 3.8 Memory Map This section shows the memory map for the MB91307 series. ■ Memory Map The address space of memory is 32 bits linear. Figure 3.8-1 shows the memory map. Figure 3.8-1 Memory Map 0000 0000H 0000 0100H 0000 0200H 0000 0400H Byte data Halfword data Direct addressing area Word data 000F FC00H Vector table initial area 000F FFFFH FFFF FFFFH ❍ Direct addressing area The following areas in the address space are the areas for I/O. When direct addressing is used in these areas, an operand address can be directly specified in an instruction. The size of an address area for which an address can be directly specified varies is determined by the data length as follows: • Byte data (8 bits): 000H to 0FFH • Halfword data (16 bits): 000H to 1FFH • Word data (32 bits): 000H to 3FFH ❍ Vector table initial area The area from 000FFC00H to 000FFFFFH is the initial EIT vector table area. You can place the vector table that will be used during EIT processing at any address by rewriting the TBR. Initialization by a reset places the table at this address. 67 CHAPTER 3 CPU AND CONTROL UNITS 3.9 Branch Instructions An operation with or without a delay slot can be specified for a branch instruction used in the MB91307 series. ■ Branch Instructions with Delay Slot Instructions written as follows perform a branch operation with a delay slot: JMP:D @Ri CALL:D label12 CALL:D @Ri RET:D BRA:D label9 BNO:D label9 BEQ:D label9 BNE:D label9 BC:D label9 BNC:D label9 BN:D label9 BP:D label9 BV:D label9 BNV:D label9 BLT:D label9 BGE:D label9 BLE:D label9 BGT:D label9 BLS:D label9 BHI:D label9 ■ Branch Instructions without Delay Slot Instructions written as follows perform a branch operation without a delay slot: 68 JMP @Ri CALL label12 CALL @Ri RET BRA label9 BNO label9 BEQ label9 BNE label9 BC label9 BNC label9 BN label9 BP label9 BV label9 BNV label9 BLT label9 BGE label9 BLE label9 BGT label9 BLS label9 BHI label9 CHAPTER 3 CPU AND CONTROL UNITS 3.9.1 Operation of Branch Instructions with Delay Slot In operation with a delay slot, the instruction located just after a branch instruction (placed in a "delay slot") is executed before the instruction that branches is executed. ■ Operation of Branch Instruction with Delay Slot Since an instruction in the delay slot is executed before the branch operation, the apparent execution speed is one cycle. However, a NOP instruction must be placed in the delay slot if there is no valid instruction put there. [Example] ; List of instructions ADD R1, BRA:D LABEL MOV R2, R3, R2, ; ; Branch instruction R3, ; Delay slot ... Executed before branch @R4 ; Branch destination ... LABEL : ST If a conditional branch instruction is used, an instruction placed in the delay slot is executed whether or not the condition for branching is met. If a delay branch instruction is used, the order of execution for some instructions seems to be reversed. However, this occurs only for updating the PC and the instructions are executed in the specified order for other operations (register update and reference, etc.) The following is a concrete example. ❍ JMP:D @Ri / CALL:D @Ri instruction Ri referenced by the JMP:D @Ri / CALL:D @Ri instruction is not affected even though Ri is updated by the instruction in the delay slot. [Example] LDI:32 #Label, JMP:D @R0 LDI:8 #0, R0 R0 ; ; Branch to Label ; No effect on the branch destination address ... 69 CHAPTER 3 CPU AND CONTROL UNITS ❍ RET:D instruction RP referenced by the RET:D instruction is not affected even though RP is updated by the instruction in the delay slot. [Example] RET:D MOV R8, RP ; Branch to address defined beforehand in RP ; No effect on the return operation ... ❍ Bcc:D rel instruction The flag referenced by the Bcc:D rel instruction is not affected by the instruction in the delay slot. [Example] ADD #1, BC:D Overflow ANDCCR #0 R0 R0 ; Flag change ; Branch to execution result of above instruction ; This flag update is not referenced by the above branch instruction. ... ❍ CALL:D instruction If RP is referenced by an instruction in the delay slot of the CALL:D instruction, the data that has been updated by the CALL:D instruction is read. [Example] CALL:D Label MOV RP, R0 ; Updating RP and branching ; Transferring RP, execution result of above CALL:D ... ■ Limitations on Branch Instruction with Delay Slot ❍ Instructions that can be placed in the delay slot Only an instruction meeting the following conditions can be executed in the delay slot. • One-cycle instruction • Instruction other than a branch instruction • Instruction whose operation is not affected even though the order is changed A one-cycle instruction is an instruction denoted in the Number of Cycles column in the list of instructions as 1, a, b, c, and d. 70 CHAPTER 3 CPU AND CONTROL UNITS ❍ Step trace trap A step trace trap does not occur between the execution of a branch instruction with a delay slot and the delay slot. ❍ Interrupt NMI An interrupt NMI is not accepted between the execution of a branch instruction with a delay slot and the delay slot. ❍ Undefined instruction exception An undefined instruction exception does not occur if there is an undefined instruction in the delay slot. If an undefined instruction is in the delay slot, it operates as a NOP instruction. 71 CHAPTER 3 CPU AND CONTROL UNITS 3.9.2 Operation of Branch Instruction without Delay Slot In operation without a delay slot, instructions are executed in the order in which they are specified. An instruction immediately following a branch is never executed before it. ■ Operation of Branch Instruction without Delay Slot [Example] ; List of instructions ADD R1, R2, BRA LABEL MOV R2, R3, ; ; Branch instruction (without a delay slot) R3, ; Not executed @R4 ; Branch destination ... LABEL : ST A branch instruction without a delay slot is executed in two cycles if a branch occurs and in one cycle if no branch occurs. Since no appropriate instruction can be placed in the delay slot, this instruction results in a more efficient instruction code than a branch instruction with a delay slot and with NOP specified. For both optimal execution speed and code efficiency, select an operation with a delay slot if a valid instruction can be placed in the delay slot; otherwise, select an operation without a delay slot. 72 CHAPTER 3 CPU AND CONTROL UNITS 3.10 EIT (Exception, Interrupt, and Trap) EIT, a generic term for exception, interrupt, and trap, refers to suspending program execution if an event occurs during execution and then executing another program. ■ EIT (Exception, Interrupt, and Trap) An exception is an event that occurs related to the execution context. Execution restarts from the instruction that caused the exception. An interrupt is an event that occurs independently of execution context. The event is caused by hardware. A trap is an event that occurs related to the execution context. Some traps, such as system calls, are specified in a program. Execution restarts from the instruction following the one that caused the trap. ■ EIT Causes The following are causes of EIT: • Reset • User interrupt (internal resource, external interrupt) • NMI • Delayed interrupt • Undefined instruction exception • Trap instruction (INT) • Trap instruction (INTE) • Step trace trap • No-coprocessor trap • Coprocessor error trap ■ Return from EIT Use the RETI instruction to return from EIT. 73 CHAPTER 3 CPU AND CONTROL UNITS 3.10.1 EIT Interrupt Levels The interrupt levels are 0 to 31 and are managed with five bits. ■ EIT Interrupt Levels Table 3.10-1 shows the allocation of the levels. Table 3.10-1 EIT Interrupt Levels Level Interrupt source Binary Decimal 00000 ... ... 00011 0 ... ... 3 (Reserved for system) ... ... (Reserved for system) 00100 4 INTE instruction Step trace trap 00101 ... ... 00101 5 ... ... 14 (Reserved for system) ... ... (Reserved for system) 01110 15 NMI (for user) 10000 10001 ... ... 11110 11111 16 17 ... ... 30 31 Interrupt Interrupt ... ... Interrupt - Remarks If the original ILM value is between 16 and 31, a program cannot set a value in this ILM range. User interrupts prohibited if ILM is set Interrupts prohibited if ICR is set Operation is possible for levels 16 to 31. The interrupt level does not affect an undefined instruction exception, no-coprocessor trap, coprocessor error trap, or an INT instruction. It does not change the ILM, either. 74 CHAPTER 3 CPU AND CONTROL UNITS ■ I Flag A flag that specifies whether an interrupt is permitted or prohibited. This flag is provided as CCR Bit 4 of the PS register. Table 3.10-2 I Flag Value Description 0 Interrupts prohibited Cleared to "0" if the INT instruction is executed. Note that a value saved on the stack is the value before it is cleared. 1 Interrupts permitted The mask processing of an interrupt request is controlled by the value in the ILM register. ■ Interrupt Level Mask (ILM) Register A PS register (Bits 20 to 16) that holds an interrupt level mask value. The CPU accepts only an interrupt request sent to it with an interrupt level higher than the level indicated by the ILM. The highest level is 0 (00000B) and the lowest level is 31 (11111B). Values that can be set by a program have a limit. If the original value is between 16 and 31, the new value must be between 16 and 31. If an instruction that sets a value between 0 and 15 is executed, the specified value plus 16 is transferred. If the original value is between 0 and 15, any value between 0 and 31 may be set. Note: Use the STILM instruction to set this register. ■ Level Mask for Interrupt and NMI If an NMI or interrupt request occurs, the interrupt level (Table 3.10-1) of the interrupt source is compared with the level mask value held in the ILM. A request meeting the following condition is masked and is not accepted: Interrupt level of cause ≥ Level mask value 75 CHAPTER 3 CPU AND CONTROL UNITS 3.10.2 Interrupt Control Register (ICR) The interrupt control register (ICR: Interrupt Control Register), located in the interrupt controller, sets the level of an interrupt request. An ICR is provided for each of the interrupt request inputs. The ICR is mapped on the I/O space and is accessed from the CPU through a bus. ■ Configuration of Interrupt Control Register (ICR) The following shows the configuration of the interrupt control register (ICR) bits. Figure 3.10-1 Bit Configuration of the Interrupt Control Register (ICR) bit 7 - 6 - 5 - 4 ICR4 R 3 ICR3 R/W 2 ICR2 R/W 1 ICR1 R/W 0 ICR0 R/W ---11111B The following describes the functions of the interrupt control register (ICR) bits. [Bit 4] ICR4 This bit is always set to "1". [Bits 3 to 0] ICR3 to ICR0 These bits are the low-order 4 bits of the interrupt level of the corresponding interrupt source. They can be read and written to. Together with Bit 4, a value between "16" and "31" can be set in the ICR. ■ Mapping of Interrupt Control Register (ICR) Table 3.10-3 shows the relationship between interrupt sources, interrupt control register, and interrupt vectors. Table 3.10-3 Interrupt Sources, Interrupt Control Registers, and Interrupt Vectors Corresponding interrupt vector Interrupt source Interrupt control register Number Address Hexadecimal Decimal IRQ00 ICR00 00000440H 10H 16 TBR + 3BCH IRQ01 ICR01 00000441H 11H 17 TBR + 3B8H IRQ02 ICR02 00000442H 12H 18 TBR + 3B4H ... ... ... ... ... ... ... ... ... ... ... ... IRQ45 ICR45 0000046DH 3DH 61 TBR + 308H IRQ46 ICR46 0000046EH 3EH 62 TBR + 304H IRQ47 ICR47 0000046FH 3FH 63 TBR + 300H Note: See "CHAPTER 10 INTERRUPT CONTROLLER". 76 CHAPTER 3 CPU AND CONTROL UNITS 3.10.3 System Stack Pointer (SSP) The system stack pointer (SSP) is used to point to the stack to save and restore data when EIT is accepted or a return operation occurs. ■ System Stack Pointer (SSP) The system stack pointer (SSP: System Stack Pointer) consists of 32 bits as shown below: Figure 3.10-2 Bit Configuration of the System Stack Pointer (SSP) bit 31 0 SSP [Initial value] 00000000H Eight is subtracted from the register value during EIT processing and eight is added to the register value during the return operation from EIT that occurs when the RETI instruction is executed. The system stack pointer (SSP) is initialized to 00000000H by a reset. The SSP is also used as general-purpose register R15 if the S flag in the CCR is set to "0". ■ Interrupt Stack The value in the PC or PS is saved to or restored from an area pointed to by the system stack pointer (SSP). After an interrupt occurs, the PC is stored at the address indicated by the SSP and the PS is stored at the address indicated by the SSP plus 4. This situation is shown in Figure 3.10-3. Figure 3.10-3 Interrupt Stack [Example] SSP [Before interrupt] 80000000H [After interrupt] SSP 7FFFFFF8H Memory 80000000H 7FFFFFFCH 7FFFFFF8H 80000000H 7FFFFFFCH 7FFFFFF8H PS PC 77 CHAPTER 3 CPU AND CONTROL UNITS 3.10.4 Table Base Register (TBR) The table base register (TBR: Table Base Register) indicates the beginning address of the vector table for EIT. ■ Table Base Register (TBR) The table base register (TBR) consists of 32 bits as shown below: bit 31 0 TBR [Initial value] 000FFC00H Obtain a vector address by adding to the TBR the offset value predetermined for an EIT cause. The table base register (TBR) is initialized to 000FFC00H by a reset. ■ EIT Vector Table A 1 KB area from the address indicated in the table base register (TBR) is the vector area for EIT. The size for each vector is 4 bytes. The relationship between a vector number and a vector address can be expressed as follows: vctadr = TBR + vctofs = TBR + (3FC H - 4 × vct) vctadr: Vector address vctofs: Vector offset vct: Vector number The low-order two bits of the addition result are always handled as "00". The area from 000FFC00H to 000FFFFFH is the initial area for the vector table upon reset. Special functions are allocated to some of the vectors. 78 CHAPTER 3 CPU AND CONTROL UNITS Table 3.10-4 shows the vector table on the architecture. Table 3.10-4 Vector Table (1/3) Interrupt number Offset Default address of TBR Decimal Hexadecimal Interrupt level Reset 0 00 - 3FCH 000FFFFCH Mode vector 1 01 - 3F8H 000FFFF8H Reserved for system 2 02 - 3F4H 000FFFF4H Reserved for system 3 03 - 3F0H 000FFFF0H Reserved for system 4 04 - 3ECH 000FFFECH Reserved for system 5 05 - 3E8H 000FFFE8H Reserved for system 6 06 - 3E4H 000FFFE4H No-coprocessor trap 7 07 - 3E0H 000FFFE0H Coprocessor error trap 8 08 - 3DCH 000FFFDCH INTE instruction 9 09 - 3D8H 000FFFD8H Instruction break exception 10 0A - 3D4H 000FFFD4H Operand break trap 11 0B - 3D0H 000FFFD0H Step trace trap 12 0C - 3CCH 000FFFCCH NMI request (tool) 13 0D - 3C8H 000FFFC8H Undefined instruction exception 14 0E - 3C4H 000FFFC4H NMI request 15 0F Fixed to 15(FH) 3C0H 000FFFC0H External Interrupt 0 16 10 ICR00 3BCH 000FFFBCH External Interrupt 1 17 11 ICR01 3B8H 000FFFB8H External Interrupt 2 18 12 ICR02 3B4H 000FFFB4H External Interrupt 3 19 13 ICR03 3B0H 000FFFB0H External Interrupt 4 20 14 ICR04 3ACH 000FFFACH External Interrupt 5 21 15 ICR05 3A8H 000FFFA8H External Interrupt 6 22 16 ICR06 3A4H 000FFFA4H External Interrupt 7 23 17 ICR07 3A0H 000FFFA0H Reload Timer 0 24 18 ICR08 39CH 000FFF9CH Reload Timer 1 25 19 ICR09 398H 000FFF98H Reload Timer 2 26 1A ICR10 394H 000FFF94H UART0 (reception completed) 27 1B ICR11 390H 000FFF90H UART1 (reception completed) 28 1C ICR12 38CH 000FFF8CH Interrupt source 79 CHAPTER 3 CPU AND CONTROL UNITS Table 3.10-4 Vector Table (2/3) Interrupt number Offset Default address of TBR Decimal Hexadecimal Interrupt level UART2 (reception completed) 29 1D ICR13 388H 000FFF88H UART0 (transmission completed) 30 1E ICR14 384H 000FFF84H UART1 (transmission completed) 31 1F ICR15 380H 000FFF80H UART2 (transmission completed) 32 20 ICR16 37CH 000FFF7CH DMAC0 (end, error) 33 21 ICR17 378H 000FFF78H DMAC1 (end, error) 34 22 ICR18 374H 000FFF74H DMAC2 (end, error) 35 23 ICR19 370H 000FFF70H DMAC3 (end, error) 36 24 ICR20 36CH 000FFF6CH DMAC4 (end, error) 37 25 ICR21 368H 000FFF68H A/D 38 26 ICR22 364H 000FFF64H I2C 39 27 ICR23 360H 000FFF60H Reserved for system 40 28 ICR24 35CH 000FFF5CH Reserved for system 41 29 ICR25 358H 000FFF58H Reserved for system 42 2A ICR26 354H 000FFF54H Reserved for system 43 2B ICR27 350H 000FFF50H Reserved for system 44 2C ICR28 34CH 000FFF4CH U-TIMER0 45 2D ICR29 348H 000FFF48H U-TIMER1 46 2E ICR30 344H 000FFF44H Time base timer overflow 47 2F ICR31 340H 000FFF40H Reserved for system 48 30 ICR32 33CH 000FFF3CH Reserved for system 49 31 ICR33 338H 000FFF38H Reserved for system 50 32 ICR34 334H 000FFF34H Reserved for system 51 33 ICR35 330H 000FFF30H Reserved for system 52 34 ICR36 32CH 000FFF2CH Reserved for system 53 35 ICR37 328H 000FFF28H Reserved for system 54 36 ICR38 324H 000FFF24H Reserved for system 55 37 ICR39 320H 000FFF20H Reserved for system 56 38 ICR40 31CH 000FFF1CH Reserved for system 57 39 ICR41 318H 000FFF18H Reserved for system 58 3A ICR42 314H 000FFF14H Reserved for system 59 3B ICR43 310H 000FFF10H Interrupt source 80 CHAPTER 3 CPU AND CONTROL UNITS Table 3.10-4 Vector Table (3/3) Interrupt number Offset Default address of TBR Decimal Hexadecimal Interrupt level Reserved for system 60 3C ICR44 30CH 000FFF0CH Reserved for system 61 3D ICR45 308H 000FFF08H Reserved for system 62 3E ICR46 304H 000FFF04H Delayed interrupt source bit 63 3F ICR47 300H 000FFF00H Reserved for system (used in REALOS) 64 40 - 2FCH 000FFEFCH Reserved for system (used in REALOS) 65 41 - 2F8H 000FFEF8H Reserved for system 66 42 - 2F4H 000FFEF4H Reserved for system 67 43 - 2F0H 000FFEF0H Reserved for system 68 44 - 2ECH 000FFEECH Reserved for system 69 45 - 2E8H 000FFEE8H Reserved for system 70 46 - 2E4H 000FFEE4H Reserved for system 71 47 - 2E0H 000FFEE0H Reserved for system 72 48 - 2DCH 000FFEDCH Reserved for system 73 49 - 2D8H 000FFED8H Reserved for system 74 4A - 2D4H 000FFED4H Reserved for system 75 4B - 2D0H 000FFED0H Reserved for system 76 4C - 2CCH 000FFECCH Reserved for system 77 4D - 2C8H 000FFEC8H Reserved for system 78 4E - 2C4H 000FFEC4H Reserved for system 79 4F - 2C0H 000FFEC0H Used in INT instruction 80 to 255 50 to FF - 2BCH to 000H 000FFEBCH to 000FFC00H Interrupt source Notes: Even though the TBR value is changed, the reset vector and the mode vector are always fixed addresses. 000FFFFCH and 000FFFF8H are used. • For information about the vector table for the MB91307 series, see the appendix. • 81 CHAPTER 3 CPU AND CONTROL UNITS 3.10.5 Multiple EIT Processing If multiple EIT causes occur at the same time, the CPU repeats the operation of selecting and accepting one of the EIT causes, executing the EIT sequence, and then detecting EIT causes again. If there are no more EIT causes be accepted while the CPU is detecting EIT causes, the CPU executes the handler instruction of the last accepted EIT cause. As a result, the order of executing handlers for multiple EIT causes that occur at the same time is determined according to the following two elements: • Priority of EIT causes to be accepted • How other causes can be masked when one cause is accepted ■ Priority of EIT Causes to Be Accepted The priority of EIT causes to be accepted is the order of causes for which the EIT sequence is to be executed (that is, saving the PS and PC, updating the PC, and masking other causes, if required). The handler of a cause accepted earlier is not necessarily executed earlier. Table 3.10-5 shows the priority of EIT causes to be accepted. Table 3.10-5 Priority of EIT Causes to Be Accepted and Masking of Other Causes Priority of acceptance Cause Masking of other causes 1 Reset Other causes are abandoned. 2 Undefined instruction exception Canceled 3 INT instruction I flag=0 4 No-coprocessor trap Coprocessor error trap 5 User interrupt ILM=level of cause accepted 6 NMI (for users) ILM=15 7 (INTE instruction) ILM=4 * 8 NMI (for emulators) ILM=4 9 Step trace trap ILM=4 10 INTE instruction ILM=4 ⎯ * : The priority is "6" only if the INTE instruction and the NMI for emulators occur at the same time. The NMI for emulators is used in the MB91307 series for breaks due to data access. 82 CHAPTER 3 CPU AND CONTROL UNITS In consideration of masking other causes after an EIT cause is accepted, the handlers of EIT causes that occur at the same time are executed in the order shown in Table 3.10-6. Table 3.10-6 Order of Executing EIT Handlers Order of executing handlers Cause 1 Reset *1 2 Undefined instruction exception 3 Step trace trap *2 4 INTE instruction *2 5 NMI (for users) 6 INT instruction 7 User interrupt 8 No-coprocessor trap, coprocessor error trap *1: Other causes are abandoned. *2: If the INTE instruction is executed in steps, only a step trace trap EIT occurs. An INTE cause is ignored. Figure 3.10-4 shows an example of multiple EIT processing. Figure 3.10-4 Multiple EIT Processing [Example] Main routine NMI handler Priority INT instruction handler (1) Executed first (High) NMI occurring (Low) INT instruction executed (2) Executed next 83 CHAPTER 3 CPU AND CONTROL UNITS 3.10.6 EIT Operations This section describes EIT operations. ■ EIT Operations In the following, it is assumed that the destination source PC indicates the address of the instruction that detected an EIT cause. In addition, "address of the next instruction" means that the instruction that detected EIT is as follows: • If LDI is 32: PC + 6 • If LDI is 20 and COPOP, COPLD, COPST, and COPSV are used: PC + 4 • Other instructions: PC + 2 ■ Operation of User Interrupt/NMI If an interrupt request for a user interrupt or a user NMI occurs, whether the request can be accepted is determined with the following procedure: 1. Compare the interrupt levels of requests that have occurred simultaneously and select the request with the highest level (the smallest value). As levels to be compared, the value held in the corresponding ICR is used for a maskable interrupt and a predetermined constant is used for an NMI. 2. If multiple interrupt requests with the same level occur, select the interrupt request with the smallest interrupt number. 3. Mask but do no accept an interrupt request with an interrupt level greater than or equal to the level mask value. Go to Step 4) if the interrupt level is less than the level mask value. 4. Mask but do not accept the selected interrupt request if it is maskable and the I flag is set to "0". Go to Step 5) if the I flag is "1". If the selected interrupt request is an NMI, go to Step 5) regardless of the I flag value. 5. If the above conditions are met, the interrupt request is accepted at a break in the instruction processing. If a user interrupt or NMI request is accepted when EIT requests are detected, the CPU operates as follows, using an interrupt number corresponding to the accepted interrupt request. Parentheses show an address indicated by the register. [Operation] 1. SSP-4 → SSP 2. PS → (SSP) 3. SSP-4 → SSP 4. Address of next instruction → (SSP) 5. Interrupt level of accepted request → ILM 6. "0" → S flag 7. (TBR + Vector offset of accepted interrupt request) → PC 84 CHAPTER 3 CPU AND CONTROL UNITS If a user interrupt or NMI request is accepted when EIT requests are detected, the CPU operates as follows, using an interrupt number corresponding to the accepted interrupt request. Parentheses show an address indicated by the register. ■ Operation of INT Instruction The INT #u8 instruction operates as shown below. A branch to the interrupt handler for the vector indicated by u8 generation. [Operation] 1. SSP-4 → SSP 2. PS → (SSP) 3. SSP-4 → SSP 4. PC + 2 → (SSP) 5. "0" → I flag 6. "0" → S flag 7. (TBR + 3FCH-4 × u8) → PC ■ Operation of INTE Instruction The INTE instruction operates as shown below. A branch to the interrupt handler for the vector indicated by vector number #9 generation. [Operation] 1. SSP-4 → SSP 2. PS → (SSP) 3. SSP-4 → SSP 4. PC + 2 → (SSP) 5. "00100" → ILM 6. "0" → S flag 7. (TBR+3D8H) → PC Do not use the INTE instruction in the processing routine of the INTE instruction or a step trace trap. During step execution, no EIT due to INTE generation. 85 CHAPTER 3 CPU AND CONTROL UNITS ■ Operation of Step Trace Trap Set the T flag in the SCR of the PS to enable the step trace function. A trap and a break then occur every time an instruction is executed. A step trace trap is detected under the following conditions: • T flag =1 • There is no delayed branch instruction. • A processing routine other than the INTE instruction or a step trace trap is in progress. If the above conditions are met, a break occurs between instruction operations. [Operation] 1. SSP-4 → SSP 2. PS → (SSP) 3. SSP-4 → SSP 4. Address of next instruction → (SSP) 5. "00100" → ILM 6. "0" → S flag 7. (TBR+3CCH) → PC Set the T flag to enable the step trace trap to prohibit a user NMI and a user interrupt. No EIT occurs due to the INTE instruction. A trap occurs in the MB91307 series in the instruction following the one in which the T flag has been set. ■ Operation of Undefined Instruction Exception If, during instruction decode, an undefined instruction is detected, an undefined instruction exception occurs. An undefined instruction exception is detected under the following conditions: • An undefined instruction is detected during instruction decode. • The instruction is not located in the delay slot (it does not immediately follow). If the above conditions are met, an undefined instruction exception and a break occur. [Operation] 1. SSP-4 → SSP 2. PS → (SSP) 3. SSP-4 → SSP 4. PC → (SSP) 5. "0" → S flag 6. (TBR+3C4H) → PC The PC value to be saved is the address of an instruction that detected an undefined instruction exception. 86 CHAPTER 3 CPU AND CONTROL UNITS ■ No-coprocessor Trap If a coprocessor instruction using a coprocessor that is not installed is executed, a nocoprocessor trap occurs. [Operation] 1. SSP-4 → SSP 2. PS → (SSP) 3. SSP-4 → SSP 4. Address of next instruction → (SSP) 5. "0" → S flag 6. (TBR+3E0H) → PC ■ Coprocessor Error Trap If an error occurs while a coprocessor is being used and then a coprocessor instruction that operates on the coprocessor is executed, a coprocessor error trap occurs. [Operation] 1. SSP-4 → SSP 2. PS → (SSP) 3. SSP-4 → SSP 4. Address of next instruction → (SSP) 5. "0" → S flag 6. (TBR+3DCH) → PC ■ Operation of RETI Instruction The RETI instruction specifies return from the EIT processing routine. [Operation] 1. (R15) → PC 2. R15+4 → R15 3. (R15) → PS 4. R15+4 → R15 The RETI instruction must be executed while the S flag is set to "0". ■ Precaution on Delay Slot A delay slot for a branch instruction has restrictions regarding EIT. See Section "3.9 Branch Instructions". 87 CHAPTER 3 CPU AND CONTROL UNITS 3.11 Reset (Device Initialization) This section describes a reset (that is, initialization) of the MB91307 series. ■ Reset (Device Initialization) If a reset source occurs, the device stops all the programs and hardware operations and completely initializes the state. This state is called the reset state. When a reset source no longer exists, the device starts programs and hardware operations from their initial state. The series of operations from the reset state to the start of operations is called the reset sequence. 88 CHAPTER 3 CPU AND CONTROL UNITS 3.11.1 Reset Levels The reset operations of the MB91307 series are classified into two levels, each of which has different causes and initialization operations. This section describes these reset levels. ■ Settings Initialization Reset (INIT) The highest-level reset, which initializes all settings, is called a settings initialization reset (INIT). A settings initialization reset (INIT) mainly performs the following initialization: ❍ Items initialized in a settings initialization reset (INIT) The operation made for a device (setting of the bus made and the external bus width) • All internal clock settings (clock source selection, PLL control, and divide-by setting) • All external bus extended interface settings • All settings on pin statuses other than the above settings • All sections initialized by an operation initialization reset (RST) For more information, see the description of each of these functions. Note: After power-on, be sure to apply the settings initialization reset (INIT) at the INIT pin. ■ Operation Initialization Reset (RST) A normal-level reset that initializes the operation of a program is called an operation initialization reset (RST). If a settings initialization reset (INIT) occurs, an operation initialization reset (RST) also occurs. An operation initialization reset (RST) mainly initializes the following items: ❍ Items initialized by an operation initialization reset (RST) • Program operation • CPU and internal buses • Register settings of peripheral circuits • I/O port settings • All CS0 area settings of external buses For more information, see the description of each of these functions. 89 CHAPTER 3 CPU AND CONTROL UNITS 3.11.2 Reset Sources This section describes the reset sources and the reset levels in the MB91307 series. To determine reset sources that have occurred in the past, read the RSRR (reset source register). For more information about registers and flags described in this section, see Section "3.12 Clock Generation Control". ■ INIT Pin Input (Settings Initialization Reset Pin) The INIT pin, which is an external pin, is used as the settings initialization reset pin. A settings initialization reset (INIT) request is generated while the "L" level is being input to this pin. Input the "H" level to this pin to clear a settings initialization reset (INIT) request. If a settings initialization reset (INIT) is generated in response to a request from this pin, Bit 15 (INIT bit) of the RSRR (reset source register) is set. Because a settings initialization reset (INIT) in response to a request from this pin has the highest interrupt level among all reset sources, it has precedence over any other input, operation, or state. Immediately after power-on, be sure to apply a settings initialization reset (INIT) at the INIT pin. To assure the oscillation stabilization wait time for the oscillation circuit immediately after poweron, input the "L" level to the INIT pin for the stabilization wait time required by the oscillation circuit. INIT at the INIT pin initializes the oscillation stabilization wait time to the minimum value. • Reset source: "L" level input to the external INIT pin • Source of clearing: "H" level input to the external INIT pin • Reset level: Settings initialization reset (INIT) • Corresponding flag: Bit 15 (INIT) ■ Software Reset (STCR: SRST Bit Writing) If "0" is written to Bit 4 (SRSI bit) of the standby control register (STCR), a software reset request occurs. A software reset request is an operation initialization reset (RST) request. When the request is accepted and a operation initialization reset (RST) is generated, the software reset request is cleared. If an operation initialization reset (RST) is generated due to a software reset request, a bit (SRST bit) in the RSRR (reset source register) is set. An operation initialization reset (RST) is generated due to a software reset request only after all bus access has stopped and if Bit 7 (SYNCR bit) of the time base counter control register (TBCR) has been set (synchronization reset mode). Thus, depending on the bus usage status, a long time is required before an operation initialization reset (RST) occurs. 90 • Reset source: Writing "0" to Bit 4 (SRST) of the standby control register (STCR) • Source of clearing: Generation of an operation initialization reset (RST) • Reset level: Operation initialization reset (RST) • Corresponding flag: Bit 11(SRST) CHAPTER 3 CPU AND CONTROL UNITS ■ Watchdog Reset Writing to the watchdog timer control register (RSRR) starts the watchdog timer. Unless A5H/ 5AH is written to the watchdog reset postpone register (WPR) within the cycle specified in Bits 9 and 8 (WT1 and WT0 bits) in the RSRR, a watchdog reset request occurs. A watchdog reset request is a settings initialization reset (INIT) request. If, after the request is accepted, a settings initialization reset (INIT) occurs or an operation initialization reset (RST) occurs, the watchdog reset request is cleared. If a settings initialization reset (INIT) is generated due to a watchdog reset request, Bit 13 (WDOG bit) in the reset source register (RSRR) is set. Note that, if a settings initialization reset (INIT) is generated due to a watchdog reset request, the oscillation stabilization wait time is not initialized. • Reset source: Setting cycle of the watchdog timer elapses • Source of clearing: Generation of a settings initialization reset (INIT) or an operation initialization reset (RST) • Reset level: Settings initialization reset (INIT) • Corresponding flag: Bit 13 (WDOG) ■ HST Pin Input (Hardware Standby Pin) (MB91307B only) The HST pin, which is an external pin, is used as a hardware standby pin. A hardware standby request is generated while the "L" level is being input to this pin. If the hardware standby request is accepted and the device enters the hardware standby state, the settings initialization reset (INIT) is generated at the same time. Input the "H" level to this pin to clear a hardware standby request and a settings initialization reset (INIT). If, in the hardware standby state, a settings initialization reset (INIT) is generated due to the external INIT pin, the hardware standby request is cleared but the settings initialization reset (INIT) remains. If a settings initialization reset (INIT) is generated due to the hardware standby state, Bit 14 (HSTB bit) of the reset source register (RSRR) is set. If a hardware standby request occurs immediately after power-on, a settings initialization reset (INIT) generated due to the INIT pin has precedence. If later the settings initialization reset (INIT) generated due to the INIT pin is cleared and the hardware standby state is entered, the oscillation stabilization wait time setting is initialized to the maximum value. The oscillation stabilization wait time is therefore the maximum value after the hardware standby request is cleared. • Reset source: "L" level input to the external HST pin • Source of clearing: "H" level input to the external HST pin or a settings initialization reset (INIT) due to the INIT pin • Reset level: Settings initialization reset (INIT) • Corresponding flag: Bit 14(HSTB) 91 CHAPTER 3 CPU AND CONTROL UNITS 3.11.3 Reset Sequence When a reset source no longer exists, the device starts to execute the reset sequence. A reset sequence has different operations depending on the reset level. This section describes the operations of the reset sequence for different reset levels. ■ Setting Initialization Reset (INIT) Clear Sequence If a settings initialization reset (INIT) request is cleared, the following operations are performed one step at a time for the device. 1. Clear the settings initialization reset (INIT) and enter the oscillation stabilization wait state. 2. For the oscillation stabilization wait time (set with Bits 3 and 2 [OS1 and OS0 bits] in the STCR), maintain the operation initialization reset (RST) state and stop the internal clock. 3. In the operation initialization reset (RST) state, start internal clock operation. 4. Clear the operation initialization reset (RST) and enter the normal operating state. 5. Read the mode vector from address 000FFFF8H. 6. Write the mode vector to the MODR (mode register) at address 000007FDH. 7. Read the reset vector from address 000FFFFCH. 8. Write the reset vector to the program counter (PC). 9. The program starts execution from the address loaded in the program counter (PC). ■ Operation Initialization Reset (RST) Clear Sequence If an operation initialization reset (RST) request is cleared, the following operations are performed one step at a time for the device. 1. Clear the operation initialization reset (RST) and enter the normal operating state. 2. Read the reset vector from address 000FFFFCH. 3. Write the reset vector to the program counter (PC). 4. The program starts execution from the address loaded in the program counter (PC). 92 CHAPTER 3 CPU AND CONTROL UNITS ■ Hardware Standby Clear Sequence (MB91307B) If a hardware standby request or a low-voltage detection standby request is cleared, the following operations are performed one step at a time for the device. 1. In the settings initialization reset (INIT) state, start internal clock operation and clear the pin high-impedance processing. 2. Clear the settings initialization reset (INIT) and enter the oscillation stabilization wait state. 3. For the oscillation stabilization wait time (set with Bits 3 and 2 [OS1 and OS0 bits] in STCR), maintain the operation initialization reset (RST) state and stop the internal clock. 4. In the operation initialization reset (RST) state, start internal clock operation. 5. Clear the operation initialization reset (RST) and enter the normal operating state. 6. Read the mode vector from address 000FFFF8H. 7. Write the mode vector to the MODR (mode register) at address 000007FDH. 8. Read the reset vector from address 000FFFFCH. 9. Write the reset vector to the program counter (PC). 10.The program starts execution from the address loaded in the program counter (PC). 93 CHAPTER 3 CPU AND CONTROL UNITS 3.11.4 Oscillation Stabilization Wait Time If a device returns from the state in which the original oscillation was or may have been stopped, the device automatically enters the oscillation stabilization wait state. This function prevents the use of oscillator output after starting before oscillation has stabilized. For the oscillation stabilization wait time, neither an internal nor an external clock is supplied; only the built-in time base counter runs until the stabilization wait time set in the standby control register (STCR) has elapsed. This section describes the oscillation stabilization wait operation. ■ Sources of an Oscillation Stabilization Wait The following lists sources of an oscillation stabilization wait. ❍ Clearing of a settings initialization reset (INIT) The device enters the oscillation stabilization wait state if a settings initialization reset (INIT) is cleared for a variety of reasons. When the oscillation stabilization wait time has elapsed, the device enters the operation initialization reset (RST) state. ❍ Returning from stop mode The device enters the oscillation stabilization wait state immediately after stop mode is cleared. However, if it is cleared by a settings initialization reset (INIT) request, the device enters the settings initialization reset (INIT) state. Then, after the settings initialization reset (INIT) is cleared, the device enters the oscillation stabilization wait state. When the oscillation stabilization wait time has elapsed, the device enters the state corresponding to the source that cleared stop mode: • Return due to input of a valid external interrupt request (including NMI): The device enters the normal operating state. • Return due to a settings initialization reset (INIT) request: The device enters the operation initialization reset (RST) state. • Return due to an operation initialization reset (RST) request: The device enters the operation initialization reset (RST) state. ❍ Returning from an abnormal state when PLL is selected If, while the device is operating with PLL as the source clock, an abnormal condition* occurs in PLL control, the device automatically enters an oscillation stabilization wait to assure the PLL lock time. When the oscillation stabilization wait time has elapsed, the device enters the normal operating state. * : The multiply-by rate is changed while PLL is working, or an incorrect bit such as a bit equivalent to PLL operation enable bit is generated. 94 CHAPTER 3 CPU AND CONTROL UNITS ■ Selecting an Oscillation Stabilization Wait Time The oscillation stabilization wait time is measured with the built-in time base counter. If a source for an oscillation stabilization wait occurs and the device enters the oscillation stabilization wait state, the built-in time base counter is initialized and then it starts to measure the oscillation stabilization wait time. Using Bits 3 and 2 (OS1 and OS2 bits) of the standby control register (STCR), select and set one of the four types of oscillation stabilization wait time. Once selected, a setting is initialized only if a settings initialization reset (INIT) is generated due to the external INIT pin. The oscillation stabilization wait time that has been set before a reset is maintained if a settings initialization reset (INIT) is generated or an operation initialization reset (RST) is generated due to a watchdog reset or hardware standby condition. The four types of oscillation stabilization wait time settings are designed for the following four types of use: • OS1, OS0=00: No oscillation stabilization wait time (if neither PLL nor the oscillator should stop in stop mode) • OS1, OS0=01: PLL lock wait time (if an external clock will be input or the oscillator should not stop in stop mode) • OS1, OS0=10: Oscillation stabilization wait time (intermediate) (if an oscillator that stabilizes quickly, such as a ceramic vibrator, is used) • OS1, OS0=10: Oscillation stabilization wait time (long) (if an ordinary quartz oscillator will be used) Immediately after power-on, be sure to apply the settings initialization reset (INIT) at the INIT pin. To assure the oscillation stabilization wait time of the oscillation circuit immediately after poweron, maintain "L" level input to the INIT pin for the stabilization wait time required by the oscillation circuit. (INIT generated due to the INIT pin initializes the oscillation stabilization wait time setting to the minimum value.) If a hardware standby request occurs immediately after power-on, a settings initialization reset (INIT) generated due to the INIT pin has precedence. If later the setting initialization rest (INIT) generated due to the INIT pin is cleared and the hardware standby state is entered, the oscillation stabilization wait time setting is initialized to the maximum value. Thus, the oscillation stabilization wait time is the maximum value after the hardware standby request has been cleared. 95 CHAPTER 3 CPU AND CONTROL UNITS 3.11.5 Reset Operation Modes Two modes for an operation initialization reset (RST) are provided: normal (asynchronous) reset mode and synchronous reset mode. The operation initialization reset mode is selected with Bit 7 (SYNCR bit) of the time base counter control register (TBCR). This mode setting is initialized only by a settings initialization reset (INIT). A settings initialization reset always results in an asynchronous reset. This section describes the operation of these modes. ■ Normal Reset Operation Normal reset operation refers to entering the operation initialization reset (RST) state or hardware standby state immediately after an operation initialization reset (RST) request or a hardware standby request occurs. If, in this mode, a reset (RST) request or a hardware standby request is accepted, the device immediately enters the reset (RST) state or the hardware standby state regardless of the operating state of the internal bus. In this mode, the result of bus access performed prior to each status transition is not guaranteed. However, these requests can certainly be accepted. If Bit 7 (SYNCR bit) of the time base counter control register (TBCR) is set to "0", normal reset mode is selected. The initial value after a settings initialization reset (INIT) is normal reset mode. ■ Synchronous Reset Operation Synchronous reset operation refers to entering the operation initialization reset (RST) state or the hardware standby state after all bus access has stopped when an operation initialization reset (RST) request or a hardware standby request occurs. If, in this mode, a reset (RST) request or a hardware standby request is accepted, the device does not enter the reset (RST) state or the hardware standby state while internal bus access is in progress. If the above request is accepted, a sleep request is issued to the internal buses. If all the buses stop and enter the sleep state, the device enters the operation initialization reset (RST) state or the hardware standby state. In this mode, the result of all bus accesses is guaranteed because all bus access is stopped prior to each status transition. If bus access does not stop for some reason, no requests can be accepted while the bus access is in progress. Even in this case, the settings initialization reset (INIT) is immediately valid. Bus access may not stop in the following cases: 96 • A bus release request (BRQ) continues to be input to the external extended bus interface, bus release acknowledge (BGRNT) is valid, and a new bus access request arrives from an internal bus. • A ready request (RDY) continues to be input to the external extended bus interface and bus wait is valid. In the following cases, the device eventually enters another state but only after a long time: CHAPTER 3 CPU AND CONTROL UNITS Reference: The DMA controller, which stops transfer when a request is accepted, does not delay transition to another state. If Bit 7 (SYNCR bit) of the time base counter control register (TBCR) is set to "1", synchronous reset mode is selected. The initial value after a settings initialization reset (INIT) is normal reset mode. 97 CHAPTER 3 CPU AND CONTROL UNITS 3.12 Clock Generation Control This section describes clock generation and control. ■ Clock Generation Control The internal operating clock of the MB91307 series is generated as follows: • Selection of a source clock: Select a clock supply source. • Generation of a base clock: Divide the source clock by two or perform PLL oscillation to generate a base clock. • Generation of an internal clock:Divide the base clock and generate four types of operating clocks, which are supplied to each section. ■ Source Clock ❍ Self-induced oscillation mode (X0/X1 pin input) In this mode, an oscillator is connected to external oscillation pins and the original oscillation generated by the built-in oscillation circuit is used as the source clock. The source for supply of all clocks, including the external bus clock, is the MB91307 series itself. The main clock, generated from the X0/X1 pins, is intended to be used as a high-speed clock. The main clock is multiplied by the built-in main PLL, each of which can be independently controlled. Generate an internal base clock by selecting one of the following source clocks: • Main clock divided by "2" • Main clock multiplied in the main PLL Select a source clock by setting the clock source control register (CLKR). 98 CHAPTER 3 CPU AND CONTROL UNITS 3.12.1 PLL Controls Operation (oscillation) enable and disable and the multiply-by rate setting can be independently controlled for each of the PLL oscillation circuits corresponding to the main source clock. Each control is set in the clock source control register (CLKR). This section describes each control. ■ PLL Operation Enable To enable or disable the main PLL oscillation, set Bit 10 (PLL1EN bit) of the clock source control register (CLKR). ❍ PLL operation control in self-induced oscillation mode In self-induced oscillation mode, either the operation enable/disable bit or the multiply-by rate setting bit is initialized to "0" after a settings initialization reset (INIT), causing the PLL oscillation to stop. While it is stopped, PLL output cannot be selected as the source clock. When the program operation starts, set the multiply-by rate of the PLL to be used as the clock source, enable it, and switch the source clock after the PLL lock wait time elapses. For the PLL lock wait time, use of a time base timer interrupt is recommended. While PLL output is selected as the source clock, the PLL cannot be stopped (writing to the register is disabled). To stop a PLL upon transition to stop mode, reselect as the source clock the main clock divided by two before stopping the PLL. If Bit 0 (OSCD1 bit) or Bit 1 (OSCD2 bit) of the standby control register (STCR) is set to stop oscillation in stop mode, the corresponding PLL automatically stops when the device enters stop mode. As a result, you do not need to set operation stop. When the device returns from stop mode later, the PLL automatically restarts the oscillation operation. If oscillation is not set to stop in stop mode, the PLL does not automatically stop. In this case, set operation stop before transition to stop mode as required. ❍ PLL operation control in external clock mode In external clock mode, the main PLL continues the oscillation operation except in the settings initialization reset (INIT) state or in stop mode regardless of the settings of both the bits. If Bit 0 (OSCD1 bit) of the standby control register (STCR) is set to stop the oscillation in stop mode, the main PLL automatically stops when the device enters stop mode. When the device returns from stop mode later, the PLL automatically restarts the oscillation operation. If oscillation is not set to stop in stop mode, the PLL does not stop. Notes: • To perform PLL operation on this model, the frequencies of self-excited oscillation and external clock input must be set to 12.5 MHz to 16.5 MHz. • If the PLL clock mode is selected, the microcontroller attempt to be working with the selfoscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. 99 CHAPTER 3 CPU AND CONTROL UNITS ■ PLL Multiply-by Rate Set the multiply-by rate of the main PLL in Bits 14 to 12 (PLL1S2, PLL1S1, and PLL1S0 bits) of the clock source control register (CLKR). After a settings initialization reset (INIT), all bits are initialized to 0. ❍ PLL multiply-by rate setting in self-induced oscillation mode To change the PLL multiply-by rate setting from the initial value in self-induced oscillation mode, do so before or as soon as the PLL is enabled after the program has started execution. After changing the multiply-by rate, switch the source clock after the lock wait time elapses. For the PLL lock wait time, use of a time base timer interrupt is recommended. To change the PLL multiply-by rate setting during operation, switch the source clock to a clock other than the PLL in question before making the change. After changing the multiply-by rate, switch the source clock after the lock wait time has elapsed, as described above. You can also change the PLL multiply-by rate setting while using a PLL. In this case, however, the program stops running after the device automatically enters the oscillation stabilization wait state after the multiply-by rate setting is rewritten and does not resume execution until the specified oscillation stabilization wait time has elapsed. The program does not stop running if the clock source is switched to a clock other than a PLL. ❍ PLL multiply-by rate setting in external clock mode If you change the PLL multiply-by rate setting from the initial value in external clock mode, after the program starts execution, the PLL is already enabled and used as the source clock. Thus, the program stops running after the device automatically enters the oscillation stabilization wait state after the multiply-by rate setting is rewritten and does not resume operation until the specified oscillation stabilization wait time elapses. Thus, be sure to set the oscillation stabilization wait time to an appropriate value (larger than the PLL lock wait time defined in the specification) before changing the multiply-by rate setting. In this mode, the oscillation stabilization wait time setting has the initial value "01" (PLL lock wait time supported). 100 CHAPTER 3 CPU AND CONTROL UNITS 3.12.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time If a clock selected as the source clock is not already stabilized, an oscillation stabilization wait time is required (See Section "3.11.4 Oscillation Stabilization Wait Time"). For a PLL, a lock wait time is required after operation starts until the output stabilizes to the specified frequency. This section describes the wait time used in various situations. ■ Self-induced Oscillation Mode This section describes various wait times used in self-induced oscillation mode. ❍ Wait time after power-on After power-on, an oscillation stabilization wait time for the main clock oscillation circuit is required. Since the oscillation stabilization wait time setting is initialized to the minimum value due to INIT pin input (settings initialization reset pin), assure the oscillation stabilization wait time by using the time during which the "L" level is sent to the INIT pin input. In this state, since no PLL is enabled, no lock wait time needs to be considered. ❍ Wait time after setting initialization If a settings initialization reset (INIT) is cleared, the device enters the oscillation stabilization wait state. In this case, the specified oscillation stabilization wait is internally generated. In the first oscillation stabilization wait state after input from the INIT pin, the setting time is initialized to the minimum value, soon ending this state, and the device enters the operation initialization reset (RST) state. However, if the "L" level is sent to the HST pin input (hardware standby pin) in this state, the device enters the hardware standby state and the oscillation circuit is stopped. Thus, the oscillation stabilization wait time is initialized to the maximum value for reasons of safety. If, after a program starts running, a settings initialization reset (INIT) is generated for a reason other than INIT pin input and is then cleared, the oscillation stabilization wait time specified in the program is internally generated. In these states, since no PLL is enabled, no lock wait time needs to be considered. ❍ Wait time after enabling a PLL If you enable a stopped PLL after a program starts execution, use the PLL output only after the lock wait time elapses. If the PLL is not selected as the source clock, the program can run even during the lock wait time. For the PLL lock wait time, use of a time base timer interrupt is recommended. 101 CHAPTER 3 CPU AND CONTROL UNITS ❍ Wait time after changing the PLL multiply-by rate If you change the multiply-by rate setting of a running PLL after a program starts execution, use the PLL output only after lock wait time elapses. If the PLL is not selected as the source clock, the program can run even during the lock wait time. For the PLL lock wait time, use of a time base timer interrupt is recommended. ❍ Wait time after returning from stop mode If, after a program starts execution, the device enters stop mode and then stop mode is cleared, the oscillation stabilization wait time specified in the program is internally generated. If the clock oscillation circuit selected as the source clock is set to stop in stop mode, the oscillation stabilization wait time of the oscillation circuit or the lock wait time of the PLL in use, whichever is longer, is required. Set the oscillation stabilization wait time before entering stop mode. If the clock oscillation circuit selected as the source clock is not set to stop in stop mode, the PLL does not automatically stop. No oscillation stabilization wait time is required unless the PLL has stopped. Setting the oscillation stabilization wait time to the minimum value before stop mode is entered is recommended. However, if a hardware standby request is entered in stop mode, the oscillation circuit stops and an oscillation stabilization wait time will required after return from stop mode. If the wait time is set to the minimum value, the oscillation stabilization wait time cannot be assured and operation after return from stop mode is not guaranteed. For cases such as this, set the oscillation stabilization wait time for the oscillation circuit. ■ External Clock Mode This section describes various wait times in external clock mode. ❍ Wait time after power-on After power-on, an oscillation stabilization wait time for the main clock oscillation circuit is required. Since the oscillation stabilization wait time setting is initialized to the setting supporting the PLL lock wait time due to INIT pin input (settings initialization reset pin), assure the oscillation stabilization wait time for the oscillation circuit by using the time during which the Low level is sent to the INIT pin input. In this state, since no PLL is enabled, no lock wait time needs to be considered. In this mode, the main PLL is enabled if a settings initialization reset (INIT) is cleared. However, the PLL must not be enabled for 1 µs after power-on because of the PLL circuit initialization. Thus, continue to input the "L" Level to the INIT pin input for 1 µs after power-on even though no oscillation stabilization wait time is required for the oscillation circuit. ❍ Wait time after setting initialization and after enabling a PLL If a settings initialization reset (INIT) is cleared, the device enters the oscillation stabilization wait state. In this case, the specified oscillation stabilization wait is internally generated. In the first oscillation stabilization wait state after input from the INIT pin, the setting time is initialized to the setting supporting the PLL lock wait time, causing this state to end after the PLL lock wait time elapses. The device then enters the operation initialization reset (RST) state. However, if the "L" level is sent to the HST pin input (hardware standby pin) in this state, the device enters the hardware standby state and the oscillation circuit is stopped. Thus, the oscillation stabilization wait time is initialized to the maximum value for reasons of safety. If, after a program starts running, a settings initialization reset (INIT) is generated for some reason other than INIT pin input and is then cleared, the oscillation stabilization wait time specified in the program is internally generated. 102 CHAPTER 3 CPU AND CONTROL UNITS ❍ Wait time after changing the PLL multiply-by rate If you change the multiply-by rate setting of a running PLL after a program starts execution, the program temporarily stops running after the setting is changed, the device enters the oscillation stabilization wait (lock wait) state, and the program operation resumes after the specified oscillation stabilization wait (lock wait) time has elapsed. This operation initializes the time base counter. ❍ Wait time after returning from stop mode If, after a program starts execution, the device enters stop mode and then stop mode is cleared, the oscillation stabilization wait time specified in the program is internally generated. If the main clock oscillation circuit is set to stop in stop mode, the oscillation stabilization wait time of the oscillation circuit or the lock wait time of the main PLL, whichever is longer, is required. Set the oscillation stabilization wait time before entering stop mode. If the main clock oscillation circuit is not set to stop in stop mode, the PLL does not automatically stop. No oscillation stabilization wait time is required unless the PLL has stopped. Setting the oscillation stabilization wait time to the minimum value before stop mode is entered is recommended. However, if a hardware standby request is entered in stop mode, the oscillation circuit stops and an oscillation stabilization wait time will required after return from stop mode. If the wait time is set to the minimum value, the oscillation stabilization wait time cannot be assured and operation after return from stop mode is not guaranteed. For cases such as these, set the oscillation stabilization wait time for the oscillation circuit. 103 CHAPTER 3 CPU AND CONTROL UNITS 3.12.3 Clock Distribution An operating clock for each function is generated based on the base clock generated from the source clock. A total of four internal operating clocks are provided. A divideby rate can be set independently for each of them. This section describes these internal operating clocks. ■ CPU Clock (CLKB) This clock is used for the CPU, internal memory, and internal buses. It is used by the following circuits: • CPU • Instruction cache • Built-in RAM and ROM • Bit search module • I-bus, D-bus, X-bus, and F-bus • DMA controller • DSU (development tool interface circuit) Since 66 MHz is the upper-limit frequency for operation, do not set a combination of multiply-by rate and divide-by rate that results in a frequency exceeding this limit. ■ Peripheral Clock (CLKP) This clock is used for peripheral circuits and peripheral buses. It is used by the following circuits: • Peripheral bus • Clock controller (only for the bus interface) • Interrupt controller • Peripheral I/O ports • I/O port bus • External interrupt input • UART • 16-bit timer • A/D converter • I2C interface Since 33 MHz is the upper-limit frequency for operation, do not set a combination of multiply-by rate and divide-by rate that results in a frequency exceeding this limit. 104 CHAPTER 3 CPU AND CONTROL UNITS ■ External Bus Clock (CLKT) This clock is used for external extended bus interfaces. It is used by the following circuits: • External extended bus interface • External CLK output Since 33 MHz is the upper-limit frequency for operation, do not set a combination of multiply-by rate and divide-by rate that results in a frequency exceeding this limit. ■ SDRAM Clock (CLKS) The MB91307 series does not support an SDRAM interface. This clock is used for an SDRAM interface. It is used by the following circuits: • SDRAM interface • SDCLK output Since 66 MHz is the upper-limit frequency for operation, do not set a combination of multiply-by rate and divide-by rate that results in a frequency exceeding this limit. 105 CHAPTER 3 CPU AND CONTROL UNITS 3.12.4 Clock Division A divide-by rate can be set independently for each of the internal operating clocks. With this function, an optimal operating frequency can be set for each circuit. ■ Clock Division Set a divide-by rate in Basic Clock Division Setting Register 0 (DIVR0) and Basic Clock Division Setting Register 1 (DIVR1). Each of these registers has four setting bits and (Register setting value + 1) is the divide-by rate of the clock in relation to the base clock. Even if the divide-by rate setting is an odd number, the duty is always 50. If the setting value is changed, the new divide-by rate becomes valid at the leading edge of the next clock after the setting is made. The divide-by rate setting is not initialized if an operation initialization reset (RST) occurs and the setting made before the reset occurs is retained. The divide-by rate setting is initialized only if a settings initialization reset (INIT) occurs. In the initial state, all clocks other than the peripheral clock (CLKP) have a divide-by rate of 1. Thus, be sure to set the divide-by rate before changing the source clock to a faster clock. An upper-limit frequency for the operation is set for each clock. If you set a combination of source clock, PLL multiply-by rate setting, and divide-by rate setting that results in a frequency exceeding this upper-limit frequency, operation is not guaranteed. Be extra careful of the order in which you change settings to select the source clock and to configure the associated setting items. 106 CHAPTER 3 CPU AND CONTROL UNITS 3.12.5 Block Diagram of Clock Generation Controller This section provides a block diagram of the clock generation controller. ■ Block Diagram Figure 3.12-1 shows a block diagram of the clock generation controller. Figure 3.12-1 Block Diagram of Clock Generation Controller [Clock generator] DIVR0,1 registers Selector Peripheral clock division Selector External bus clock division Selector SDRAM clock division CPU clock Stop control R-bus CPU clock division Selector Peripheral clock External bus clock SDRAM clock X0 X1 Oscillation circuit Internal interrupt PLL 1/2 Selector CLKR register [Stop and sleep controller] Internal reset Stop status STCR register Status transition control circuit HST pin Sleep status Reset occurrence F/F Reset occurrence F/F Internal reset (RST) Internal reset (INIT) [Reset source circuit] RST pin INIT pin RSRR register [Watchdog controller] WPR register Watchdog F/F Time base counter CTBR register TBCR register Interrupt enable Counter clock Selector Overflow detection F/F Time base timer interrupt request 107 CHAPTER 3 CPU AND CONTROL UNITS 3.12.6 Register of Clock Generation Controller This section describes the functions of registers to be used in the clock generation controller. ■ Reset Source Register/Watchdog Timer Control Register (RSRR) Figure 3.12-2 shows the configuration of the reset source register/watchdog timer control register (RSRR). Figure 3.12-2 Reset Source Register/Watchdog Timer Control Register (RSRR) bit Address : 00000480H Initial value (INIT pin) Initial value (INIT) Initial value (RST) 15 INIT R 1 * × 14 13 12 11 10 HSTB WDOG ERST SRST LINIT R R R R R 0 0 0 0 0 * * × × * × × * * × 9 WT1 R/W 0 0 0 8 WT0 R/W 0 0 0 *: Varies according to the source. ×: Not initialized This register holds the source of the last reset that occurred as well as the interval setting and startup control for the watchdog timer. If the timer is read, the reset source that has been held is cleared after it is read. If more than one reset is generated before this register is read, reset source flags are accumulated and the multiple flags are set. Writing to this register starts the watchdog timer. Thereafter, the watchdog timer continues running until a reset (RST) occurs. The following describes the functions of the reset source register/watchdog timer control register (RSRR) bits. [Bit 15] INIT (INITialize reset occurred) This bit indicates whether a reset (INIT) occurred due to INIT pin input. 0 No INIT occurred due to INIT pin input. 1 INIT occurred due to INIT pin input. • This bit is initialized to "0" after it is read. • This bit is readable; writing to the bit has no effect on the bit value. [Bit 14] HSTB (Hardware STandBy reset occurred) This bit indicates whether a reset (INIT) occurred due to HST pin input. 108 0 No INIT occurred due to HST pin input. 1 INIT occurred due to HST pin input. • This bit is initialized to "0" after a reset (INIT) due to INIT pin input or just after it is read. • This bit is readable; writing to the bit has no effect on the bit value. CHAPTER 3 CPU AND CONTROL UNITS [Bit 13] WDOG (WatchDOG reset occurred) This bit indicates whether a reset (INIT) occurred due to the watchdog timer. 0 No INIT occurred due to the watchdog timer. 1 INIT occurred due to watchdog timer. • This bit is initialized to "0" after a reset (INIT) due to INIT pin input or just after it is read. • This bit is readable; writing to the bit has no effect on the bit value. [Bit 12] ERST (External ReSeT occurred) This bit indicates whether a reset (RST) occurred due to RST pin input. 0 No RST occurred due to RST pin input. 1 RST occurred due to RST pin input. • This bit is initialized to "0" after a reset (INIT) due to INIT pin input or just after it is read. • This bit is readable; writing to the bit has no effect on the bit value. Note: The MB91307 series has no RST pin. [Bit 11] SRST (Software ReSeT occurred) This bit indicates whether a reset (RST) occurred due to writing to the SRST bit of the STCR register (a software reset). 0 No RST occurred due to a software reset. 1 RST occurred due to a software reset. • This bit is initialized to "0" after a reset (INIT) due to INIT pin input or just after it is read. • This bit is readable; writing to the bit has no effect on the bit value. [Bit 10] LINIT (Low voltage detect INITialize reset occurred) This bit indicates whether a reset (INIT) occurred due to LINIT pin input occurred. 0 No INIT occurred due to LINIT pin input. 1 INIT occurred due to LINIT pin input. • This bit is initialized to "0" after a reset (INIT) due to LINIT pin input or just after it is read. • This bit is readable; writing to the bit has no effect on the bit value. Note: The MB91307 series has no LINIT pin. It is not supported by the MB91307 series. 109 CHAPTER 3 CPU AND CONTROL UNITS [Bits 9, 8] WT1, WT0 (Watchdog interval Time select) This bit sets the interval of the watchdog timer. The values written to these bits determine the interval of the watchdog timer, which can be selected from the four types shown in Table 3.12-1. Table 3.12-1 Interval Setting of Watchdog Timer WT1 WT0 Minimum required interval for writing to the WPR to suppress a watchdog reset Time from writing the last 5AH to the WPR until a watchdog reset occurs 0 0 φ × 216 (initial value) φ × 216 - φ × 217 0 1 φ × 218 φ × 218 - φ × 219 1 0 φ × 220 φ × 220 - φ × 221 1 1 φ × 222 φ × 222 - φ × 223 φ: Frequency of the system base clock • These bits are initialized to "00" after a reset (RST). • These bits are readable, but are writable only once after a reset (RST). Any further writing is disabled. ■ Standby Control Register (STCR) Figure 3.12-3 shows the configuration of the standby control register (STCR). Figure 3.12-3 Configuration of Standby Control Register (STCR) Bits bit 7 6 5 Address : 00000481H STOP SLEEP HIZ R/W R/W R/W Initial value (INIT pin) 0 0 1 Initial value (HST)* 0 0 1 Initial value (INIT) 0 0 1 Initial value (RST) 0 0 × 4 SRST R/W 1 1 1 1 3 OS1 R/W 0 1 × × 2 1 0 OS0 OSCD2 OSCD1 R/W R/W R/W 0 1 1 1 1 1 × 1 1 × × × * : Occurs only at the same time as initialization due to the INIT pin. Otherwise, the same as INIT. The standby control register (STCR) controls the operating mode of the device. This register controls the transition to the two standby modes of stop and sleep, pins when in stop mode, and the stopping of oscillation stop. It also sets the oscillation stabilization wait time and issues software resets. The following describes the functions of the standby control register (STCR) bits. 110 CHAPTER 3 CPU AND CONTROL UNITS [Bit 7] STOP (STOP mode) This bit specifies entry into stop mode. If "1" is written to both Bit 6 (SLEEP bit) and this bit, this bit (STOP) has precedence and the device enters stop mode 0 Stop mode not entered (initial value) 1 Stop mode entered • This bit is initialized to "0" by a reset (RST) and by a stop return source. • This bit is readable and writable. [Bit 6] SLEEP (SLEEP mode) This bit specifies entry into sleep mode. If "1" is written to both Bit 7 (STOP bit) and this bit, Bit 7 (STOP) has precedence and the device enters stop mode. 0 Sleep mode not entered (initial value) 1 Sleep mode entered • This bit is initialized to "0" by a reset (RST) and by a sleep return source. • This bit is readable and writable. [Bit 5] HIZ (HIZ mode) This bit controls the pin state in stop mode. 0 The pin state before stop mode entered is maintained. 1 Pin output is set to high-impedance state in stop mode (initial value). • This bit is initialized to "1" by a reset (INIT). • This bit is readable and writable. [Bit 4] SRST (Software ReSeT) This bit specifies issuing of a software reset (RST). 0 A software reset is issued. 1 A software reset is not issued (initial value). • This bit is initialized to "1" by a reset (RST). • This bit is readable and writable. The read value is always "1". 111 CHAPTER 3 CPU AND CONTROL UNITS [Bits 3, 2] OS1, OS0 (Oscillation Stabilization time select) These bits set the oscillation stabilization wait time used after a reset (INIT), return from stop mode, etc. The values written to these bits determine the interval of the watchdog timer, which can be selected from the four types shown in Table 3.12-2. Table 3.12-2 Oscillation Stabilization Wait Settings CS1 CS0 Oscillation stabilization wait time If the source oscillation is 16.5 MHz 0 0 φ × 21 (initial value) 0.242 [µs] 0 1 φ × 211 248 [µs] 1 0 φ × 216 7.94 [ms] 1 1 φ × 222 508.4 [ms] φ: Frequency of the system base clock; in this case, twice the cycle of the source oscillation input • These bits are initialized to "00" by a reset (INIT) generated due to INIT pin input. If both resets (INIT) generated due to INIT and HST pin input are valid, these bits are initialized to "11". • These bits are readable and writable. [Bit 1] OSCD2 (OSCillation Disable mode for XIN2) This bit controls stopping of the sub-oscillation input (XIN2) in stop mode. 0 Not stopping the sub-oscillation in stop mode 1 Stopping the sub-oscillation in stop mode (initial value) • This bit is initialized to "1" by a reset (INIT). • This bit is readable and writable. Note: This function is not supported by the MB91307 series. [Bit 0] OSCD1 (OSCillation Disable mode for XIN1) This bit controls stopping of main oscillation input (XIN1) in stop mode. 112 0 Main oscillation does not stop in stop mode. 1 Main oscillation stops in stop mode (initial value). • This bit is initialized to "1" by a reset (INIT). • This bit is readable and writable. CHAPTER 3 CPU AND CONTROL UNITS Note: • Use the following sequences after using the synchronous standby mode (TBCR:Set by time base counter control register bit8 SYNCS bit) when putting in the standby mode. (LDI #value_of_standby, R0) (LDI #_STCR, R12) STB R0, @12) // Writing in standby control register (STCR) LDUB @R12, R0 // STCR lead for synchronous standby LDUB @R12, R0 // Dummy re-lead of STCR NOP // five NOPs for timing adjustment NOP NOP NOP NOP • Do not do the following when the monitor debugger is used. - Set the break point to the above-mentioned instruction row. - Execute the step for the above-mentioned instruction row. ■ Time Base Counter Control Register (TBCR) Figure 3.12-4 shows the configuration of the time base counter control register (TBCR) bits. Figure 3.12-4 Configuration of Time Base Counter Control Register (TBCR) Bits bit 15 Address : 00000482H TBIF Initial value (INIT) 0 Initial value (RST) 0 R/W 14 TBIE 0 0 R/W 13 12 11 TBC2 TBC1 TBC0 × × × × × × R/W R/W R/W 10 9 8 SYNCR SYNCS × 0 0 × × × R/W R/W R/W The time base counter control register (TBCR) controls time base timer interrupts, among other things. This register enables time base timer interrupts, selects an interrupt interval time, and sets an optional function for the reset operation. The following describes the functions of the time base counter control register (TBCR) bits. [Bit 15] TBIF (TimeBasetimer Interrupt Flag) This bit is the time base timer interrupt flag. It indicates that the interval time (TBC2 to TBC0 bits, which are Bits 13 to 11) specified by the time base counter has elapsed. A time base timer interrupt request is generated if this bit is set to "1" when interrupts are enabled by Bit 14 (TBIE bit, TBIE=1). Clear source An instruction writes 0. Set source The specified interval time elapses (the trailing edge of the time base counter is detected). • This bit is initialized to "0" by a reset (RST). • This bit is readable and writable, although only "0" can be written to it. Writing 1 does not change the bit value. The value read by a read modify write instruction is always 1. [Bit 14] TBIE (TimeBasetimer Interrupt Enable) This bit is the time base timer interrupt request output enable bit. 113 CHAPTER 3 CPU AND CONTROL UNITS It controls output of an interrupt request when the interval time of the time base counter has elapsed. A time base timer interrupt request is generated if the TBIF bit is set to "1" when this bit is set to "1". 0 Time base timer interrupt request output disabled (initial value) 1 Time base timer interrupt request output enabled • This bit is initialized to "1" by a reset (RST). • This bit is readable and writable. [Bits 13 to 11] TBC2, TBC1, TBC0 (TimeBasetimer Counting time select) These bits set the interval time of the time base counter that is used for the time base timer. The values written to these bits determine the interval time, which can be selected from the eight types shown in Table 3.12-3. Table 3.12-3 Interval Settings TBC2 TBC1 TBC0 Timer interval time If the source oscillation is 16.5 MHz and PLL is multiplied by 4 0 0 0 φ × 211 31.0 [µs] 0 0 1 φ × 212 62.0 [µs] 0 1 0 φ × 213 124.1 [µs] 0 1 1 φ × 222 63.5 [ms] 1 0 0 φ × 223 127.1 [ms] 1 0 1 φ × 224 254.2 [ms] 1 1 0 φ × 225 508.3 [ms] 1 1 1 φ × 226 1016 [ms] φ: Frequency of the system base clock • The initial value is undefined. Be sure to set a value before enabling an interrupt. • These bits are readable and writable. [Bit 10] (reserved bit) This bit is reserved. The read value is undefined. Writing to this bit has no effect on operation. [Bit 9] SYNCR (SYNChronous Reset enable) This bit is the synchronous reset enable bit. It is used to select one of the following operations, which is to be used if an operation initialization reset (RST) request or a hardware standby request occurs: (1) Immediately performing a reset (RST) or a normal reset operation followed by transition to hardware standby or (2) performing an operation initialization reset (RST) or a synchronous reset operation followed by transition to hardware standby after all bus access have stopped. 114 CHAPTER 3 CPU AND CONTROL UNITS 0 Normal reset operation (initial value) 1 Synchronous reset operation • This bit is initialized to "0" by a reset (INIT). • This bit is readable and writable. [Bit 8] SYNCS (SYNChronous Standby enable) This bit is the synchronous standby enable bit. It is used to select one of the following operations, which is to be used if an standby request (either sleep or stop mode request) occurs: (1) Performing a normal standby operation only by writing to the control bit in the STCR register or (2) performing a synchronous standby operation by reading the STCR register after writing to the control bit in the STCR register. 0 Normal standby operation (initial value) 1 Synchronous standby operation • This bit is initialized to "0" by a reset (INIT). • This bit is readable and writable. Note: Please set the synchronous standby operation by setting "1" to this bit at changing to the standby mode. ■ Time Base Counter Clear Register (CTBR) Figure 3.12-5 shows the configuration of the time base counter clear register (CTBR) bits. Figure 3.12-5 Configuration of Time Base Counter Clear Register (CTBR) Bits bit Address : 00000483H Initial value (INIT) Initial value (RST) 7 D7 × × W 6 D6 × × W 5 D5 × × W 4 D4 × × W 3 D3 × × W 2 D2 × × W 1 D1 × × W 0 D0 × × W The time base counter clear register (CTBR) initializes the time base counter. If {A5H} and {5AH} are written successively to this register, all the bits in the time base counter are cleared to 0 as soon as {5AH} is written. There is no time limit between writing of {A5H} and {5AH}. However, if data other than {5AH} is written after {A5H} is written, {A5H} must be written again before {5AH} is written. Otherwise, a clear operation will not occur. The value read from this register is undefined. Note: If the time base counter is cleared using this register, the oscillation stabilization wait interval, watchdog timer interval, and time base timer interval temporarily vary. 115 CHAPTER 3 CPU AND CONTROL UNITS ■ Clock Source Control Register (CLKR) Figure 3.12-6 shows the configuration of the clock source control register (CLKR) bits. Figure 3.12-6 Configuration of Clock Source Control Register (CLKR) Bits bit 15 14 13 12 11 10 9 8 Address : 00000484H PLL2S0 PLL1S2 PLL1S1 PLL1S0 PLL2EN PLL1EN CLKS1 CLKS0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value (INIT) 0 0 0 0 0 0 0 0 Initial value (RST) × × × × × × × × The clock source control register (CLKR) is used to select the clock source that will be used as the base clock of the system and controls the PLL. Use this register to select one of three clock sources (the MB91307 series supports only two of these). This register also enables the main PLL and each of the sub-PLLs and selects the multiply-by rate for them. The following describes the functions of the clock source control register (CLKR) bits. [Bit 15] PLL2S0 (PLL2 ratio Select 0) This bit is the multiply-by selection bit for the sub-PLL. Select one of the two multiply-by rates. Rewriting of this bit is disabled while the sub-PLL is selected as the clock source. 0 Multiply-by rate setting 1 (initial value) 1 Multiply-by rate setting 1 • This bit is initialized to "0" by a reset (INIT). • This bit is readable and writable. Note: This function is not supported by the MB91307 series. [Bits 14 to 12] PLL1S2, PLL1S1, PLL1S0 (PLL1 ratio Select 2 to 0) These bits are the multiply-by selection bits for the main PLL. Select one of the eight multiply-by rates (the MB91307 series supports only four of these) shown in Table 3.12-4. Rewriting of these bits is disabled while the main PLL is selected as the clock source. 116 CHAPTER 3 CPU AND CONTROL UNITS Table 3.12-4 Main PLL Multiply-By Rate Settings PLL1S2 PLL1S1 PLL1S0 Main PLL multiply-by rate If the source oscillation is 16.5 MHz 0 0 0 × 1 (equal) φ=60.60[ns](16.5[MHz]) 0 0 1 × 2 (multiplied by 2) φ=30.30[ns](33.0[MHz]) 0 1 0 × 3 (multiplied by 3) φ=20.20[ns](49.5[MHz]) 0 1 1 × 4 (multiplied by 4) φ=15.15[ns](66.0[MHz]) 1 0 0 × 5 (multiplied by 5) * 1 0 1 × 6 (multiplied by 6) * 1 1 0 × 7 (multiplied by 7) * 1 1 1 × 8 (multiplied by 8) * φ: Frequency of the system base clock * : Not supported by the MB91307 series. • These bits are initialized to "000" by a reset (INIT). • These bits are readable and writable. Note: The upper-limit frequency for operation is 66 MHz. Do not make a setting exceeding this frequency. [Bit 11] PLL2EN (PLL2 ENable) This bit is the enable bit of the sub-PLL. Rewriting of this bit is disabled while the sub-PLL is selected as the clock source. Selection of the sub-PLL as the clock source is disabled while this bit is set to 0 (because of the setting of Bits 9 and 8, which are the CLKS1 and CLK0 bits). The sub-PLL stops in stop mode even when this bit is set to "1" as long as the STCR bit (OSCD2 bit) is set to "1". After the device returns from stop mode, the sub-PLL is enabled again. 0 Sub-PLL stopped (initial value) 1 Sub-PLL enabled • This bit is initialized to "0" by a reset (INIT). • This bit is readable and writable. Note: This function is not supported by the MB91307 series. 117 CHAPTER 3 CPU AND CONTROL UNITS [Bit 10] PLL1EN (PLL1 ENable) This bit is the enable bit of the main PLL. Rewriting of this bit is disabled while the main PLL is selected as the clock source. Selection of the main PLL as the clock source is disabled while this bit is set to 0 (because of the setting of Bits 9 and 8, which are the CLKS1 and CLK0 bits). The main PLL stops in stop mode even when this bit is set to "1" as long as the STCR bit (OSCD2 bit) is set to "1". After the device returns from stop mode, the main PLL is enabled again. 0 Main PLL stopped (initial value) 1 Main PLL enabled • This bit is initialized to "0" by a reset (INIT). • This bit is readable and writable. [Bits 9, 8] CLKS1, CLKS0 (CLocK source Select) These bits set the clock source that will be used by the MB91307 series. The values written to these bits determine the clock source, which can be selected from the three types shown in Table 3.12-5 (the MB91307 series supports only two of these). Table 3.12-5 Clock Source Settings CLKS1 CLKS0 Clock source setting 0 0 Source oscillation input from X0/X1 divided by 2 (initial value) 0 1 Source oscillation input from X0/X1 divided by 2 1 0 Main PLL 1 1 Sub-PLL* * : Not supported by the MB91307 series Table 3.12-6 shows the combinations of the CLKS1 and CLKS0 bits that cannot be changed and those that can. Table 3.12-6 Combinations of CLKS1 and CLKS0 Bits that Can and Cannot Be Changed Cannot be changed Can be changed "00" → "11" "00" → "01" or "10" "01" → "10" "01" → "11" or "00" "10" → "01" or "11" "10" → "00" "11" → "00" or "10" "11" → "01" The value of Bit 8 (CLKS0) cannot be changed while Bit 9 (CLKS1) is set to "1". To select the sub-PLL in the post-INIT state, first write "01" and then write "11". (The setting "11" is not supported by the MB91307 series.) 118 • These bits are initialized to "00" by a reset (INIT). • These bits are readable and writable. CHAPTER 3 CPU AND CONTROL UNITS ■ Watchdog Reset Postpone Register (WPR) Figure 3.12-7 shows the configuration of the watchdog reset postpone register (WPR) bits. Figure 3.12-7 Configuration of Watchdog Reset Postpone Register (WPR) Bits bit Address : 00000485H Initial value (INIT) Initial value (RST) 7 D7 W × × 6 D6 W × × 5 D5 W × × 4 D4 W × × 3 D3 W × × 2 D2 W × × 1 D1 W × × 0 D0 W × × The watchdog reset postpone register (WPR) postpones a watchdog reset. If {A5H} and {5AH} are written successively to this register, the detection FF for the watchdog timer is cleared immediately after {5AH} is written and the watchdog reset is postponed. There is no time limit between writing of {A5H} and {5AH}. However, if data other than {5AH} is written after {A5H} is written, {A5H} must be written again before {5AH} is written. Otherwise, a clear operation will not occur. Also, a watchdog reset is generated unless writing of these data items is completed within the time shown in Table 3.12-7. The setting varies as shown in Table 3.12-7 depending on the state of Bit 9 (WT1) and Bit 8 (WT0) of the RSRR register. Table 3.12-7 Settings for Generation of a Watchdog Reset WT1 WT0 Required minimum interval of writing to the WPR of the RSRR to suppress the generation of a watchdog reset Time elapsing between writing of the last 5AH to the WPR and the generation a watchdog reset 0 0 φ × 216 (initial value) φx 216-φ × 217 0 1 φ × 218 φx 218-φ × 219 1 0 φ × 220 φx 220-φ × 221 1 1 φ × 222 φx 222-φ × 223 Note: φ is the frequency of the system base clock. WT1 and WT0 are Bits 9 and 8 of the RSRR and are used to set the watchdog timer interval. A watchdog reset is not postponed when an external bus hold request (BRQ) has been accepted. To hold the external bus for a long time, enter sleep mode and then input a hold request (BRQ). The value read from this register is undefined. 119 CHAPTER 3 CPU AND CONTROL UNITS ■ Base Clock Division Setting Register 0 (DIVR0) Figure 3.12-8 shows the configuration of the Base Clock Division Setting Register 0 (DIVR0) bits. Figure 3.12-8 Configuration of Base Clock Division Setting Register 0 (DIVR0) Bits bit Address : 00000486H Initial value (INIT) Initial value (RST) 7 B3 R/W 0 × 6 B2 R/W 0 × 5 B1 R/W 0 × 4 B0 R/W 0 × 3 P3 R/W 0 × 2 P2 R/W 0 × 1 P1 R/W 1 × 0 P0 R/W 1 × Base Clock Division Setting Register 0 (DIVR0) controls the divide-by rate of an internal clock in relation to the base clock. This register sets the divide-by rates of the CPU clock, the clocks of an internal bus (CLKB) and a peripheral circuit, and the peripheral bus clock (CLKP). An upper-limit frequency for the operation is set for each clock. If you set a combination of source clock, PLL multiply-by rate setting, and divide-by rate setting that results in a frequency exceeding this upper-limit frequency, operation is not guaranteed. Be extra careful of the order in which you change settings to select the source clock and to configure the associated setting items. If the setting in this register is changed, the new divide-by rate takes effect for the clock rate following the one in which the setting was made. [Bits 7 to 4] B3, B2, B1, B0 (clkB divide select 3 to 0) These bits are the clock divide-by rate setting bits of the CPU clock (CLKB). Set the clock divide-by rate of the CPU, internal memory, and internal bus clock (CLKB). The values written to these bits determine the divide-by rate (clock frequency) of the CPU and internal bus clock in relation to the base clock, which can be selected from the 16 types shown in Table 3.12-8. The upper-limit frequency for operation is 66 MHz. Do not set a divide-by rate that results in a frequency exceeding this limit. Table 3.12-8 Clock Divide-By Rate (CPU Clock) Settings B3 B2 B1 B0 Clock divide-by rate Clock frequency: if the source oscillation is 16.5 [MHz] and the PLL is multiplied by 4 0 0 0 0 φ 66 [MHz] (initial value) 0 0 0 1 φ × 2 (divided by 2) 33 [MHz] 0 0 1 0 φ × 3 (divided by 3) 22 [MHz] 0 0 1 1 φ × 4 (divided by 4) 16.5 [MHz] 0 1 0 0 φ × 5 (divided by 5) 13.2 [MHz] 0 1 0 1 φ × 6 (divided by 6) 11 [MHz] 0 1 1 0 φ × 7 (divided by 7) 9.43 [MHz] 0 1 1 1 φ × 8 (divided by 8) 8.25 [MHz] ... ... ... ... ... ... 1 1 1 1 φ × 16 (divided by 16) 4.13 [MHz] φ: Frequency of the system base clock 120 CHAPTER 3 CPU AND CONTROL UNITS • These bits are initialized to "0000" by a reset (INIT). • These bits are readable and writable. [Bits 3 to 0] P3, P2, P1, P0 (clkP divide select 3 to 0) These bits are the clock divide-by rate setting bits of the peripheral clock (CLKP). Set the clock divide-by rate of the peripheral circuit and the peripheral bus clock (CLKP). The values written to these bits determine the divide-by rate (clock frequency) of the peripheral circuit and the peripheral bus clock in relation to the base clock, which can be selected from the 16 types shown in Table 3.12-9. Table 3.12-9 Clock Divide-by Rate (Peripheral Clock) Settings P3 P2 P1 P0 Clock divide-by rate Clock frequency: if the source oscillation is 16.5[MHz] and the PLL is multiplied by 4 0 0 0 0 φ 66 [MHz] * 0 0 0 1 φ × 2 (divided by 2) 33 [MHz] 0 0 1 0 φ × 3 (divided by 3) 22 [MHz] 0 0 1 1 φ × 4 (divided by 4) 16.5 [MHz] (initial value) 0 1 0 0 φ × 5 (divided by 5) 13.2 [MHz] 0 1 0 1 φ × 6 (divided by 6) 11 [MHz] 0 1 1 0 φ × 7 (divided by 7) 9.43 [MHz] 0 1 1 1 φ × 8 (divided by 8) 8.25 [MHz] ... ... ... ... ... ... 1 1 1 1 φ × 16 (divided by 16) 4.13 [MHz] φ: Frequency of the system base clock * : Disabled because 33 MHz is exceeded • These bits are initialized to "0011" by a reset (INIT). • These bits are readable and writable. Note: The upper-limit frequency for operation is 33 MHz. Do not set a divide-by rate that results in a frequency exceeding this limit. 121 CHAPTER 3 CPU AND CONTROL UNITS ■ Base Clock Division Setting Register 1 (DIVR1) Figure 3.12-9 shows the configuration of the Base Clock Division Setting Register 1 (DIVR1) bits. Figure 3.12-9 Configuration of Base Clock Division Setting Register 1 (DIVR1) Bits bit Address : 00000487H Initial value (INIT) Initial value (RST) 7 T3 R/W 0 × 6 T2 R/W 0 × 5 T1 R/W 0 × 4 T0 R/W 0 × 3 S3 R/W 0 × 2 S2 R/W 0 × 1 S1 R/W 0 × 0 S0 R/W 0 × Base Clock Division Setting Register 1 (DIVR1) controls the divide-by rate of an internal clock in relation to the base clock. This register sets the divide-by rates of the external extended bus interface clock (CLKT) and the SDRAM interface clock (CLKS). An upper-limit frequency for operation is set for each clock. If you set a combination of source clock, PLL multiply-by rate setting, and divide-by rate setting that results in a frequency exceeding this upper-limit frequency, operation is not guaranteed. Be extra careful of the order in which you change settings to select the source clock and to configure the associated setting items. If the setting in this register is changed, the new divide-by rate takes effect for the clock rate following the one in which the setting was made. [Bits 7 to 4] T3, T2, T1, T0 (clkT divide select 3 to 0) These bits are the clock divide-by rate setting bits of the external bus clock (CLKT). Set the clock divide-by rate of the external extended bus interface clock (CLKT). The values written to these bits determine the divide-by rate (clock frequency) of the external extended bus interface clock in relation to the base clock, which can be selected from the 16 types shown in Table 3.12-10. Table 3.12-10 Clock Divide-By Rate (External Bus Clock) Settings T3 T2 T1 T0 Clock divide-by rate Clock frequency: if the source oscillation is 16.5[MHz] and the PLL is multiplied by 4 0 0 0 0 φ 66 [MHz] * (initial value) 0 0 0 1 φ × 2 (divided by 2) 33 [MHz] 0 0 1 0 φ × 3 (divided by 3) 22 [MHz] 0 0 1 1 φ × 4 (divided by 4) 16.5 [MHz] 0 1 0 0 φ × 5 (divided by 5) 13.2 [MHz] 0 1 0 1 φ × 6 (divided by 6) 11 [MHz] 0 1 1 0 φ × 7 (divided by 7) 9.43 [MHz] 0 1 1 1 φ × 8 (divided by 8) 8.25 [MHz] ... ... ... ... ... ... 1 1 1 1 φ × 16 (divided by 16) 4.13 [MHz] φ: Frequency of the system base clock * : Disabled because 33 MHz is exceeded 122 • These bits are initialized to "0000" by a reset (INIT). • These bits are readable and writable. CHAPTER 3 CPU AND CONTROL UNITS Note: The upper-limit frequency for operation is 33 MHz. Do not set a divide-by rate that results in a frequency exceeding this limit. [Bits 3 to 0] S3, S2, S1, S0 (clkS divide select 3 to 0) This function is not supported by the MB91307 series. These bits are the clock divide-by rate setting bits of the SDRAM clock (CLKS). Set the clock divide-by rate of the SDRAM interface clock (CLKS). The values written to these bits determine the divide-by rate (clock frequency) of the SDRAM interface clock in relation to the base clock, which can be selected from the 16 types shown in Table 3.12-11. Table 3.12-11 Clock Divide-By Rate (SDRAM Clock) Settings S3 S2 S1 S0 Clock divide-by rate Clock frequency: if the source oscillation is 16.5[MHz] and the PLL is multiplied by 4 0 0 0 0 φ 66 [MHz] (initial value) 0 0 0 1 φ × 2 (divided by 2) 33 [MHz] 0 0 1 0 φ × 3 (divided by 3) 22 [MHz] 0 0 1 1 φ × 4 (divided by 4) 16.5 [MHz] 0 1 0 0 φ × 5 (divided by 5) 13.2 [MHz] 0 1 0 1 φ × 6 (divided by 6) 11 [MHz] 0 1 1 0 φ × 7 (divided by 7) 9.43 [MHz] 0 1 1 1 φ × 8 (divided by 8) 8.25 [MHz] ... ... ... ... ... ... 1 1 1 1 φ × 16 (divided by 16) 4.13 [MHz] φ: Frequency of the system base clock • These bits are initialized to "0000" by a reset (INIT). • These bits are readable and writable. Note: The upper-limit frequency for operation is 66 MHz. Do not set a divide-by rate that results in a frequency exceeding this limit. 123 CHAPTER 3 CPU AND CONTROL UNITS ■ Precautions on Dividing the CLKB Clock • To divide the CLKB clock, be sure to enable the PLL (Bit 10 of the CLKR register (PLL1EN=1)) and then set the DIVR0 register. • Write to the DIVR0 and DIVR1 registers at the same time (halfword write). • The CLKT clock must be the same divide-by rate as CLKB or a multiple of the CLKB clock. Table 3.12-12 is a list of possible combinations of the DIVR0 (B3 to 0) and DIVR1 (T3 to 0) registers. Table 3.12-12 Possible Combinations of DIVR0 (B3 to 0) and DIVR1 (T3 to 0) Registers (1/3) 124 DIVR0 (B3 to B0) DIVR1 (T3 to T0) Divide CLKB:CLKT Remarks 0000 XXXX 1:X Possible 0001 0000 2:1 Not possible 0001 0001 2:2 Possible 0001 0010 2:3 Not possible 0001 0011 2:4 Possible 0001 0100 2:5 Not possible 0001 0101 2:6 Possible 0001 0110 2:7 Not possible 0001 0111 2:8 Possible 0001 1111 2:16 Possible 0010 0000 3:1 Not possible 0010 0001 3:2 Not possible 0010 0010 3:3 Possible 0010 0011 3:4 Not possible 0010 0100 3:5 Not possible 0010 0101 3:6 Possible 0010 0110 3:7 Not possible 0010 0111 3:8 Not possible 0010 1111 3:16 Not possible 0011 0000 4:1 Not possible 0011 0001 4:2 Not possible 0011 0010 4:3 Not possible 0011 0011 4:4 Possible 0011 0100 4:5 Not possible 0011 0101 4:6 Not possible CHAPTER 3 CPU AND CONTROL UNITS Table 3.12-12 Possible Combinations of DIVR0 (B3 to 0) and DIVR1 (T3 to 0) Registers (2/3) DIVR0 (B3 to B0) DIVR1 (T3 to T0) Divide CLKB:CLKT Remarks 0011 0110 4:7 Not possible 0011 0111 4:8 Possible 0011 1111 4:16 Possible 0100 0000 5:1 Not possible 0100 0001 5:2 Not possible 0100 0010 5:3 Not possible 0100 0011 5:4 Not possible 0100 0100 5:5 Possible 0100 0101 5:6 Not possible 0100 0110 5:7 Not possible 0100 0111 5:8 Not possible 0100 1111 5:16 Not possible 0101 0000 6:1 Not possible 0101 0001 6:2 Not possible 0101 0010 6:3 Not possible 0101 0011 6:4 Not possible 0101 0100 6:5 Not possible 0101 0101 6:6 Possible 0101 0110 6:7 Not possible 0101 0111 6:8 Not possible 0101 1111 6:16 Not possible 0110 0000 7:1 Not possible 0110 0001 7:2 Not possible 0110 0010 7:3 Not possible 0110 0011 7:4 Not possible 0110 0100 7:5 Not possible 0110 0101 7:6 Not possible 0110 0110 7:7 Possible 0110 0111 7:8 Not possible 0110 1111 7:16 Not possible 0111 0000 8:1 Not possible 125 CHAPTER 3 CPU AND CONTROL UNITS Table 3.12-12 Possible Combinations of DIVR0 (B3 to 0) and DIVR1 (T3 to 0) Registers (3/3) DIVR0 (B3 to B0) DIVR1 (T3 to T0) Divide CLKB:CLKT Remarks 0111 0001 8:2 Not possible 0111 0010 8:3 Not possible 0111 0011 8:4 Not possible 0111 0100 8:5 Not possible 0111 0101 8:6 Not possible 0111 0110 8:7 Not possible 0111 0111 8:8 Possible 0111 1111 8:16 Possible 1111 0000 16:1 Not possible 1111 0001 16:2 Not possible 1111 0010 16:3 Not possible 1111 0011 16:4 Not possible 1111 0100 16:5 Not possible 1111 0101 16:6 Not possible 1111 0110 16:7 Not possible 1111 0111 16:8 Not possible 1111 1111 16:16 Possible Note: X is 1 or 0. To enter stop mode while the CLKB clock is divided, be sure to set all of the divide-by rates to "1", set the divide-by-2 mode (Bits 9 and 8 of the CLKR register (CLKS1, CLKS0=00)), and then enter stop mode. 126 CHAPTER 3 CPU AND CONTROL UNITS 3.12.7 Peripheral Circuits of Clock Controller This section describes the peripheral circuit functions of the clock controller. ■ Time Base Counter The clock controller has a 26-bit time base counter that runs on the system base clock. The time base counter is used to measure the oscillation stabilization wait time in addition to having the uses listed below (For more information about the oscillation stabilization wait time, see Section "3.11.4 Oscillation Stabilization Wait Time".) • Watchdog timer The watchdog timer, which is used to detect a system runaway, measures time using the bit output of the time base counter. • Time base timer The time base timer generates an interval interrupt using output from the time base counter. The following describes these functions. ❍ Watchdog timer The watchdog timer detects a runaway using output from the time base counter. If a program runaway results in a watchdog reset no longer being postponed for a specified interval, a settings initialization reset (INIT) request is generated as a watchdog reset. [Startup and interval setting of the watchdog timer] The watchdog timer is started when the reset source register and the watchdog timer control register (RSRR) are written to for the first time after a reset (RST). At this time, the interval time of the watchdog timer is set in Bits 09 and 08 (WT1 and WT0 bits). Only the time defined in this first write is valid as the interval time setting. Any further writing is ignored. [Postponing a watchdog reset] Once the watchdog timer is started, the program must write {A5H} and {5AH} in this order to the watchdog reset postpone register (WPR). This operation initializes the watchdog reset generation flag. [Generation of a watchdog reset] The watchdog reset generation flag is set at the trailing edge of the time base counter output of the specified interval. If the flag has already been set when a trailing edge is detected a second time, a settings initialization reset (INIT) request is generated as a watchdog reset. [Stopping the watchdog timer] The watchdog timer, once started, cannot be stopped until an operation initialization reset (RST) occurs. In the following states, when an operation initialization reset (RST) occurs, the watchdog timer is stopped and remains inoperative until a program starts it. • Operation initialization reset (RST) state • Settings initialization reset (INIT) state • Oscillation stabilization wait reset (RST) state • Hardware standby state 127 CHAPTER 3 CPU AND CONTROL UNITS [Suspending the watchdog timer (automatic postponement)] If program operation stops on the CPU, the watchdog reset generation flag is initialized and generation of a watchdog reset is postponed. Stopping of program operation specifically refers to the following statuses: • Sleep state • Stop state • Oscillation stabilization wait RUN state • DMA transfer in progress on the instruction bus (I-bus) or the data bus (D-bus) • During Data Access operation of cache memory at Instruction cache control register (ISIZE, ICHCR) or RAM Mode • During breaking an emulator debugger and a monitor debugger in use • Period of execution from INTE Instruction to RETI Instruction • Step Trace Trap (the break by each I instruction caused by T Flag = 1 in the PS Register) If the time base counter is cleared, the watchdog reset generation flag is initialized at the same time, postponing generation of a watchdog reset. If system falls into the condition mentioned above because of system runaway, the watchdog reset cannot be executed. In that case, execute initialization reset (INIT) from external INIT pin. ■ Time Base Timer The time base timer generates an interval using output from the time base counter. This timer is appropriate for measurements that require a relatively long time (for example, a maximum interval of {base clock × 227} cycles such as for the PLL lock wait time or a subclock. If the trailing edge of the time base counter output for the specified interval is detected, a time base timer interrupt request is generated. [Startup and interval settings of the time base timer] For the time base timer, the interval time is set in Bits 13 to 11 (TBC2, TBC1, and TBC0 bits) of the time base counter control register (TBCR). The trailing edge of the time base counter output for the specified interval is always detected. Thus, after setting the interval time, clear Bit 15 (TBIF bit) and then set Bit 14 (TBIE bit) to "1" to enable output of an interrupt request. Before changing the interval time, set Bit 14 (TBIE bit) to "0" to disable interrupt request output. Since the time base counter always counts regardless of these settings, before enabling interrupts, clear the time base counter to obtain an accurate interval interrupt time. Otherwise, an interrupt request may be generated immediately after an interrupt is enabled. [Clearing of the time base counter due to a program] If {A5H} and {5AH} are written in this order to the time base counter clear register (CTBR), all bits of the time base counter are cleared to 0 immediately after {5AH} is written. There is no time limit between writing of {A5H} and {5AH}. However, if data other than {5AH} is written after {A5H} is written, {A5H} must be written again before {5AH} is written. Otherwise, no clear operation occurs. If the time base counter is cleared, the watchdog reset generation flag is initialized at the same time, postponing generation of a watchdog reset. 128 CHAPTER 3 CPU AND CONTROL UNITS [Clearing of the time base counter due to the device state] All bits of the time base counter are cleared to 0 at the same time if the device enters one of the following states: • Stop state • Settings initialization reset (INIT) state • Hardware standby state Especially in the stop state, an interval interrupt of the time base timer may unintentionally be generated because the time base counter is used to measure the oscillation stabilization wait time. Before setting stop mode, therefore, disable time base timer interrupts to prevent the time base timer from being used. In any other state, time base timer interrupts are automatically disabled because an operation initialization reset (RST) occurs. 129 CHAPTER 3 CPU AND CONTROL UNITS 3.13 Device State Control This section describes the states of the MB91307 series and their control. It also describes low-power mode. ■ Device States The MB91307 series has the operating states listed below. For more information about these states, see Section "3.13.1 Transitions". • RUN state (normal operation) • Sleep state • Stop state • Hardware standby state • Oscillation stabilization wait RUN state • Oscillation stabilization wait reset (RST) state • Operation initialization reset (RST) state • Settings initialization reset (INIT) state ■ Low-power Modes The following two low-power modes are provided. For more information, see Section "3.13.2 Low-power Modes". 130 • Sleep mode • Stop mode Device States and State CHAPTER 3 CPU AND CONTROL UNITS 3.13.1 Device States and State Transitions This section describes device operating states and the transition between operating states. ■ RUN State (Normal Operation) In the RUN state, a program is being executed. All internal clocks are supplied and all circuits are enabled. For the 16-bit peripheral bus, however, only the bus clock is stopped, when it is not being accessed. In this state, a state transition request is accepted. If synchronous reset mode is selected, however, state transition operations different from normal reset mode are used for some requests. For more information, see "■Synchronous Reset Operation" in Section "3.11.5 Reset Operation Modes". ■ Sleep State In the sleep state, a program is stopped. Program operation causes a transition to this state. Only execution of the program on the CPU is stopped; peripheral circuits are enabled. The instruction cache is stopped and the built-in memory modules and the internal and external buses are stopped unless the DMA controller issues a request. • If a valid interrupt request occurs, the state is cleared and the RUN state (normal operation) is entered. • If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) state is entered. • If an operation initialization reset (RST) request occurs, the operation initialization reset (RST) state is entered. • If a hardware standby request occurs, the hardware standby state is entered. ■ Stop State In the stop state, the device is stopped. Program operation causes a transition to this state. All internal circuits are stopped. All internal clocks are stopped and the oscillation circuit and PLL can be stopped if set to do so. In addition, the external pins (except some) can be set to high impedance via settings. • If a specific valid interrupt request (no clock required) occurs, the oscillation stabilization wait RUN state is entered. • If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) state is entered. • If an operation initialization reset (RST) request occurs, the oscillation stabilization wait reset (RST) state is entered. • If a hardware standby request occurs, the hardware standby state is entered. 131 CHAPTER 3 CPU AND CONTROL UNITS ■ Hardware Standby State In the hardware standby state, the device is stopped. This state occurs after the "L" level is input (a hardware standby request) to the external HST pin. All internal circuits are stopped. All internal clocks are stopped and the oscillation circuit and PLL are also stopped. • A settings initialization reset (INIT) is supplied to the internal circuits. • Most of the external pins are set to high impedance. • "H" level input to the external HST pin or Low level input to the external INIT pin causes a transition to the settings initialization reset (INIT) state. ■ Oscillation Stabilization Wait RUN State In the oscillation stabilization wait RUN state, the device is stopped. This state occurs after a return from the stop state. All internal circuits except the clock generation controller (time base counter and device state controller) are stopped. All internal clocks are stopped, but the oscillation circuit and the PLL that has been enabled are running. • High impedance control of external pins in the stop or other state is cleared. • If the specified oscillation stabilization wait time elapses, the RUN state (normal operation) is entered. • If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) state is entered. • If an operation initialization reset (RST) request occurs, the oscillation stabilization wait reset (RST) state is entered. • If a hardware standby request occurs, the hardware standby state is entered. ■ Oscillation Stabilization Wait Reset (RST) Status In the oscillation stabilization wait reset (RST) state, the device is stopped. This state occurs after a return from the stop state or the settings initialization reset (INIT) state. All internal circuits except the clock generation controller (time base counter and device state controller) are stopped. All internal clocks are stopped, but the oscillation circuit and the PLL that has been enabled are running. 132 • High impedance control of external pins in the stop state, etc., is cleared. • An operation initialization reset (RST) is output to the internal circuits. • If the specified oscillation stabilization wait time elapses, the oscillation stabilization wait reset (RST) state is entered. • If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) state is entered. • If a hardware standby request occurs, the hardware standby state is entered. CHAPTER 3 CPU AND CONTROL UNITS ■ Operation Initialization Reset (RST) State In the operation initialization reset (RST) state, a program is initialized. This state occurs if an operation initialization reset (RST) request is accepted or the oscillation stabilization wait reset (RST) state is ended. Execution of a program on the CPU is stopped and the program counter is initialized. Most peripheral circuits are initialized. All internal clocks, the oscillation circuit and the PLL that has been enabled are running. • An operation initialization reset (RST) is output to the internal circuits. • If an operation initialization reset (RST) no longer exists, the RUN state (normal operation) is entered and the operation initialization reset sequence is executed. After a return from the settings initialization reset (INIT), the settings initialization reset sequence is executed. • If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) state is entered. • If a hardware standby request occurs, the hardware standby state is entered. ■ Settings Initialization Reset (INIT) State In the settings initialization reset (INIT) state, all settings are initialized. This state occurs if a settings initialization reset (INIT) is accepted or the hardware standby state is ended. Execution of a program on the CPU is stopped and the program counter is initialized. All peripheral circuits are initialized. The oscillation circuit runs, but the PLL stops running. All internal clocks are stopped while the "L" level is input to the external INIT pin; otherwise, they run. • A settings initialization reset (INIT) and an operation initialization reset (RST) are output to the internal circuits. • If a settings initialization reset (INIT) no longer exists, the state is cleared and the oscillation stabilization wait reset (RST) state is entered. Then, the operation initialization reset (RST) state is entered and the settings initialization reset sequence is executed. ■ Priority of State Transition Requests In any state, state transition requests conform to the priority listed below. However, some requests that occur only in a specific state are valid only in that state. [Highest] Settings initialization reset (INIT) request Hardware standby request End of oscillation stabilization wait time (occurs only in the oscillation stabilization wait reset state and the oscillation stabilization wait RUN state) Operation initialization reset (RST) request Valid interrupt request (occurs only in the RUN, sleep, and stop states) [Lowest] Stop mode request (writing to a register) (occurs only in the RUN state) 133 CHAPTER 3 CPU AND CONTROL UNITS 3.13.2 Low-power Modes This section describes the low-power modes, some MB91307 series states, and how to use the low-power modes. ■ Low-power Modes The MB91307 series has the following low-power modes: • Sleep mode: The device enters the sleep state due to writing to a register. • Stop mode: The device enters the stop state due to writing to a register. • Hardware standby mode: The device enters the hardware standby state due to Low level input to the external HST pin. These modes are described below. ■ Sleep Mode If "1" is set for Bit 6 (SLEEP bit) of the standby control register (STCR), sleep mode is initiated and the device enters the sleep state. The sleep state is maintained until a source for return from the sleep state is generated. If 1 is set for both Bit 7 (STOP bit) and Bit 6 of the standby control register (STCR), Bit 7 (STOP bit) has precedence and the device enters the stop state. For more information about the sleep state, see "■Sleep State" in Section "3.13.1 Device States and State Transitions". ❍ Circuits that stop in the sleep state • Program execution on the CPU • Instruction cache • Data cache • Bit search module (enabled if DMA transfer occurs) • Various built-in memory (enabled if DMA transfer occurs) • Internal types of and external buses (enabled if DMA transfer occurs) ❍ Circuits that do not stop in the sleep state 134 • Oscillation circuit • PLL that has been enabled • Clock generation controller • Interrupt controller • Peripheral circuit • DMA controller CHAPTER 3 CPU AND CONTROL UNITS ❍ Sources of return from the sleep state • Generation of a valid interrupt request If an interrupt request with a higher level than defined in ILM of the CPU occurs, sleep mode is cleared and the RUN state (normal operation) is entered. If an interrupt request with a lower level than defined in ILM of the CPU occurs, sleep mode is not cleared. • Generation of a settings initialization reset (INIT) request If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) state is unconditionally entered. • Generation of a hardware standby request If a hardware standby request occurs, the hardware standby state is unconditionally entered. • Generation of an operation initialization reset (RST) If an operation initialization reset (RST) occurs, the operation initialization reset (RST) state is unconditionally entered. For information about the priority of sources, see "■Priority of State Transition Requests" in Section "3.13.1 Device States and State Transitions". ❍ Normal and synchronous standby operations If "1" is set for Bit 8 (SYNCS bit) of the time base counter control register (TBCR), synchronous standby operation is enabled. In this case, simply writing to the SLEEP bit does not cause a transition to the sleep state. Instead, writing to the SLEEP bit and then reading the STCR register causes a transition to the sleep state. If "0" is set for the SYNCS bit, normal standby operation is selected. In this case, simply writing to the SLEEP bit causes a transition to the sleep state. If, in normal standby operation, the value set for the divide-by rate of the peripheral clock (CLKP) is larger than the CPU clock (CLKB), many instructions are executed before writing to the SLEEP bit actually occurs. Thus, after the write instruction to the SLEEP bit, the same number of NOP instructions as {5 + (CPU clock divide-by rate/peripheral clock divide-by rate)} instructions or more must be inserted. Otherwise, subsequent instructions are executed before the transition to the sleep state. In synchronous standby operation, the sleep state occurs only after writing to the SLEEP bit actually occurs and reading of the STCR register are completed. This is because the CPU uses the bus until the value read from the STCR register is stored in the CPU. Thus, in any setting of the relationship between the divide-by rates of the CPU clock (CLKB) and the peripheral clock (CLKP), insert only two NOP instructions after the write instruction for the SLEEP bit and the read instruction for the STCR register to prevent any subsequent instructions from being executed before transition to the sleep state. 135 CHAPTER 3 CPU AND CONTROL UNITS ■ Stop Mode If "1" is set for Bit 7 (STOP bit) of the standby control register (STCR), stop mode is initiated and the device enters the stop state. The stop state is maintained until a source for return from the stop state occurs. If "1" is set for both Bit 6 (SLEEP bit) and Bit 7 bit of the standby control register (STCR), Bit 7 (STOP bit) has precedence and the device enters the stop state. For more information about the stop state, see "■Stop State" in Section "3.13.1 Device States and State Transitions". ❍ Circuits that stop in the stop state • Oscillation circuits set to stop If "1" is set for Bit 1 (OSCD2 bit) of the standby control register (STCR), the subclock oscillation circuit in the stop state is stopped. If "1" is set for Bit 0 (OSCD1 bit) of the standby control register (STCR), the main clock oscillation circuit in the stop state is stopped. • PLL connected to the oscillation circuit that is either disabled or set to stop If "1" is set for Bit 1 (OSCD2 bit) of the standby control register (STCR) and "1" is set for Bit 11 (PLL2EN bit) of the clock source control register (CLKR), the subclock PLL in the stop state is stopped. If "1" is set for Bit 0 (OSCD1 bit) of the standby control register (STCR) and "1" is set for Bit 10 (PLL1EN bit) of the clock source control register (CLKR), the main clock PLL in the stop state is stopped. • All internal circuits except those, described below, that do not stop in the stop state ❍ Circuits that do not stop in the stop state • • Oscillation circuits that are set not to stop • If "0" is set for Bit 1 (OSCD2 bit) of the standby control register (STCR), the subclock oscillation circuit in the stop state is not stopped. (The MB91307 series has no subclock.) • If "0" is set for Bit 0 (OSCD1 bit) of the standby control register (STCR), the main clock oscillation circuit in the stop state is not stopped. PLL connected to the oscillation circuit that is enabled and is not set to stop • If "0" is set for Bit 1 (OSCD2 bit) of the standby control register (STCR) and "1" is set for Bit 11 (PLL2EN bit) of the clock source control register (CLKR), the subclock PLL in the stop state is not stopped. (The MB91307 series has no subclock.) • If "0" is set for Bit 0 (OSCD1 bit) of the standby control register (STCR) and "1" is set for Bit 10 (PLL1EN bit) of the clock source control register (CLKR), the main clock PLL in the stop state is not stopped. ❍ High impedance control of a pin in the stop state 136 • If "1" is set for Bit 5 (HIZ bit) of the standby control register (STCR), the output of a pin in the stop state is set to the high impedance state. For information about pins subject to this control, see the appendix, "STATUS OF PINS IN THE CPU STATES." • If "0" is set for Bit 5 (HIZ bit) of the standby control register (STCR), the output of a pin in the stop state maintains the value before transition to the stop state. For more information, see the appendix, "STATUS OF PINS IN THE CPU STATES." CHAPTER 3 CPU AND CONTROL UNITS ❍ Sources of return from the stop state • Generation of a specific valid interrupt request (no clock required) The external interrupt input pins (INT0 to INT7 pins) are enabled. If an interrupt request with a higher level than defined in ILM of the CPU occurs, stop mode is cleared and the RUN state (normal operation) is entered. If an interrupt request with a lower level than defined in ILM of the CPU occurs, stop mode is not cleared. • Generation of a settings initialization reset (INIT) request If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) is unconditionally entered. • Generation of a hardware standby request If a hardware standby request occurs, the hardware standby is unconditionally entered. • Generation of an operation initialization reset (RST) If an operation initialization reset (RST) occurs, the operation initialization reset (RST) is unconditionally entered. For information about the priority of sources, see "Priority of State Transition Requests" in Section "3.13.1 Device States and State Transitions". ❍ Selecting a clock source in stop mode In self-induced oscillation mode, select the main clock divided by "2" as the source clock before setting stop mode. For more information, see Section "3.12 Clock Generation Control" especially Section "3.12.1 PLL Controls". The same limitations as in the normal operation apply to the setting of a divide-by rate. ❍ Normal and synchronous standby operations If "1" is set for Bit 8 (SYNCS bit) of the time base counter control register (TBCR), synchronous standby operation is enabled. In this case, simply writing to the STOP bit does not cause a transition to the stop state. Instead, writing to the STOP bit and then reading the STCR register causes a transition to the stop state. If "0" is set for the SYNCS bit, normal standby operation is selected. In this case, simply writing to the STOP bit causes a transition to the stop state. If, in normal standby operation, the value set for the divide-by rate of the peripheral clock (CLKP) is larger than the CPU clock (CLKB), many instructions are executed before writing to the STOP bit actually occurs. Thus, after the write instruction to the STOP bit, the same number of NOP instructions as {5 + (CPU clock divide-by rate/peripheral clock divide-by rate)} instructions or more must be inserted. Otherwise, subsequent instructions are executed before the transition to the stop state. In synchronous standby operation, the stop state occurs only after writing to the STOP bit actually occurs and the reading of STCR register are completed. This is because the CPU uses the bus until the value read from the STCR register is stored into the CPU. Thus, in any setting of relationship between divide-by rates of the CPU clock (CLKB) and the peripheral clock (CLKP), insert only two NOP instructions after the write instruction for the STOP bit and the read instruction for the STCR register to prevent any subsequent instructions from being executed before transition to the stop state. 137 CHAPTER 3 CPU AND CONTROL UNITS ■ Hardware Standby Mode If the "L" level is input to the external HST pin, a hardware standby request occurs, causing a transition to the hardware standby state. As long as the "L" level is input thereafter, the hardware standby state is maintained. For information about the hardware standby state, see "■Hardware Standby State" in Section "3.13.1 Device States and State Transitions". ❍ Circuits that stop in the hardware standby state • All oscillation circuits • All PLLs • All internal circuits ❍ Circuits that do not stop in the hardware standby state All circuits stop in the hardware standby state. ❍ High impedance control of a pin in the hardware standby state In the hardware standby state, the output of a pin is set to the high impedance state. For information about pins subject to this control, see the "APPENDIX C PIN STATE IN EACH CPU STATE". ❍ Sources of return from the hardware standby state • "H" level input to the external HST pin If a hardware standby no longer exists, the settings initialization reset (INIT) state is entered. • Generation of a settings initialization reset (INIT) due to Low level input to the external INIT pin If a settings initialization reset (INIT) request generated due to the external INIT pin occurs, the settings initialization reset (INIT) is unconditionally entered. No other settings initialization reset (INIT) requests occur in the hardware standby state. For the priority of sources, see "■Priority of State Transition Requests" in Section "3.13.1 Device States and State Transitions". ❍ Normal and synchronous reset operations If "1" is set for Bit 9 (SYNCR bit) of the time base counter control register (TBCR), synchronous standby operation is enabled. In this case, no transition to the hardware standby state occurs while internal bus access is in progress even though a hardware standby request has been accepted. For more information, see "■Synchronous Reset Operation" in Section "3.11.5 Reset Operation Modes". If "0" is set for the SYNCR bit, a normal reset operation is selected. If a hardware standby request is accepted, the hardware standby state occurs regardless of the operating state of internal bus access. For more information, see "■Normal Reset Operation" in Section "3.11.5 Reset Operation Modes". 138 CHAPTER 3 CPU AND CONTROL UNITS 3.14 Operating Modes Two operating modes are provided: bus mode and access mode. This section describes these modes. ■ Operating Modes Figure 3.14-1 Operating Modes Bus mode External-ROM/Internal-RAM/external-bus External-ROM/external-bus Access mode 16-bit bus width 8-bit bus width ❍ Bus mode Bus mode refers to a mode in which the operations of internal ROM and the external access function are controlled. A bus mode is specified using the setting pins (MD2, MD1, and MD0) and the ROMA bit in the mode data. ❍ Access mode An access mode is specified using the WTH1 and WTH0 bits in the mode register and the DBW1 and DBW0 bits in ACR0 to ACR7 (Area Configuration Register). ■ Bus Modes The MB91307 series has the following two bus modes. ❍ Bus Mode 1 (internal-RAM/external-bus mode) In this mode, the access to the region where which built-in RAM 128KB (0004000H to 0005FFFH) into is effective. Access to an area that enables external access is handled as access to an external space. Some external pins serve as bus pins. ❍ Bus Mode 2 (external-ROM/external-bus mode) In this mode, the access to built-in RAM 128KB (0004000H to 0005FFFH) into is prohibited. All accesses are handled as access to an external space. Some external pins serve as bus pins. 139 CHAPTER 3 CPU AND CONTROL UNITS ■ Mode Settings For the MB91307 series, set the operating mode using the mode pins (MD2, MD1, and MD0) and the mode register (MODR). ❍ Mode pins Use the three mode pins (MD2, MD1, and MD0) to specify mode vector fetch and to set a test mode. Mode pin MD2 MD1 MD0 0 0 1 Mode name Reset vector access area External ROM mode vector External Remarks Set the bus width using the mode register. ❍ Mode register (MODR) The mode register (MODR: MODe Register) determines the operating mode. Figure 3.14-2 shows the configuration of the mode register (MODR). Figure 3.14-2 Configuration of the Mode Register (MODR) bit (0000 07FDH) 7 6 5 4 3 Reserved Reserved Reserved Reserved Reserved 2 1 0 ROMA WTH1 WTH0 Initial value INIT RST Access ********B xxxxxxxxB (R/W) This register automatically writes the 1-byte mode data placed at 000FFFF8H by hardware during a reset sequence. The data can be read and written only by the tool programs. ■ Functions of Bits in the Mode Register (MODR) The following explains the functions of the bits in the mode register (MODR). [Bits 7 to 3] Reserved These bits are reserved. Be sure to set them to "0". If you set the other value of "0", the operation is not guaranteed. [Bit 2] ROMA (Internal ROM enable bit) This bit sets whether to making built-in RAM region effective. Refer to "3.1 Memory Space" when you effectively use built-in RAM region. ROMA Function Remark 0 External ROM mode Built-in RAM region becomes an external region. 1 Internal RAM mode Built-in RAM region becomes effective, and builtin RAM128KB can be used. [Bits 1, 0] WTH1, WTH0 (Bus width specification bit) These bits specify the bus width when the reset vector and the initial value of the DBW1, DBW0 bits of the ACR0 register are read. 140 CHAPTER 3 CPU AND CONTROL UNITS Table 3.14-1 shows the settings for the initial bus width. Table 3.14-1 Settings of the Initial Bus Width WTH1 WTH0 Bus width 0 0 8 bits 0 1 16 bits 1 0 Setting prohibited 1 1 Setting prohibited The setting of the WTH1, WHT0 bits is written to the DBW1, DBW0 bits of the ACR0 register during initialization. 141 CHAPTER 3 CPU AND CONTROL UNITS 142 CHAPTER 4 EXTERNAL BUS INTERFACE The external bus interface controller controls the interfaces with the internal bus for chips and with external memory and I/O devices. This chapter explains each function of the external bus interface and its operation. 4.1 Overview of the External Bus Interface 4.2 External Bus Interface Registers 4.3 Setting Example of the Chip Select Area 4.4 Endian and Bus Access 4.5 Operation of the Ordinary bus interface 4.6 Burst Access Operation 4.7 Address/data Multiplex Interface 4.8 Prefetch Operation 4.9 DMA Access Operation 4.10 Bus Arbitration 4.11 Procedure for Setting a Register 4.12 Notes on Using the External Bus Interface 143 CHAPTER 4 EXTERNAL BUS INTERFACE 4.1 Overview of the External Bus Interface This section explains the features, block diagram, I/O pins, and registers of the external bus interface. ■ Features The external bus interface has the following features: ❍ Addresses of up to 32 bits (4 GB space) can be output. ❍ Various kinds of external memory (8-bit/16-bit modules) can be directly connected and multiple access timings can be mixed and controlled. • Asynchronous SRAM and asynchronous ROM/Flash memory (multiple write strobe method or byte enable method) • Page mode ROM/Flash memory (Page sizes 2, 4, and 8 can be used) • Burst mode ROM/Flash memory (such as MBM29BL160D/161D/162D) • Address/data multiplex bus (8-bit/16-bit width only) • Synchronous memory (such as ASIC built-in memory) (Synchronous SRAM cannot be directly connected) ❍ Eight independent banks (chip select areas) can be set, and chip select corresponding to each bank can be output. • The size of each area can be set in multiples of 64 KB (64 KB to 2 GB for each chip select area). • An area can be set at any location in the logical address space (Boundaries may be limited depending on the size of the area.) ❍ In each chip select area, the following functions can be set independently: 144 • Enabling and disabling of the chip select area (Disabled areas cannot be accessed) • Setting of the access timing type to support various kinds of memory • Detailed access timing setting (individual setting of the access type such as the wait cycle) • Setting of the data bus width (8-bit/16-bit) • Setting of the order of bytes (big or little endian) (Only big endian can be set for the CS0 area) • Setting of write disable (read-only area) • Enabling and disabling of fetches from the built-in cache • Enabling and disabling of the prefetch function • Maximum burst length setting (1, 2, 4, 8) CHAPTER 4 EXTERNAL BUS INTERFACE ❍ A different detailed timing can be set for each access timing type. • For the same type of access timing, a different setting can be made in each chip select area. • Auto-wait can be set to up to 15 cycles (asynchronous SRAM, ROM, Flash, and I/O area). • The bus cycle can be extended by external RDY input (asynchronous SRAM, ROM, Flash, and I/O area). • The first access wait and page wait can be set (burst, page mode, and ROM/Flash area). • Various kinds of idle/recovery cycles and setting delays can be inserted. ❍ Fly-by transfer by DMA can be performed. • Transfer between memory and I/O can be performed in a single access operation. • The memory wait cycle can be synchronized with the I/O wait cycle in fly-by transfer. • The hold time can be secured by only extending transfer source access. • Idle/recovery cycles specific to fly-by transfer can be set. ❍ External bus arbitration using BRQ and BGRNT can be performed. ❍ Pins that are not used by the external interface can be used as general-purpose I/O ports through settings. 145 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Block Diagram Figure 4.1-1 Block Diagram of the External Bus Interface Internal address bus Internal data bus 32 32 External data bus MUX write buffer switch read buffer switch DATA BLOCK ADDRESS BLOCK +1 or +2 External address bus address buffer ASR CS0-CS7 ASZ comparator External terminal controller All-block control resisters & control 146 RD WR0,WR1, AS,BAA BRQ BGRNT RDY CLK CHAPTER 4 EXTERNAL BUS INTERFACE ■ I/O Pins The I/O pins are external bus interface pins (Some pins have other uses). The following lists the I/O pins for each interface: ❍ Ordinary bus interface • A24 to A0, D31 to D16 • CS0, CS1, CS2, CS3, CS4, CS5, CS6, CS7 • AS, SYSCLK, MCLK • RD • WE, WR0(UUB), WR1(ULB) • RDY, BRQ, BGRNT ❍ Memory interface • MCLK • LBA(=AS), BAA (for burst ROM/Flash) ❍ DMA interface • IOWR, IORD • DACK0, DACK1, DACK2, DACK3 • DREQ0, DREQ1, DREQ2, DREQ3 • DEOP0/DSTP0, DEOP1/DSTP1, DEOP2/DSTP2, DEOP3/DSTP3 147 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Register List Figure 4.1-2 shows the registers used by the external bus interface: Figure 4.1-2 List of External Bus Interface Registers Address 31 24 23 16 15 8 7 0 00000640H ASR0 ACR0 00000644H ASR1 ACR1 00000648H ASR2 ACR2 0000064CH ASR3 ACR3 00000650H ASR4 ACR4 00000654H ASR5 ACR5 00000658H ASR6 ACR6 0000065CH ASR7 ACR7 00000660H AWR0 AWR1 00000664H AWR2 AWR3 00000668H AWR4 AWR5 0000066CH AWR6 AWR7 00000670H Reserved Reserved Reserved Reserved 00000674H Reserved Reserved Reserved Reserved 00000678H IOWR0 IOWR1 IOWR2 Reserved 0000067CH Reserved Reserved Reserved Reserved 00000680H CSER CHER Reserved TCR 00000684H Reserved Reserved Reserved Reserved 00000688H Reserved Reserved Reserved Reserved 0000068CH Reserved Reserved Reserved Reserved 000007F8H 000007FCH Reserved Reserved Reserved (MODR) Reserved Reserved *1 : Reserved indicates a reserved register. Be sure to set "0". *2 : MODR cannot be accessed from user programs. 148 Reserved Reserved CHAPTER 4 EXTERNAL BUS INTERFACE 4.2 External Bus Interface Registers This section explains the registers used in the external bus interface. ■ Register Types The following registers are used by the external bus interface: • Area select registers (ASR0 to ASR7) • Area configuration registers (ACR0 to ACR7) • Area wait registers (AWR0 to AWR7) • I/O wait registers for DMAC (IOWR0 to IOWR7) • Chip select enable register (CSER) • Cache enable register (CHER) • Pin/timing control register (TCR) 149 CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.1 Area Select Registers 0 to 7(ASR0 to ASR7) This section explains the configuration and functions of area select registers 0 to 7 (ASR0 to ASR7). ■ Configuration of area select registers 0 to 7 (ASR0 to ASR7) The area select registers (ASR0 to ASR7: Area Select Registers 0 to 7) specify the start address of each chip select area of CS0 to CS7. Figure 4.2-1 shows the configuration of area select registers 0 to 7 (ASR0 to ASR7: Area Select Register). Figure 4.2-1 Configuration of the Area Select Registers (ASR0 to ASR7) Initial value ASR0 0000 0640H ASR1 0000 0644H ASR2 0000 0648H ASR3 0000 064CH ASR4 0000 0650H ASR5 0000 0654H ASR6 0000 0658H ASR7 0000 065CH 150 15 14 13 A31 A30 A29 15 14 13 A31 A30 A29 15 14 13 A31 A30 A29 15 14 13 A31 A30 A29 15 14 13 A31 A30 A29 15 14 13 A31 A30 A29 15 14 13 A31 A30 A29 15 14 13 A31 A30 A29 12 ... ... ... 12 ... ... ... 12 ... ... ... 12 ... ... ... 12 ... ... ... 12 ... ... ... 12 ... ... ... 12 ... ... ... 2 1 0 INIT Access 0000H RST 0000H A18 A17 A16 2 1 0 A18 A17 A16 XXXXH XXXXH R/W 2 1 0 A18 A17 A16 XXXXH XXXXH R/W 2 1 0 A18 A17 A16 XXXXH XXXXH R/W 2 1 0 A18 A17 A16 XXXXH XXXXH R/W 2 1 0 A18 A17 A16 XXXXH XXXXH R/W 2 1 0 A18 A17 A16 XXXXH XXXXH R/W 2 1 0 A18 A17 A16 XXXXH XXXXH R/W R/W CHAPTER 4 EXTERNAL BUS INTERFACE ■ Functions of Bits in the Area Select Registers (ASR0 to ASR7) The start address can be set in the high-order 16 bits (bits A31 to A16). Each chip select area starts with the address set in this register and covers the range set by the four bits ASZ3 to ASZ0 of the ACR0 to ACR7 registers. The boundary of each chip select area obeys the setting of the four bits ASZ3 to ASZ0 of the ACR0 to ACR7 registers. For example, if an area of 1 MB is set by the four bits ASZ3 to ASZ0, the low-order four bits of the ASR0 to ASR7 registers are ignored and only bits A31 to A20 are valid. The ASR0 register is initialized to 0000H by INIT and RST. ASR1 to ASR7 are not initialized by INIT and RST, and are therefore undefined. After starting chip operation, be sure to set the corresponding ASR register before enabling each chip select area with the CSER register. 151 CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.2 Area Configuration Registers 0 to 7 (ACR0 to ACR7) This section explains the configuration and functions of area configuration registers 0 to 7 (ACR0 to ACR7). ■ Configuration of Area Configuration Registers 0 to 7 (ACR0 to ACR7) The area configuration registers 0 to 7 (ACR0 to ACR7: Area Configuration Registers 0 to 7) set the function of each chip select area. Figure 4.2-2 shows the configuration of area configuration registers 0 to 7 (ACR0 to ACR7). Figure 4.2-2 Configuration of Area Configuration Registers 0 to 7 (ACR0 to ACR7) Initial value ACR0H 0000 0642H 15 14 13 12 11 10 9 8 INIT ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 1111xx00B ACR0L 7 6 5 0000 0643H SREN PFEN WREN 4 ACR1H 0000 0646H 12 15 14 13 0 3 2 1 RST 1111xx00B 10 9 R/W 0 TYP3 TYP2 TYP1 TYP0 00000000B 00000000B 11 Access R/W 8 ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB R/W ACR1L 7 6 5 4 3 2 1 0 0000 0647H SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB R/W ACR2H 0000 064AH ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB R/W ACR2L 7 6 5 4 3 2 1 0 0000 064BH SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB R/W ACR3H 0000 064EH ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB R/W ACR3L 7 6 5 4 3 2 1 0 0000 064FH SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB R/W ACR4H 0000 0652H ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB R/W ACR4L 7 6 5 4 3 2 1 0 0000 0653H SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB R/W 15 15 15 14 14 14 13 13 13 12 12 12 11 11 11 10 10 10 9 9 9 8 8 8 (Continued) 152 CHAPTER 4 EXTERNAL BUS INTERFACE (Continued) Initial value ACR5H 0000 0656H 15 14 13 12 11 10 9 8 INIT RST ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB Access R/W ACR5L 7 6 5 4 3 2 1 0 0000 0657H SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB R/W ACR6H 0000 065AH ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB R/W ACR6L 7 6 5 4 3 2 1 0 0000 065BH SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB R/W ACR7H 0000 065EH ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB R/W ACR7L 7 6 5 4 3 2 1 0 0000 065FH SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB R/W 15 15 14 14 13 12 13 12 11 11 10 10 9 9 8 8 Note: Set both ASR and ACR at the same time using word access. When accessing ASR and ACR using half word, please set ACR after setting ASR. The following explains the function of each bit: [Bits 15 to 12] ASZ3 to ASZ0 (Area Size Bits 3 to 0) These bits set the area size. Table 4.2-1 shows their settings. Table 4.2-1 Area Size Settings (1/2) ASZ3 ASZ2 ASZ1 ASZ0 Size of each chip select area 0 0 0 0 64 KB (00010000H byte, ASR A[31:16] bits are valid) 0 0 0 1 128 KB (00020000H byte, ASR A[31:17] bits are valid) 0 0 1 0 256 KB (00040000H byte, ASR A[31:18] bits are valid) 0 0 1 1 512 KB (00080000H byte, ASR A[31:19] bits are valid) 0 1 0 0 1 MB (00100000H byte, ASR A[31:20] bits are valid) 0 1 0 1 2 MB (00200000H byte, ASR A[31:21] bits are valid) 0 1 1 0 4 MB (00400000H byte, ASR A[31:22] bits are valid) 0 1 1 1 8 MB (00800000H byte, ASR A[31:23] bits are valid) 1 0 0 0 16 MB (01000000H byte, ASR A[31:24] bits are valid) 1 0 0 1 32 MB (02000000H byte, ASR A[31:25] bits are valid) 1 0 1 0 64 MB (04000000H byte, ASR A[31:26] bits are valid) 1 0 1 1 128 MB (08000000H byte, ASR A[31:27] bits are valid) 153 CHAPTER 4 EXTERNAL BUS INTERFACE Table 4.2-1 Area Size Settings (2/2) ASZ3 ASZ2 ASZ1 ASZ0 Size of each chip select area 1 1 0 0 256 MB (10000000H byte, ASR A[31:28] bits are valid) 1 1 0 1 512 MB (20000000H byte, ASR A[31:29] bits are valid) 1 1 1 0 1024 MB (40000000H byte, ASR A[31:30] bits are valid) 1 1 1 1 2048 MB (80000000H byte, ASR A[31] bit is valid) ASZ3 to ASZ0 are used to set the size of each area by modifying the number of bits for address comparison to a value different from ASR. Thus, an ASR contains bits that are not compared. Bits ASZ3 to ASZ0 of ACR0 are initialized to 1111B (0FH) by RST. Despite this setting, however, the CS0 area just after RST is executed is specially set from 00000000H to FFFFFFFFH (setting of entire area). The entire-area setting is reset after the first write to ACR0 and an appropriate size is set as indicated in Table 4.2-1. [Bits 11, 10] DBW1, DBW0 (Data Bus Width 1, 0) These bits set the data bus width of each chip select area as indicated in Table 4.2-2: Table 4.2-2 Setting of the Data Bus Width of Each Chip Select Area DBW1 DBW0 Data bus width 0 0 8 bits (byte access) 0 1 16 bits (halfword access) 1 0 Reserved Setting disabled 1 1 Reserved Setting disabled The same values as those of the WTH bits of the mode vector are written automatically to bits DBW1, DBW0 of ACR0 during the reset sequence. [Bits 9, 8] BST1, BST0 (Burst Size 1, 0) These bits set the maximum burst length of each chip select area as indicated in Table 4.2-3. Table 4.2-3 Setting of the Maximum Burst Length of Each Chip Select BST1 BST0 Maximum burst length 0 0 1 (single access) 0 1 2 bursts (address boundary: 1 bit) 1 0 4 bursts (address boundary: 2 bits) 1 1 8 bursts (address boundary: 3 bits) In areas for which a burst length other than the single access is set, continuous burst access is performed within the address boundary determined by the burst length only when prefetch access is performed or data having a size exceeding the bus width is read. Setting of 2 bursts or less as the maximum burst length in the bus width 16-bit area is recommended. RDY input is ignored in areas for which any burst length other than the single access is set. 154 CHAPTER 4 EXTERNAL BUS INTERFACE [Bit 7] SREN (ShaRed Enable) This bit sets enabling or disabling of sharing of each chip select area by BRQ/BGRNT as indicated in the following table. Table 4.2-4 Enabling/Disabling of Sharing of Each Chip Select Area by BRQ/BGRNT SREN Sharing enable/disable 0 Disable sharing by BRQ/BGRNT (CS cannot be high impedance) 1 Enable sharing by BRQ/BGRNT (CS can be high impedance) In areas where sharing is enabled, chip select output (CSn) is set to high impedance while the bus is open (during BGRNT=Low output). In areas where sharing is disabled, chip select output (CSn) is not set to high impedance even though the bus is open (during BGRNT=Low output). Access strobe output (AS, BAA, RD, WR0, WR1, WE, etc.) is set to high impedance only if sharing of all areas enabled by CSER is enabled. [Bit 6] PFEN (PreFetch Enable) This bit sets enabling and disabling of prefetching of each chip select area as indicated in the following table. Table 4.2-5 Enabling/Disabling of Prefetching of Each Chip Select Area PFEN Prefetch enable/disable 0 Disable prefetch 1 Enable prefetch When reading from an area for which prefetching is enabled, the subsequent address is read in advance and stored in the built-in prefetch buffer. When the stored address is accessed from the internal bus, the lookahead data in the prefetch buffer is returned without performing external access. For more information, see Section "4.8 Prefetch Operation". [Bit 5] WREN (WRite Enable) This bit sets enabling and disabling of writing to each chip select area. WREN Write enable/disable 0 Disable write 1 Enable write If an area for which write operations are disabled is accessed for a write operation from the internal bus, the access is ignored and no external access at all is performed. Set the WREN bit of areas for which write operations are required, such as data areas, to "1". 155 CHAPTER 4 EXTERNAL BUS INTERFACE [Bit 4] LEND (Little ENDian select) This bit sets the order of bytes of each chip select area as indicated in the following table. LEND Order of bytes 0 Big endian 1 Little endian Be sure to set the LEND bit of ACR0 to "0". CS0 supports only the big endian method. [Bits 3 to 0] TYP3 to TYP0 (TYPe select) These bits set the access type of each chip select area as indicated in Table 4.2-6. Table 4.2-6 Access Type Settings for Each Chip Select Area TYP3 TYP2 TYP1 TYP0 Access type 0 0 x x Normal access (asynchronous SRAM, I/O, and single/page/burst-ROM/Flash) 0 1 x x Address data multiplex access (8/16-bit bus width only) 0 x x 0 Disable WAIT insertion by the RDY pin. 0 x x 1 Enable WAIT insertion by the RDY pin (disabled during bursts). 0 x 0 x Use the WR0, WR1 pins as write strobes (WE is always H). 0 x 1 x Use the WE pin as the write strobe. *1 1 0 0 0 Setting disabled *2 1 0 0 1 Setting disabled *2 1 0 1 0 Setting disabled *2 1 0 1 1 Setting disabled *2 1 1 0 0 Setting disabled *2 1 1 0 1 Setting disabled *2 1 1 1 0 Setting disabled *2 1 1 1 1 Mask area setting (The access type is the same as that of the overlapping area) *3 *1: If this setting is made, WR0, WR1 can be used as the enable of each bit. *2: Only the ACR6 and ACR7 registers are valid. The ACR0, ACR1, ACR2, ACR3, ACR4, and ACR5 registers are disabled. *3: See the CS area mask setting function (next bullet). Set the access type as the combination of all bits. For details of the operations of each access type, see the explanation (4.5.1 to 4.7) of each operation type. 156 CHAPTER 4 EXTERNAL BUS INTERFACE ❍ CS area mask setting function If you want to set an area some of whose operation settings are changed for a certain CS area (referred to as the base setting area), you can set TYPE3 to TYPE0 of ARC in another CS area to "1111" so that the area can function as a mask setting area. If you do not use the mask setting function, disable any overlapping area settings for multiple CS areas. Access operations to the mask setting area are as follows: • CS corresponding to a mask setting area is not asserted. • CS corresponding to a base setting area is asserted. • For the following ACR settings, the settings on the mask setting area side are valid: • • Bits 11, 10 (DBW1, 0): Bus width setting • Bits 9, 8 (BST1, 0): Burst length setting • Bit 7 (SREN): Sharing-enable setting • Bit 6 (PFEN): Prefetch-enable setting • Bit 5 (WREN): Write-enable setting (For this setting only, only a setting that is the same as that of the base setting area is allowed) • Bit 4 (LEND): Little endian setting For the following ACR setting, the setting on the base setting area side is valid: • Bits 3 to 0 (TYPE3 to TYPE0): Access type setting • For the AWR settings, the settings on the mask setting area side are valid. • For the CHER settings, the settings on the mask setting area side are valid. A mask setting area can be set for only part of another CS area (base setting area). You cannot set a mask setting area for an area without a base setting area. Take care when setting ASR and bits ASZ3 to ASZ0 of ACR. The following restrictions apply when using these bits: • A write-enable setting cannot be implemented by a mask. • Write-enable settings in the base CS area and the mask setting area must be identical. • If write operations to a mask setting area are disabled, the area is not masked and operates as a base CS area. • If write operations to the base CS area are disabled but are enabled to the mask setting area, the area has no base, resulting in malfunctions. 157 CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.3 Area Wait Register (AWR0 to AWR7) This section explains the configuration and functions of the area wait registers (AWR0 to AWR7). ■ Configuration of the Area Wait Registers (AWR0 to AWR7) The area wait registers (AWR0 to AWR7: Area Wait Register 0 to 7) specify various kinds of waits for each chip select area. Figure 4.2-3 shows the configuration of the area wait registers (AWR0 to AWR7). Figure 4.2-3 Configuration of the Area Wait Registers (AWR0 to AWR7) Initial value AWR0H 0000 0660H AWR0L 0000 0661H AWR1H 0000 0662H AWR1L 0000 0663H AWR2H 0000 0664H AWR2L 0000 0665H AWR3H 0000 0666H AWR3L 0000 0667H AWR4H 0000 0668H AWR4L 0000 0669H 31 30 29 28 27 26 25 24 W15 W14 W13 W12 W11 W10 W09 23 22 21 20 19 18 17 W07 W06 W05 W04 W03 W02 W01 15 14 13 12 11 10 9 8 W15 W14 W13 W12 W11 W10 W09 W08 7 6 5 4 3 2 1 0 W07 W06 W05 W04 W03 W02 W01 W00 31 30 29 28 27 26 25 24 W15 W14 W13 W12 W11 W10 W09 W08 23 22 21 20 19 18 17 16 W07 W06 W05 W04 W03 W02 W01 W00 15 14 13 12 11 10 9 8 W15 W14 W13 W12 W11 W10 W09 W08 7 6 5 4 3 2 1 0 W07 W06 W05 W04 W03 W02 W01 W00 31 30 29 28 27 26 25 24 W15 W14 W13 W12 W11 W10 W09 W08 23 22 21 20 19 18 17 16 W07 W06 W05 W04 W03 W02 W01 W00 INIT RST W08 01111111B 01111111B Access R/W 16 W00 11111111B 11111111B R/W xxxxxxxxB xxxxxxxxB R/W xxxxxxxxB xxxxxxxxB R/W xxxxxxxxB xxxxxxxxB R/W xxxxxxxxB xxxxxxxxB R/W xxxxxxxxB xxxxxxxxB R/W xxxxxxxxB xxxxxxxxB R/W xxxxxxxxB xxxxxxxxB R/W xxxxxxxxB xxxxxxxxB R/W (Continued) 158 CHAPTER 4 EXTERNAL BUS INTERFACE (Continued) Initial value AWR5H 0000 066AH 15 14 13 12 11 10 9 W15 W14 W13 W12 W11 W10 W09 8 INIT RST W08 xxxxxxxxB xxxxxxxxB Access AWR5L 0000 066BH 7 6 5 4 3 2 1 W07 W06 W05 W04 W03 W02 W01 W00 xxxxxxxxB xxxxxxxxB R/W AWR6H 0000 066CH 31 30 29 28 27 26 25 W15 W14 W13 W12 W11 W10 W09 24 W08 xxxxxxxxB xxxxxxxxB R/W AWR6L 0000 066DH 23 22 21 20 19 18 17 W07 W06 W05 W04 W03 W02 W01 16 W00 xxxxxxxxB xxxxxxxxB R/W AWR7H 0000 066EH 15 14 13 12 11 10 9 W15 W14 W13 W12 W11 W10 W09 8 W08 xxxxxxxxB xxxxxxxxB R/W AWR7L 0000 066FH 7 6 5 4 3 2 1 W07 W06 W05 W04 W03 W02 W01 R/W 0 0 W00 xxxxxxxxB xxxxxxxxB R/W The function of each bit changes according to the access type (TYP(3 to 0) bits) setting of the ACR0 to ACR7 registers. A chip select area determined by either of the following settings becomes the area for normal access or address/data multiplex access operation. TYP3 TYP2 TYP1 TYP0 Access type 0 0 x x Normal access (asynchronous SRAM, I/O, and single/page/burst-ROM/Flash) 0 1 x x Address data multiplex access (8/16-bit bus width only) The following lists the functions of each AWR0 to AWR7 bit for a normal access or address/data multiplex access area. Since the initial values of registers other than AWR0 are undefined, set them to their initial values before enabling each area with the CSER register. The following explains the functions of the bits in the area wait registers (AWR0 to AWR7). 159 CHAPTER 4 EXTERNAL BUS INTERFACE [Bits 31 to 28/15 to 12] W15 to W12 (First Wait Cycle) These bits set the number of auto-wait cycles to be inserted into the first access cycle of each cycle. Except for the burst access cycles, only this wait setting is used. Table 4.2-7 lists the settings for the number of auto-wait cycles during first access. Table 4.2-7 Settings for the Number of Auto-Wait Cycles (During First Access) W15 W14 W13 W12 First access wait cycle 0 0 0 0 Auto-wait cycle 0 0 0 0 1 Auto-wait cycle 1 ... 1 1 ... 1 1 Auto-wait cycle 15 [Bits 27 to 24/11 to 8] W11 to W08 (Inpage Access Wait Cycle) These bits set the number of auto-wait cycles to be inserted into the inpage access cycle during burst access. They are valid only for burst cycles. Table 4.2-8 lists the settings for the number of auto-wait cycles during burst access. Table 4.2-8 Settings for the Number of Auto-Wait Cycles (During Burst Access) W11 W10 W09 W08 Inpage access wait cycle 0 0 0 0 Auto-wait cycle 0 0 0 0 1 Auto-wait cycle 1 ... 1 1 ... 1 1 Auto-wait cycle 15 If the same value is set for the first access wait cycle and inpage access wait cycle, the access time for the address in each access cycle is not the same. This is because the inpage access cycle contains an address output delay. 160 CHAPTER 4 EXTERNAL BUS INTERFACE [Bits 23, 22/7,6] W07, 06 (Read → Write Idle Cycle) The read → write idle cycle is set to prevent collision of read data and write data on the data bus when a write cycle follows a read cycle. During an idle cycle, all chip select signals are negated and the data terminals maintain the high impedance state. If a write cycle follows a read cycle or an access operation to another chip select area occurs after a read cycle, the specified idle cycle is inserted. Table 4.2-9 lists the settings for idle cycles. Table 4.2-9 Settings of the Idle Cycle W07 W06 Read → write idle cycles 0 0 0 cycle 0 1 1 cycle 1 0 2 cycles 1 1 3 cycles [Bits 21, 20/5, 4] W05, W04 (Write Recovery Cycle) The write recovery cycle is set if a device that limits the access period after write access is to be controlled. During a write recovery cycle, all chip select signals are negated and the data pins maintain the high impedance state. If the write recovery cycle is set to "1" or more, a write recovery cycle is always inserted after write access. Table 4.2-10 lists the settings for the number of write recovery cycles. Table 4.2-10 Settings for the Number of Write Recovery Cycles W05 W04 Write recovery cycles 0 0 0 cycle 0 1 1 cycle 1 0 2 cycles 1 1 3 cycles 161 CHAPTER 4 EXTERNAL BUS INTERFACE [Bits 19/3] W03 (WR0, WR1, WE Output Timing Selection) The WR0, WR1, WE output timing setting selects whether to use write strobe output as an asynchronous strobe or synchronous write enable. The asynchronous strobe setting corresponds to normal memory or I/O. The synchronous enable setting corresponds to clock-synchronized memory or I/O (such as the memory in an ASIC). W03 WR0, WR1, WE output timing selection 0 MCLK synchronous write enable output (valid from AS=L) 1 Asynchronous write strobe output (normal operation) If synchronous write enable (W03 bit of AWR is "1") is used, operations are as follows: • The timing of synchronous write enable output assumes that the output is captured by the rising edge of MCLK output of an external memory access clock. This timing is different from the asynchronous strobe output timing. • The WR0, WR1 and WE terminal output asserts synchronous write enable output at the timing at which AS pin output is asserted. For a write to an external bus, the synchronous write enable output is "L". For a read from an external bus, the synchronous write enable output is "H". • Write data is output from the external data output pin in the clock cycle following the cycle in which synchronous write enable output is asserted. If write data cannot be output because the internal bus is temporarily unavailable, assertion of synchronous write enable output may be extended until write data can be output. • Read strobe output (RD) functions as an asynchronous read strobe regardless of the setting of the WR0, WR1 and WE output timing. Use it as is for controlling the data I/O direction. If synchronous write enable output is used, the following restrictions apply: • • • 162 Do not make the following additional wait settings: • CS →RD/WE setup (Always set "0" for the W01 bit of AWR) • First wait cycle setting (Always set 0000B for the W15 to W12 bits of AWR) Do not make the following access type settings (TYPE3 to TYPE0 bits in the ACR register (bits 3 to 0)) • Address/data multiplex bus setting (Always set "0" for the TYPE2 bit of ACR) • Setting to use WR0, WR1 as a strobe (Always set "0" for the TYPE1 bit of ACR) • RDY input enable setting (Always set "0" for the TYPE0 bit of ACR) For synchronous write enable output, always set 1(00B for bits BST1, BST0 bits of ACR) as the burst length. CHAPTER 4 EXTERNAL BUS INTERFACE [Bits 18/2] W02 (Address → CS Delay) The address → CS delay setting is made when a certain type of setup is required for the address when CS falls or CS edges are needed for successive accesses to the same chip select area. Set the address and set the delay from AS output to CS0 to CS7 output. W02 Address → CS delay 0 No delay 1 Delay If no delay is selected by setting "1", assertion of CS0 to CS7 starts at the same timing that AS is asserted. If, at this point, successive accesses are made to the same chip select area, assertion of CS0 to CS7 without change between two access operations may continue. If delay is specified by selecting "0", assertion of CS0 to CS7 starts when the external clock memory MCLK output rises. If, at this point, successive accesses are made to the same chip select area, CS0 to CS7 are negated at a timing between two access operations. If CS delay is selected, one setup cycle is inserted before asserting the read/write strobe after assertion of the delayed CS (operation is the same as the CS →RD/WE setup setting of W01). The address → CS delay setting works for DACK signal (basic mode) output to the same area in the same way. DACK output in basic mode has the same waveforms as those of CS output to the same area. [Bits 17/1] W01 (CS → RD/WE Setup Extension Cycle) The CS → RD/WE setup extension cycle is set to extend the period before the read/write strobe is asserted after CS is asserted. At least one setup extension cycle is inserted before the read/write strobe is asserted after CS is asserted. W01 CS → RD/WE setup delay cycle 0 0 cycle 1 1 cycle If 0 cycle is selected by setting "0", RD/WR0, WR1/WE are output at the earliest when external memory clock MCLK output rises just after CS is asserted. WR0, WR1/WE may be delayed one cycle or more depending on the internal bus state. If 1 cycle is selected by setting "1", RD/WR0, WR1/WE are always output 1 cycle or more later. When successive accesses are made within the same chip select area without negating CS, a setup extension cycle is not inserted. If a setup extension cycle for determining the address is required, set the W02 bit and insert the address → CS delay. Since CS is negated for each access operation, the setup extension cycle is enabled. If the CS delay set by W02 is inserted, this setup cycle is always enabled regardless of the setting of the W01 bit. 163 CHAPTER 4 EXTERNAL BUS INTERFACE [Bits 16/0] W00 (RD/WE → CS Hold Extension Cycle) The RD/WE → CS hold extension cycle is set to extend the period before negating CS after the read/write strobe is negated. One hold extension cycle is inserted before CS is negated after the read/write strobe is negated. W00 RD/WE → CS hold extension cycle 0 0 cycle 1 1 cycle If 0 cycle is selected by setting "0", CS0 to CS7 are negated after the hold delay after it starts on the rising edge of external memory clock MCLK output after RD/WR0, WR1/WE are negated. If 1 cycle is selected by setting "1", CS0 to CS7 are negated one cycle later. When making successive accesses within the same chip select area without negating CS, the hold extension cycle is not inserted. If a hold extension cycle for determining the address is required, set the W02 bit and insert the address → CS delay. Since CS is negated for each access operation, this hold extension cycle is enabled. 164 CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.4 I/O Wait Registers for DMAC (IOWR0 to IOWR2) This section explains the configuration and functions of the I/O wait registers for DMAC (IOWR0 to IOWR2). ■ Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR2) The I/O wait registers for DMAC (IOWR0 to IOWR2: I/O Wait Register for DMAC0 to DMAC3) set various kinds of waits during DMA fly-by access. Figure 4.2-4 shows the configuration of the I/O wait registers for DMAC (IOWR0 to IOWR2). Figure 4.2-4 Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR2) Initial value IOWR0 0000 0678H IOWR1 0000 0679H IOWR2 0000 067AH 31 RST RYE0 HLD0 WR01 WR00 IW03 IW02 IW01 IW00 xxxxxxxxB xxxxxxxxB 23 30 22 29 21 28 20 27 19 26 18 25 17 24 INIT 14 13 12 11 10 9 R/W 16 RYE1 HLD1 WR11 WR10 IW13 IW12 IW11 IW10 xxxxxxxxB xxxxxxxxB 15 Access R/W 8 RYE2 HLD2 WR21 WR20 IW23 IW22 IW21 IW20 xxxxxxxxB xxxxxxxxB R/W ■ Functions of Bits in the I/O Wait Registers for DMAC (IOWR0 to IOWR2) The following explains the functions of the bits in the I/O wait registers for DMAC (IOWR0 to IOWR2). [Bits 31, 23, 15] RYE0,1,2 (RDY function setting 0,1,2) These bits set the wait control, using RDY, of channels 0 to 2 during DMA fly-by access. RYEn RDY function setting 0 Disable RDY input for I/O access. 1 Enable RDY input for I/O access. When "1" is set, wait insertion by the RDY pin can be performed during fly-by transfer on the relevant channel. IOWR and IORD are extended until the RDY pin is enabled. Also, RD/WR0, WR1/WE on the memory side are extended synchronously. If the chip select area of the fly-by transfer destination is set to RDY-enabled in the ACR register, wait insertion by the RDY pin can be performed regardless of the RYEn bit of IOWR. When the chip select area of the fly-by transfer destination is set to RDY-disabled in the ACR register, wait insertion by the RDY pin can only be performed during fly-by access if the area is set to RDY-enabled by the RYEn bit on the IOWR side. 165 CHAPTER 4 EXTERNAL BUS INTERFACE [Bits 30,22,14] HLD0,1,2 (Hold Wait Setting) These bits control the hold cycle of the read strobe signal on the transfer source access side during DMA fly-by access. HLDn Hold wait setting 0 Do not insert a hold extension cycle. 1 Insert a hold extension cycle to extend the read cycle by one cycle. If "0" is set, the read strobe signal (RD for memory → I/O and IORD for I/O → memory) and the write strobe signal (IOWR for memory → I/O and WR0, WR1 and WE for I/O → memory) on the transfer source access side are output at the same timing. If "1" is set, the read strobe signal is output one cycle longer than the write strobe signal to secure a hold time for data at the transfer source access side when sending it to the transfer destination. [Bits 29, 28, 21, 20, 13, 12] WR0 to WR3 (I/O Idle Cycle setting) These bits set the number of idle cycles for continuous access during DMA fly-by access. Table 4.2-11 lists the settings for the number of I/O idle cycles. Table 4.2-11 Settings for the Number of I/O Idle Cycles WRn1 WRn0 Setting of the number of I/O idle cycles 0 0 0 cycle 0 1 1 cycle 1 0 2 cycles 1 1 3 cycles If one or more cycles is set as the number of idle cycles, cycles equal to the number specified are inserted after I/O access during DMA fly-by access. During the idle cycles, all CS and strobe output is negated and the data pin is set to the high impedance state. 166 CHAPTER 4 EXTERNAL BUS INTERFACE [Bits 27 to 24, 19 to 16, 11 to 8, 3 to 0] IW03 to IW00, IW13 to IW10, IW23 to IW20, IW33 to IW30 (I/O Wait Cycle) These bits set the number of auto-wait cycles for I/O access during DMA fly-by access. Table 4.2-12 lists the settings for the number of I/O wait cycles. Table 4.2-12 Settings for the Number of I/O Wait Cycles IWn3 IWn2 IWn1 IWn0 Number of I/O wait cycles 0 0 0 0 0 cycle 0 0 0 1 1 cycle ... 1 1 ... 1 1 15 cycles Because data is synchronized between the transfer source and transfer destination, the I/O side setting of the IWnn bits and the wait setting for the fly-by transfer destination (such as memory), whichever is larger, is used as the number of wait cycles to be inserted. Consequently, more wait cycles than specified by the IWnn bits may be inserted. 167 CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.5 Chip Select Enable Register (CSER) Because data is synchronized between the transfer source and transfer destination, the I/O side setting of the IWnn bits and the wait setting for the fly-by transfer destination (such as memory), whichever is larger, is used as the number of wait cycles to be inserted. Consequently, more wait cycles than specified by the IWnn bits may be inserted. ■ Configuration of the Chip Select Enable Register (CSER) The chip select enable register (CSER: Chip Select Enable register) enables and disables each chip select area. Figure 4.2-5 shows the configuration of the chip select enable register (CSER). Figure 4.2-5 Configuration of the Chip Select Enable Register (CSER) Initial value 31 0000 0680H 30 29 28 27 26 25 24 INIT RST CSE7 CSE6 CSE5 CSE4 CSE3 CSE2 CSE1 CSE0 00000001B 00000001B Access R/W ■ Functions of Bits in the Chip Select Enable Register (CSER) The following explains the functions of the bits in the chip select enable register (CSER). [Bits 31 to 24] CSE7 to CSE0 (Chip Select Enable 0 to 7) These bits are the chip select enable bits for CS0 to CS7. The initial value is "00000001B", which enables only the CS0 area. When "1" is written, a chip select area operates according to the settings of ASR0 to ASR7, ACR0 to ACR7, and AWR0 to AWR7. Before setting this register, be sure to make all settings required for the corresponding chip select areas. 168 CSE7 to CSE0 Area control 0 Disable 1 Enable CHAPTER 4 EXTERNAL BUS INTERFACE Table 4.2-13 lists the corresponding CSn for the chip select enable bits. Table 4.2-13 CSn Corresponding to the Chip Select Enable Bits CSE bit Corresponding CSn Bit 24: CSE0 CS0 Bit 25: CSE1 CS1 Bit 26: CSE2 CS2 Bit 27: CSE3 CS3 Bit 28: CSE4 CS4 Bit 29: CSE5 CS5 Bit 30: CSE6 CS6 Bit 31: CSE7 CS7 169 CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.6 Cache Enable Register (CHER) This section explains the configuration and functions of the cache enable register (CHER). ■ Configuration of the Cache Enable Register (CHER) The cache enable register (CHER: CacHe Enable Register) controls the transfer of data read from each chip select area. Figure 4.2-6 shows the configuration of the cache enable register (CHER). Figure 4.2-6 Configuration of the Cache Enable Register (CHER) Initial value 23 0000 0681H 22 21 20 19 18 17 16 INIT RST CHE7 CHE6 CHE5 CHE4 CHE3 CHE2 CHE1 CHE0 11111111B 11111111B Access R/W ■ Functions of Bits in the Cache Enable Register (CHER) The following explains the functions of the bits in the cache enable register (CHER). [Bits 23 to 16] CHE7 to CHE0 (Cache area setting 7 to 0) These bits enable and disable each chip select area for transfers to the built-in cache. 170 CHEn Cache area setting 0 Not a cache area (data read from the applicable area is not saved in the cache) 1 Cache area (data read from the applicable area is saved in the cache) CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.7 Pin/Timing Control Register (TCR) This section explains the configuration and functions of the pin/timing control register. ■ Configuration of the Pin/Timing Control Register (TCR) The pin/timing control register (TCR: Pin and Timing Control Register) controls the functions related to the general external bus interface controller, such as the setting of common pin functions and timing control. Figure 4.2-7 shows the configuration of the pin/timing control register (TCR). Figure 4.2-7 Configuration of the Pin/Timing Control Register (TCR) Initial value 7 6 5 0000 0683H BREN PSUS PCLR 4 Reserved 3 2 1 0 INIT OHT1 OHT0 RDW1 RDW0 00000000B RST 0000xxxxB Access R/W ■ Functions of Bits in the Pin/Timing Control Register (TCR) The following explains the functions of the bits in the pin/timing control register (TCR). [Bit 7] BREN (BRQ input enable) This bit enables BRQ pin input and external bus sharing. BREN BRQ input enable setting 0 No bus sharing by BRQ/BGRNT. BRQ input is disabled. 1 Bus sharing by BRQ/BGRNT. BRQ input is enabled. In the initial state ("0"), BRQ input is ignored. When "1" is set, the bus is made open (control with high impedance) and BGRNT is activated ("L" level is output) when the bus is ready to be made open after the BRQ input becomes "H" level. [Bit 6] PSUS (Prefetch suspend) This bit controls temporary stopping of prefetch to all areas. PSUS Prefetch control 0 Enable prefetch 1 Suspend prefetch. If "1" is set, no new prefetch operation is performed before "0" is written. Since during this time the contents of the prefetch buffer are not deleted unless a prefetch buffer occurs, clear the prefetch buffer using the PCLR bit function (bit 5) before restarting prefetch. 171 CHAPTER 4 EXTERNAL BUS INTERFACE [Bit 5] PCLR (Prefetch buffer all clear) This bit completely clears the prefetch buffer. PCLR Prefetch buffer control 0 Normal state 1 Clear the prefetch buffer. If "1" is written, the prefetch buffer is cleared completely. When clearing is completed, the bit value automatically returns to "0". Interrupt (set to "1") the prefetch by the PSUS bit (bit 6) and then clear the buffer (It is also possible to write 10B to both the PSUS and PCLR bits). [Bit 4] Reserved This bit is reserved. Be sure to set it to "0". [Bits 3, 2] OHT1, OHT0 (Output hold delay selection) These bits adjust the delay value for holding external control signal output to external memory clock MCLK output. Table 4.2-14 lists the settings for the output hold delay selection for combinations of these bits. Table 4.2-14 Settings for Output Hold Delay Selection OHT1 OHT0 Output hold delay selection 0 0 Output on fall of SYSCLK/MCLK. 0 1 Output (3 ns) after SYSCLK/MCLK rises. 1 0 Output (4 ns) after SYSCLK/MCLK rises. 1 1 Output (5 ns) SYSCLK/MCLK rises. The delay value is the target value under typical conditions. Asynchronous reading, write strobes (RD/WR0/WR1/WE/IOWR/IORD), and the fall timing of delayed CS are not subject to this delay value adjustment. Although OHT1, OHT0 do not malfunction if they are rewritten during operation, external bus operation stops temporarily when the timing is switched. [Bits 1,0] RDW1,RDW0 (Wait cycle reduction) These bits instruct all chip select areas and fly-by I/O channels to reduce only the number of auto-wait cycles in the auto-access cycle wait settings uniformly while the AWR register settings are retained unchanged. The settings for idle cycles, recovery cycles, setup, and hold cycles are not affected. Table 4.2-15 lists the settings for the wait cycle reduction for combinations of these bits. Table 4.2-15 Settings for Wait Cycle Reduction 172 RDW1 RDW0 Wait cycle reduction 0 0 Normal wait (AWR0 to AWR7 settings) 0 1 1/2 (1-bit shift to the right) of the AWR0 to AWR7 settings 1 0 1/4 (2-bit shift to the right) of the AWR0 to AWR7 settings 1 1 1/8 (3-bit shift to the right) of the AWR0 to AWR7 settings CHAPTER 4 EXTERNAL BUS INTERFACE The purpose of this function is to prevent an excessive access cycle wait during operation on a low-speed clock (for example, when the base clock is switched to low speed or the frequency division ratio setting of the external bus clock is large). To reset the wait cycle in these cases, each of the AWRs must usually be rewritten one at a time. However, when the RDW1/0 bit function is used, the access cycle wait is reduced for all of the AWRs in a single operation while all of the other high-speed clock settings in each register are retained. Before returning the clock to high speed, be sure to reset the RDW1/0 bits to "00B". 173 CHAPTER 4 EXTERNAL BUS INTERFACE 4.3 Setting Example of the Chip Select Area In the external bus interface, a total of eight chip select areas can be set. This section presents an example of setting the chip select area. ■ Example of Setting the Chip Select Area The address space of each area can be placed, in units of a minimum of 64 KB, anywhere in the 4 GB space using ASR0 to ASR7 (Area Select Registers) and ACR0 to ACR7 (Area Configuration Registers). When bus access is made to an area specified by these registers, the corresponding chip select signals (CS0 to CS7) are activated ("L" output) during the access cycle. ❍ Example of setting ASRs and ASZ3 to ASZ0 • ASR1=0003h ACR1 ASZ3 to ASZ0=0000B: Chip select area 1 is assigned to 00030000H to 0003FFFFH. • ASR2=0FFCh ACR2 ASZ3 to ASZ0=0010B: Chip select area 2 is assigned to 0FFC0000H to 10000000H. • ASR3=0011h ACR3 ASZ3 to ASZ0=0100B: Chip select area 3 is assigned to 00100000H to 00200000H. Since at this point 1 MB is set for bits ASZ3 to ASZ0 of the ACR, the unit for boundaries 1 MB and bits 19 to 16 of ASR3 are ignored. Before there is any writing to ACR0 after a reset, 00000000H to FFFFFFFFH is assigned to chip select area 0. Set the chip select areas so that there is no overlap. Figure 4.3-1 shows an example of setting the chip select area. Figure 4.3-1 Example of Setting the Chip Select Area (Initial value) 00000000H (Example) 00000000H 00030000H Area 1 64 KB Area 3 1 MB Area 2 256 KB 00040000H Area 0 00100000H 00200000H 0FFC0000H 0FFFFFFFH FFFFFFFFH 174 FFFFFFFFH CHAPTER 4 EXTERNAL BUS INTERFACE 4.4 Endian and Bus Access There is a one-to-one correspondence between the WR0/WR1 control signal and the byte location regardless of the endian method (big or little) and the data bus width. The following summarizes the location of bytes on the data bus of the MB91307 series used according to the specified data bus width and the corresponding control signal for each bus mode. ■ Relationship between Data Bus Width and Control Signal This section summarizes the location of bytes on the data bus used according to the specified data bus width and the corresponding control signal for each bus mode. ❍ Ordinary bus interface Figure 4.4-1 Data Bus Width and Control Signal on the Ordinary Bus Interface a) 32-bit bus width data bus Control signal D31 D0 b) 16-bit bus width c) 8-bit bus width data bus data bus Control signal Control signal WR0 (UUB) WR0 (UUB) WR0 (UUB) WR1 (ULB) WR1 (ULB) - - WR2 (LUBX) - - - - WR3 (LLBX) - - - - (D15-0 are not used) (D23-0 are not used) 175 CHAPTER 4 EXTERNAL BUS INTERFACE ❍ Time division I/O interface Figure 4.4-2 Data Bus Width and Control Signal in the Time Division I/O Interface a) 16-bit bus width b) 8-bit bus width data bus Output address Control signal D31 A15-8 WR0 A7-0 WR1 data bus Output address Control signal A7-0 WR0 - - - D16 - - - - - - - - - - - - (D15-0 are not used) 176 (D23-0 are not used) CHAPTER 4 EXTERNAL BUS INTERFACE 4.4.1 Big Endian Bus Access With the exception of the CS0 area of the MB91307 series, either the big endian method or the little endian method can be selected for each chip select area. If "0" is set for the LEND bit of the ACR register, the area is treated as big endian. The MB91307 series is normally big endian and performs external bus access. ■ Data Format The relationship between the internal register and the external data bus is as follows: ❍ Word access (when LD/ST instruction executed) Figure 4.4-3 Relationship between Internal Register and External Data Bus for Word Access Internal register External bus D31 AA AA D23 D31 D23 BB BB CC CC DD DD D15 D15 D7 D7 D0 D0 Figure 4.4-4 Relationship between the Internal Register and External Data Bus for Halfword Access a) Output address low-order digits "00" b) Output address low-order digits "10" Internal register External bus Internal register External bus D31 AA D23 D31 D31 D31 D23 D23 D23 D15 D15 BB D15 AA D7 D7 D0 AA BB BB D7 BB D0 D15 AA D0 D7 D0 177 CHAPTER 4 EXTERNAL BUS INTERFACE Figure 4.4-5 Relationship between Internal Register and External Data Bus for Byte Access a) Output address low-order digits "00" Internal register D31 b) Output address low-order digits "01" External bus AA D23 Internal register c) Output address low-order digits "10" External bus D31 D31 D23 D23 Internal register d) Output address low-order digits "11" External bus Internal register External bus D31 D31 D31 D31 D31 D23 D23 D23 D23 D23 D15 D15 D15 D15 D15 AA D15 D15 D15 D7 D7 AA D7 AA D7 D7 AA D0 D0 D7 D7 AA D0 D0 D7 AA D0 D0 D0 AA D0 ■ Data Bus Width ❍ 16-bit bus width Figure 4.4-6 Relationship between Internal Register and External Bus Having 16-Bit Bus Width Internal register External bus Output address low-order digits D31 D23 D15 AA BB read/write "00" "10" AA CC BB DD D31 D23 CC D07 DD ❍ 8-bit bus width Figure 4.4-7 Relationship between Internal Register and External Bus having 8-Bit bus Width Internal register External bus Output address low-order digits "00" "01" "10" read/write D31 AA BB CC AA D23 BB D15 CC D07 DD 178 "11" D31 DD CHAPTER 4 EXTERNAL BUS INTERFACE ■ External Bus Access Figure 4.4-8 and Figure 4.4-9 show external bus access (16-bit/8-bit bus width) separately for word, halfword, and byte access. The following items are included in Figure 4.4-8 and Figure 4.4-9: • Access byte location • Program address and output address • Bus access count The MB91307 series does not detect misalignment errors. Therefore, for word access, the lower 2 bits of the output address are always "00" regardless of whether "00", "01", "10", or "11" is specified as the lower 2 bits by the program. For halfword access, the lower 2 bits of the output address are "00" if the lower 2 bits specified by the program are "00" or "01", and are "10" if "10" or "11". ❍ 16-bit bus width Figure 4.4-8 External bus Access for 16-Bit Bus Width (A) Word access (a) PA1/PA0="00" (b) PA1/PA0="01" (c) PA1/PA0="10" (1) Output A1/A0="00" (1) Output A1/A0="00" (1) Output A1/A0="00" (2) Output A1/A0="10" (2) Output A1/A0="10" (2) Output A1/A0="10" (d) PA1/PA0="11" (1) Output A1/A0="00" (2) Output A1/A0="10" LSB MSB (1) 00 01 (1) 00 01 (1) 00 01 (1) 00 01 (2) 10 11 (2) 10 11 (2) 10 11 (2) 10 11 16bits (B) Halfword access (a) PA1/PA0="00" (b) PA1/PA0="01" (c) PA1/PA0="10" (1) Output A1/A0="00" (1) Output A1/A0="00" (1) Output A1/A0="00" (1) 00 01 10 11 (1) 00 01 10 11 (1) 00 01 10 11 (d) PA1/PA0="11" (1) Output A1/A0="00" (1) 00 01 10 11 (C) Byte access (a) PA1/PA0="00" (b) PA1/PA0="01" (c) PA1/PA0="10" (1) Output A1/A0="00" (1) Output A1/A0="00" (1) Output A1/A0="00" (1) 00 01 10 11 (1) 00 01 10 11 (1) 00 01 10 11 (d) PA1/PA0="11" (1) Output A1/A0="00" (1) 00 01 10 11 179 CHAPTER 4 EXTERNAL BUS INTERFACE ❍ 8-bit bus width Figure 4.4-9 External Bus Access for 8-Bit Bus Width (A) Word access (b) PA1/PA0="01" (c) PA1/PA0="10" (d) PA1/PA0="11" (a) PA1/PA0="00" (1) Output A1/A0="00" (1) Output A1/A0="00" (1) Output A1/A0="00" (1) Output A1/A0="00" (2) Output A1/A0="01" (2) Output A1/A0="01" (2) Output A1/A0="01" (2) Output A1/A0="01" (3) Output 1/A0="10" (3) Output 1/A0="10" (3) Output 1/A0="10" (3) Output 1/A0="10" (4) Output 1/A0="11" (4) Output 1/A0="11" (4) Output 1/A0="11" (4) Output 1/A0="11" MSB LSB (1) 00 (1) 00 (1) 00 (1) 00 (2) 01 (2) 01 (2) 01 (2) 01 (3) 10 (3) 10 (3) 10 (3) 10 (4) 11 (4) 11 (4) 11 (4) 11 8bits (B) Halfword access (a) PA1/PA0="00" (b) PA1/PA0="01" (c) PA1/PA0="10" (d) PA1/PA0="11" (1) Output A1/A0="00" (1) Output A1/A0="00" (1) Output A1/A0="10" (1) Output A1/A0="10" (2) Output A1/A0="01" (2) Output A1/A0="01" (2) Output A1/A0="11" (2) Output A1/A0="11" (1) 00 (1) 00 00 00 (2) 01 (2) 01 01 01 10 10 (1) 10 (1) 10 11 11 (2) 11 (2) 11 (C) Byte access (a) PA1/PA0="00" (b) PA1/PA0="01" (c) PA1/PA0="10" (d) PA1/PA0="11" (1) Output A1/A0="00" (1) Output A1/A0="00" (1) Output A1/A0="10" (1) Output A1/A0="10" (1) 00 01 180 (1) 00 00 00 01 01 01 10 10 10 10 11 11 (1) 11 (1) 11 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Example of Connection with External Devices Figure 4.4-10 shows an example of connection for the MB91307 series to external devices. Figure 4.4-10 Example of Connecting the MB91307 Series to External Devices This LSI D31 W D23 W | R | R D24 0 D16 0 X X 00 01 D15 W | R D08 0 X D07 W | R D00 0 X 10 11 D31 D24 D23 D16 D15 D08 D07 32-bit device (low-order 2 bits of the address 00-11) *) For 16/8-bit devices, use the data bus on the MSB side of this LSI. 0 D00 D15 1 D08 D07 D00 *) 16-bit device (low-order 1 bit of the address 0/1) 0 D07 D00 *) 8-bit device 181 CHAPTER 4 EXTERNAL BUS INTERFACE 4.4.2 Little Endian Bus Access Little endian (LER) external bus access is performed for an area for which the little endian method is set. Little endian bus access on the MB91307 series is implemented by using the bus access operation used for the big endian method. Basically, the order of output addresses and control signal output are the same as for the big endian method and the byte locations on the data bus are swapped in accordance with the bus width. Note that, when a connection is made, the big endian area and the little endian area must be kept physically separate. ■ Differences between Little Endian and Big Endian The following explains the differences between little endian and big endian. The order of addresses that are output is the same for little endian and big endian. The data bus control signal used for 16/8-bit bus width is the same for little endian and big endian. ❍ Word access The byte data on the MSB side for big endian address "00" becomes byte data on the LSB side when the little endian method is used. For a word address, the locations of all four bytes in the word are reversed: "00" → "11", "01" → "10", "10" → "01", "11" → "00" ❍ Halfword access The byte data on the MSB side for the big endian address "0" becomes byte data on the LSB side when the little endian method is used. For halfword access, the byte locations of 2 bytes are reversed. "0" → "1", "1" → "0" ❍ Byte access There is no difference between little endian and big endian. ■ Restrictions on the Little Endian Area 182 • If prefetch is enabled for a little endian area, always use word access to access the area. If data written to the prefetch buffer is accessed with any length other than word length, the correct endian conversion is not performed and the wrong data will be read. The reason is hardware restrictions related to the endian conversion mechanism. • Do not place any instruction code in a little endian area. CHAPTER 4 EXTERNAL BUS INTERFACE ■ Data Format The relationship between the internal register and external data bus is as follows: Figure 4.4-11 Relationship between the Internal Register and External Data Bus for Word Access (1) Word access (when executing the LD/ST instructions) Internal register D31 AA D23 BB D15 CC D7 DD D0 External bus D31 DD D23 CC D15 BB D7 AA D0 Figure 4.4-12 Relationship between Internal Register and External Data Bus for Halfword Access (2) Halfword access (when executing the LDUH/STH instructions) a) Output address low-order digits "00" Internal register External bus D31 Internal register External bus D31 D31 D31 D23 D23 D23 D15 D15 BB D23 b) Output address low-order digits "10" AA D15 AA D7 D7 D0 BB BB AA D7 BB D0 D15 AA D0 D7 D0 Figure 4.4-13 Relationship between Internal Register and External Data Bus for Byte Access (3) Byte access (when executing the LDUB/STB instructions) a) Output address b) Output address c) Output address d) Output address low-order digits "00" low-order digits "01" low-order digits "10" low-order digits "11" Internal External Internal External Internal External Internal External register bus register bus register bus register bus D31 D31 D31 D31 D31 D31 D31 D31 AA D23 D23 D23 D23 D23 D23 D23 D23 AA D15 D15 D15 D15 D15 D15 D15 D15 AA D7 D7 D7 D7 D7 D7 D7 D7 AA AA AA AA AA D0 D0 D0 D0 D0 D0 D0 D0 183 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Data Bus Width The following shows the relationships between the internal register and external data bus for each data bus width. ❍ 16-bit bus width Figure 4.4-14 Relationship between Internal Register and External Bus Data for 16-bit Bus Width Internal register Output address low-order digits D31 AA read/write D23 BB D15 CC D07 DD External bus "00" "10" DD BB CC AA D31 D23 ❍ 8-bit bus width Figure 4.4-15 Relationship between the Internal Register and External Data Bus in the 8-bit Bus Width Internal register Output address low-order digits External bus "00" "01" D31 D23 184 AA BB D15 CC D07 DD read/write DD CC "10" "11" BB AA D31 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Examples of Connection with External Devices The following shows examples of connecting the MB91307 series to external devices for each bus width. ❍ 16-bit bus width Figure 4.4-16 Example of Connecting the MB91307 Series to External Devices (16-Bit Bus Width) This LSI D31 W D23 W | R | R D24 0 D16 0 X X 0 1 D15 D08 D07 D00 big endian area 0 1 D15 D08 D07 D00 little endian area 185 CHAPTER 4 EXTERNAL BUS INTERFACE ❍ 8-bit bus width Figure 4.4-17 Example of Connecting the MB91307 Series to External Devices (8-Bit Bus Width) This LSI D31 W | R D24 0 X D07 D00 big endian area 186 D07 D00 little endian area CHAPTER 4 EXTERNAL BUS INTERFACE 4.4.3 Comparison of Big Endian and Little Endian External Access This section shows a comparison of big endian and little endian external access in word access, halfword access, and byte access for each bus width. ■ Word Access Big endian mode 16-bit bus width Internal External Reg terminal address: "0" "2" D31 D31 AA AA CC BB D16 BB DD Little endian mode Control terminal WR0 Internal External Reg terminal address: "0" "2" D31 WR1 8-bit bus width CC DD AA BB WR0 CC AA WR1 D16 D16 D31 D00 (2) AA BB CC DD Control terminal WR0 (1) (2) Internal External Reg terminal address: "0" "1" "2" "3" D31 D24 AA D31 D24 DD CC BB AA Control terminal WR0 BB CC CC DD DD D00 DD BB DD (1) Internal External Reg terminal address: "0" "1" "2" "3" D31 D31 BB CC D00 AA Control terminal (1) (2) (3) (4) D00 (1) (2) (3) (4) 187 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Halfword Access Big endian mode 16-bit bus width Internal External Reg terminal address: "2" D31 D31 D16 Little endian mode Control terminal AA WR0 BB WR1 Internal External Reg terminal address: "0" D31 D16 AA BB Internal External Reg terminal address: "2" D31 Control terminal CC WR0 DD WR1 D31 D31 Control terminal CC WR0 DD WR1 D16 CC DD DD D00 D00 (1) Internal External Reg terminal address: "0" "1" D31 D31 AA BB D24 Control terminal WR0 (1) Internal External Reg terminal address: "0" "1" D31 D31 BB AA D24 AA 188 WR1 Internal External Reg terminal address: "2" CC BB A (1) D16 D00 WR0 BB D00 (1) D31 B AA D00 8-bit bus width D31 Control terminal AA D00 (1) (2) D00 BB D00 (1) (2) Control terminal WR0 CHAPTER 4 EXTERNAL BUS INTERFACE Big endian mode 8-bit bus width Internal External Reg terminal address: "2" "3" D31 D31 CC DD D24 Little endian mode Control terminal WR0 Internal External Reg terminal address: "2" "3" D31 D31 DD CC D24 CC D00 DD Control terminal WR0 CC D00 (1) (2) D00 DD D00 (1) (2) 189 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Byte Access Big endian mode 16-bit bus width Internal External Reg terminal address: "0" D31 D31 AA Little endian mode Control terminal WR0 Internal External Reg terminal address: "0" D31 D31 AA D16 AA D00 (1) Internal External Reg terminal address: "1" D31 D31 BB Control terminal (1) Internal External Reg terminal address: "1" D31 D31 BB WR1 Control terminal WR1 D16 D16 BB BB D00 D00 (1) Internal External Reg terminal address: "2" D31 D31 CC Control terminal WR0 (1) Internal External Reg terminal address: "2" D31 D31 CC D16 D16 CC 190 WR0 D16 AA D00 D00 Control terminal CC (1) D00 (1) Control terminal WR0 CHAPTER 4 EXTERNAL BUS INTERFACE Big endian mode 16-bit bus width Internal External Reg terminal address: "3" D31 D31 DD Little endian mode Control terminal Internal External Reg terminal address: "3" D31 D31 DD WR1 WR1 D16 D16 DD DD D00 8-bit bus width D00 (1) Internal External Reg terminal address: "0" D31 D31 AA Control terminal WR0 (1) Internal External Reg terminal address: "0" D31 D31 AA D24 Control terminal WR0 D24 AA AA D00 D00 (1) Internal External Reg terminal address: "1" D31 D31 BB Control terminal WR0 (1) Internal External Reg terminal address: "1" D31 D31 BB D24 Control terminal WR0 D24 BB BB D00 D00 (1) Internal External Reg terminal address: "2" D31 D31 CC Control terminal WR0 (1) Internal External Reg terminal address: "2" D31 D31 CC D24 Control terminal WR0 D24 CC D00 Control terminal CC (1) D00 (1) 191 CHAPTER 4 EXTERNAL BUS INTERFACE Big endian mode 8-bit bus width Internal External Reg terminal address: "3" D31 D31 DD Little endian mode Control terminal WR0 Internal External Reg terminal address: "3" D31 D31 DD D24 D24 DD D00 192 DD (1) D00 (1) Control terminal WR0 CHAPTER 4 EXTERNAL BUS INTERFACE 4.5 Operation of the Ordinary bus interface This section explains operation of the ordinary bus interface. ■ Ordinary Bus Interface For the ordinary bus interface, two clock cycles are the basic bus cycles for both read access and write access. The following operational phases of the ordinary bus interface are explained below with the use of a timing chart. • Basic timing (for successive accesses) • WE + byte control type • Read → write • Write → write • Auto-wait cycle • External wait cycle • Synchronous write enable output • CS delay setting • CS → RD/WE setup, RD/WE → CS hold setting • DMA fly-by transfer (I/O → memory) • DMA fly-by transfer (memory → I/O) 193 CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.1 Basic Timing This section shows the basic timing for successive accesses. ■ Basic Timing (For Successive Accesses) Figure 4.5-1 shows the operation timing for (TYP3 to TYP0 = 0000B, AWR = 0008H) Figure 4.5-1 Basic Timing (For Successive Accesses) MCLK A[24:0] #2 #1 AS CSn RD READ D[31:16] #1 #2 WRn WRITE D[31:16] 194 #1 #2 • AS is asserted for one cycle in the bus access start cycle. • A24 to A0 continues to output the address of the location of the start byte in word/halfword/ byte access from the bus access start cycle to the bus access end cycle. • If the W02 bit of the AWR0 to AWR7 registers is "0", CS0 to CS7 are asserted at the same timing as AS. For successive accesses, CS0 to CS7 are not negated. If the W00 bit of the AWR register is "0", CS0 to CS7 are negated after the bus cycle ends. If the W00 bit is "1", CS0 to CS7 are negated one cycle after bus access ends. • RD and WR0, WR1 are asserted from the 2nd cycle of the bus access. Negation occurs after the wait cycle of bits W15 to W12 of the AWR register is inserted. The timing of asserting RD and WR0, WR1 can be delayed by one cycle by setting the W01 bit of the AWR register to "1". However, depending on the internal state, the assertion of WR0, WR1 may not start in the 2nd cycle and may even be delayed if the W01 bit is set to "0". • If a setting is made so that WR0, WR1 is used like TYP3 to TYP0=0x0xB, WE is always "H". • For read access, D31 to D0 is read when MCLK rises in the cycle in which the wait cycle ended after RD was asserted. • For write access, data output to D31 to D0 starts at the timing at which WR0, WR1 are asserted. CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.2 Operation of WE + Byte Control Type This section shows the operation timing for the WE + byte control type. ■ Operation Timing of the WE + Byte Control Type Figure 4.5-2 shows the operation timing for (TYP3 to TYP0 = 0010B, AWR = 0008H). Figure 4.5-2 Timing Chart for the WE + Byte Control Type MCLK A[24:0] AS CSn RD WR0 READ WR1 D[31:16] WE WR0 WRITE WR1 D[31:16] • Operation of AS, CSn, RD, A24 to A0, and D31 to D16 is the same as that described in "4.5.1 Basic Timing". WE is asserted from the 2nd cycle of the bus access. Negation occurs after the wait cycle of bits W15 to W12 of the AWR register is inserted. The timing of asserting RD and WR0, WR1 can be delayed by one cycle by setting the W01 bit of the AWR register to "1". However, depending on the internal state, assertion of WR0, WR1 may not start in the 2nd cycle and may even be delayed if the W01 bit is set to "0". (Operation is the same as that for WR0, WR1 described in "4.5.1 Basic Timing".) • WR0, WR1 indicate the byte location expressed with negative logic when they are used for access as the byte enable signal. Assertion continues from the bus access start cycle to the 195 CHAPTER 4 EXTERNAL BUS INTERFACE bus access end cycle and changes at the same timing as the address timing. The byte location for access is indicated for both read access and write access. • 196 For write access, data output to D31 to D16 starts at the timing at which WE is asserted. If the areas defined by TYP3 to TYP0=0x0xB (WR0, WR1 used) and TYP3 to TYP0=0x1xB (WE + byte control) are mixed, be sure to make the following setting for all areas that will be used. (For details, see "4.12 Notes on Using the External Bus Interface"). • Set at least one read → write idle cycle. • Set write recovery cycle to "1" or more. CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.3 Read → Write Operation This section shows the operating timing for read → write. ■ Operation Timing of Read → Write Figure 4.5-3 shows the operation timing for (TYP3 to TYP0=0000B, AWR=0048H). Figure 4.5-3 Timing Chart for Read → Write Read Idle* Write MCLK A[24:0] AS CSn RD WRn D[31:16] • Setting of the W07/W06 bits of the AWR register enables 0 to 3 idle cycles to be inserted. • Settings in the CS area on the read side are enabled. • This idle cycle is inserted if the next access after a read access is write access or access to another area. 197 CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.4 Write → Write Operation This section shows the operation timing for write → write. ■ Write → Write Operation Figure 4.5-4 shows the operation timing for (TYP3 to TYP0=0000B, WR=0018H). Figure 4.5-4 Timing Chart for the Write → Write Operation Read Write recovery * Write MCLK A[24:0] AS CSn WRn D[31:16] 198 • Setting of the W05/W04 bits of the AWR register enables 0 to 3 write cycles to be inserted. • After all of the write cycles, recovery cycles are generated. • Write recovery cycles are also generated if write access is divided into phases for access with a bus width wider than that specified. CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.5 Auto-Wait Cycle This section shows the operation timing for the auto-wait cycle. ■ Auto-Wait Cycle Timing Figure 4.5-5 shows the operation timing for (TYP3 to TYP0=0000B, AWR=2008H). Figure 4.5-5 Timing Chart for the Auto-Wait Cycle Basic cycle Wait cycle * MCLK A[24:0] AS CSn RD D[31:16] WRn D[31:16] Setting of the W15 to W12 bits (first wait cycles) of the AWR register enables 0 to 15 auto-wait cycles to be set. In Figure 4.5-5, two auto-wait cycles are inserted, making a total of four cycles for access. If auto-wait is set, the minimum number of bus cycles is 2 cycles + (first wait cycles). For a write operation, the minimum number of bus cycles may be still longer depending on the internal state. 199 CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.6 External Wait Cycle This section shows the operation timing for the external wait cycle. ■ External Wait Cycle Timing Figure 4.5-6 shows the operation timing for (TYP3 to TYP0=0001B, AWR=2008H). Figure 4.5-6 Timing Chart for the External Wait Cycle Basic cycle 2 auto-wait cycles Wait cycle by RDY MCLK A[24:0] AS CSn RD D[31:16] WR1 D[31:16] Release RDY Wait Setting "1" for the TYP0 bit of the ACR register and enabling the external RDY input pin enables external wait cycles to be inserted. 200 CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.7 Synchronous Write Enable Output This section shows the operation timing for synchronous write enable output. ■ Operation Timing for Synchronous Write Enable Output Figure 4.5-7 shows the operation timing for (TYP3 to TYP0=0000B, AWR=0000H). Figure 4.5-7 Timing Chart for Synchronous Write Enable Output MCLK A[31:16] #2 #1 AS CSn RD Read D[31:16] #1 #2 WRn Write D[31:16] #1 #2 • If synchronous write enable output is enabled (If the W03 bit of the AWR is "1"), operation is as follows. • WR0, WR1 and WE pin output asserts synchronous write enable output at the timing at which AS pin output is asserted. For a write to an external bus, the synchronous write enable output is "L". For a read from an external bus, the synchronous write enable output is "H". • Write data is output from the external data output pin in the clock cycle following the cycle in which synchronous write enable output is asserted. If write data cannot be output because the internal bus is temporarily unavailable, assertion of synchronous write enable output may be extended until write data can be output. • Read strobe output (RD) functions as an asynchronous read strobe regardless of the setting of WR0, WR1 and WE output timing. Use it as is for controlling the data I/O. 201 CHAPTER 4 EXTERNAL BUS INTERFACE • If synchronous write enable output is used, the following restrictions apply: Do not set the following additional wait because the timing for synchronous write enable output becomes meaningless: - CS → RD/WE setup (Always write "0" to the W01 bit of AWR) - First wait cycle setting (Always write "0000" to bits W15 to W12 of AWR) Do not set the following access types (TYPE3 to TYPE0 bits (Bits 3 to 0) in the ACR register) because the timing for synchronous write enable output becomes meaningless: - Multiplex bus setting (Always write "0" to the TYPE2 bit of ACR) - RDY input enable setting (Always write "0" to the TYPE0 bit of ACR) • 202 For synchronous write enable output, always set 1(00B for bits BST1, BST0 bits of ACR) as the burst length. CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.8 CS Delay Setting This section shows the operation timing for the CS delay setting. ■ Operation Timing for the CS Delay Setting Figure 4.5-8 shows the operation timing for (TYP3 to TYP0=0000B, AWR=000CH). Figure 4.5-8 Operation Timing Chart for the CS Delay Setting MCLK A[24:0] AS CSn RD READ D[31:16] WRn WRITE D[31:16] If the W02 bit is "1", assertion starts in the cycle following the cycle in which AS is asserted. For successive accesses, a negation period is inserted. 203 CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.9 CS → RD/WE Setup and RD/WE → CS Hold Setting This section shows the operation timing for the CS → RD/WE setup and RD/WE → CS hold settings. ■ Operation Timing for the CS → RD/WE Setup and RD/WE → CS Hold Settings Figure 4.5-9 shows the operation timing for (TYP3 to TYP0=0000B AWR=000BH). Figure 4.5-9 Timing Chart for the CS → RD/WE Setup and RD/WE → CS Hold Settings MCLK A[24:0] AS CSn CS->RD/WR Delay RD/WR->CS Delay RD READ D[31:16] WRn WRITE D[31:16] 204 • Setting "1" for the W01 bit of the AWR register enables the CS → RD/WE setup delay to be set. Set this bit to extend the period between chip select assertion and read/write strobe. • Setting "1" for the W00 bit of the AWR register enables the RD/WE → CS hold delay to be set. Set this bit to extend the period between read/write strobe negation and chip select negation. • The CS → RD/WE setup delay (W01 bit) and RD/WE → CS hold delay (W00 bit) can be set independently. • When making successive accesses within the same chip select area without negating the chip select, neither a CS → RD/WE setup delay nor an RD/WE → CS hold delay is inserted. • If a setup cycle for determining the address or a hold cycle for determining the address is needed, set "1" for the address → CS delay setting (W02 bit of the AWR register). CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.10 DMA Fly-By Transfer (I/O → Memory) This section shows the operation timing for DMA fly-by transfer (I/O → memory). ■ Operation Timing for DMA Fly-By Transfer (I/O → Memory) Figure 4.5-10 shows the operation timing for (TYP3 to TYP0=0000B, AWR=0008H, IOWR=51H). This timing chart shows a case in which a wait is not set on the memory side. Figure 4.5-10 Timing Chart for DMA Fly-By Transfer (I/O → Memory) Basic cycle I/O wait I/O hold I/O idle cycle * wait * cycle Basic cycle I/O wait I/O hold cycle * wait * MCLK A[24:0] AS CSn WRn D[31:16] DACKn (IORD) • Setting "1" for the HLD bit of the IOWR0 to IOWR2 registers enables the I/O read cycle to be extended by one cycle. • Setting bits IW3 to IW0 of the IOWR0 to IOWR2 registers enables 0 to 15 wait cycles to be inserted. • If wait is also set on the memory side (AWR15 to AWR12 is not "0"), the larger value is used as the wait cycle after comparison with the I/O wait (IW3 to IW0 bits). 205 CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.11 DMA Fly-By Transfer (Memory → I/O) This section shows the operation timing for DMA fly-by transfer (memory → I/O). ■ Operation Timing for DMA Fly-By Transfer (Memory → I/O) Figure 4.5-11 shows the operation timing chart for (TYP3 to TYP0=0000B, AWR=0008H, IOWR=51H). This timing chart shows a case in which a wait is not set on the memory side. Figure 4.5-11 Timing Chart for DMA Fly-By Transfer (Memory → I/O) Basic cycle I/O wait I/O hold I/O idle cycle *1 wait *2 cycle Basic cycle I/O wait I/O hold cycle *1 wait *2 MCLK A[24:0] AS CSn RD D[31:16] DACKn (IOWR) 206 • Setting "1" for the HLD bit of the IOWR0 to IOWR2 registers enables the I/O read cycle to be extended by one cycle. • Setting the WR1, WR0 bits of the IOWR0 to IOWR2 registers enables 0 to 3 write recovery cycles to be inserted. • If the write recovery cycle is set to "1" or more, a write recovery cycle is always inserted after write access. • Setting bits IW3 to IW0 of the IOWR0 to IOWR2 registers enables 0 to 15 wait cycles to be inserted. • If wait is also set on the memory side (AWR15 to AWR12 is not "0"), the larger value is used as the wait cycle after comparison with the I/O wait (IW3 to IW0 bits). CHAPTER 4 EXTERNAL BUS INTERFACE 4.6 Burst Access Operation In the external bus interface, the operation that transfers successive data items in one access sequence is called burst access. The normal access cycle (that is, not burst access) is called single access. One access sequence starts with an assertion of AS and CS and ends with negation of CS. Multiple data items two or more units of data of the unit set for the area. This section explains burst access operation. ■ Burst Access Operation Figure 4.6-1 shows the operation timing chart for (first wait cycle=1, inpage access wait cycle=1, TYP3 to TYP0=0000B, AWR=3208H). Figure 4.6-1 Timing Chart for Burst Access First cycle wait *1 Inpage access wait *2 Inpage access wait Inpage access wait MCLK A[24:0] AS (LBA) CSn RD WRn WR WRn BAA D[31:16] • In addition to more efficient use of access cycles when a sizable amount of data of asynchronous memory such as page mode ROM and burst flash memory is read, burst cycles can also be used for reading from normal asynchronous memory. • The access sequence when burst cycles are used can be divided into the following two types: - First access cycle The first access cycle is the start cycle for the burst access and operates in the same way as the normal single access cycle. 207 CHAPTER 4 EXTERNAL BUS INTERFACE - Page access cycle The page access cycle is a cycle following the first access cycle in which both CS and RD (read strobe) are asserted. Wait cycles that are different from those set for a single cycle can be set. The page access cycle is repeated while access remains in the address boundary determined by the burst length setting. When access within the address boundary ends, burst access terminates and CS is negated. 208 • Setting of the W15 to W12 bits of the AWR register enable the first 0 to 15 wait cycles to be inserted. At this point, the minimum number of the first access cycles is the wait cycles + 2 cycles (three cycles in the timing chart shown in Figure 4.6-1). • Setting of the W11 to W08 bits of the AWR register enables 0 to 15 page wait cycles to be inserted. At this point, the page access cycles can be obtained from the page wait cycles + 1 cycle (Two cycles in the timing chart shown in Figure 4.6-1). • Setting of the BST bits of the ACR register enables the burst length to be set as 1, 2, 4, or 8. If the burst length is set to "1", single access mode is set and only the first cycle is repeated. However, if the data bus width is set to 32 bits (the BST bits of the ACR register are "10B"), set the burst length to "4" or less (A malfunction occurs if the burst length is set to "8"). • If burst access is enabled, burst access is used when prefetch access or transfer with a larger size than the specified data bus width is performed. For example, if word access to an area whose data bus width is set to 8 bits and burst length to "4" is performed, access of 4 bursts is performed once instead of repeating byte access four times. • Since RDY input is ignored in areas for which burst access is set, do not set TYP3 to TYP0=0xx1B. • The LBA and BAA signals are designed for burst Flash memory. LBA indicates the start of access and BAA indicates the address increment. • A24 to A0 is updated after the wait cycles that were set during burst access. CHAPTER 4 EXTERNAL BUS INTERFACE 4.7 Address/data Multiplex Interface This section explains the following three cases of operation of the address/data multiplex interface: • Without external wait • With external wait • CS → RD/WE setup ■ Without External Wait Figure 4.7-1 shows the operation timing chart for (TYP3 to TYP0=0100B, AWR=0008H). Figure 4.7-1 Timing Chart for the Address/Data Multiplex Interface (without External Wait) MCLK A[24:0] address[31:0] AS CSn RD READ D[31:16] address[15:0] data[15:0] WE WRITE D[31:16] address[15:0] data[15:0] • Making a setting such as TYP3 to TYP0=01xxB in the ACR register enables the address/ data multiplex interface to be set. • If the address/data multiplex interface is set, set 8 bits or 16 bits for the data bus width (DBW1 to DBW0 bits). • In the address/data multiplex interface, the total of 3 cycles of 2 address output cycles + 1 data cycle becomes the basic number of access cycles. • In the address output cycles, AS is asserted as the output address latch signal. • As with a normal interface, the address indicating the start of access is output to A24 to A0 during the time division bus cycle. Use this address if you want to use an address more than 8/16 bits in the address/data multiplex interface. 209 CHAPTER 4 EXTERNAL BUS INTERFACE • As with the normal interface, auto-wait (AWR15 to AWR12), read → write idle cycle (AWR7, AWR6), write recovery (AWR5 to AWR4), address → CS delay (AWR2), CS → RD/WE setup delay (AWR1), and RD/WE → CS hold delay (AWR0) can be set. • In areas for which the address/data multiplex interface is set, set 1(DBW1, DBW0=00B) as the burst length. ■ With External Wait Figure 4.7-2 shows the operation timing chart for (TYP3 to TYP0=0101B, AWR=1008H). Figure 4.7-2 Timing Chart for the Address/Data Multiplex Interface (with External Wait) MCLK address[31:0] A[24:0] AS CSn RD READ D[31:16] address[15:0] data[15:0] WE WRITE D[31:16] address[15:0] data[15:0] Release RDY External wait Making a setting such as TYP3 to TYP0=01x1B in the ACR register enables RDY input in the address/data multiplex interface. 210 CHAPTER 4 EXTERNAL BUS INTERFACE ■ CS → RD/WE Setup Figure 4.7-3 shows the operation timing chart for (TYP3 to TYP0=0101B, AWR=100BH). Figure 4.7-3 Timing Chart for the Address/Data Multiplex Interface (CS → RD/WE Setup) MCLK A[24:0] address[31:0] AS CSn RD READ D[31:16] address[15:0] data[15:0] WE WRITE D[31:16] address[15:0] data[15:0] Setting "1" for the CS → RD/WE setup delay (AWR1) enables the multiplex address output cycle to be extended by one cycle as shown in Figure 4.7-3, allowing the address to be latched directly to the rising edge of AS. Use this setting if you want to use AS as an ALE (Address Latch Enable) strobe without using MCLK. 211 CHAPTER 4 EXTERNAL BUS INTERFACE 4.8 Prefetch Operation This section explains the prefetch operation. ■ Prefetch Operation The external bus interface controller contains a prefetch buffer consisting of 16 × 8 bits. If the PSUS bit of the TCR register is "0" and read access to an area to which the PFEN bit of the ACR register is set to "1" occurs, the subsequent address is prefetched and then stored in the prefetch buffer. If the stored address is accessed from the internal bus, the lookahead data in the prefetch buffer is returned without external access being performed. This can reduce the wait time for successive accesses to the external bus areas. ❍ Basic conditions for starting external access using prefetch External bus access using prefetch occurs when the following conditions are met: • The PSUS bit of the TCR register is "0". • Neither sleep mode nor stop mode is set. • Read access by the external bus to a chip select area for which prefetch is enabled has been performed. DMA access and read access by a read modified write system instruction, however, are excluded. • No external bus access request (external bus area access to an area for which prefetch is not enabled or DMA transfer with an external bus area) other than the prefetch access has occurred. • The part of the prefetch buffer for the next operation of capturing the prefetch access is completely empty. While the above conditions are met, the prefetch access will continue. If external bus area access to an area for which prefetch is not enabled occurs after prefetch access, prefetch access to the area for which prefetch is enabled will continue as long as the prefetch buffer clear conditions are not met. For an access that mixes multiple prefetch-enabled areas and multiple prefetch-disabled areas, the prefetch buffer always holds data of the prefetch-enabled area accessed last. Since, in this case, access to prefetch-disabled areas does not affect the prefetch buffer state at all, data in the prefetch buffer is not wasted even if prefetch-disabled data access and prefetch-enabled instruction fetch are mixed. ❍ Optional clear for temporary stopping of a prefetch access Setting "1" for the PSUS bit of the TCR register temporarily stops a prefetch. The prefetch can be restarted by setting the PSUS bit to "0". At this point, the contents of the buffer are retained if no error occurs or a buffer clear such as occurs when the PCLR bit is set does not occur. Setting "1" for the PCLR bit of the TCR register completely clears the prefetch buffer. Clear the buffer by setting the PSUS bit when prefetch is interrupted. Prefetch is temporarily stopped for the minimum unit (64 KB) of the boundary=chip select area where the high-order 16 bits of an address change. If the boundary is crossed, first a buffer read error occurs and then prefetch starts in a new area. 212 CHAPTER 4 EXTERNAL BUS INTERFACE ❍ Unit for one prefetch access operation The unit for one prefetch access operation is determined by the DBW bits (bus width) and BST bits (burst length). Prefetch access always occurs with the full size of the bus width specified by the DBW bits and access for the count of the burst length set by the BST bits in one access operation is performed. That is, if any value other than "00B" is set for the BST bits, the prefetch always occurs in page mode/burst mode. Keep in mind whether ROM/RAM is conformable and enough access time is applicable. (Set an appropriate value bits W15 to W08 bits of the AWR register). During burst access, successive accesses occur only within the address boundary that is determined by the burst length. Thus, if the boundary is crossed, for example, 4 bytes of free space are available in the buffer, these 4 bytes cannot be accessed in one operation (If the prefetch buffer starts at xxxxxx0EH, 4 bytes of free space are available in the buffer, and two bursts are set even though the bus width is 16 bits, only 2 bytes, xxxxxx0EH and xxxxxx0FH, can be captured in the next prefetch access). The following provides two examples: • Area whose bus width is set to 16 bits and whose burst length is set to "2" The amount of data read into the buffer in one prefetch operation is 4 bytes. In this case, prefetch access is delayed until 4 bytes of free space are available in the prefetch buffer. • Area whose bus width is set to 8 bits and whose burst length is set to "8" The amount of data read into the buffer in one prefetch operation is 8 bytes. In this case, prefetch access is delayed until 8 bytes of free space are available in the prefetch buffer. ❍ Burst length setting and prefetch efficiency If requests for external bus access, other than prefetch access, or errors in the prefetch buffer occur during one operation of prefetch access as explained in the previous bullet, "Unit of one prefetch access operation," these access requests must wait until access to the prefetch buffer that is being executed is completed. Thus, if the burst length is too long, the efficiency and reaction of bus access other than prefetch may be degraded. If, on the other hand, the burst length is set to "1", many read cycles may be wasted even if burst/page access memory is connected because single access is always performed. If settings are made so that the amount of data read in one prefetch access operation is large, prefetch access can be started only after free space in the prefetch buffer for this amount is available. Thus, access to the prefetch buffer is infrequent, and the external bus tends to be idle. For example, if the bus width is set to 16 bits and the burst length is set to "8", the amount of data read into the buffer in one prefetch operation is 16 bytes. Thus, a new prefetch access can be started only after the prefetch buffer is completely empty. Adjust the optimum burst length to suit use and the environment after taking the above into consideration. Generally, when connecting asynchronous memory to which burst/page access cannot be applied, it is best to set the burst length to "1" (single access). Conversely, when memory whose burst/page access cycle is short is connected, it is better to set the burst length to any value other than "1" (single access). In this case, it is best to make the setting so that 8 bytes (half of the buffer) are read in one read operation according to the bus width. However, the optimum condition varies with the frequency of external access and varies with the frequency divide-by rate setting of the external access clock. 213 CHAPTER 4 EXTERNAL BUS INTERFACE ❍ Reading from the prefetch buffer Data stored in the prefetch buffer is read in response to access from the internal bus if an address matches, and no external access is performed. In reading from the buffer, addresses can be hit (up to 16 bytes) if they are in the forward direction but not continuous, so that a second read from the external bus is avoided, if possible, even for a short forward branch. If the address currently being accessed for prefetch matches during access from the internal bus, a wait signal is returned internally before data is captured after prefetch access is completed. In this case, no buffer error occurs. If an address in the prefetch buffer matches when a read is performed for DMA transfer, data in the prefetch buffer is not used, and instead, external data is read by the external bus. In this case, a buffer error occurs. The prefetch is not continued and no prefetch access is performed until a new external access operation to a prefetch-enabled area occurs. ❍ Clearing/updating the prefetch buffer If either of the following conditions is met, the prefetch buffer is completely cleared: • If "1" is written to the PCLR bit of the TCR register • If a buffer read error occurs. A buffer read error is if any of the following events occurs: • • When no address is found in the buffer that matches in an to read from a prefetchenabled area. In this case, the external bus is accessed again. Data read in this case is not stored in the buffer, but the prefetch access is started from the subsequent address to store addresses in the buffer. • In an access to read from a prefetch-enabled area with a read modified system instruction. In this case, the external bus is accessed again. Data read in this case is not stored in the buffer. Also, no prefetch access is performed (This is because data is written to the next address). • In an access to read from a prefetch-enabled area for DMA transfer. In this case, the external bus is accessed again. Data read in this case is not stored in the buffer. Also, no prefetch access is performed. If a buffer write hit occurs. A buffer write hit is as follows: • When the address of just one byte that matches is found in the buffer in an access to write to a prefetch-enabled area. In this case, the external bus is accessed again, but no prefetch access is performed before a new read access occurs. Only part of the prefetch buffer is cleared when the following condition is met: • If a buffer read hit occurs In this case, only the part of the buffer before the hit address is cleared. ❍ Restrictions on prefetch-enabled areas If prefetch to a little endian area is enabled, be sure to access the area using word access. If data read into the prefetch buffer is accessed with any length other than word length, the correct endian conversion is not performed and thus the wrong data will be read. This is due to hardware restrictions related to the endian conversion mechanism. 214 CHAPTER 4 EXTERNAL BUS INTERFACE 4.9 DMA Access Operation This section explains DMA access operation. ■ DMA Access Operation This section explains the following five DMA operations: • DMA fly-by transfer (I/O → memory) • DMA fly-by transfer (memory → I/O) • 2-cycle transfer (internal RAM → external I/O, RAM) • 2-cycle transfer (external → I/O) • 2-cycle transfer (I/O → external) 215 CHAPTER 4 EXTERNAL BUS INTERFACE 4.9.1 DMA Fly-By Transfer (I/O → Memory) This section explains DMA fly-by transfer (I/O → memory). ■ DMA Fly-By Transfer (I/O → Memory) Figure 4.9-1 shows the operation timing chart for (TYP3 to TYP0=0000B, AWR=0008H, IOWR=41H). Figure 4.9-1 shows a case when a wait is not set on the memory side. Figure 4.9-1 Timing Chart for DMA Fly-By Transfer (I/O → Memory) Basic cycle I/O wait cycle *1 I/O hold wait *2 MCLK A[24:0] memory address AS CSn WRn D[31:16] DACKn FR30 compatible mode DEOPn Basic mode DACKn DEOPn IORD DREQn Sense timing in demand mode n = 0, 1, 2 *1: It can be set from 0 to 15 cycles as I/O wait cycles. *2: It can be set I/O hold wait ON/OFF. • 216 Setting "1" for the W01 bit of the AWR register enables the CS → RD/WE setup delay to be set. Set this bit to extend the period between assertion of chip select and the read/write strobe. CHAPTER 4 EXTERNAL BUS INTERFACE • Setting "1" for the W00 bit of the AWR register enables the RD/WE → CS hold delay to be set. Set this bit to extend the period between negation of the read/write strobe and negation of chip select. • The CS → RD/WE setup delay (W01 bit) and RD/WE → CS hold delay (W00 bit) can be set independently. • When successive accesses are made within the same chip select area without negating the chip select, neither CS → RD/WE setup delay nor RD/WE → CS hold delay is inserted. • If a setup cycle for determining the address or a hold cycle for determining the address is needed, set "1" for the address → CS delay setting (W02 bit of the AWR register). For I/O on the data output side, a read strobe of three bus cycles extended by the I/O wait cycle and I/O hold wait cycle is generated. For memory on the receiving side, a write strobe of two bus cycles extended by the I/O wait cycle is generated. The I/O hold wait cycle does not affect the write strobe. However, the address and CS signal are retained until the fly-by bus access cycles end. 217 CHAPTER 4 EXTERNAL BUS INTERFACE 4.9.2 DMA Fly-By Transfer (Memory → I/O) This section explains DMA fly-by transfer (memory → I/O). ■ DMA Fly-By Transfer (Memory → I/O) Figure 4.9-2 shows the operation timing chart for (TYP3 to TYP0=0000B, AWR=0008H, IOWR=41H). Figure 4.9-2 shows a case in which a wait is not set on the memory side. Figure 4.9-2 Timing chart for DMA Fly-By Transfer (Memory → I/O) I/O wait cycle *1 Basic cycle I/O hold wait *2 MCLK A[24:0] memory address AS CSn RD D[31:16] DACKn FR30 compatible mode DEOPn Basic mode DACKn DEOPn IORD DREQn Sense timing in demand mode n = 0, 1, 2 *1: It can be set from 0 to 15 cycles as I/O wait cycles. *2: It can be set I/O hold wait ON/OFF. • 218 Setting "1" for the HLD bit of the IOWR0 to IOWR2 registers extends the I/O read cycle by one cycle. CHAPTER 4 EXTERNAL BUS INTERFACE • Setting bits WR1, WR0 bits of the IOWR0 to IOWR2 registers enables 0 to 3 write recovery cycles to be inserted. • If the write recovery cycle is set to "1" or more, a write recovery cycle is always inserted after write access. • Setting bits IW3 to IW0 of the IOWR0 to IOWR2 registers enables 0 to 15 wait cycles to be inserted. • If wait is also set on the memory side (AWR15 to AWR12 is not "0"), the larger value is used as the wait cycle after comparison with the I/O wait (IW3 to IW0 bits). Reference: For memory on the data output side, a read strobe of three bus cycles extended by the I/O wait cycle and I/O hold wait cycle is generated. For I/O on the receiving side, a write strobe of two bus cycles extended by the I/O wait cycle is generated. The I/O hold wait cycle does not affect the write strobe. However, the address and CS signal are retained until the fly-by bus access cycles end. 219 CHAPTER 4 EXTERNAL BUS INTERFACE 4.9.3 2-Cycle Transfer (Internal RAM → External I/O, RAM) This section explains 2-cycle transfer (internal RAM → external I/O, RAM) operation. The timing is the same as for external I/O, RAM → internal RAM. ■ 2-Cycle Transfer (Internal RAM → External I/O, RAM) Figure 4.9-3 shows the operation timing chart for (TYP3 to TYP0=0000B, AWR=0008H, IOWR=00H). Figure 4.9-3 shows a case in which a wait is not set on the I/O side. Figure 4.9-3 Timing Chart for 2-cycle Transfer (Internal RAM → External I/O, RAM) Basic cycle MCLK A[24:0] I/O address AS CSn (I/O side) WRn D[31:16] FR30 compatible mode Basic mode DACKn DEOPn DACKn DEOPn DREQn Sense timing in demand mode n = 0, 1, 2 220 • The bus is accessed in the same way as an interface when DMAC transfer is not performed. • DACKn/DEOPn is not output in the internal RAM access cycles. CHAPTER 4 EXTERNAL BUS INTERFACE 4.9.4 2-Cycle Transfer (External → I/O) This section explains 2-cycle transfer (external → I/O) operation. ■ 2-Cycle Transfer (External → I/O) Figure 4.9-4 shows the operation timing chart for (TYP3 to TYP0=0000B, AWR=0008H, IOWR=00H). Figure 4.9-4 shows a case in which a wait is not set for memory and I/O. Figure 4.9-4 Timing Chart for 2-Cycle Transfer (External → I/O) Basic cycle Basic cycle MCLK A[24:0] Memory address Idle I/O address AS CSn RD CSn WRn D[31:16] FR30 compatible mode Basic mode DACKn DEOPn DACKn DEOPn DREQn n = 0, 1, 2 • The bus is accessed in the same way as an interface when the DMAC transfer is not performed. • In basic mode, DACKn/DEOPn is output in both transfer source bus access and transfer destination bus access. 221 CHAPTER 4 EXTERNAL BUS INTERFACE 4.9.5 2-Cycle Transfer (I/O → External) This section explains 2-cycle transfer (I/O → external) operation. ■ 2-Cycle Transfer (I/O → External) Figure 4.9-5 shows the operation timing chart for (TYP3 to TYP0=0000B, AWR=0008H, IOWR=00H). Figure 4.9-5 shows a case in which a wait is not set for memory and I/O. Figure 4.9-5 Timing Chart for 2-Cycle Transfer (I/O → External) Basic cycle Basic cycle MCLK A[24:0] I/O address Idle Memory address AS CSn WRn CSn RD D[31:16] DACKn FR30 compatible mode DEOPn Basic mode DACKn DEOPn DREQn n = 0, 1, 2 222 • The bus is accessed in the same way as an interface when the DMAC transfer is not performed. • In basic mode, DACKn/DEOPn is output both in the transfer source bus access and transfer destination bus access. CHAPTER 4 EXTERNAL BUS INTERFACE 4.10 Bus Arbitration This section shows timing charts for releasing the bus right and for acquiring the bus right. ■ Releasing the Bus Right Figure 4.10-1 shows the timing chart for releasing the bus right. Figure 4.10-2 shows the timing chart for acquiring the bus right. Figure 4.10-1 Timing Chart for Releasing the Bus Right MCLK A23-A0 AS CSn * Read RD D31-D16 BRQ BGRNT 1 cycle 223 CHAPTER 4 EXTERNAL BUS INTERFACE Figure 4.10-2 Timing Chart for Acquiring the Bus Right MCLK A23-A0 AS CSn Write WE D31-D16 BRQ BGRNT 1 cycle 224 • Setting "1" for the BREN bit of the TRC register enables bus arbitration by BRQ/BGRNT to be performed. • When the bus right is released, the pin is set to high impedance and then BGRNT is asserted one cycle later. • When the bus right is acquired, BGRNT is negated and then each pin is activated one cycle later. • CSn is set to high impedance only if the SREN bit in the ACR0 to ACR7 registers is set. • If all areas enabled by the CSER register are shared (the SREN bit of the ACR register is "1"), AS, BAA, RD, WE, and WR0, WR1 are set to high impedance. CHAPTER 4 EXTERNAL BUS INTERFACE 4.11 Procedure for Setting a Register This section explains the procedure for setting a register. ■ Procedure for Setting a Register Using the following procedures to make external bus interface settings: 1. Before rewriting the contents of a register, be sure to set the CSER register so that the corresponding area is not used ("0"). If you change the settings while "1" is set, access before and after the change cannot be guaranteed. 2. Use the following procedure to change a register: • Set "0" for the CSER bit corresponding to the applicable area. • Set both ASR and ACR at the same time using word access. When accessing ASR and ACR using halfword, please set ACR after setting ASR. • Set AWR. • Set the CHER bit corresponding to the applicable area. • Set the CSER bit corresponding to the applicable area. 3. The CS0 area is enabled after a reset is released. If the area is used as a program area, the register contents need to be rewritten while the CSER bit is "1". In this case, make the settings described in 2) to 4) above in the initial state with a low-speed internal clock. Then, switch the clock to a high-speed clock. 4. Use the following procedure to change the register value in an area for which prefetch: • Set "0" for the bit of CSER corresponding to the applicable area. • Set "1" for both the PSUS bit and PCLR bit of the TCR register. • Set both ASR and ACR at the same time using word access. When accessing ASR and ACR using halfword, please set ACR after setting ASR. • Set AWR. • Set the CHER bit corresponding to the applicable area. • Set "0" for both the PSUS bit and PCLR bit of the TCR register. • Set "1" for the bit of CSER corresponding to the applicable area. 225 CHAPTER 4 EXTERNAL BUS INTERFACE 4.12 Notes on Using the External Bus Interface This section explains some notes when using the external bus interface. ■ Notes for Use If settings are made so that the area (TYP3 to TYP0=0x0xB) where WR0, WR1 are used as a write strobe and the area (TYP3 to TYP0=0x1xB) where WE is used as a write strobe are mixed, be sure to make the following setting in all areas that will be used: • Set at least one read → write idle cycle (other than AWR W07, W06=00B). • Set at least one write recovery cycle (other than AWR W05, W04=00B). However, if WR0, WR1 are disabled (ROM only is connected) in the area (TYP3 to TYP0=0x0xB) where WR0, WR1 are used as a write strobe, the above restriction does not apply. Also, the above restriction does not apply if both the address → RD/WE setup cycle (W01=1) and RD/WE → address hold cycle (W00=1) are set in the area (TYP3 to TYP0=0x1xB) where WE is used as a write strobe. The reason for the restriction is explained below. In the area where WE is used as a write strobe by setting TYPE3 to TYP0=0x1xB, the WR0/ WR1 pin is set to byte enable (UUB/ULB) output. In this case, the byte enable output pin outputs the enable signal of each byte location at the same timing as that of the address and CS output. Thus, if an area where the WR0/WR1 pin is used as an asynchronous write strobe is accessed just before or after the current access, the AC standard between CS and WR0/WR1 cannot be satisfied in the area, possibly causing data to be written incorrectly. If the read → write idle cycle and write recovery cycle are set, the above AC standard can be satisfied because CS is not asserted ("H" level is maintained) in these cycles. This restriction is not needed if there is allowance for the AC standard (setup and hold) between CS and WR0/WR1 in the area where the WR0/WR1 pin is used as an asynchronous write strobe. 226 CHAPTER 5 I/O PORT This chapter describes the I/O ports and the configuration and functions of registers. 5.1 Overview of the I/O Port 5.2 I/O Port Registers 227 CHAPTER 5 I/O PORT 5.1 Overview of the I/O Port This section provides an overview of the I/O port. ■ Basic Block Diagram of the I/O Port The MB91307 series interface can be used as an I/O port if settings are made so that the external bus interface or peripherals corresponding to pins do not use the pins as input/output pins. Figure 5.1-1 shows the basic configuration of the I/O port. Figure 5.1-1 Basic Block Diagram of the I/O Port Peripheral input Port Bus 0 1 Peripheral output PDR 1 Pin 0 PFR DDR PDR: Port Data Register DDR: Data Drection Register PFR: Port Function Register The I/O port consists of PDRs (Port Data Registers), DDRs (Data Direction Registers), and PFRs (Port Function Registers). 228 CHAPTER 5 I/O PORT ■ I/O Port Modes The I/O port has the following three modes: ❍ Port input mode (PFR=0 & DDR=0) • PDR read: Reads the level of the corresponding external pin. • PDR write: Writes a setting value to the PDR. ❍ Port output mode (PFR=0 & DDR=1) • PDR read: Reads the value of the PDR. • PDR write: Outputs the value of the PDR to the corresponding external pin. ❍ Peripheral output mode (PFR=1 & DDR=x) • PDR read: Reads the value of the corresponding peripheral output. • PDR write: Writes a setting value to the PDR. Notes: • Use byte access to access the I/O port registers. • When a port from port 0 to port A (excluding Bit3 of the port 9) is used as an external bus pin, the external bus function has priority. Thus, if the DDR register is rewritten while the port is functioning as an external bus pin, no input/output switching occurs. The DDR register value is enabled when the pin is switched to a general-purpose pin by changing the PFR register. 229 CHAPTER 5 I/O PORT 5.2 I/O Port Registers This section describes the configuration and functions of the I/O port registers. ■ Configuration of the Port Data Registers (PDR) Shown below is the configuration of the port data registers (PDR). Figure 5.2-1 Configuration of the Port Data Registers (PDR) 230 PDR2 Address: 00000002H 7 P27 6 P26 5 P25 4 P24 3 P23 2 P22 1 P21 0 P20 Initial value XXXXXXXXB PDR6 Address: 00000006H 7 P67 6 P66 5 P65 4 P64 3 P63 2 P62 1 P61 0 P60 Initial value XXXXXXXXB PDR7 Address: 00000007H 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 P70 Initial value -------XB PDR8 Address: 00000008H 7 - 6 - 5 P85 4 - 3 - 2 P82 1 P81 0 P80 Initial value --X--XXXB PDR9 Address: 00000009H 7 P97 6 P96 5 P95 4 P94 3 P93 2 P92 1 P91 0 P90 Initial value XXXXXXXXB PDRA Address: 0000000AH 7 PA7 6 PA6 5 PA5 4 PA4 3 PA3 2 PA2 1 PA1 0 PA0 Initial value XXXXXXXXB PDRB Address: 0000000BH 7 PB7 6 PB6 5 PB5 4 PB4 3 PB3 2 PB2 1 PB1 0 PB0 Initial value XXXXXXXXB PDRG Address: 00000010H 7 - 6 - 5 - 4 - 3 - 2 PG2 1 PG1 0 PG0 Initial value -----XXXB PDRH Address: 00000011H 7 PH7 6 PH6 5 PH5 4 PH4 3 PH3 2 PH2 1 PH1 0 PH0 Initial value XXX00XXXB PDRI Address: 00000012H 7 - 6 - 5 PI5 4 PI4 3 PI3 2 PI2 1 PI1 0 PI0 Initial value --XXXXXXB PDRJ Address: 00000013H 7 PJ7 6 PJ6 5 PJ5 4 PJ4 3 PJ3 2 PJ2 1 PJ1 0 PJ0 Initial value XXXXXXXXB • PDR2 to PDRJ are the input/output data registers for the I/O port. • Input/output is controlled by the corresponding DDR0 to DDRJ and PFR6 to PFRJ. CHAPTER 5 I/O PORT ■ Configuration of the Data Direction Registers (DDR) Shown below is the configuration of the data direction registers (DDR). Figure 5.2-2 Configuration of the Data Direction Registers (DDR) DDR2 Address: 00000602H 7 P27 6 P26 5 P25 4 P24 3 P23 2 P22 1 P21 0 P20 Initial value 00000000B Access R/W DDR6 Address: 00000606H 7 P67 6 P66 5 P65 4 P64 3 P63 2 P62 1 P61 0 P60 Initial value 00000000B Access R/W DDR7 Address: 00000607H 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 P70 Initial value -------0B Access R/W DDR8 Address: 00000608H 7 - 6 - 5 P85 4 - 3 - 2 P82 1 P81 0 P80 Initial value --0--000B Access R/W DDR9 Address: 00000609H 7 P97 6 P96 5 P95 4 P94 3 P93 2 P92 1 P91 0 P90 Initial value 00000000B Access R/W DDRA Address: 0000060AH 7 PA7 6 PA6 5 PA5 4 PA4 3 PA3 2 PA2 1 PA1 0 PA0 Initial value 00000000B Access R/W DDRB Address: 0000060BH 7 PB7 6 PB6 5 PB5 4 PB4 3 PB3 2 PB2 1 PB1 0 PB0 Initial value 00000000B Access R/W DDRG Address: 00000400H 7 - 6 - 5 - 4 - 3 - 2 PG2 1 PG1 0 PG0 Initial value -----000B Access R/W DDRH Address: 00000401H 7 PH7 6 PH6 5 PH5 4 PH4 3 PH3 2 PH2 1 PH1 0 PH0 Initial value 00011000B Access R/W DDRI Address: 00000402H 7 - 6 - 5 PI5 4 PI4 3 PI3 2 PI2 1 PI1 0 PI0 Initial value --000000B Access R/W DDRJ Address: 00000403H 7 PJ7 6 PJ6 5 PJ5 4 PJ4 3 PJ3 2 PJ2 1 PJ1 0 PJ0 Initial value 00000000B Access R/W DDR2 to DDRJ control the input/output direction of the corresponding I/O port at the bit level. • • If PFR=0 • DDR=0: Port input • DDR=1: Port output If PFR=1 • DDR=0: Peripheral input • DDR=1: Peripheral output 231 CHAPTER 5 I/O PORT ■ Configuration of the Port Function Registers (PFR) The configuration of the port function registers (PFR) is as follows: Figure 5.2-3 Configuration of the Port Function Registers (PFR) PFR6 Address: 00000616H 7 6 5 4 3 2 1 0 A23E A22E A21E A20E A19E A18E A17E A16E Initial value 11111111B Access R/W PFR7 Address: 00000617H 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 A24E Initial value -------1B Access R/W PFR8 Address: 00000618H 7 - 6 - 5 WRXE 4 - 3 - 2 BRQE 1 - 0 - Initial value --1--0--B Access R/W PFR9 Address: 00000619H 7 WEXE 6 - 5 4 3 2 1 0 BAAE ASXE MCIN MCKE MCEE SYSE Initial value 0-001101B Access R/W PFRA Address: 0000061AH 7 6 5 4 3 2 1 0 CS7E CS6E CS5E CS4E CS3E CS2E CS1E CS0E Initial value 11111111B Access R/W PFRB1 Address: 0000061BH 7 6 5 4 3 2 1 0 DES1 AK12 AK11 AK10 DES0 AK02 AK01 AK00 Initial value 00000000B Access R/W PFRB2 Address: 0000061CH 7 6 DRDE DWRE Initial value 00------B Access R/W Initial value ----0000B Access R/W 0 - Initial value 0000000-B Access R/W 0 - Initial value --00-00-B Access R/W PFRG Address: 00000410H PFRH Address: 00000411H PFRI Address: 00000412H 7 - 6 - 5 - 4 - 5 - 4 - 3 - 2 - 1 - 3 2 1 0 DES2 AK22 AK21 AK20 7 6 5 4 3 2 1 TEST I2CE TOE2 TOE1 TOE0 SCE2 SOE2 7 - 6 - 5 4 SCE1 SOE1 0 - 3 - 2 1 SCE0 SOE0 PFR6 to RFRI control the output of the corresponding external bus interface and peripherals at the bit level. Note: Be sure to set "0" for Bit7 (TEST) of PFRH. 232 CHAPTER 5 I/O PORT ■ Function of the Port Function Registers (PFR) The following table summarizes the initial values and functions of the PFR registers. Table 5.2-1 Functions of the Port Function Registers (PFR) (1/5) Register name PFR6(A16E to A23E) [P60/A16 to P67/A23] Bit name A16E A17E A18E A19E A20E A21E A22E A23E PFR7(A24) [P70/A24] A24E − PFR8(BRQE) [P81/BGRNT,P82/BRQ] PFR8(WRXE) [P85/WR1/ULB] PFRA(CS0E) [PA0/CS0] PFRA(CS1E) [PA1/CS1] PFRA(CS2E) [PA2/CS2] BRQE WRXE CS0E CS1E CS2E Bit value Function 0 General-purpose port 1 Address output (initial value) 0 General-purpose port 1 Address output (initial value) 0 General-purpose port 1 Address output (initial value) 0 General-purpose port 1 Address output (initial value) 0 General-purpose port 1 Address output (initial value) 0 General-purpose port 1 Address output (initial value) 0 General-purpose port 1 Address output (initial value) 0 General-purpose port 1 Address output (initial value) 0 General-purpose port 1 Address output (initial value) − None (BGRNT-dedicated pin if bit P82 is set as the BRQ pin) 0 General-purpose port 1 BRQ 0 General-purpose port 1 WR1 output 0 General-purpose port 1 CS output (initial value) 0 General-purpose port 1 CS output (initial value) 0 General-purpose port 1 CS output (initial value) 233 CHAPTER 5 I/O PORT Table 5.2-1 Functions of the Port Function Registers (PFR) (2/5) Register name Bit name PFRA(CS3E) [PA3/CS3] PFRA(CS4E) [PA4/CS4] PFRA(CS5E) [PA5/CS5] PFRA(CS6E) [PA6/CS6] PFRA(CS7E) [PA7/CS7] PFR9(SYSE) [P90/SYSCLK] PFR9(MCEE) [P91] PFR9(MCKE) [P92/MCLK] PFR9(MCIN),DDR9(P93) CS3E CS4E CS5E CS6E CS7E SYSE MCEE MCKE MCIN,P93 [P93] PFR9(ASXE) [P94/AS/LBA] PFR9(BAAE) [P95/BAA] PFRA(WEXE) [P97/WE] 234 ASXE BAAE WEXE Bit value Function 0 General-purpose port 1 CS output (initial value) 0 General-purpose port 1 CS output (initial value) 0 General-purpose port 1 CS output (initial value) 0 General-purpose port 1 CS output (initial value) 0 General-purpose port 1 CS output (initial value) 0 General-purpose port 1 Set to "1" to use SYSCLK output. (initial value) 0 General-purpose port (initial value) 1 Setting disabled 0 General-purpose port 1 Set to "1" to use memory clock output. (initial value) 0,0 Setting disabled 0,1 Setting disabled 1,0 General-purpose input port. The internal clock (MCLK) is input as MCLK. (initial value) 1,1 General-purpose output port. The internal clock (MCLK) is input as MCLK. 0 General-purpose port (initial value) 1 Set to use general-purpose memory/burst mode memory. 0 General-purpose port (initial value) 1 Set to use burst mode memory. 0 General-purpose port (initial value) 1 Set to use 16-bit memory. CHAPTER 5 I/O PORT Table 5.2-1 Functions of the Port Function Registers (PFR) (3/5) Register name PFRB1(AK02,01,00) [PB1/DACK0] PFRB1(DES0),DDRB(PB2) [PB2/DEOP0] PFRB1(AK12,AK11,AK10) [PB4/DACK1] PFRB1(DES1),DDRB(PB5) [PB5/DEOP1] PFRB2(DWRE) [PB6/IOWR] PFRB2(DRDE) [PB7/IORD] Bit name Bit value AK02, AK01, AK00 * 0,0,0 General-purpose port (initial value) 0,0,1 DACK0 output (FR30-compatible for fly-by transfer) 0,1,0 DACK0 output (FR30-compatible for two-cycle transfer RD timing) 1,0,0 DACK0 output (FR30-compatible for two-cycle transfer WE timing) 1,1,0 DACK0 output (FR30-compatible for two-cycle transfer WE/RD timing) 1,1,1 DACK0 output (chip select timing) DES0, PB2 AK12, AK11, AK10 * DES1, PB5 DWRE DRDE Function 0,0 General-purpose port input (initial value) 0,1 General-purpose port output 1,0 DMAC: DSTP0 input 1,1 DMAC: DEOP0 output 0,0,0 General-purpose port (initial value) 0,0,1 DACK1 output (FR30-compatible for fly-by transfer) 0,1,0 DACK1 output (FR30-compatible for two-cycle transfer RD timing) 1,0,0 DACK1 output (FR30-compatible for two-cycle transfer WE timing) 1,1,0 DACK1 output (FR30-compatible for two-cycle transfer WE/RD timing) 1,1,1 DACK1 output (chip select timing) 0,0 General-purpose port input (initial value) 0,1 General-purpose port output 1,0 DMAC: DSTP1 input 1,1 DMAC: DEOP1 output 0 General-purpose port (initial value) 1 IOWR output 0 General-purpose port (initial value) 1 IORD output 235 CHAPTER 5 I/O PORT Table 5.2-1 Functions of the Port Function Registers (PFR) (4/5) Register name PFRG(AK22,21,20) [PG1/DACK2] PFRG(DES2),DDRG(PG2) [PG2/DEOP2] PFRH(SOE2) [PH1/SO2] PFRH(SCE2) [PH2/SC2] PFRH(TOE0) [PH3/TOT0] PFRH(TOE1) [PH4/TOT1] PFRH(TOE2) [PH5/TOT2] PFRH(I2CE) [PH6/SDA,PH7/SCL] Bit name Bit value AK22, AK21, AK20 * 0,0,0 General-purpose port (initial value) 0,0,1 DACK2 output (FR30-compatible for fly-by transfer) 0,1,0 DACK2 output (FR30-compatible for two-cycle transfer RD timing) 1,0,0 DACK2 output (FR30-compatible for two-cycle transfer WE timing) 1,1,0 DACK2 output (FR30-compatible for two-cycle transfer WE/RD timing) 1,1,1 DACK2 output (chip select timing) DES2, PG2 SOE2 SCE2 TOE0 TOE1 TOE2 I2CE − PFRH(TEST) TEST PFRI(SOE0) [PI1/SO0] PFRI(SCE0) [PI2/SC0] 236 SOE0 SCE0 Function 0,0 General-purpose port input (initial value) 0,1 General-purpose port output 1,0 DMAC: DSTP2 input 1,1 DMAC: DEOP2 output 0 General-purpose port (initial value) 1 SO2 output 0 General-purpose port (initial value) 1 SC2 output 0 General-purpose port (initial value) 1 TOT0 output 0 General-purpose port (initial value) 1 TOT1 output 0 General-purpose port (initial value) 1 TOT2 output 0 Functions as a port. (initial value) 1 SDA input/output 0 If I2CE=0, the PH7 pin functions as a port. (initial value) 1 If I2CE=1, the PH7 pin functions as SDL I/O. 0 Be sure to set "0". (initial value) 1 Test function. Setting disabled. 0 General-purpose port (initial value) 1 SO0 output 0 General-purpose port (initial value) 1 SC0 output CHAPTER 5 I/O PORT Table 5.2-1 Functions of the Port Function Registers (PFR) (5/5) Register name PFRI(SOE1) [PI4/SO1] PFRI(SCE1) [PI5/SC1] Bit name SOE1 DWRE Bit value Function 0 General-purpose port (initial value) 1 SO1 output 0 General-purpose port (initial value) 1 SC1 output *: Refer to "CHAPTER 14 DMA CONTROLLER (DMAC)". The output timing of DEOP changes in synchronization with the setting of the DACK timing. 237 CHAPTER 5 I/O PORT 238 CHAPTER 6 16-BIT RELOAD TIMER This chapter describes the 16-bit reload timer, the configuration and functions of registers, and 16-bit reload timer operation. 6.1 Overview of the 16-bit Reload Timer 6.2 16-bit Reload Timer Registers 6.3 16-bit Reload Timer Operation 6.4 Operating States of the Counter 6.5 Precautions on Using the 16-bit Reload Timer 239 CHAPTER 6 16-BIT RELOAD TIMER 6.1 Overview of the 16-bit Reload Timer The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a prescaler for creating an internal count clock, and a control register. ■ Overview of the 16-bit Reload Timer The MB91307 series has three built-in channels, numbered 0 to 2, for the 16-bit reload timer. Channels 0 and 1 support the activation of DMA transfers resulting from interrupts. The input clock can be selected from three internal clocks (machine clock divided by 2, 8, and 32) and an external clock. The output pin (TOUT) outputs a toggle output waveform whenever an underflow occurs in reload mode and outputs a square wave that indicates that counting is in progress in one-shot mode. The input pin (TTG) can be used as the event input in external event count mode and as the trigger or gate input in internal clock mode. The external event count function, when used in reload mode, can be used as a divider for external clock mode. ■ Block Diagram Figure 6.1-1 is a block diagram of the 16-bit reload timer. Figure 6.1-1 Block Diagram of the 16-bit Reload Timer 16 R- bus 16-bit reload register 8 16 Reload 16-bit down counter UF 2 GATE Clock selector CSL1 CSL0 2 φ 21 φ 23 φ 25 Internal clock 3 240 EXCK OUT CTL. 2 Re-trigger IN CTL. Prescaler clear RELD OUTE OUTL INTE UF CNTE TRG Port (T1) 3 MOD0 MOD1 MOD2 Port (T0) IRQ CHAPTER 6 16-BIT RELOAD TIMER 6.2 16-bit Reload Timer Registers This section describes the configuration and functions of the registers used by the 16bit reload timer. ■ 16-bit Reload Timer Registers Figure 6.2-1 16-bit Reload Timer Registers 15 14 13 12 11 10 - - - - CSL1 CSL0 7 6 5 4 3 2 1 0 MOD0 - OUTL RELD INTE UF CNTE TRG 15 9 8 MOD2 MOD1 Control status register(TMCSR) 0 16-bit timer register (TMR) 15 0 16-bit reload register (TMRLR) 241 CHAPTER 6 16-BIT RELOAD TIMER 6.2.1 Control Status Register (TMCSR) The control status register (TMCSR) controls the operating modes and interrupts of the 16-bit timer. ■ Bit Configuration of the Control Status Register (TMCSR) Figure 6.2-2 Bit Configuration of the Control Status Register (TMCSR) TMCSR Address: 11 10 9 8 7 0000000EH CSL1 CSL0 MOD2 MOD1 MOD0 00000056H R/W R/W R/W R/W R/W 0000005EH 6 "0" R 5 4 3 OUTL RELD INTE R/W R/W R/W 2 1 0 UF CNTE TRG R/W R/W R/W Initial value 000000 000000B Rewrite bits other than the UF, CNTE, and TRG bits only when CNTE=0. The control status register (TMCSR) supports simultaneous writing. ■ Bit Functions of the Control Status Register (TMCSR) The following describes the bit functions of the control status register (TMCSR). [Bits 11, 10] CSL1, CSL0 (Count clock SeLect) These bits are the count clock select bits. Table 6.2-1 shows the clock sources that can be selected using these bits. Countable edges are set using the MOD1 and MOD0 bits when external event count mode are set. Table 6.2-1 Clock Sources Set Using the CSL Bits CSL1 CSL0 Clock source (φ: Machine clock) 0 0 φ/21 0 1 φ/23 1 0 φ/25 1 1 External clock (event) Note: The minimum pulse width required for an external clock is 2T (T: Peripheral clock machine cycle). 242 CHAPTER 6 16-BIT RELOAD TIMER [Bits 9, 8, 7] MOD2, MOD1, MOD0 (MODe) These bits set the operating modes and the functions of the input-output pins. The MOD2 bit selects the function of an input pin. If it is set to "0", the input pin becomes the trigger input pin. When a valid edge is then input, the contents of the reload register are loaded into the counter and the count operation is continued. If it is set to "1", gate count mode is entered and the input pin provides the gate input. While a valid level is input, the count operation is performed. The MOD1 and MOD0 bits set the functions of pins in various modes. Table 6.2-2 and Table 6.2-3 describe the settings of the MOD2, MOD1, and MOD0 bits. Table 6.2-2 Bit MOD2, 1, and 0 Setting Method 1 (in Internal Clock Mode (CSL0, 1=00, 01, 10)) MOD2 MOD1 MOD0 Input pin function Valid edge or level 0 0 0 Trigger disabled - 0 0 1 0 1 0 0 1 1 1 x 0 1 x 1 Rising edge Trigger input Falling edge Both edges Gate input "L" level "H" level Table 6.2-3 Bit MOD2, 1, and 0 Setting Method 2 (in Event Count Mode (CSL0, 1=11)) MOD2 x MOD1 MOD0 Input pin function Valid edge or level 0 0 - - 0 1 1 0 1 1 Rising edge Event input Falling edge Both edges Note: x in this table represents any value. [Bit 6] (reserved) This bit is reserved. The read value is always "0". 243 CHAPTER 6 16-BIT RELOAD TIMER [Bit 5] OUTL This bit sets the output level of the TOUT pin. The pin levels are reversed while this bit is set to "0" and "1". Specify an output waveform using a combination of this bit, bit 4 (RELD bit), and the corresponding bit of the PFR register of the I/O port. Table 6.2-4 shows the settings when these bits are combined. Table 6.2-4 Settings of OUTE, RELD, and OUTL MOD2 MOD1 MOD0 Output waveform 0 x x General-purpose port 1 0 0 H level square waves while counting is in progress 1 1 0 L level square waves while counting is in progress 1 0 1 L level toggle output when the counter is started 1 1 1 H level toggle output when the counter is started Note: PFR is the corresponding bit of the PFR register of the I/O port. [Bit 4] RELD This bit is the reload enable bit. If it is set to "1", reload mode is entered. As soon as the counter value underflows from 0000H to FFFFH, the contents of the reload register are loaded into the counter and the count operation is continued. If this bit is set to "0", the count operation is stopped when the counter value underflows from 0000H to FFFFH. [Bit 3] INTE This bit is the interrupt request enable bit. If the INTE bit is set to "1", an interrupt request is generated when the UF bit is set to "1". If it is set to "0", no interrupt request is generated. [Bit 2] UF This bit is the timer interrupt request flag. This bit is set to "1" when the counter value underflows from 0000H to FFFFH. Write "0" to this bit to clear it. Writing "1" to this bit is meaningless. When this bit is read by a read modify write instruction, "1" is always read. [Bit 1] CNTE This bit is the count enable bit of the timer. Write "1" to this bit to enter the start trigger wait state. Write "0" to this bit to stop the count operation. [Bit 0] TRG This bit is the software trigger bit. Write "1" to this bit to generate a software trigger, load the contents of the reload register into the counter, and start the count operation. Writing "0" to this bit is meaningless. The read value is always "0". The trigger input to this register is valid only if CNTE=1. No operation occurs if CNTE=0. 244 CHAPTER 6 16-BIT RELOAD TIMER 6.2.2 16-bit Timer Register (TMR) The 16-bit timer register (TMR) is a register to which the count value of the 16-bit timer can be read. The initial value is undefined. Be sure to read this register using a 16-bit data transfer instruction. ■ Bit Configuration of the 16-bit Timer Register (TMR) Figure 6.2-3 shows the bit configuration of the 16-bit timer register (TMR). Figure 6.2-3 Bit Configuration of the 16-bit Timer Register (TMR) TMR Initial value 0 ~ ~ ~ ~ 15 Address: 00004AH 000052H 00005AH R X R X R X R X ... ... R X R X R X R X R X 245 CHAPTER 6 16-BIT RELOAD TIMER 6.2.3 16-bit Reload Register (TMRLR) The 16-bit reload register (TMRLR) holds the initial value of a counter. The initial value is undefined. Be sure to write into this register using a 16-bit data transfer instruction. ■ Bit Configuration of the 16-bit Reload Register (TMRLR) Figure 6.2-4 shows the bit configuration of the 16-bit reload register (TMRLR). Figure 6.2-4 Bit Configuration of the 16-bit Reload Register (TMRLR) TMRLR Initial value 246 0 ~ ~ ~ ~ 15 Address: 000048H 000050H 000058H W X W X W X W X ... ... W X W X W X W X W X CHAPTER 6 16-BIT RELOAD TIMER 6.3 16-bit Reload Timer Operation This section describes the following operations of the 16-bit reload timer: • Internal clock operation • Underflow operation • Operation of the input pin function • Operation of the output pin function ■ Internal Clock Operation If the timer operates with a divide-by clock of the internal clock, one of the clocks created by dividing the machine clock by 2, 8, or 32 can be selected as the clock source. The external input pin can be used as the trigger or gate input depending on the register setting. To start the count operation as soon as counting is enabled, write "1" to the CNTE and TRG bits of the control status register. Trigger input occurring due to the TRG bit is always valid regardless of the operating mode while the timer is running (CNTE=1). Figure 6.3-1 shows the startup and operations of the counter. Time as long as T (T: peripheral clock machine cycle) is required after the counter start trigger is input and before the data of the reload register is actually loaded into the counter. Figure 6.3-1 Startup and Operations of the Counter Count clock Reload data Counter -1 -1 -1 Data load CNTE (register) TRG (register) T 247 CHAPTER 6 16-BIT RELOAD TIMER ■ Underflow Operation An underflow is an event in which the counter value changes from 0000H to FFFFH. Thus, an underflow occurs at the count of [Reload register setting value + 1]. If the RELD bit of the control status register (TMCSR) is set to "1" when an underflow occurs, the contents of the 16-bit reload register (TMRLR) are loaded and the count operation is continued. If the RELD bit is set to "0", the counter stops at FFFFH. An underflow sets the UF bit of the control status register (TMCSR) and, if the INTE bit is set to "1", generates an interrupt request. Figure 6.3-2 shows the timing chart of the underflow operation. Figure 6.3-2 Timing Chart of the Underflow Operation [RELD=1] Count clock Counter 0000H Reload data Data load Underflow set [RELD=0] Count clock Counter Underflow set 248 0000H FFFFH -1 -1 -1 CHAPTER 6 16-BIT RELOAD TIMER ■ Operation of the Input Pin Function (in Internal Clock Mode) If the internal clock is selected as the clock source, the TTG pin can be used as the trigger or gate input. ❍ Trigger input operation If the TTG pin is used as the trigger input, the input of a valid edge loads the contents of the 16bit reload register (TMRLR) into the counter, clears the internal prescaler, and then starts the count operation. Input a pulse longer than 2T (where T is the peripheral clock machine cycle) to TTG. Figure 6.3-3 shows the timing chart of the trigger input operation. Figure 6.3-3 Timing Chart of the Trigger Input Operation Count clock TTG Rising edge detected Prescaler clear Counter -1 Reload data -1 -1 -1 Load 2T to 2.5T ❍ Gate input operation If the TTG pin is used as gate input, the count operation continues only while the TTG pin accepts the input of a valid level defined by the MOD0 bit of the control status register (TMCSR). At this time, the count clock continues without stopping. In gate mode, a software trigger is enabled regardless of the gate level. The pulse width of the TTG pin must be 2T (where T is a peripheral clock machine cycle) or more. Figure 6.3-4 shows the timing chart of gate input operation. Figure 6.3-4 Timing Chart of Gate Input Operation Count clock TTG Counter If MOD0=1 (counts while "H" is input) -1 -1 -1 249 CHAPTER 6 16-BIT RELOAD TIMER ■ External Event Count Operation If the external clock is selected, the TTG pin becomes the external event input pin and valid edges defined in the register are counted. The pulse width of the TTG pin must be 2T (where T is a peripheral clock machine cycle) or more. ■ Operation of the Output Pin Function The TOUT pin provides toggle output that is reversed upon an underflow in reload mode or pulse output that indicates that counting is in progress in one-shot mode. The output polarity can be set in the OUTL bit of the control status register (TMCSR). If OUTL=0, toggle output is 0 for the initial value and the one-shot pulse output is 1 while the count operation is in progress. If OUTL=1, the output waveform is reversed. Figure 6.3-5 shows the timing chart of output pin function operation. Figure 6.3-5 Timing Chart of Output Pin Function Operation [RELD=1, OUT=0] Count started Underflow Reversed if OUTL=1 TOUT General-purpose port CNTE Startup trigger [RELD=0, OUT=0] Underflow Reversed if OUTL=1 TOUT General-purpose port CNTE Startup trigger Startup trigger wait status 250 CHAPTER 6 16-BIT RELOAD TIMER ■ Other Operation Channels 0 and 1 of the 16-bit reload timer support the start of DMA transfer occurring due to interrupt request signals. The DMA controller clears the interrupt flag of the reload timer as soon as a transfer request is accepted. The DMA transferring start by the interrupt request signal cannot be used (only MB91306R/ 307R). 251 CHAPTER 6 16-BIT RELOAD TIMER 6.4 Operating States of the Counter The counter state is determined by the CNTE bit of the control status register (TMCSR) and the WAIT signal, which is an internal signal. The states that can be set include the stop state, when CNTE=0 and WAIT=1 (STOP state); the startup trigger wait state, when CNTE=1 and WAIT=1 (WAIT status); and the operation state, when CNTE=1 and WAIT=0 (RUN state). ■ Operating States of the Counter Figure 6.4-1 shows the state transitions. Figure 6.4-1 Status Transitions of Counter State transition due to hardware Reset STOP CNTE=0, WAIT=1 T1: Input disabled T0: General-purpose port Counter: Holds the value when it stops; undefined just after reset CNTE="0" CNTE="1" TRG="0" WAIT CNTE=1, WAIT=1 T1: Only trigger input enabled T0: Initial value output Counter: Holds the value when it stops; undefined just after reset and until data is loaded Trigger from TIN 252 CNTE="0" CNTE="1" TRG="1" RUN T1: T0: Counter: RELD UF TRG="1" State transition due to register access TRG="1" LOAD CNTE=1, WAIT=0 Loads contents of reload register into counter. CNTE=1, WAIT=0 Serves as T1 Serves as T0 Running RELD UF Load completed CHAPTER 6 16-BIT RELOAD TIMER 6.5 Precautions on Using the 16-bit Reload Timer This section contains precautions on using the 16-bit reload timer. ■ Precautions on Using the 16-bit Reload Timer ❍ Internal prescaler The internal prescaler is enabled if a trigger (software or external trigger) is applied while bit 1 (timer enable: CNTE) of the control status register (TMCSR) is set to "1". Even when only gate count mode is to be used, be sure to apply a trigger one time before a valid gate level is input. When you set CNTE, it is recommended that you write "1" to bit 0 (TRG) of the TMCSR register. ❍ Timing of setting and clearing the interrupt request flag If the device attempts to set and clear the interrupt request flag at the same time, the flag is set and the clear operation becomes ineffective. ❍ 16-bit timer register (TMR)/16-bit reload register (TMRLR) If the device attempts to write to the 16-bit timer register and reload the data into the 16-bit reload register at the same time, old data is loaded into the counter. New data is loaded into the counter only in the next reload timing. ❍ 16-bit timer register (TMR) If the device attempts to load and count the 16-bit timer register at the same time, the load (reload) operation takes precedence. 253 CHAPTER 6 16-BIT RELOAD TIMER 254 CHAPTER 7 U-TIMER This chapter describes the U-TIMER, the configuration and functions of registers, and U-TIMER operation. 7.1 Overview of the U-TIMER 7.2 U-TIMER Registers 7.3 U-TIMER Operation 255 CHAPTER 7 U-TIMER 7.1 Overview of the U-TIMER This section provides an overview and a block diagram of the U-TIMER (16-bit timer for UART baud rate generation). ■ Overview of the U-TIMER The U-TIMER is a 16-bit timer used to generate the baud rate for the UART. Use a combination of a chip operating frequency and a reload value of the U-TIMER to specify a baud rate. The U-TIMER, which generates an interrupt upon a counter underflow, can be used as an interval timer. The MB91307 series has three built-in U-TIMER channels. When used as an interval timer, two sets of U-TIMERs can be cascaded to count a maximum interval of 232 × φ. Only the combinations of Channels 0 and 1 and Channels 0 and 2 can be connected in cascade fashion. ■ Block Diagram Figure 7.1-1 Block Diagram of the U-TIMER 0 15 UTIMR (reload register) load 15 0 UTIM (timer) clock underflow φ (Peripheral Clock) Only MUX Channel 0 under flow U-TIMER 1 256 control f.f. to UART CHAPTER 7 U-TIMER 7.2 U-TIMER Registers This section describes the configuration and functions of the registers used by the UTIMER. ■ U-TIMER Registers Figure 7.2-1 shows the registers used by the U-TIMER. Figure 7.2-1 U-TIMER Registers 15 8 7 0 UTIM (R) UTIMR (W) UTIMC (R/W) ■ U-TIMER (UTIM) Figure 7.2-2 shows the bit configuration of the U-TIMER (UTIM). Figure 7.2-2 Bit Configuration of the U-TIMER (UTIM) ch0 Address: 0000 0064H ch1 Address: 0000 006CH ch2 Address: 0000 0074H 15 14 2 1 0 b15 b14 b2 b1 b0 R 0 Access Initial value UTIM indicates the timer value. Use a 16-bit transfer instruction to access this register. ■ Reload Register (UTIMR) Figure 7.2-3 shows the bit configuration of the reload register (UTIMR). Figure 7.2-3 Bit Configuration of the Reload Register (UTIMR) ch0 Address: 0000 0064H ch1 Address: 0000 006CH ch2 Address: 0000 0074H 15 14 2 1 0 b15 b14 b2 b1 b0 W 0 Access Initial value UTIMR is a register that stores the value to be reloaded into UTIM if UTIM underflows. Use a 16-bit transfer instruction to access this register. 257 CHAPTER 7 U-TIMER ■ U-TIMER Control Register (UTIMC) Figure 7.2-4 shows the bit configuration of the U-TIMER control register (UTIMC). Figure 7.2-4 Bit Configuration of the U-TIMER Control Register (UTIMC) ch0 Address: 0000 0067H ch1 Address: 0000 006FH ch2 Address: 0000 0077H 7 UCC1 R/W 0 6 - 5 - 4 3 2 1 0 UTIE UNDR CLKS UTST UTCR R/W R/W R/W R/W R/W Access 0 0 0 0 1 Initial value UTIMC controls the operation of the U-TIMER. The following describes the functions of the U-TIMER control register (UTIMC) bits. [Bit 7] UCC1 (U-timer Count Control 1) This bit controls the U-TIMER counting method. UCC1 Operation 0 Normal operation α=2n+2 [initial value] 1 +1 mode α=2n+3 Notes: • • n is the setting value of UTIMR. α is the cycle of the output clock for UART. The U-TIMER can set a normal cycle, 2(n+1) as well as an odd-numbered division for the UART. Set UCC1 to 1 to generate a cycle of 2n+3. Examples: 1. UTIMR=5, UCC1=0 → Generation cycle =2n+2= 12 cycles 2. UTIMR=25, UCC1=1 → Generation cycle =2n+3= 53 cycles 3. UTIMR=60, UCC1=0 → Generation cycle =2n+2=122 cycles Set UCC1 to "0" to use the U-TIMER as the interval timer. [Bits 6, 5] (reserved) This bit is reserved. [Bit 4] UTIE (U-TIMER Interrupt Enable) This bit is the interrupt enable bit for a U-TIMER underflow. UTIE 258 Operation 0 Interrupt disabled 1 Interrupt enabled [initial value] CHAPTER 7 U-TIMER [Bit 3] UNDR (UNDeR flow flag) This bit indicates that an underflow has occurred. If the UNDR bit is set while Bit 4 of the UTIE bit is set to "1", an underflow interrupt occurs. The UNDR bit is cleared upon a reset or if "0" is written to it. For a read by a read modify write instruction, "1" is always read. Writing "1" to the UNDR has no effect. [Bit 2] CLKS (clock select) This bit is the cascade specification bit for Channels 0 and 1 of the U-TIMER. CLKS Operation 0 Uses a peripheral clock (φ) as the clock source. [initial value] 1 Uses an underflow signal of Channel 0 as the U-TIMER source clock timing. CLKS is valid only for Channels 1 and 2. This bit must always be set to "0" for Channel 0. φ (Peripheral clock = clkp) has a different cycle depending on the gear setting. [Bit 1] UTST (U-TIMER STart) This bit is the U-TIMER operation enable bit. UTST Operation 0 Stopped. Writing "0" during operation stops running of the U-TIMER. [initial value] 1 Writing "1" during operation does not stop the U-TIMER. [Bit 0] UTCR (U-TIMER CleaR) Writing "0" to UTCR clears the U-TIMER to 0000H (also clears the f.f. to "0"). The read value is always "1". 259 CHAPTER 7 U-TIMER ■ Precautions on the U-TIMER Control Register (UTIMC) 260 • In the stop state, assert the start bit UTST (started) to automatically reload data. • In the stop state, assert both the clear bit UTCR and the start bit UTST at the same time to clear the counter to "0" and generate an underflow in the count-down immediately after the counter is cleared. • During operation, the clear bit UTCR is asserted to clear the counter to "0". As a result, a short, whisker-like pulse may be output in the output waveform, possibly causing the UART or U-TIMER on the master side in cascade mode to malfunction. While the output clock is being used, do not clear it using the clear bit. • In cascade mode, setting the slave-side UTIMR (reload register) to "0" or "1" causes the count to be performed incorrectly. • In the timer stop state, assert both bit 1 (U-TIMER start bit: UTST) and bit 0 (U-TIMER clear bit: UTCR) of the U-TIMER control register at the same time to set bit 3 (underflow flag: UNDR) of this register when the counter is loaded after it has been cleared. At this timing, the internal baud rate clock is set to "H" level. • If the device attempts to set and clear the interrupt request flag at the same time, the flag is set and the clear operation becomes ineffective. • If you select not to use ch0 in cascade mode or use this module only as the timer function, always write "0" to bit 2 (Reference clock selection bit: CLKS). Additionally, change the setting of the CLKS bit when this module has stopped. • If the device attempts to write to and reload the data into the U-TIMER reload register at the same time, old data is loaded into the counter. New data is loaded into the counter only in the next reload timing. • If the device attempts to clear and load U-TIMER at the same time, the timer clear operation takes precedence. CHAPTER 7 U-TIMER 7.3 U-TIMER Operation This section describes calculation of a baud rate for the U-TIMER and the timing in cascade mode. ■ Calculation of Baud Rate The UART uses the underflow flip-flop (f.f. in the block diagram) of the corresponding U-TIMER (from U-TIMER0 to UART0 or from U-TIMER1 to UART1) as the clock source for baud rates. ❍ Asynchronous (start-stop synchronization) mode The UART uses the U-TIMER output divided by 16. [If UCC1=0] φ bps = (2n+2) 16 n : UTIMR (reload value) φ : Peripheral machine clock frequency [If UCC1=1] φ bps = (Varies depending on the gear) (2n+3) 16 Maximum bps 20 MHz 312,500 bps, 25 MHz 39,0625 bps ❍ CLK synchronous mode [If UCC1=0] bps = φ (2n+2) n : UTIMR (reload value) φ : Peripheral machine clock frequency [If UCC1=1] bps = φ (Varies depending on the gear) (2n+3) Maximum bps 20 MHz 5,000,000bps, 25 MHz 6,250,000 bps 261 CHAPTER 7 U-TIMER ■ Cascade Mode Channels 0 and 1 of the U-TIMER can be used in cascade mode. Figure 7.3-1 shows a sample timing chart for when UTIMR ch.0 is set to "0002" and UTIMR ch.1 is set to "0100". Figure 7.3-1 Timing Chart for Cascade Mode φ UTIM ch.0 01 00 02 01 00 02 01 00 02 01 00 02 01 00 02 01 00 02 01 00 f.f. ch.0 UTIM ch.1 f.f. ch.1 262 0002 0001 0000 0100 CHAPTER 8 EXTERNAL INTERRUPT AND NMI CONTROLLER This chapter describes the external interrupt and NMI controller, the configuration and functions of registers, and operation of the external interrupt and NMI controller. 8.1 Overview of the External Interrupt and NMI Controller 8.2 External Interrupt and NMI Controller Registers 8.3 Operation of the External Interrupt and NMI Controller 263 CHAPTER 8 EXTERNAL INTERRUPT AND NMI CONTROLLER 8.1 Overview of the External Interrupt and NMI Controller The external interrupt controller is a block that controls external interrupt requests input to NMI and INT0 to INT7. H level, L level, rising edge, or falling edge can be selected as the level of a request to be detected (except for NMI). ■ Block Diagram of the External Interrupt and NMI Controller Figure 8.1-1 is a block diagram of the external interrupt and NMI controller. Figure 8.1-1 Block Diagram of the External Interrupt and NMI Controller R-bus 8 Interrupt request Interrupt enable register 9 Source F/F Edge detection circuit 9 INT0-7 NMI 8 8 264 Gate Interrupt source register Request level setting register CHAPTER 8 EXTERNAL INTERRUPT AND NMI CONTROLLER 8.2 External Interrupt and NMI Controller Registers This section describes the configuration and functions of the registers used by the external interrupt and NMI controller. ■ External Interrupt and NMI Controller Registers Figure 8.2-1 shows the registers used by the external interrupt and NMI controllers. Figure 8.2-1 List of External Interrupt and NMI Controller Registers ❍ External interrupt enable register (ENIR) bit 7 EN7 6 EN6 5 EN5 4 EN4 3 EN3 2 EN2 1 EN1 0 EN0 11 ER3 10 ER2 9 ER1 8 ER0 ❍ External interrupt source register (EIRR) bit 15 ER7 14 ER6 13 ER5 12 ER4 ❍ Request level setting register (ELVR) bit 15 LB7 14 LA7 13 LB6 12 LA6 11 LB5 10 LA5 9 LB4 8 LA4 bit 7 LB3 6 LA3 5 LB2 4 LA2 3 LB1 2 LA1 1 LB0 0 LA0 265 CHAPTER 8 EXTERNAL INTERRUPT AND NMI CONTROLLER 8.2.1 Interrupt Enable Register (ENIR) The interrupt enable register (ENIR) performs mask control for external interrupt request output. ■ Interrupt Enable Register (ENIR: ENable Interrupt Request Register) Figure 8.2-2 shows the bit configuration of the interrupt enable register (ENIR) Figure 8.2-2 Bit Configuration of the Interrupt Enable Register (ENIR) bit 7 ENIR Address :000041H EN7 6 5 4 3 2 1 0 Initial value EN6 EN5 EN4 EN3 EN2 EN1 EN0 00000000B [R/W] Output for an interrupt request is enabled based on the bit in this register to which "1" has been written (INT0 enable is controlled by EN0), after which the interrupt request is output to the interrupt controller. The pin corresponding to the bit to which "0" is written holds the interrupt source but does not generate a request to the interrupt controller. Note: No mask bit exists for NMI. 266 CHAPTER 8 EXTERNAL INTERRUPT AND NMI CONTROLLER 8.2.2 External Interrupt Source Register (EIRR) This section describes the bit configuration and functions of the external interrupt source register. ■ External Interrupt Source Register (EIRR: External Interrupt Request Register) Figure 8.2-3 shows the bit configuration of the external interrupt source register (EIRR). Figure 8.2-3 Bit Configuration of the External Interrupt Source Register (EIRR) bit 15 EIRR Address :000040H ER7 14 13 12 11 10 9 8 Initial value ER6 ER5 ER4 ER3 ER2 ER1 ER0 00000000B [R/W] The EIRR register, when it is read, indicates that a corresponding external interrupt request exists. When it is written to, the contents of the flip-flop (NMI flag) that indicates this request are cleared. If "1" is read from the EIRR register, an external interrupt request exists at the pin corresponding to this bit. Write "0" to this register to clear the request flip-flop of the corresponding bit. Writing "1" to this has no effect. For a read by a read modify write instruction, "1" is read. Note: The MI flag cannot be read or written to by a user. For information about the NMI flag, see "■NMI" in Section "8.3 Operation of the External Interrupt and NMI Controller". 267 CHAPTER 8 EXTERNAL INTERRUPT AND NMI CONTROLLER 8.2.3 External Interrupt Request Level Setting Register (ELVR) This section describes the bit configuration and functions of the external interrupt request level setting register (ELVR). ■ External Interrupt Request Level Setting Register (ELVR: External Level Register) Figure 8.2-4 shows the bit configuration of the external interrupt request level setting register (ELVR). Figure 8.2-4 Bit Configuration of the External Interrupt Request Level Setting Register (ELVR) bit ELVR Address :000042H bit ELVR Address :000043H 15 14 13 12 11 10 9 8 Initial value LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 00000000B 7 6 5 4 3 2 1 0 Initial value LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 00000000B [R/W] The external interrupt request level setting register (ELVR) selects how a request is detected. Two bits are assigned to each of INT0 to 7, which results in the settings shown in Table 8.21"Settings of the LBx and Lax Bits". Even though the bits of the EIRR are cleared while the request input is a level, the pertinent bits are set again as long as the input is an active level. Table 8.2-1 Settings of the LBx and LAx Bits LBx LAx Operation 0 0 L level indicates the existence of a request. 0 1 H level indicates the existence of a request. 1 0 A rising edge indicates the existence of a request. 1 1 A falling edge indicates the existence of a request. A falling edge is always detected at NMI (except in the stop state). In the stop state, the "L" level is detected. 268 CHAPTER 8 EXTERNAL INTERRUPT AND NMI CONTROLLER 8.3 Operation of the External Interrupt and NMI Controller If, after a request level and an enable register are defined, a request defined in the ELVR register is input to the corresponding pin, this module generates an interrupt request signal to the interrupt controller. ■ Operation of an External Interrupt For simultaneous interrupt requests from resources, the interrupt controller determines the interrupt request with the highest priority and generates an interrupt for it. Figure 8.3-1 shows external interrupt operation. Figure 8.3-1 External Interrupt Operation External interrupt ELVR Resource request Interrupt controller ENIR IL ICR y y EIRR CPU CMP ICR x x CMP ILM Source ■ Return from Standby To use an external interrupt to return from the standby state in clock stop mode, use an "H" level request as the input request. If you use an "L" level request, a malfunction may occur. If you use an edge request, the device does not return from the stop state in clock stop mode. ■ Operating Procedure for an External Interrupt Set up a register located inside the external interrupt controller as follows: 1. The general-purpose I/O port that shared with the pin used as an external interruption input is set to the input port. 2. Disable the target bit in the enable register. 3. Set the target bit in the request level setting register. 4. Clear the target bit in the interrupt source register. 5. Enable the target bit in the enable register. Simultaneous writing of 16-bit data is supported for steps 4) and 5). Before setting a register in this module, you must disable the enable register. In addition, before enabling the enable register, you must clear the interrupt source register. This procedure is required to prevent an interrupt source from occurring by mistake while a register is being set or an interrupt is enabled. Note: ch0 to ch7 can be used to use an external interrupt to return from standby. Before entering standby, set an external interrupt as required. 269 CHAPTER 8 EXTERNAL INTERRUPT AND NMI CONTROLLER ■ External Interrupt Request Level If the request level is an edge request, a pulse width of at least three machine cycles (peripheral clock machine cycles) is required to detect an edge. If the request input level is a level setting and request input arrives from outside and is then cancelled, the request to the interrupt controller remains active because a source holding circuit exists internally. The external interrupt source register must be cleared to cancel a request to the interrupt controller. Figure 8.3-2 shows clearing of the external interrupt source register when a level is set. Figure 8.3-3 shows an interrupt source and an interrupt request to the interrupt controller when interrupts are enabled. Figure 8.3-2 Clearing the External Interrupt Source Register when a Level is Set Interrupt input External interrupt source register (Source holding circuit) Level detection Enable gate Interrupt controller Holds a source while it is not cleared Figure 8.3-3 Interrupt Source and Interrupt Request to Interrupt Controller when Interrupts are Enabled Interrupt input Interrupt request to interrupt controller "H" level Becomes inactive when external interrupt source register is cleared ■ NMI An NMI has the highest level among the user interrupts and usually cannot be masked. However, as an exception, an NMI can be masked from the moment a reset occurs until ILM is set. An NMI is accepted under the following conditions: • Normal: Rising edge • STOP mode: "L" level An NMI can be used to clear stop mode. Inputting the "L" level in the stop state clears the stop state and causes the oscillation stabilization wait time to start. Returning the NMI pin to the "H" level during the oscillation stabilization wait time eliminates the NMI source and performs no NMI processing after operation is restarted. To perform NMI processing after clearing the stop state, maintain the NMI pin at the "L" level and return it to the "H" level in the NMI processing routine. The NMI request detector has an NMI flag that is set for an NMI request and is cleared only if an interrupt for the NMI itself is accepted or a reset occurs. Note that this bit is not readable or writable. Figure 8.3-4 shows the NMI request detector. 270 CHAPTER 8 EXTERNAL INTERRUPT AND NMI CONTROLLER Figure 8.3-4 NMI Request Detector (NMI flag) NMI request (Stop clearing) Q SX R 0 Falling edge detection NMI 1 STOP φ clear (RST, interrupt acknowledge) 271 CHAPTER 8 EXTERNAL INTERRUPT AND NMI CONTROLLER 272 CHAPTER 9 DELAYED INTERRUPT MODULE This chapter describes the functions and operation of the delayed interrupt module. 9.1 Overview of the Delayed Interrupt Module 9.2 Delayed Interrupt Module Registers 9.3 Operation of the Delayed Interrupt Module 273 CHAPTER 9 DELAYED INTERRUPT MODULE 9.1 Overview of the Delayed Interrupt Module The delayed interrupt module generates an interrupt for switching tasks. Use this module to allow a software program to generate an interrupt request for the CPU or to clear an interrupt request. ■ Block Diagram of the Delayed Interrupt Module Figure 9.1-1 is a block diagram of the delayed interrupt module. Figure 9.1-1 Block Diagram of the Delayed Interrupt Module R-bus Interrupt request 274 DLYI CHAPTER 9 DELAYED INTERRUPT MODULE 9.2 Delayed Interrupt Module Registers This section describes the configuration and functions of the registers used by the delayed interrupt module. ■ Delayed Interrupt Module Registers The interrupt delay module includes the delayed interrupt control register (DICR). Figure 9.2-1 shows the configuration of the delayed interrupt control register (DICR). Figure 9.2-1 Configuration of the Delayed Interrupt Control Register (DICR) bit Address: 00000044H 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DLYI DICR [R/W] ■ Delayed Interrupt Control Register (DICR) The delayed interrupt control register (DICR: Delayed Interrupt Control Register) controls delayed interrupts. Figure 9.2-2 shows the bit configuration of the delayed interrupt control register (DICR). Figure 9.2-2 Bit Configuration of the Delayed Interrupt Control Register (DICR) bit 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DLYI 0 (Initial value) [R/W] The following describes the functions of the delayed interrupt control register (DICR) bits. [Bit 0] DLYI DLYI Description 0 A delayed interrupt source is cleared or no request exists. [initial value] 1 A delayed interrupt source is generated. This bit controls the generation and clearing of the pertinent interrupt source. 275 CHAPTER 9 DELAYED INTERRUPT MODULE 9.3 Operation of the Delayed Interrupt Module A delayed interrupt refers to an interrupt generated for switching tasks. Use this function to allow a software program to generate an interrupt request for the CPU or to clear an interrupt request. ■ Interrupt Number A delayed interrupt is assigned to the interrupt source corresponding to the largest interrupt number. On the MB91307 series, a delayed interrupt is assigned to interrupt number 63 (3FH). ■ DLYI Bit of DICR Write "1" to this bit to generate a delayed interrupt source. Write "0" to it to clear a delayed interrupt source. This bit is the same as the interrupt source flag for a normal interrupt. Therefore, clear this bit and switch tasks in the interrupt routine. 276 CHAPTER 10 INTERRUPT CONTROLLER This chapter describes the interrupt controller, the configuration and functions of registers, and interrupt controller operation. It also presents an example of using the hold request cancellation request function. 10.1 Overview of the Interrupt Controller 10.2 Interrupt Controller Registers 10.3 Interrupt Controller Operation 10.4 Example of Using the Hold Request Cancellation Request Function (HRCR) 277 CHAPTER 10 INTERRUPT CONTROLLER 10.1 Overview of the Interrupt Controller The interrupt controller controls interrupt acceptance and arbitration processing. ■ Hardware Configuration of the Interrupt Controller The interrupt controller consists of the following components: • ICR register • Interrupt priority decision circuit • Interrupt level and interrupt number (vector) generator • HOLD request cancellation request generator ■ Major Functions The interrupt controller has the following major functions: 278 • Detecting NMI requests and interrupt requests • Deciding priority (using a level or number) • Passing an interrupt level based on the decision result to provide information about the interrupt source (to CPU) • Passing an interrupt number based on the decision result to provide information about the interrupt source (to CPU) • Instruction for return from stop mode due to the occurrence of an interrupt with an NMI/ interrupt level other than "11111" (to CPU) • Generating a HOLD request cancellation request for the bus master CHAPTER 10 INTERRUPT CONTROLLER ■ Block Diagram Figure 10.1-1 is a block diagram of the interrupt controller. Figure 10.1-1 Block Diagram of the Interrupt Controller UNMI WAKEUP (LEVEL 11111: '1') Priority decision 5 NMI processing LEVEL4-0 LEVEL decision RI00 ICR00 RI47 (DLYIRQ) ICR47 . . . . . . VECTOR decision 6 LEVEL and VECTOR generation HLDREQ cancellation request MHALTI VCT5-0 R-bus 279 CHAPTER 10 INTERRUPT CONTROLLER 10.2 Interrupt Controller Registers This section describes the configuration and functions of the registers used by the interrupt controller. ■ Interrupt Controller Registers Figure 10.2-1 shows the registers used by the interrupt controller. Figure 10.2-1 Interrupt Controller Registers bit 7 6 5 4 3 2 1 0 Initial value Address : 00000440H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR00 Address : 00000441H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR01 Address : 00000442H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR02 Address : 00000443H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR03 Address : 00000444H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR04 Address : 00000445H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR05 Address : 00000446H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR06 Address : 00000447H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR07 Address : 00000448H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR08 Address : 00000449H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR09 Address : 0000044AH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR10 Address : 0000044BH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR11 Address : 0000044CH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR12 Address : 0000044DH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR13 Address : 0000044EH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR14 Address : 0000044FH Address : 00000450H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR15 - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR16 Address : 00000451H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR17 Address : 00000452H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR18 Address : 00000453H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR19 Address : 00000454H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR20 Address : 00000455H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR21 Address : 00000456H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR22 Address : 00000457H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR23 Address : 00000458H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR24 00000459H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR25 Address : 0000045AH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR26 Address : 0000045BH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR27 Address : 0000045CH - - - ICR4 R ICR3 R/W ICR2 R/W ICR1 R/W ICR0 R/W ICR28 Address : (Continued) 280 CHAPTER 10 INTERRUPT CONTROLLER (Continued) 7 6 5 4 3 2 1 0 Initial value Address : 0000045DH bit - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR29 Address : 0000045EH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR30 Address : 0000045FH Address : 00000460H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR31 - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR32 Address : 00000461H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR33 Address : 00000462H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR34 Address : 00000463H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR35 Address : 00000464H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR36 Address : 00000465H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR37 Address : 00000466H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR38 Address : 00000467H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR39 Address : 00000468H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR40 Address : 00000469H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR41 Address : 0000046AH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR42 Address : 0000046BH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR43 Address : 0000046CH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR44 Address : 0000046DH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR45 Address : 0000046EH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR46 Address : 0000046FH - - - ICR4 R ICR3 R/W ICR2 R/W ICR1 R/W ICR0 R/W ICR47 LVL4 R LVL3 R/W LVL2 R/W LVL1 R/W LVL0 R/W HRCL Address : 00000045H MHALTI R/W 281 CHAPTER 10 INTERRUPT CONTROLLER 10.2.1 Interrupt Control Register (ICR) An interrupt control register is provided for each of the interrupt input and sets the interrupt level of the corresponding interrupt request. ■ Interrupt Control Register (ICR) Figure 10.2-2 shows the bit configuration of the interrupt control register (ICR: Interrupt Control Register). Figure 10.2-2 Bit Configuration of the Interrupt Control Register (ICR) bit 7 6 5 4 3 2 1 0 Initial value - - - ICR4 R ICR3 R/W ICR2 R/W ICR1 R/W ICR0 R/W ---11111 The following describes the functions of the interrupt control register (ICR) bits. [Bits 4 to 0] ICR4 to ICR0 These bits, which are the interrupt level setting bits, specify the interrupt level of the corresponding interrupt request. If an interrupt request has an interrupt level defined in this register that exceeds the level mask value defined in the ILM register of the CPU, it is masked by the CPU. These bits are initialized to "11111B" by a reset. Table 10.2-1 shows the correspondence between possible interrupt level setting bits and interrupt levels. 282 CHAPTER 10 INTERRUPT CONTROLLER Table 10.2-1 Correspondence Between Possible Interrupt Level Setting Bits and Interrupt Levels ICR4 ICR3 ICR2 ICR1 ICR0 Interrupt level 0 0 0 0 0 0 0 1 1 1 0 14 0 1 1 1 1 15 NMI 1 0 0 0 0 16 Maximum level that can be set 1 0 0 0 1 17 (High) 1 0 0 1 0 18 1 0 0 1 1 19 1 0 1 0 0 20 1 0 1 0 1 21 1 0 1 1 0 22 1 0 1 1 1 23 1 1 0 0 0 24 1 1 0 0 1 25 1 1 0 1 0 26 1 1 0 1 1 27 1 1 1 0 0 28 1 1 1 0 1 29 1 1 1 1 0 30 (Low) 1 1 1 1 1 31 Interrupt disabled Reserved for system Note: This register has no ICR4 bit because ICR4 is predetermined by the system. 283 CHAPTER 10 INTERRUPT CONTROLLER 10.2.2 Hold Request Cancellation Request Level Setting Register (HRCL) The hold request cancellation request level setting register (HRCL) is a level setting register used to generate a hold request cancellation request. ■ Hold Request Cancellation Request Level Setting Register (HRCL) Figure 10.2-3 shows the bit configuration of the hold request cancellation request level setting register (HRCL). Figure 10.2-3 Bit Configuration of the Hold Request Cancellation Request Level Setting Register (HRCL) bit Address :00000045H 7 6 5 4 3 2 1 0 MHALTI R/W - - LVL4 R LVL3 R/W LVL2 R/W LVL1 R/W LVL0 R/W Initial value 0--11111(Initial value) The following describes the functions of the hold request cancellation request level setting register (HRCL) bits. [Bit 7] MHALTI This bit is the DMA transfer disable bit controlled by an NMI request. An NMI request sets this bit to "1". Write "0" to this bit to clear it. At the end of an NMI routine, clear this bit the same way it would be cleared in a normal interrupt routine. [Bits 4 to 0] LVL4 to LVL0 This bit sets the interrupt level used to issue a hold request cancellation request to the bus master. If an interrupt request with a higher level than the level defined in the HRCL register occurs, issue a hold request cancellation request to the bus master. The LVL4 bit is always "1"; "0" cannot be written to it. 284 CHAPTER 10 INTERRUPT CONTROLLER 10.3 Interrupt Controller Operation This section describes the following items regarding operation of the interrupt controller: • Priority decision • NMI • Hold request cancellation request • Return from standby mode (stop/sleep) ■ Priority Decision The interrupt controller selects the interrupt source with the highest priority from among those that exist simultaneously and outputs the interrupt level and the interrupt number of this source to the CPU. The following shows the priority decision criteria for interrupt sources: • NMI • Source that meets the following conditions: • Source with a value other than "31" as the interrupt level ("31" means interrupts disabled) • Source with the smallest value for the interrupt level • Source with the smallest interrupt number that satisfies the both conditions above If no interrupt source is selected according to the above decision criteria, "31" (11111B) is output as the interrupt level. The interrupt number at this time is undefined. Table 10.3-1 shows the relationship between interrupt sources, interrupt numbers and interrupt levels. Table 10.3-1 Relationship Between Interrupt Sources, Interrupt Numbers, and Interrupt Levels (1/4) Interrupt number Offset Default address of TBR Decimal Hexadecimal Interrupt level Reset 0 00 − 3FCH 000FFFFCH Mode vector 1 01 − 3F8H 000FFFF8H Reserved for system 2 02 − 3F4H 000FFFF4H Reserved for system 3 03 − 3F0H 000FFFF0H Reserved for system 4 04 − 3ECH 000FFFECH Reserved for system 5 05 − 3E8H 000FFFE8H Reserved for system 6 06 − 3E4H 000FFFE4H No-coprocessor trap 7 07 − 3E0H 000FFFE0H Coprocessor error trap 8 08 − 3DCH 000FFFDCH INTE instruction 9 09 − 3D8H 000FFFD8H Instruction break exception 10 0A − 3D4H 000FFFD4H Interrupt source 285 CHAPTER 10 INTERRUPT CONTROLLER Table 10.3-1 Relationship Between Interrupt Sources, Interrupt Numbers, and Interrupt Levels (2/4) Interrupt number Offset Default address of TBR Decimal Hexadecimal Interrupt level Operand break trap 11 0B − 3D0H 000FFFD0H Step trace trap 12 0C − 3CCH 000FFFCCH NMI request (tool) 13 0D − 3C8H 000FFFC8H Undefined instruction exception 14 0E − 3C4H 000FFFC4H NMI request 15 0F Always (FH) 3C0H 000FFFC0H External Interrupt 0 16 10 ICR00 3BCH 000FFFBCH External Interrupt 1 17 11 ICR01 3B8H 000FFFB8H External Interrupt 2 18 12 ICR02 3B4H 000FFFB4H External Interrupt 3 19 13 ICR03 3B0H 000FFFB0H External Interrupt 4 20 14 ICR04 3ACH 000FFFACH External Interrupt 5 21 15 ICR05 3A8H 000FFFA8H External Interrupt 6 22 16 ICR06 3A4H 000FFFA4H External Interrupt 7 23 17 ICR07 3A0H 000FFFA0H Reload Timer 0 24 18 ICR08 39CH 000FFF9CH Reload Timer 1 25 19 ICR09 398H 000FFF98H Reload Timer 2 26 1A ICR10 394H 000FFF94H UART0 (reception completed) 27 1B ICR11 390H 000FFF90H UART1 (reception completed) 28 1C ICR12 38CH 000FFF8CH UART2 (reception completed) 29 1D ICR13 388H 000FFF88H UART0 (transmission completed) 30 1E ICR14 384H 000FFF84H UART1 (transmission completed) 31 1F ICR15 380H 000FFF80H UART2 (transmission completed) 32 20 ICR16 37CH 000FFF7CH DMAC0 (end, error) 33 21 ICR17 378H 000FFF78H DMAC1 (end, error) 34 22 ICR18 374H 000FFF74H DMAC2 (end, error) 35 23 ICR19 370H 000FFF70H DMAC3 (end, error) 36 24 ICR20 36CH 000FFF6CH DMAC4 (end, error) 37 25 ICR21 368H 000FFF68H A/D conversion end 38 26 ICR22 364H 000FFF64H I2C 39 27 ICR23 360H 000FFF60H Reserved for system 40 28 ICR24 35CH 000FFF5CH Interrupt source 286 CHAPTER 10 INTERRUPT CONTROLLER Table 10.3-1 Relationship Between Interrupt Sources, Interrupt Numbers, and Interrupt Levels (3/4) Interrupt number Offset Default address of TBR Decimal Hexadecimal Interrupt level Reserved for system 41 29 ICR25 358H 000FFF58H Reserved for system 42 2A ICR26 354H 000FFF54H Reserved for system 43 2B ICR27 350H 000FFF50H U-TIMER0 44 2C ICR28 34CH 000FFF4CH U-TIMER1 45 2D ICR29 348H 000FFF48H U-TIMER2 46 2E ICR30 344H 000FFF44H Time base timer overflow 47 2F ICR31 340H 000FFF40H Reserved for system 48 30 ICR32 33CH 000FFF3CH Reserved for system 49 31 ICR33 338H 000FFF38H Reserved for system 50 32 ICR34 334H 000FFF34H Reserved for system 51 33 ICR35 330H 000FFF30H Reserved for system 52 34 ICR36 32CH 000FFF2CH Reserved for system 53 35 ICR37 328H 000FFF28H Reserved for system 54 36 ICR38 324H 000FFF24H Reserved for system 55 37 ICR39 320H 000FFF20H Reserved for system 56 38 ICR40 31CH 000FFF1CH Reserved for system 57 39 ICR41 318H 000FFF18H Reserved for system 58 3A ICR42 314H 000FFF14H Reserved for system 59 3B ICR43 310H 000FFF10H Reserved for system 60 3C ICR44 30CH 000FFF0CH Reserved for system 61 3D ICR45 308H 000FFF08H Reserved for system 62 3E ICR46 304H 000FFF04H Delayed interrupt source bit 63 3F ICR47 300H 000FFF00H Reserved for system (used in REALOS) 64 40 − 2FCH 000FFEFCH Reserved for system (used in REALOS) 65 41 − 2F8H 000FFEF8H Reserved for system 66 42 − 2F4H 000FFEF4H Reserved for system 67 43 − 2F0H 000FFEF0H Reserved for system 68 44 − 2ECH 000FFEECH Reserved for system 69 45 − 2E8H 000FFEE8H Reserved for system 70 46 − 2E4H 000FFEE4H Interrupt source 287 CHAPTER 10 INTERRUPT CONTROLLER Table 10.3-1 Relationship Between Interrupt Sources, Interrupt Numbers, and Interrupt Levels (4/4) Interrupt number Offset Default address of TBR Decimal Hexadecimal Interrupt level Reserved for system 71 47 − 2E0H 000FFEE0H Reserved for system 72 48 − 2DCH 000FFEDCH Reserved for system 73 49 − 2D8H 000FFED8H Reserved for system 74 4A − 2D4H 000FFED4H Reserved for system 75 4B − 2D0H 000FFED0H Reserved for system 76 4C − 2CCH 000FFECCH Reserved for system 77 4D − 2C8H 000FFEC8H Reserved for system 78 4E − 2C4H 000FFEC4H Reserved for system 79 4F − 2C0H 000FFEC0H Used in INT instruction 80 to 255 50 to FF − 2BCH to 000H 000FFEBCH to 000FFC00H Interrupt source ■ NMI An NMI (Non Maskable Interrupt) has the highest priority among the interrupt sources handled by the interrupt controller. Thus, an NMI is always selected if it occurs at the same time as other interrupt sources. • • If an NMI occurs, the following information is reported to the CPU: • Interrupt level: 15 (01111B) • Interrupt number: 15 (0001111B) Detecting an NMI The external interrupt and NMI module sets and detects an NMI. This module only generates an interrupt level, interrupt number, and MHALTI in response to an NMI request. • Preventing a DMA transfer occurring due to an NMI If an NMI request occurs, the MHALTI bit of the HRCL register is set to "1" to prevent DMA transfer. To clear the state preventing DMA transfer, clear the MHALTI bit to "0" at the end of the NMI routine. 288 CHAPTER 10 INTERRUPT CONTROLLER ■ Hold Request Cancellation Request (HRLC: Hold Request Cancel Request) For an interrupt with a higher priority to be processed during CPU hold, the device that has generated the hold request must cancel the request. Set in the HRCL register the interrupt level to be used as the criterion of generating a cancellation request. ❍ Generation criteria If an interrupt source with a higher interrupt level than the level defined in the HRCL register occurs, a hold request cancellation request is generated. • If the interrupt level of the HRCL register is greater than the interrupt level after a priority decision, a cancellation request occurs. • If the interrupt level of the HRCL register is equal to or less than the interrupt level after a priority decision, no cancellation request occurs. Because the cancellation request remains valid, no DMA transfer occurs unless the interrupt source that has caused the cancellation request is cleared. Be sure to clear the corresponding interrupt source. If an NMI is used, the cancellation request is valid because the MHALTI bit of the HRCL register is set to "1". ❍ Possible levels Values that can be set in the HRCL register range from "10000B" to "11111B", which is the same range as for the ICR. If this register is set to "11111B", an interrupt request is issued for all the interrupt levels. If this register is set to "10000B", an interrupt request is issued only for an NMI. Table 10.3-2 shows the settings of interrupt levels at which a hold request cancellation request occurs. Table 10.3-2 Settings of Interrupt Levels at which Hold Request Cancellation Request Occurs HRCL register Interrupt levels at which a cancellation request occurs 16 (NMI only) 17 Interrupt level 16 18 Interrupt levels 16 and 17 − − 31 Interrupt levels 16 to 30 [initial value] After a reset, since DMA transfer is not allowed at any interrupt level, no DMA transfer is performed if an interrupt has occurred. Be sure to set the HRCL register to the necessary value. 289 CHAPTER 10 INTERRUPT CONTROLLER ■ Return from Standby Mode (Sleep/Stop) This module implements a function that causes a return from stop mode if an interrupt request occurs. If at least one interrupt request that includes NMI occurs (with an interrupt level other than "11111"), a return request from stop mode is generated for the clock controller. Since the priority decision unit restarts operation when a clock is supplied after returning from stop, the CPU executes instructions until the result of the priority decision unit is obtained. The same operation occurs after a return from the sleep state. Registers in the interrupt controller can be accessed even in the sleep state. Notes: • The device returns from stop mode if an NMI request is issued. However, set an NMI so that valid input can be detected in the stop state. • Provide an interrupt level of "11111" in the corresponding peripheral control register for an interrupt source that you do not want to cause return from stop or sleep. 290 CHAPTER 10 INTERRUPT CONTROLLER 10.4 Example of Using the Hold Request Cancellation Request Function (HRCR) To allow the CPU to perform high-priority processing during DMA transfer, cancel a hold request for DMA and clear the hold state. In this example, an interrupt is used to cancel a hold request to the DMA, allowing the CPU to perform priority operations. ■ Control Registers ❍ HRCL (hold request cancellation level setting register): This module If an interrupt with a higher interrupt level than the level in the HRCL register occurs, a hold request cancellation request is generated for DMA. This register sets the level to be used as the criterion for this purpose. ❍ ICR: This module This register sets a level higher than the level in the HRCL register for the ICR corresponding to the interrupt source that will be used. ■ Hardware Configuration The flow of signals is as follows. Figure 10.4-1 Flow of Signals This module IRQ Bus access request MHALTI I-UNIT DHREQ DMA B-UNIT CPU (ICR) (HRCL) DHACK DHREQ: D bus hold request DHACK: D bus hold acknowledge IRQ: Interrupt request MHALTI: Hold request cancellation request 291 CHAPTER 10 INTERRUPT CONTROLLER ■ Hold Request Cancellation Request Sequence Figure 10.4-2 shows the timing chart of a hold request cancellation request. Figure 10.4-2 Timing Chart of a Hold Request Cancellation Request RUN Bus hold Bus hold (DMA transfer) Interrupt processing DHREQ Example of interrupt routine (1) Interrupt source clear DHACK (2) RETI CPU Bus access request | IRQ LEVEL MHALTI If an interrupt request occurs, the interrupt level changes. If the interrupt level is higher than the level in the HRCL register, MHALTI is started for DMA. This causes DMA to cancel an access request and the CPU to return from the hold state to perform the interrupt processing. Figure 10.4-3 shows the timing chart for multiple interrupts. Figure 10.4-3 Interrupt Level HRCL > a > b RUN Bus hold Interrupt processing II Interrupt I CPU Bus access request (3) (4) Interrupt processing I (1) Bus hold (DMA transfer) (2) DHREQ DHACK IRQ1 IRQ2 LEVEL MHALTI Example of Interrupt Routine (1), (3) Interrupt source clear (2), (4) RETI In the above example, while Interrupt Routine I is being executed, an interrupt with a higher priority occurs. While the interrupt with a higher level than the level in the HRCL register remains, DHREQ is low. Note: Be especially careful about the relationship between interrupt levels defined in the HRCL register and ICR. 292 CHAPTER 11 A/D CONVERTER This chapter describes the A/D converter, the configuration and functions of registers, and A/D converter operation. 11.1 Overview of the A/D Converter 11.2 A/D Converter Registers 11.3 A/D Converter Operation 11.4 Conversion Data Protection Function 11.5 Precautions on the Using A/D Converter 293 CHAPTER 11 A/D CONVERTER 11.1 Overview of the A/D Converter The A/D converter is a module that converts an analog input voltage to a digital value in the successive approximation conversion method. Four analog input pins can be selected as channels for input signals. Conversion is started by software, an external trigger (falling edge), or the reload timer (rising edge). ■ Features The A/D converter, which converts an analog voltage input to an analog input pin (input voltage) to a digital value, has the following features: 294 • Minimum conversion time: 5.4 µs per channel (for a 33 MHz = CLKP machine clock) • Built-in sample hold circuit • Resolution: 10 bits (Accuracy: 8 bits) • A program can select one of four analog input channels: • Single-shot conversion mode: Converts one channel. • Scan conversion mode: Continuously converts multiple channels. Up to four channels can be programmed. • Continuous conversion mode: Repetitiously converts a specified channel. • Stop conversion mode: Converts one channel, pauses, and stands by until the next activation occurs (conversion start can be synchronized). • DMA transfer can be started due to an interrupt. • To start conversion, select software, an external trigger (falling edge), or the reload timer (rising edge). CHAPTER 11 A/D CONVERTER ■ Block Diagram Figure 11.1-1 is a block diagram of the A/D converter. Figure 11.1-1 Block Diagram of the A/D Converter AVCC AVRH AVSS Internal voltage generator Input switch Sample and hold circuit R-bus Sequential comparison register Data register (ADCR) Channel decoder A/D control status register (ADCS) Timing generation circuit Clock (CLKP) Prescaler ATG (External pin trigger) Reload timer ch1 (Internal connection) 295 CHAPTER 11 A/D CONVERTER 11.2 A/D Converter Registers This section describes the configuration and functions of the registers used by the A/ D converter. ■ A/D Converter Registers Figure 11.2-1 shows the registers used by the A/D converter. Figure 11.2-1 A/D Converter Registers ❍ A/D control status register (ADCS) bit 15 BUSY 14 INT 13 INTE 12 PAUS 11 STS1 10 STS0 9 STRT 8 - bit 7 MD1 6 MD0 5 ANS2 4 ANS1 3 ANS0 2 ANE2 1 ANE1 0 ANE0 ❍ Data register (ADCR) 296 bit 15 - 14 - 13 - 12 - 11 - 10 - 9 9 8 8 bit 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 CHAPTER 11 A/D CONVERTER 11.2.1 A/D Control Status Register (ADCS) The A/D control status register (ADCS) controls and displays the status of the A/D converter. ■ A/D Control Status Register (ADCS) Figure 11.2-2 shows the bit configuration of the A/D control status register (ADCS). Figure 11.2-2 Bit Configuration of the A/D Control Status Register (ADCS) Address: 00003AH bit 15 BUSY 0 R/W 14 INT 0 R/W 13 INTE 0 R/W 12 PAUS 0 R/W 11 STS1 0 R/W 10 STS0 0 R/W 9 STRT 0 R/W 7 MD1 0 R/W 6 MD0 0 R/W 5 ANS2 0 R/W 4 ANS1 0 R/W 3 ANS0 0 R/W 2 ANE2 0 R/W 1 ANE1 0 R/W bit 8 0 R/W ←Initial value ←Read/Write 0 ANE0 0 ←Initial value R/W ←Read/Write Note: Do not rewrite the A/D control status register (ADCS) while the A/D conversion is in progress. The following describes the functions of the A/D control status register (ADCS) bits. [Bit 15] BUSY (BUSY flag and stop) This bit has the following different functions during reading and writing: • Reading: This bit indicates whether the A/D converter is operating. It is set when A/D conversion starts and cleared when it ends. • Writing: Write "0" to this bit during A/D operation to forcibly terminate operation. Use this bit for forcible termination in continuous mode and stop mode. "1" cannot be written to the bit that indicates whether the converter is operating. For a read by a RMW instruction, "1" is read. In single-shot mode, this bit is cleared when A/D conversion ends. In continuous mode and stop mode, this bit is not cleared until "0" is written to terminate operation. This bit is initialized to "0" by a reset. Do not forcibly terminate operation and start software at the same time (BUSY=0, STRT=1). [Bit 14] INT (INTerrupt) This bit indicates data. It is set when conversion data is written to the ADCR. If this bit is set while INTE (Bit 13) is set to "1", an interrupt request occurs. If start of DMA transfer has been selected, DMA is started. Writing "1" to this bit is meaningless. This bit is cleared if "0" is written to it or a clear signal from DMAC is received. 297 CHAPTER 11 A/D CONVERTER Note: Clear this bit by writing "0" to it while the A/D is stopped. This bit is initialized to "0" by a reset. For a read by a read modify write instruction, "1" is read. [Bit 13] INTE (INTerrupt Enable) This bit specifies enabling or disabling of interrupts when conversion is completed. • 0: Interrupts are disabled. • 1: Interrupts are enabled. To start DMA transfer occurring due to an interrupt, set this bit. This bit is initialized to "0" by a reset. [Bit 12] PAUS (A/D converter PAUSe) This bit is set if the A/D conversion operation is temporarily stopped. Since only there is only one register that can store the A/D conversion result, previous data is corrupted unless the conversion result is transferred via DMA when data is repeatedly converted. To protect data, the data register stores the conversion result only after the contents of the register are transferred via DMA. During this time, the A/D conversion operation is stopped. The A/D converter restarts conversion as soon as the DMA transfer is completed (specifically, when INT=0). This bit is valid only while interrupts are enabled (INTE=1) (see Section "11.4 Conversion Data Protection Function"). This bit is initialized to "0" by a reset. [Bits 11, 10] STS, CSTS0 (STart Source select) These bits are initialized to "00" by a reset. Set these bits to select the source of starting A/D conversion. Table 11.2-1 shows the possible settings. Table 11.2-1 Settings of A/D Conversion Start Causes STS1 STS0 Functions 0 0 Started due to software 0 1 Started due to an external pin trigger or software 1 0 Started due to a reload timer or software 1 1 Started due to an external pin trigger, reload timer, or software In a mode with multiple start sources, the first detected source starts the A/D conversion. Notes: Since start sources change at the same time that rewriting occurs, be careful when this bit is rewritten during the A/D conversion operation. • An external pin trigger is detected at a rising edge. If this bit is rewritten to select starting due to an external trigger while the external trigger input level is set to "L", the A/D converter may be started. • While a timer is selected, Channel 1 of the reload timer is selected. If this bit is rewritten to select starting due to a timer while the external trigger output level is set to "H", the A/D converter may be started. 298 CHAPTER 11 A/D CONVERTER [Bit 9] STRT (STaRT) Write "1" to this bit to start the A/D converter. If the system is restarted, write to this bit again. In stop mode, restart is disabled because of the nature of the function. This bit is initialized to "0" by a reset. Do not forcibly terminate operation and start a software program at the same time (BUSY=0, STRT=1). For a read by a read modify write instruction, "0" is read. For all other types of read, "1" is read. [Bit 8] Test bit This bit is used for testing. For a write, write "0". [Bits 7, 6] MD1,MD0 (A/D converter MoDe set) This bit selects the operating mode. Table 11.2-2 shows the settings for the operating modes. Table 11.2-2 Operating Mode Settings MD1 MD0 Function 0 0 Restart enabled both in single-shot mode and during operation 0 1 Restart disabled both in single-shot mode and during operation 1 0 Restart disabled both in continuous mode and during operation 1 1 Restart disabled both in stop mode and during operation • Single-shot mode: Performs A/D conversion from the channels defined by ANS2 to ANS0 to the channels defined by ANE2 to ANE0. Stops when one conversion session is completed. • Continuous mode: Repeatedly performs A/D conversion from the channels defined by ANS2 to ANS0 to the channels defined by ANE2 to ANE0. • Stop mode: Performs A/D conversion from each of the channels defined by ANS2 to ANS0 to each of the channels defined by ANE2 to ANE0 and then temporarily stops. The conversion is restarted when a start source occurs. This bit is initialized to "00" by a reset. Notes: If A/D conversion is started in continuous or stop mode, the conversion operation continues until it is stopped due to the BUSY bit. • Write "0" to the BUSY bit to stop A/D conversion. • The restart disabled status in each of the single, continuous, and stop modes applies to all the start operation caused by a timer, external trigger, and software. [Bits 5, 4, 3] ANS2, ANS1, ANS0 (ANalog Start channel set) These bits set the channel where A/D conversion will start. When the A/D converter is started, A/D conversion starts at the channel selected in these bits. 299 CHAPTER 11 A/D CONVERTER Table 11.2-3 shows the settings for the A/D conversion start channels. Table 11.2-3 Settings for A/D Conversion Start Channels • ANS2 ANS1 ANS0 Start channel 0 0 0 AN0 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 Setting disabled 1 0 1 Setting disabled 1 1 0 Setting disabled 1 1 1 Setting disabled During reading:A conversion channel is read from these bits during A/D conversion. This bit is updated as soon as A/D conversion starts. The previous conversion channel is read in the stop state. • These bits are initialized to "000" by a reset. [Bits 2, 1, 0] ANE2, ANE1, ANE0 (ANalog End channel set) These bits set an A/D conversion end channel. Table 11.2-4 shows the settings for the A/D conversion end channels. Table 11.2-4 Settings for A/D Conversion End Channels 300 ANE2 ANE1 ANE0 End channel 0 0 0 AN0 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 Setting disabled 1 0 1 Setting disabled 1 1 0 Setting disabled 1 1 1 Setting disabled • Set the same channel as defined by ANS2 to ANS0 to perform one-channel conversion (single-shot conversion). • If continuous or stop mode is set, A/D conversion returns to the start channel defined by ANS2 to ANS0 when the conversion for the channel defined by these bits is completed. • Define channels ANS and ANE so that the ANS is equal to or less than the ANE. • These bits are initialized to "000" by a reset. CHAPTER 11 A/D CONVERTER Example If the channel settings are ANS=1-channel and ANE=3-channel in single-shot mode: The operation is performed for convert channels in the order of 1-channel, 2-channel, and 3channel. Note: After setting the start channel to the ANalog Start channel set (ANS2, ANS1, ANS0), please set neither the A/D converter mode set (MD1, MD0) nor the ANalog End channel set (ANE2, ANE1, ANE0) by the read-modify-write type instruction. The last conversion channel is read from the ANS2, ANS1, ANS0 bits until the A/D conversion operating starts. Therefore, when the MD1, MD0 bits and ANE2, ANE1, ANE0 bits are set by the read-modify-write type instruction after setting the start channel to the ANS2, ANS1, ANS0 bits, the value of ANE2, ANE1, ANE0 bits may be re-written. 301 CHAPTER 11 A/D CONVERTER 11.2.2 Data Register (ADCR) The data register (ADCR) stores the A/D conversion result. A digital value is stored as the result of conversion. ■ Data Register (ADCR) Figure 11.2-3 shows the bit configuration of the data register (ADCR). Figure 11.2-3 Bit Configuration of the Data Register (ADCR) Address: 000078H bit bit 15 X R 14 X R 13 X R 12 X R 11 X R 10 X R 9 9 X R 8 8 X R ←Initial value ←Read/Write 7 7 X R 6 6 X R 5 5 X R 4 4 X R 3 3 X R 2 2 X R 1 1 X R 0 0 X R ←Initial value ←Read/Write The data register (ADCR), which is a conversion storage register, stores a digital value that results from conversion. The value in the data register (ADCR) is updated every time a conversion session is completed. Normally, this register stores the last conversion value. This register is set to an undefined value by a reset. "0" is read from the high-order bits 15 to 10 during reading. A conversion data protection function is provided. For more information, see Section "11.4 Conversion Data Protection Function". 302 CHAPTER 11 A/D CONVERTER 11.3 A/D Converter Operation The A/D converter operates using the successive approximation conversion method and has a 10-bit resolution. Since the A/D converter has only one register (16 bits) for storing the conversion result, the conversion data register (ADCR) is updated each time one conversion session is completed. To perform continuous conversion, you can use the DMA transfer. The A/D converter has three modes: single-shot conversion mode, continuous conversion mode, and stop conversion mode. This section describes the operation of these modes. ■ Single-shot Conversion Mode This mode sequentially converts the analog input defined by the ANS and ANE bits and stops operation after performing conversion up to the end channel defined by the ANE bit. The one-channel conversion operation occurs when the start and end channels are the same (ANS=ANE). Example: If ANS=000, ANE=011: Beginning → AN0 → AN1→ AN2 → AN3→ End If ANS=010, ANE=010: Beginning→ AN2→ End ■ Continuous Conversion Mode This mode sequentially converts the analog input defined by the ANS and ANE bits, returns to the analog input of ANS after performing the conversion up to the end channel defined by the ANE bit, and continues the A/D conversion operation. The one-channel conversion operation is continued if the start and end channels are the same (ANS=ANE). Example: If ANS=000, ANE=011: Beginning → AN0→ AN1→ AN2 → AN3→ AN0→→→→ Repeated If ANS=010, ANE=010: Beginning → AN2 → AN2 → AN2→→→→ Repeated Continuous conversion mode continues to repeatedly perform conversion until "0" is written to the BUSY bit. Write "0" to the BUSY bit to forcibly terminate operation. Be careful when you forcibly terminate the operation because the conversion in progress is stopped before it is completed. If operation is forcibly terminated, the conversion register holds the previous data 303 CHAPTER 11 A/D CONVERTER that has been converted. ■ Stop Conversion Mode This mode sequentially converts the analog input defined by the ANS and ANE bits and stops operation each time conversion has been performed for one channel. To clear the temporary stop, start A/D conversion again. This mode returns to the analog input of ANS after performing conversion up to the end channel defined by the ANE bit and then continues the A/D conversion operation. The one-channel conversion operation is performed if the start and end channels are the same (ANS=ANE). Example: ANS=000, ANE=011 Beginning→ AN0 → Stop → Start → AN1 → Stop → Start → AN2 → Stop → Start → AN3 → Stop→ Start →AN0 →→→→ Repeated If ANS=010, ANE=010: Beginning → AN2 → Stop → Start → AN2 → Stop → Start → AN2→→→→ Repeated Only start sources defined by STS1 and STS0 are used at this time. Use this mode to synchronize the beginning of conversion. 304 CHAPTER 11 A/D CONVERTER 11.4 Conversion Data Protection Function The conversion data protection function trips if A/D conversion is executed while interrupts are enabled. This section describes the conversion data protection function. ■ Conversion Data Protection Function The A/D converter, which includes a conversion data protection function, can perform continuous conversion using DMAC and store multiple data items. Since the A/D converter has only one data register, continuously performing A/D conversion stores conversion data and discards the previous data each time a conversion session is completed. To protect data, the MB91307 series has a function whereby, even though the conversion has been completed, the MB91307 series does not store conversion data and temporarily stops the A/D conversion unless the previous data is transferred via DMAC to memory. The temporary stop is cleared after the data is transferred via DMA to memory. The A/D converter continuously performs the conversion without temporary stopping if the previous data has been transferred. Figure 11.4-1 shows an example of the flow of the data protection function. Note: This function is related to the INT and INTE bits of ADCS. The data protection function is enabled only if interrupts are enabled (INTE=1). This function is disabled if interrupts are disabled (INTE=0). If A/D conversion is continuously performed, the conversion data is stored in the register, causing the previous data to be lost. If DMA transfer is not used while interrupts are enabled (INTE=1), the INT bit is not cleared and the data protection function trips, causing the A/D converter to temporarily stop conversion. In this case, clear the INT bit in the interrupt sequence to clear the stop state. If, during a DMA operation, interrupts are disabled while the A/D converter is temporarily stopped, the A/D converter trips, changing the contents of the conversion data register before transferring them. The standby data is corrupted if a restart occurs while the A/D converter is temporarily stopped. 305 CHAPTER 11 A/D CONVERTER Figure 11.4-1 Example of the Flow of the Data Protection Function (while DMA Transfer is Used) DMAC setup A/D continuous conversion starts First conversion session ends Stored in data register DMAC startup Second conversion session ends Transfer ends No A/D temporarily stops Yes Stored in data register Third conversion session ends All conversion sessions ends End Yes Transfer ends No DMAC startup DMAC startup and transfer A/D stops DMAC end interrupt routine Note: The standby conversion data is corrupted if a restart occurs while the A/D converter is temporarily stopped. 306 CHAPTER 11 A/D CONVERTER 11.5 Precautions on the Using A/D Converter This section contains precautions on using the A/D converter. ■ Precautions on Using the A/D Converter To start the A/D converter using an external trigger or an internal timer, set the A/D start source bits (STS1 and STS0) of the ADCS register. At this time, the input value of an external trigger or an internal timer must be set to inactive. If it is set to active, a malfunction occurs. If STS1 and STS0 are set, set ATG=1 input and reload timer (channel 2)=0 output. A correct conversion result will not be obtained if the external impedance exceeds the specified value, since then the analog input value cannot be sampled within the specified sampling time. 307 CHAPTER 11 A/D CONVERTER 308 CHAPTER 12 UART This chapter describes the UART, the configuration and functions of registers, and UART operation. 12.1 Overview of the UART 12.2 UART Registers 12.3 UART Operation 12.4 Example of Using the UART 12.5 Example of Setting U-TIMER Baud Rates and Reload Values 309 CHAPTER 12 UART 12.1 Overview of the UART The UART is a serial I/O port used to perform asynchronous (start-stop synchronization) communication and CLK synchronous communication. The MB91307 series has three UART channels. ■ Features The UART has the following features: 310 • Full-duplex double buffer • Either asynchronous (start-stop synchronization) or CLK synchronous communication can be selected. • Multiprocessor mode is supported. • Fully programmable baud rate: An arbitrary baud rate can be set using a built-in timer. • An external clock can be used to set a baud rate. • Error detection functions (parity, framing, overrun) • The transfer signal is an NRZ code. • DMA transfer is started as the result of an interrupt. • The DMAC interrupt source is cleared if the DRCL register is written to. CHAPTER 12 UART ■ Block Diagram Figure 12.1-1 is a block diagram of the UART. Figure 12.1-1 Block Diagram of the UART Control signal Receive interrupt (to CPU) From U-TIMER External clock SC SC (clock) Send clock Clock selection circuit Receive clock SI (receive data) Send interrupt (to CPU) Receive control circuit Send control circuit Start bit detection circuit Send control circuit Receive bit counter Send bit counter Receive parity counter Send parity counter SO (send data) Receive status decision circuit Receive shifter Receiving completed SIDR Send shifter Sending starts SODR DMA receive error occurrence signal (To DMC) R-bus MD1 MD0 SMR register CS0 SCKE SOE SCR register PEN P SBL CL A/D REC RXE TXE SSR register PE ORE FRE RDRF TDRE RIE TIE Control signal 311 CHAPTER 12 UART 12.2 UART Registers This section describes the configuration and functions of the registers used by the UART. ■ UART Registers Figure 12.2-1 shows the registers used by the UART. Figure 12.2-1 UART Registers 15 8 7 0 SCR SMR (R/W) SSR SIDR(R)/SODR(W) (R/W) DRCL (W) 8-bit 312 8-bit 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 7 6 5 4 3 2 1 0 PE ORE FRE - RIE TIE 7 6 5 4 3 2 1 0 MD1 MD0 - - CS0 - SCKE - 7 6 5 4 3 2 1 0 PEN P SBL CL A/D REC RXE TXE 7 6 5 4 3 2 1 0 - - - - - - - - RDRF TDRE Serial Input Register Serial Output Register (SIDR/SODR) Serial Status Register (SSR) Serial Mode Register (SMR) Serial Control Register (SCR) (DRCL) CHAPTER 12 UART 12.2.1 Serial Mode Register (SMR) The serial mode register (SMR) specifies the UART operating mode. Set an operating mode while operation is stopped. Do not write to this register while operation is in progress. ■ Serial Mode Register (SMR) Figure 12.2-2 shows the bit configuration of the serial mode register (SMR). Figure 12.2-2 Bit Configuration of the Serial Mode Register (SMR) SMR Address: ch0 000063H ch1 00006BH ch2 000073H 7 MD1 R/W 6 MD0 R/W 5 - 4 - 3 CS0 W 2 - 1 SCKE R/W 0 - Initial value 00--0-0-B The following describes the functions of the serial mode register (SMR) bits. [Bits 7, 6] MD1, MD0 (MoDe select) These bits select a UART operating mode. Table 12.2-1 shows the settings for the UART operating modes. Table 12.2-1 Settings for UART Operating Modes Mode MDA MD0 Operating mode 0 0 0 Asynchronous (start-stop synchronization) normal mode [initial value] 1 0 1 Asynchronous (start-stop synchronization) multiprocessor mode 2 1 0 CLK synchronous mode − 1 1 Setting disabled Notes: • In Mode 1, which is CLK asynchronous mode (multiprocessor), more than one slave PC can be connected to one host CPU. Since this resource cannot identify the data format of received data, however, only the master in multiprocessor mode is supported. Because the parity check function cannot be used, set PEN of the SCR register to "0". • Set an operating mode while operation is stopped. Data sent and received while a mode is set is not guaranteed. Write to the DRCL register before starting DMA transfer resulting from an interrupt for the first time. [Bits 5, 4] (reserved) These bits are reserved. Always write "1" to these bits. 313 CHAPTER 12 UART [Bit 3] CS0 (Clock Select) This bit selects the UART operating clock. CS0 Operating clock 0 Built-in timer (U-TIMER) [initial value] 1 External clock [Bit 2] (reserved) This bit is reserved. Always write "0" to this bit. [Bit 1] SCKE (SCLK Enable) This bit specifies whether the SC pin is used as a clock input pin or a clock output pin when communication is performed in CLK synchronous mode (Mode 2). Set this bit to "0" in CLK asynchronous mode or external clock mode. SCKE Function 0 SC pin serves as clock input pin. [initial value] 1 SC pin serves as clock output pin. Note: When using the SC pin as a clock input pin, set the CS0 bit to "1" to select external clock mode. [Bit 0] (Reverse) This bit is reserved. 314 CHAPTER 12 UART 12.2.2 Serial Control Register (SCR) The serial control register (SCR) controls the transfer protocol that is used for serial communication. This section describes the configuration and functions of the serial control register (SCR) ■ Serial Control Register (SCR) Figure 12.2-3 shows the bit configuration of the serial control register (SCR). Figure 12.2-3 Bit Configuration of the Serial Control Register (SCR) SCR Address: ch0 000062H ch1 00006AH ch2 000072H 7 PEN R/W 6 P R/W 5 SBL R/W 4 CL R/W 3 A/D R/W 2 REC R/W 1 RXE R/W 0 TXE R/W Initial value 00000100B The following describes the functions of the serial control register (SCR) bits. [Bit 7] PEN (Parity Enable) This bit specifies whether to add parity in serial communication when data communication is performed. PEN Function 0 No parity [initial value] 1 Parity Note: Parity can be added only in normal mode (Mode 0) of asynchronous (start-stop synchronization) communication mode. No parity can be added in multiprocessor mode (Mode 1) or CLK synchronous communication mode (Mode 2). [Bit 6] P (Parity) This bit specifies that even or odd parity be added to perform data communication. P Parity 0 Even parity [initial value] 1 Odd parity 315 CHAPTER 12 UART [Bit 5] SBL (Stop Bit Length) This bit specifies the number of stop bits, which marks the end of a frame in asynchronous (start-stop synchronization) communication. SBL Stop bit length 0 1 stop bit [initial value] 1 2 stop bits [Bit 4] CL (Character Length) This bit specifies the data length of one frame that is sent or received. CL Data length of one frame 0 7 bits [initial value] 1 8 bits Note: 7-bit data can be handled only in normal mode (Mode 0) of asynchronous (start-stop synchronization) communication mode. Use 8-bit data in multiprocessor mode (Mode 1) or CLK synchronous communication mode (Mode 2). [Bit 3] A/D (Address/Data) This bit specifies the data format of a frame that is sent or received in multiprocessor mode (Mode 1) of asynchronous (start-stop synchronization) communication mode. A/D Data format of frame 0 Data frame [initial value] 1 Address frame [Bit 2] REC (Receiver Error Clear) Write "0" to this bit to clear the error flags (PE, ORE, and FRE) in the SSR register. Writing "1" to this bit has no effect. "1" is always read from this bit. [Bit 1] RXE (Receiver Enable) This bit controls the UART receive operation. RXE Enabling or disabling the receive operation 0 Disables receive operation. [initial value] 1 Enables receive operation. Note: If a receive operation is disabled while it is in progress (while data is being input to the receive shift register), reception of the frame is completed. The receive operation is stopped when the received data is stored in the receive data buffer register (SIDR). 316 CHAPTER 12 UART [Bit 0] TXE (Transmitter Enable) This bit controls the UART send operation. TXE Enabling or disabling send operation 0 Disables send operation. [initial value] 1 Enables send operation. Note: If a send operation is disabled while it is in progress (while data is being output from the transmission register), sending is stopped when no more send data is stored in the send data buffer register (SODR). 317 CHAPTER 12 UART 12.2.3 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) These registers are data buffer registers for receiving and sending. ■ Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) Figure 12.2-4 shows the bit configurations of the serial input data register (SIDR) and the serial output data register (SODR). Figure 12.2-4 Bit Configurations of the Serial Input Data Register (SIDR) and the Serial Output Data Register (SODR) SIDR Address: ch0 000061H ch1 000069H ch1 000071H 7 D7 R 6 D6 R 5 D5 R 4 D4 R 3 D3 R 2 D2 R 1 D1 R 0 D0 R Initial value Undefined 7 D7 W 6 D6 W 5 D5 W 4 D4 W 3 D3 W 2 D2 W 1 D1 W 0 D0 W Initial value Undefined SODR Address: ch0 000061H ch1 000069H ch2 000071H If the data length is 7 bits, Bit 7 (D7) is invalid data. Write to the SODR register only while the TDRE bit of the SSR register is set to "1". Note: Writing to the register with this address means writing to the SODR register. Reading from the register with this address means reading from the SIDR register. 318 CHAPTER 12 UART 12.2.4 Serial Status Register (SSR) The serial status register (SSR) consists of flags that indicate the operation state of the UART. This section describes the configuration and functions of the serial status register (SSR). ■ Serial Status Register (SSR) Figure 12.2-5 shows the bit configuration of the serial status register (SSR) Figure 12.2-5 Bit Configuration of the Serial Status Register (SSR) SSR Address: ch0 000060H ch1 000068H ch2 000070H 7 PE R 6 ORE R 5 FRE R 4 3 RDRF TDRE R R 2 - 1 RIE R/W 0 TIE R/W Initial value 00001-00B The following describes the functions of the serial status register (SSR) bits. [Bit 7] PE (Parity Error) This bit, which is an interrupt request flag, is set when a parity error occurs during receiving. PE Occurrence of parity error 0 No parity error has occurred. [initial value] 1 A parity error has occurred. To clear the flag when it has been set, write "0" to the REC bit (Bit 10) of the SCR register. If the PE bit is set, the SIDR data becomes invalid. [Bit 6] ORE (Over Run Error) This bit, which is an interrupt request flag, is set when an overrun error occurs during reception. ORE Occurrence of overrun error 0 No overrun error has occurred. [initial value] 1 An overrun error has occurred. To clear the flag when it has been set, write "0" to the REC bit of the SCR register. If the ORE bit is set, the SIDR data becomes invalid. [Bit 5] FRE (FRaming Error) This bit, which is an interrupt request flag, is set when a framing error occurs during 319 CHAPTER 12 UART reception. FRE Occurrence of framing error 0 No framing error has occurred. [initial value] 1 A framing error has occurred. To clear the flag when it has been set, write "0" to the REC bit of the SCR register. If the FRE bit is set, the SIDR data becomes invalid. Note: Switch the internal and external baud rate clocks using Bit 3 of the serial mode register only while the UART is stopped, since the switching takes effect immediately after writing. Bit 3 of the serial mode register is write-only. [Bit 4] RDRF (Receiver Data Register Full) This bit, which is an interrupt request flag, indicates that the SIDR register has receive data. RDRF Presence of receive data 0 No receive data exists. [initial value] 1 Receive data exists. This bit is set when receive data is loaded into the SIDR register. It is automatically cleared when the data is read from the SIDR register. [Bit 3] TDRE (Transmitter Data Register Empty) This bit, which is an interrupt request flag, indicates whether send data can be written to SODR. TDRE Disabling or enabling writing of send data 0 Disables writing of send data. 1 Enables writing of send data. [initial value] This bit is cleared when send data is written to the SODR register. It is set again when the written data is loaded into the send shifter and begins to be transferred, indicating that the next send data can be written. [Bit 2] (reserved) This bit is reserved. [Bit 1] RIE (Receiver Interrupt Enable) This bit controls a reception interrupt. RIE 320 Disabling or enabling receive interrupts 0 Disables receive interrupts. [initial value] 1 Enables receive interrupts. CHAPTER 12 UART Note: Receive interrupt sources include errors due to PE, ORE, and FRE as well as normal receive due to RDRF. [Bit 0] TIE (Transmitter Interrupt Enable) This bit controls send interrupts. TIE Disabling or enabling send interrupts 0 Disables send interrupts. [initial value] 1 Enables send interrupts. Note: Send interrupt sources include send requests due to TDRE. 321 CHAPTER 12 UART 12.2.5 DRCL Register The DRCL register clears a DMAC interrupt source. ■ DRCL Register Figure 12.2-6 shows the configuration of the DRCL register. Figure 12.2-6 Configuration of the DRCL Register DRCL Address: ch0 000066H ch1 00006EH ch2 000076H 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0 W Initial value --------B Write an arbitrary value to the DRCL register to clear a DMAC interrupt source. When the DMAC is started for the first time or when the UART has already been used, use this register to clear an interrupt source. This register is write-only. 322 CHAPTER 12 UART 12.3 UART Operation The UART has two operating modes: asynchronous (start-stop synchronization) mode and CLK mode. Asynchronous (start-stop synchronization) mode consists of normal and multiprocessor mode. This section describes the operation of these operating modes. ■ Operating Modes The UART has the operating modes shown in Table 12.3-1. Set a value in the SMR and SCR registers to switch mode. Table 12.3-1 UART Operating Modes Mode Parity Data length Operating mode Yes/No 7 Yes/No 8 Asynchronous (start-stop synchronization) normal mode 1 No 8+1 Asynchronous (start-stop synchronization) multiprocessor mode 2 No 8 CLK mode 0 Stop bit length 1 bit or 2 bits No Note: The stop bit length in asynchronous (start-stop synchronization) mode can be specified only for a send operation. The stop bit length is always one bit for a receive operation. Since operation is possible only in the above modes, do not make any other setting. ■ Selecting a Clock for the UART ❍ Internal timer If you select the U-TIMER by setting CS0 to "0", the baud rate is determined according to the reload value set for the U-TIMER. At this time, you can calculate the baud rate as follows: Asynchronous (start-stop synchronization) : φ/(16 × β) CLK synchronous : φ/β φ : Peripheral machine clock frequency β : Cycle defined for the U-TIMER (2n+2 or 2n+3, n is the reload value.) In asynchronous (start-stop synchronization) mode, data can be transferred in the range from -1% to +1% of the specified baud rate. 323 CHAPTER 12 UART ❍ External clock If you select an external clock by setting CS0 to "1", the baud rate is as follows (the frequency of the external clock is assumed to be f): Asynchronous (start-stop synchronization): f/16 CLK synchronous :f Note, however, that the maximum value for f is 3.125 MHz. 324 CHAPTER 12 UART 12.3.1 Asynchronous (Start-stop Synchronization) Mode When the UART is used in Operating Mode 0 (normal mode) or Operating Mode 1 (multiprocessor mode), the asynchronous transfer method is used. ■ Transfer Data Format UART handles only data in the NRZ (Non Return to Zero) format. Figure 12.3-1 shows the data format. Figure 12.3-1 Transfer Data Format (Modes 0 and 1) SI,SO 0 1 0 Start LSB 1 1 0 0 1 0 1 1 MSB Stop A/D Stop (Mode 0) (Mode 1) Data that has been transferred is 01001101B. As shown in Figure 12.3-1, the transfer of data always starts with the start bit ("L" level data), continues as long as the data bit length specified in LSB First, and ends with a stop bit ("H" level data). If an external clock is selected, always input a clock. The data length can be set to 7 or 8 bits in normal mode (Mode 0), but must be set to 8 bits in multiprocessor mode (Mode 1). In multiprocessor mode, no parity can be added; instead, the A/ D bit is always added. ■ Receive Operation If the RXE bit (Bit 1) of the SCR register is set to "1", a receive operation is always in progress. If a start bit appears on the receive line, one-frame data is received according to the data format specified in the SCR register. If an error occurs before reception of one frame is completed, the error flag is set and then the RDRF flag (Bit 4 of the SSR register) is set. If, at this time, the RIE bit (Bit 1) of the same SSR register is set to "1", a receive interrupt is generated for the CPU. Check the flags of the SSR register and read the SIDR register if normal reception has occurred or perform the necessary processing if an error has occurred. The RDRF flag is cleared when the SIDR register is read. ■ Send Operation If the TDRE flag (Bit 3) of the SSR register is set to "1", send data is written to the SODR register. If, at this time, the TXE bit (bit 0) of the SCR register is set to "1", transmission occurs. The TDRE flag is set again when the data set in the SODR register is loaded into the send shift register and begins to be transferred, indicating that the next send data can be set. If, at this time, the TIE bit (bit 0) of the same SSR register is set to "1", a send interrupt requesting that the send data be set in the SODR register is generated for the CPU. The TDRE flag is cleared if data is set in the SODR register. 325 CHAPTER 12 UART ■ Detecting the start bit Implement the following settings to detect the start bit: • Set the communication line level to "H" (attach the mark level) before the communication period. • Specify reception permission (RXE = H) while the communication line level is "H" (mark level). • Do not specify reception permission (RXE = H) for periods other than the communication period (without mark level). Otherwise, data is not received correctly. • After the stop bit is detected (the RDRF flag is set to "1"), specify reception inhibition (RXE = L) while the communication line level is "H" (mark level). Figure 12.3-2 Normal Operation Communication period Non-communication period Mark level Start bit SIN ST Non-communication period Stop bit Data D0 D1 D0 D1 D2 D3 D4 D5 D6 D7 SP (Sending 01010101b) RXE Receive clock Sampling clock Receive clock (8 pulse) Recognition by the microcontroller ST Generating sampling clocks by dividing the receive clock by 16 D2 D3 D4 D5 D6 D7 SP (Receiving 01010101b) Note that specifying reception permission at the timing shown below obstructs the correct recognition of the input data (SIN) by the microcontroller. • Example of operation if reception permission (RXE = H) is specified while the communication line level is "L". Figure 12.3-3 Error Operation Communication period Non-communication period Mark level Start bit SIN (Sending 01010101b) RXE Non-communication period Stop bit Data ST D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SP SP Receive clock Sampling clock Recognition by the microcontroller ST recognition (Receiving 10101010b) PE,ORE,FRE Occurrence of a reception error 326 CHAPTER 12 UART 12.3.2 CLK Synchronous Mode If the UART is used in Operating Mode 2, the clock synchronous transfer method is used. ■ Transfer Data Format The UART handles only data in the NRZ (Non Return to Zero) format. Figure 12.3-4 shows the relationship between send and receive clocks and data. Figure 12.3-4 Transfer Data Format (Mode 2) Writing to SODR Mark SC RXE, TXE SI, SO 1 0 1 1 0 0 1 0 LSB MSB (Mode 2) Data that has been transferred is 01001101B. When the internal clock (U-TIMER) has been selected, a data receive synchronous clock is automatically generated as soon as data is received. While an external clock has been selected, you must check that data exists in the send data buffer SODR register of the send side UART (TDRE flag is 0) and then supply an accurate clock for one byte. Before sending starts and after it ends, be sure to set the mark level. The data length is 8 bits only, and no parity can be added. Only overrun errors are detected because there is no start or stop bit. 327 CHAPTER 12 UART ■ Initialization The following shows the setting values of the control registers required to use CLK synchronous mode. • • • SMR register • MD1, MD0: "10" • CS: Specifies the clock input. • SCKE: Set to "1" for an internal timer and to "0" for an external clock. • SOE: Set to "1" for send and to "0" for receive. SCR register • PEN: "0" • P,SBL,A/D: These bits are meaningless. • CL: "1" • REC: 0 (to initialize the register) • RXE, TXE: At least one of the bits must be set to "1". SSR register • RIE: Set to "1" to enable interrupts and to "0" to disables interrupts. • TIE: "0" ■ Start of Communication Write to the SODR register to start communication. If only reception is performed, dummy send data must be written to the SODR register. ■ End of Communication Check for the end of communication by making sure that the RDRF flag of the SSR register has changed to "1". Use the ORE bit of the SSR register to check that communication has been performed correctly. 328 CHAPTER 12 UART 12.3.3 Occurrence of Interrupts and Timing for Setting Flags The UART has five flags and two interrupt sources. The five flags are PE, ORE, FRE, RDRF, and TDRE. PE means parity error, ORE means overrun error, and FRE means framing error. These flags are set when an error occurs during reception and are then cleared when "0" is written to REC of the SCR register. RDRF is set when receive data is loaded into the SIDR register and then cleared when data is read from the SIDR register. Mode 1 does not provide a parity detection function. Mode 2 does not provide a parity detection function or a framing error function. TDRE is set when the SODR register is empty, and writing to it is enabled and then cleared when data is written to the SODR register. ■ Occurrence of Interrupts and Timing for Setting Flags There are two interrupt sources, one for receiving and one for sending. During receiving, an interrupt is requested due to PE, ORE, FRE, or RDRF. During sending, an interrupt is requested due to TDRE. The following shows the timing for setting the interrupt flags in each of these modes. ❍ Receive operation in Mode 0 The PE, ORE, FRE, and RDRF flags are set when the last stop bit is detected after a receive transfer is completed, causing an interrupt request to be generated for the CPU. The SIDR data is invalid while PE, ORE, and FRE are active. Figure 12.3-5 shows the timing for setting ORE, FRE, and RDRF in Mode 0. Figure 12.3-5 Timing for Setting ORE, FRE, and RDRF (Mode 0) Data D6 D7 Stop PE,ORE,FRE RDRF Receive interrupt 329 CHAPTER 12 UART ❍ Receive operation in Mode 1 The ORE, FRE, and RDRF flags are set when the last stop bit is detected after a receive transfer is completed, causing an interrupt request to be generated for the CPU. The data indicating an address or the data in Bit 9 is invalid because the length of data that can be received is 8 bits. The SIDR data is invalid while ORE and FRE are active. Figure 12.3-6 shows the timing for setting ORE, FRE, and RDRF in Mode 1. Figure 12.3-6 Timing for Setting ORE, FRE, and RDRF (Mode 1) Data D6 Address/Data Stop ORE,FRE RDRF Receive interrupt ❍ Reception operation in Mode 2 The ORE and RDRF flags are set when the last data (D7) is set after the reception transfer is completed, generating an interrupt request to the CPU. The SIDR data is invalid while ORE is active. Figure 12.3-7 shows the timing of setting ORE and RDRF in Mode 2. Figure 12.3-7 Timing of Setting ORE and RDRF (Mode 2) Data ORE RDRF Receive interrupt 330 D5 D6 D7 CHAPTER 12 UART ❍ Send operation in modes 0, 1, and 2 TDRE is cleared when data is written to the SODR register. This bit is set when data is transferred to the internal shift register and the next data can be written, causing an interrupt request to be generated for the CPU. If "0" is written to TXE of the SCR register (as well as RXE in mode 2) during a send operation, TDRE of the SSR register is set to "1", disabling the UART send operation after the transmission shifter stops. The device sends data written to the SODR register before transmission stops after "0" is written to the TXE of the SCR register (as well as RXE in mode 2) during the send operation. Figure 12.3-8 shows the timing for setting TDRE in Modes 0 and 1. Figure 12.3-9 shows the timing for setting TDRE in Mode 2. Figure 12.3-8 Timing for Setting TDRE (Modes 0 and 1) Writing to SODR TDRE Interrupt request to CPU SO interrupt SO output ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3 A/D ST: Start bit, D0 to D7: Data bits SP: Stop bit, A/D: Address/data multiplexer Figure 12.3-9 Timing for Setting TDRE (Mode 2) Writing to SODR TDRE Interrupt request to CPU SO interrupt SO output D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 to D7: Data bits ■ Precautions on Usage Set an operating mode when operation has stopped. Data sent and received while a mode is set is not guaranteed. Write to the DRCL register before starting DMA transfer due to an interrupt for the first time. 331 CHAPTER 12 UART 12.4 Example of Using the UART This section provides an example of using the UART. Mode 1 is used if more than one slave PC is connected to a single host CPU. ■ Example of Using the UART Figure 12.4-1 shows an example of constructing a system using mode 1. This resource supports only a communications interface on the host. Figure 12.4-1 Example of Constructing a System Using Mode 1 SO SI Host CPU SO SI Slave CPU #0 SO SI Slave CPU #1 Communication starts when the host CPU transfers address data. Address data is data used when A/D of the SCR register is set to "1". This data is used to select a destination slave CPU, enabling communication with the host CPU. Normal data is data used when A/D of the SCR register is set to "0". Figure 12.4-2 shows the flowchart. In this mode, set the PEN bit of the SCR register to "0", since the parity check function cannot be used. 332 CHAPTER 12 UART Figure 12.4-2 Communication Flowchart in Mode 1 (Host CPU) START Set transfer mode to "1". Set data used to select slave CPUs in D0 to D7, set "1" in A/D, and transfer one byte. Set "0" in A/D. Enable receive operation. Communicate with a slave CPU. Communication completed? No Yes Communicate with other slave CPUs? No Yes Disable the receive operation. END 333 CHAPTER 12 UART 12.5 Example of Setting U-TIMER Baud Rates and Reload Values This section provides an example of setting U-TIMER baud rates and reload values. ■ Example of Setting U-TIMER Baud Rates and Reload Values Table 12.5-1 shows setting values to be used in asynchronous (start-stop synchronization) mode. Table 12.5-2 shows setting values to be used in CLK synchronous mode. A frequency in the tables represents a peripheral machine clock frequency. UCC1 is a value to be set in the UCC1 bit of the UTIMC register of the U-TIMER. A dash (-) in the tables means that the baud rate cannot be used because the error exceeds plus minus 1%. Table 12.5-1 Setting Values in Asynchronous (Start-Stop Synchronization) Mode Baud rate (bps) ms 33MHz 20MHz 16.5MHz 10MHz 1200 833.33 858(UCC1=0) 520(UCC1=0) 428(UCC1=1) 259(UCC1=1) 2400 416.67 428(UCC1=1) 259(UCC1=1) 214(UCC1=0) 129(UCC1=0) 4800 208.33 214(UCC1=0) 129(UCC1=0) 106(UCC1=0) 64(UCC1=0) 9600 104.17 106(UCC1=1) 64(UCC1=0) 52(UCC1=1) 31(UCC1=1) 19200 52.08 52(UCC1=1) 31(UCC1=1) 26(UCC1=0) − 38400 26.04 26(UCC1=0) − 12(UCC1=1) − 57600 17.36 17(UCC1=0) − 8(UCC1=0) − 10400 96.15 98(UCC1=0) 59(UCC1=0) 48(UCC1=1) 29(UCC1=0) 31250 32.00 32(UCC1=0) 19(UCC1=0) 15(UCC1=1) 9(UCC1=0) 62500 16.00 15(UCC1=1) 9(UCC1=0) − 4(UCC1=0) Table 12.5-2 Setting Values in CLK Synchronous Mode Baud rate (bps) ms 33MHz 20MHz 16.5MHz 10MHz 250k 4.00 65(UCC1=0) 39(UCC1=0) 32(UCC1=0) 19(UCC1=0) 500k 2.00 32(UCC1=0) 19(UCC1=0) 15(UCC1=1) 9(UCC1=0) 1M 1.00 15(UCC1=1) 9(UCC1=0) 7(UCC1=0) * 4(UCC1=0) *: An error exceeding plus minus 1% occurs. 334 CHAPTER 13 I2C INTERFACE This chapter describes the I2C interface, the configuration and functions of registers, and I2C interface operation. 13.1 Overview of the I2C Interface 13.2 I2C Interface Registers 13.3 I2C Interface Operation 13.4 Operation Flowcharts 335 CHAPTER 13 I2C INTERFACE 13.1 Overview of the I2C Interface The I2C interface is a serial I/O port that supports Inter IC BUS. ■ Features The I2C interface serves as a master or slave device on the I2C bus and has the following features: 336 • Master or slave sending and receiving • Arbitration function • Clock synchronization function • Slave address and general call address detection function • Transfer direction detection function • Function that repeatedly generates and detects a start condition • Bus error detection function • 10-bit and 7-bit master and slave addresses • Standard mode (maximum of 100 Kbps) and high-speed mode (maximum of 400 Kbps at the maximum) available • Generation of transfer end interrupts and bus error interrupts CHAPTER 13 I2C INTERFACE ■ Block Diagram Figure 13.1-1 is a block diagram of the I2C interface. Figure 13.1-1 Block Diagram of the I2C Interface R-bus ICCR EN I2C operation enable IDBL DBL Clock enable ICCR Clock division 2 2345 32 CS4 CS3 CS2 CS1 CS0 IBSR BB RSC LRB TRX Sync Shift clock generation Clock selection 2 (1/12) Shift clock edge change timing Bus busy Repeat start Last Bit Start-stop condition detection Send/receive Error ADT First Byte Arbitration lost detection AL IBCR SCL BER BEIE IBCR SCC MSS ACK GCAA End Start Master ACK enable Start-stop condition generation GC-ACK enable IDAR IBSR AAS SDA Interrupt request INTE INT Slave Global call GCA Slave address comparison ENTB ISMK RAL ITBA ITMK ISBA ISMK 337 CHAPTER 13 I2C INTERFACE 13.2 I2C Interface Registers This section describes the configuration and functions of registers used by the I2C interface. ■ I2C Interface Registers Figure 13.2-1 shows the registers used by the I2C interface. Figure 13.2-1 I2C Interface Registers (1/2) ❍ Bus control register (IBCR) Address : 000094H Initial value→ 15 14 13 12 11 10 9 8 BER BEIE SCC MSS ACK GCAA INTE INT R/W R/W W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 BB R 0 RSC R 0 AL R 0 LRB R 0 TRX R 0 AAS R 0 GCA R 0 ADT R 0 15 - 14 - 13 - 12 - 11 - 10 - - - - - - - 9 TA9 R/W 0 8 TA8 R/W 0 7 6 5 4 3 2 1 0 TA6 R/W 0 TA5 R/W 0 TA4 R/W 0 TA3 R/W 0 TA2 R/W 0 TA1 R/W 0 TA0 R/W 0 ❍ Bus status register (IBSR) Address : 000095H Initial value→ ❍ 10-bit slave address register Address : 000096H Initial value→ Address : 000097H TA7 R/W Initial value→ 0 338 CHAPTER 13 I2C INTERFACE Figure 13.2-1 I2C Interface Registers (2/2) ❍ 10-bit slave address mask register (ITMK) 15 ENTB R/W Initial value→ 0 14 RAL R 0 Address : 000098H 7 Address : 000099H TM7 R/W Initial value→ 1 13 - 12 - 11 - 10 - - - - - 9 TM9 R/W 1 8 TM8 R/W 1 6 5 4 3 2 1 0 TM6 R/W 1 TM5 R/W 1 TM4 R/W 1 TM3 R/W 1 TM2 R/W 1 TM1 R/W 1 TM0 R/W 1 ❍ 7-bit slave address register (ISBA) Address : 00009BH Initial value→ 7 6 5 4 3 2 1 0 - SA6 R/W 0 SA5 R/W 0 SA4 R/W 0 SA3 R/W 0 SA2 R/W 0 SA1 R/W 0 SA0 R/W 0 - ❍ 7-bit slave address mask register (ISMK) 15 ENSB Address : 00009AH R/W Initial value→ 0 14 13 12 11 10 9 8 SM6 R/W 1 SM5 R/W 1 SM4 R/W 1 SM3 R/W 1 SM2 R/W 1 SM1 R/W 1 SM0 R/W 1 6 5 4 3 2 1 0 D6 R/W 0 D5 R/W 0 D4 R/W 0 D3 R/W 0 D2 R/W 0 D1 R/W 0 D0 R/W 0 ❍ Data register (IADR) 7 Address : 00009DH D7 R/W Initial value→ 0 ❍ Clock control register (ICCR) 15 14 13 12 11 10 9 8 - EN R/W 0 CS4 R/W 1 CS3 R/W 1 CS2 R/W 1 CS1 R/W 1 CS0 R/W 1 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - DBL R/W 0 Address : 00009EH TEST W Initial value→ 0 ❍ Clock disable register (IDBL) Address : 00009FH Initial value→ 339 CHAPTER 13 I2C INTERFACE 13.2.1 Bus Status Register (IBSR) The bus status register (IBSR) indicates the status of the I2C interface. This register is read-only. ■ Bus Status Register (IBSR) Figure 13.2-2 shows the bit configuration of the bus status register (IBSR). Figure 13.2-2 Bit Configuration of the Bus Status Register (IBSR) Address : 000095H Initial value→ 7 6 5 4 3 2 1 0 BB R 0 RSC R 0 AL R 0 LRB R 0 TRX R 0 AAS R 0 GCA R 0 ADT R 0 This register is cleared when the interface is stopped (ICCR EN=0). The following describes the functions of the bus status register (IBSR) bits. [Bit 7] BB (Bus Busy) This bit indicates the status of the I2C bus. 0 STOP condition detected (bus idle) 1 START condition detected (bus used) [Bit 6] RSC (Repeated Start Condition) This bit is the repeated START detection bit. 0 Repeated START condition not detected 1 Repeated START condition detected while bus is being used This bit is cleared when the address data transfer ends (ADT=0) or when the STOP condition is detected. [Bit 5] AL (Arbitration Lost) This bit is the arbitration lost detection bit. 0 Arbitration lost not detected 1 Arbitration lost detected during master transmission Write "0" to the INT bit or 1 to the MSS bit of the IBCR register to clear this bit. Arbitration lost is detected if: • The transmission data does not match the data on the SDA line at the rising edge of SCL. • A repeated START condition is generated in the first bit of the data by another master. • No START or STOP condition can be generated because the SCL line is driven to L by another slave device. 340 CHAPTER 13 I2C INTERFACE [Bit 4] LRB (Last Received Bit) This bit is an acknowledge storage bit that stores an acknowledge from the receiving device. 0 Slave acknowledge detected 1 Slave acknowledge not detected This bit is rewritten if an acknowledge is detected (reception 9 bits). This bit is cleared if a START or STOP condition is detected. [Bit 3] TRX (Transferring Data) This bit indicates the transmission status during a data transfer. 0 Data transmission stopped 1 Data transmission in progress This bit is set to "1" if: • A START condition occurs in master mode. • When the transfer of the first byte ends or this bit is read in slave mode or when data is sent in master mode, this bit is set to "0" if: • The bus is idle (IBCR BB=0). • An arbitration loss occurs. • "1" is written to the SCC bit in the master interrupt status (MSS=1, INT=1). • The MSS bit is cleared in the master interrupt status (MSS=1, INT=1). • No acknowledge occurred for the last transfer byte in slave mode. • Data is received in slave mode. • Data is received from a slave in master mode. [Bit 2] AAS (Addressed As Slave) This bit is the slave addressing detection bit. 0 No addressing in slave mode 1 Addressing in slave mode This bit is cleared when a (repeated) START or STOP condition is detected. This bit is set when a 7-bit or 10-bit slave address is detected. [Bit 1] GCA (General Call Address) This bit is the general call address (00H) detection bit. 0 No general call address received in slave mode 1 General call address received in slave mode This bit is cleared when a (repeated) START or STOP condition is detected. 341 CHAPTER 13 I2C INTERFACE [Bit 0] ADT (Address Data Transfer) This bit is the address data detection bit. 0 Received data is not an address (or the bus is open). 1 Received data is an address. This bit is set to "1" if a START condition is detected. It is cleared after the second byte if, during write access, the header section of a 10-bit slave address is detected. Otherwise, it is cleared after the first byte. "After the first or second byte" means the following: • Writing "0" to the MCC bit during master interrupt (MSS=1, INT=1) • Writing "1" to the SCC bit during master interrupt (MSS=1, INT=1) • Clearing the INT bit • Beginning of a transfer byte that is not used for the transfer destination as master or slave 342 CHAPTER 13 I2C INTERFACE 13.2.2 Bus Control Register (IBCR) This section describes the configuration and functions of the bus control register (IBCR). ■ Bus Control Register (IBCR) Figure 13.2-3 shows the bit configuration of the bus control register (IBCR). Figure 13.2-3 Bit Configuration of the Bus Control Register (IBCR) Address : 000094H Initial value→ 15 14 13 12 11 10 9 8 BER BEIE SCC MSS ACK GCAA INTE INT R/W R/W W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits other than BER and BEIE are cleared if the interface is stopped (ICCR EN=0). The following describes the functions of the bus control register (IBCR) bits. [Bit 15] BER (Bus ERror) This bit is the bus error interrupt request flag bit. For a read by a read modify instruction, "1" is always read. During writing 0 Clears the bus error interrupt request flag. 1 Irrelevant During reading 0 Bus error not detected 1 Bus error detected If this bit is set, the EN bit of the CCR register is cleared, stopping the I2C interface and halting data transfer. All bits other than BER and BEIE are cleared. This bit must be cleared before operation is enabled (ICCR EN=1) again. This bit is set to "1" if: • An illegal START or STOP condition at a specific location is detected (while an address or data is being transferred).* • The header section of a 10-bit read access is received before a 10-bit write access is performed. * • A STOP condition is detected in master mode. *: While the I2C interface is enabled during transfer, this detection is performed after the first [STOP] condition is received to prevent an illegal bus error report. 343 CHAPTER 13 I2C INTERFACE [Bit 14] BEIE (Bus Error Interrupt Enable) This bit is the bus error interrupt enable bit. 0 Bus error interrupt disabled 1 Bus error interrupt enabled An interrupt occurs if this bit is set to "1" and the BER bit is set to "1". [Bit 13] SCC (Start Condition Continue) This bit is the repeated [START] condition generation bit. During writing 0 Irrelevant 1 Generates a repeated START condition in master transfer. The read value of this bit is always "0". If, during an interrupt in master mode, this bit is set to "1" to generate a write START condition, the INT bit is automatically cleared. [Bit 12] MSS (Master Slave Select) This bit is the master or slave selection bit. 0 Selects slave mode. 1 Selects master mode. Generates a START condition to enable the value of the IDAR register to be sent as a slave address. This bit is cleared when arbitration lost occurs during master transmission, causing slave mode to start. Write "0" to this bit during a master interrupt (MSS=1, INT=1) to automatically clear the INT bit. Then, generate a [STOP] condition to end the transfer. Note: The MSS bit is directly reset. To detect a STOP condition, check the BB bit of the IBSR register. Write "1" while the bus is idle (MSS=0, BB=0) to generate a START condition. The contents of the IDAR register are also sent. While the bus is being used (IBSR register BB=1, TRX=0, IBCR register MSS=0), write "1" to the MSS bit to cause the interface to start transmission after waiting for the bus to be opened. If, during this time, the I2C interface is specified as the address for a slave that is accompanied by a write access, the bus is opened after the transfer ends. If the interface is transmitting as a slave (IBCS AAS=1, TRX=1) during this time, no data is sent even if the bus has been opened. It is important to check whether the I2C interface is specified as a slave (IBSR AAS=1), whether data transmission is normal at the next interrupt, and whether an illegal termination has occurred (IBSR AL=1). If there are the other master mode LSIs on the bus, MB91307 series can not use as master mode. 344 CHAPTER 13 I2C INTERFACE • Example of usable as master mode I2C bus MB91307 series Slave A Slave B Master I2C bus MB91307 series Slave A Master A Slave • Example of non-usable as master mode I2C bus MB91307 series Slave A Master A Master When using on the following condition, the transmission of the general call address is prohibited because it cannot receive it as a slave. • When other LSI that becomes a mastering mode besides this LSI exists on the bus and this LSI transmits the general call address as a master and the arbitration lost is generated since the second byte. [Bit 11] ACK (ACKnowledge) This bit is an acknowledge enable bit used when data is received. 0 Acknowledge not generated when data is received 1 Acknowledge generated when data is received This bit is disabled when address data is received in slave mode. An acknowledge is generated if the interface detects a 7-bit or 10-bit slave address when the enable bits (ENTB ITMK, ENSB ISMK) are set. Write to this bit while an interrupt exists (INT=1), the bus is idle (IBSR BB=1), or the interface is disabled (ICCR register EN=1). 345 CHAPTER 13 I2C INTERFACE [Bit 10] GCAA (General Call Address Acknowledge) This bit is an acknowledge enable bit used when a general call address is received. 0 Acknowledge not generated when general call address is received 1 Acknowledge generated when general call address is received Write to this bit while an interrupt exists (INT=1), the bus is idle (IBSR BB=1), or the interface is disabled (ICCR register EN=1). [Bit 9] INTE (INTerrupt Enable) This bit is the interrupt enable bit. 0 Interrupts disabled 1 Interrupts enabled When this bit is "1", interrupt is generated if the INT bit is "1". [Bit 8] INT (INTerrupt) This bit is the transfer end interrupt request flag bit. For a read by a read modify instruction, "1" is read. During writing 0 Clears the transfer end interrupt request flag. 1 Irrelevant During reading 0 • • • Transfer not ended Not a transfer target Bus is open. 1 This bit is set to 1 if a one-byte transfer that includes the acknowledge bit is completed and the following conditions are met: • Bus master • Addressed slave • A general call address was received. • Arbitration lost occurred. If the interface is specified as a slave address, this bit is set at the end of slave address reception that includes an acknowledge. If this bit is set to "1", the SCL line is maintained at the "L" level. Write "0" to this bit to clear it and to open the SCL line to transfer the next byte. In master mode, a START or STOP condition is generated. This bit is cleared when the SCC bit is set to "1" or the MSS bit is cleared. Note: If data is simultaneously written to the SCC, MSS, and INT bits, contention occurs between the next-byte transfer, START condition generation, and STOP condition generation. If this situation occurs, the priorities are as follows: 1. Next-byte transfer and STOP condition generation 346 CHAPTER 13 I2C INTERFACE When the INT bit is set to "0" and the MSS bit is set to "0", writing of the MSS bit has precedence and a STOP condition is generated. 2. Next-byte transfer and START condition generation When the INT bit is set to "0" and the SCC bit is set to "1", writing of the SCC bit has precedence and a START condition is generated. Contention occurs if a repeated start condition is sent to the IDAR register. 3. Repeated START condition generation and STOP condition generation When the SCC bit is set to "1" and the MSS bit is set to "0" at the same time, clearing of the MSS bit has precedence. A STOP condition is generated and the interface enters slave mode. Note: When an instruction which generates a start condition is executed (the MSS bit is set to "1") at the timing shown in Figure 13.2-4 and Figure 13.2-5, arbitration lost detection (AL bit = 1) prevents an interrupt (INT bit = 1) from being generated. • Condition "1" in which an interrupt (INT bit = 1) upon detection of "AL bit = 1" does not occurs When an instruction which generates a start condition is executed (setting the MSS bit in the IBCR register to "1") with no start condition detected (BB bit = 0) and with the SDA or SCL pin at the "L" level. Figure 13.2-4 Diagram of timing at which an interrupt upon detection of "AL bit = 1" does not occur SCL or SDA pin at "L" level SCL pin SDA pin "L" "L" 1 I2C operating enable state (EN bit = 1) Master mode setting (MSS bit = 1) Arbitration lost detection bit (AL bit = 1) Bus busy (BB bit ) 0 Interrupt (INT bit ) 0 • Condition "2" in which an interrupt (INT bit = 1) upon detection of "AL bit = 1" does not occurs When an instruction which generates a start condition by enabling I2C operation (EN bit = 1) is executed (setting the MMS bit in the IBCR register to "1") with the I2C bus occupied by another master. This is because, as shown in Figure 13.2-5, when the other master on the I2C bus starts communication with I2C disabled (EN bit = 0), the I2C bus enters the occupied state with no start condition detected (BB bit = 0). 347 CHAPTER 13 I2C INTERFACE Figure 13.2-5 Diagram of timing at which an interrupt upon detection of "AL bit = 1" does not occur The INT bit interrupt does not occur in the ninth clock cycle. Start Condition Stop Condition SCL pin SDA pin SLAVE ADDRESS ACK DAT ACK EN bit MSS bit AL bit BB bit 0 0 INT bit If a symptom as described above can occur, follow the procedure below for software processing. 1) Execute the instruction that generates a start condition (set the MSS bit to "1"). 2) Use, for example, the timer function to wait for the time* for three-bit data transmission at the I2C transfer frequency set in the ICCR register. Example: Time for three-bit data transmission at an I2C transfer frequency of 100 kHz {1/(100 × 103)} × 3 = 30 µs 3) Check the AL and BB bits in the IBSR register and, if the AL and BB bits are "1" and "0", respectively, set the EN bit in the ICCR register to "0" to initialize I2C. When the AL and BB bits are not so, perform normal processing. A sample flow is given below. Master mode setting Set the MSS bit in the bus control register (IBCR) to "1". Wait * for the time for three-bit data transmission at the I2C transfer frequency set in the clock control register (ICCR). BB bit = 0 and AL bit = 1 ? no yes Set the EN bit to "0" to initialize I2C to normal process *: When "arbitration lost" is detected, the MSS bit is set to "1" and then the AL bit is set to "1" without fail after the time for three-bit data transmission at the I2C transfer frequency. 348 CHAPTER 13 I2C INTERFACE • Example of occurrence of an interrupt (INT bit = 1) upon detection of "AL bit = 1" When an instruction which generates a start condition is executed (setting the MSS bit to "1") with "bus busy" detected (BB bit = 1) and arbitration is lost, the INT bit interrupt occurs upon detection of "AL bit = 1". Figure 13.2-6 Diagram of timing at which an interrupt upon detection of "AL bit = 1" occurs Start Condition Interrupt in the ninth clock cycle SCL pin SDA pin SLAVE ADDRESS ACK DAT EN bit MSS bit AL bit BB bit Clearing the AL bit by software Releasing the SCL by clearing the INT bit by software INT bit 349 CHAPTER 13 I2C INTERFACE 13.2.3 Clock Control Register (ICCR) This section describes the configuration and functions of the clock control register (ICCR). ■ Clock Control Register (ICCR) Figure 13.2-7 shows the bit configuration of the clock control register (ICCR). Figure 13.2-7 Bit Configuration of the Clock Control Register (ICCR) 15 Address : 00009EH TEST W Initial value→ 0 14 13 12 11 10 9 8 - EN R/W 0 CS4 R/W 1 CS3 R/W 1 CS2 R/W 1 CS1 R/W 1 CS0 R/W 1 - The following describes the functions of the clock control register (ICCR) bits. [Bit 15] Test bit This bit is used for testing. Be sure to write "0" to it. [Bit 14] Reserved bit This bit is reserved. Be sure to write "0" to it. [Bit 13] EN (ENable) This bit is the enable bit for the I2C interface. 0 Disabled 1 Enabled If this bit is set to "0", all bits of the IBSR and IBCR registers (except the BER and BEIE bits) are cleared. This bit is cleared when a bus error occurs and the BER bit is set. Note: If operation is disabled, the interface immediately stops sending and receiving and the I2C bus enters an undesirable state. 350 CHAPTER 13 I2C INTERFACE [Bit 12 to 8] CS4 to CS0 (Clock Period Select 4 to 0) These bits set the frequency of the serial clock. They store the frequency of the shift clock, fsck, which is calculated as shown below. These bits can be rewritten only when operation is disabled (EN=0). fsck= φ n 12+16 φ : Machine clock (CLKP) n > 1 Table 13.2-1 Serial Clock Frequency Settings n CS4 CS3 CS2 CS1 CS0 1 0 0 0 0 1 2 0 0 0 1 0 3 0 0 0 1 1 ... ... ... ... ... ... 31 1 1 1 1 1 Setting disabled for CS4 to CS0=00000 100kbps 400kbps Clock frequency CLKP [MHz] n fsck n fsck 33 26 100.6 6 375 16.5 13 95.9 3 317.3 22 17 100 4 343.8 11 8 98.2 2 275 10 7 100 2 250 8 6 90.9 2 200 351 CHAPTER 13 I2C INTERFACE 13.2.4 10-bit Slave Address Register (ITBA) This section describes the configuration and functions of the 10-bit slave address register (ITBA). ■ 10-bit Slave Address Register (ITBA) Figure 13.2-8 shows the bit configuration of the 10-bit slave address register (ITBA). Figure 13.2-8 Bit Configuration of the 10-bit Slave Address Register (ITBA) Address : 000096H Initial value→ Address : 000097H 15 - 14 - 13 - 12 - 11 - 10 - - - - - - 7 6 5 4 TA6 R/W 0 TA5 R/W 0 TA4 R/W 0 TA7 R/W Initial value→ 0 - 9 TA9 R/W 0 8 TA8 R/W 0 3 2 1 0 TA3 R/W 0 TA2 R/W 0 TA1 R/W 0 TA0 R/W 0 ITBAH ITBAL Rewrite this register while operation is disabled (ICCR EN=0). The following describes the functions of the 10-bit slave address register (ITBA) bits. [Bits 15 to 10] Reserved bits These bits are reserved. The values read from these bits are 0s. [Bits 9 to 0] Sleep address bits (A9 to A0) If a 10-bit address is enabled (ITMK ENTB=1), slave address data is received and then compared with the ITBA register. An acknowledge is sent to the master after the address header {11110,TA9,TA8,0} of a 10-bit write access is received. If the second receive bit and the ITBAL register value are compared and produce a match, an acknowledge is sent to the master and the AAS bit is set. The slave address of this register can be masked using the ITMK register setting. In addition, the interface receives 10-bit data for the read access header {11110,TA9,TA8,1} after a repeated START condition is generated. All bits can be masked for the ITMK register using a stop address. The received 10-bit slave address is written to the ITBA register. This bit is valid when the ASS bit of the IBSR register is set to "1". 352 CHAPTER 13 I2C INTERFACE 13.2.5 10-bit Slave Address Mask Register (ITMK) This section describes the configuration and functions of the 10-bit slave address mask register (ITMK). ■ 10-bit Slave Address Mask Register (ITMK) Figure 13.2-9 shows the bit configuration of the 10-bit slave address mask register (ITMK). Figure 13.2-9 Bit Configuration of the 10-bit Slave Address Mask Register (ITMK) 15 ENTB R/W Initial value→ 0 Address : 000098H 14 RAL R 0 7 Address : 000099H TM7 R/W Initial value→ 1 13 - 12 - 11 - 10 - - - - - 9 TM9 R/W 1 8 TM8 R/W 1 6 5 4 3 2 1 0 TM6 R/W 1 TM5 R/W 1 TM4 R/W 1 TM3 R/W 1 TM2 R/W 1 TM1 R/W 1 TM0 R/W 1 The following describes the functions of the 10-bit slave address mask register (ITMK) bits. [Bit 15] ENTB (10-bit slave address enable bit) This bit is the 10-bit slave address enable bit. 0 10-bit slave address disabled 1 10-bit slave address enabled Write access is enabled while the interface is disabled (ICCR EN=0). [Bit 14] RAL (Slave address length bit) This bit indicates the slave address length. 0 7-bit slave address 1 10-bit slave address This bit indicates an interfaced address length if both the 10-bit and 7-bit slave addresses are enabled (ENTB=1 and ENSB=1). This bit is valid if the AAS bit is set to "1". This bit is cleared when the interface is disabled. This bit is read-only. [Bits 13 to 10] Reserved bits These bits are reserved. The values read from these bits are always 1s. 353 CHAPTER 13 I2C INTERFACE [Bits 9 to 0] 10-bit slave address mask bits These bits mask the bits of the 10-bit slave address register (ITBA). Write access is enabled while the interface is disabled (ICCR EN=0). 0 This bit not used for comparison of slave addresses 1 This bit used for comparison of slave addresses Set this bit to enable transmission of an acknowledge to a 10-bit slave address in a particular space. Each of TM9 to TM0 of ITMK corresponds to one bit of the ITBA address. If the value of each of the TM9 to TM0 bits is "1", the ITBA address becomes valid; if it is "0", the ITBA address becomes invalid. Example: ITBA address is 0010010111B and ITMK address is 1111111100B: The slave address is in the space from 0010010100B to 0010010111B. Rewrite this register while the interface is stopped (ICCR EN=0). Note: An address is masked after the interface is enabled. An address is also masked when a slave address is set again. 354 CHAPTER 13 I2C INTERFACE 13.2.6 7-bit Slave Address Register (ISBA) This section describes the configuration and functions of the 7-bit slave address register (ISBA). ■ 7-bit Slave Address Register (ISBA) Figure 13.2-10 shows the bit configuration of the 7-bit slave address register (ISBA). Figure 13.2-10 Bit Configuration of the 7-bit Slave Address Register (ISBA) Address : 00009BH Initial value→ 7 - 6 5 4 3 2 1 0 SA6 R/W 0 SA5 R/W 0 SA4 R/W 0 SA3 R/W 0 SA2 R/W 0 SA1 R/W 0 SA0 R/W 0 Rewrite this register while operation is stopped (ICCR EN=0). The following describes the functions of the 7-bit slave address register (ISBA) bits. [Bit 7] Reserved bit This bit is reserved. The value read from this bit is "0". [Bits 6 to 0] A6 to A0 (Slave address bits) Bits A6 to A0 are a register that specifies a 7-bit slave address. In slave mode, address data is received and then compared with the ISBA register. If a match is found, an acknowledge is sent to the master and the AAS bit is set. The slave address in this register can be masked using the setting of the ISMK register. This register operates when 7-bit slave address operation is enabled (ISMK ENSB=1). 355 CHAPTER 13 I2C INTERFACE 13.2.7 7-bit Slave Address Mask Register (ISMK) This section describes the configuration and functions of the 7-bit slave address mask register (ISMK). ■ 7-bit Slave Address Mask Register (ISMK) Figure 13.2-11 shows the bit configuration of the 7-bit slave address mask register (ISMK). Figure 13.2-11 Bit Configuration of the 7-bit Slave Address Mask Register (ISMK) 15 Address : 00009AH ENSB R/W Initial value→ 0 14 13 12 11 10 9 8 SM6 R/W 1 SM5 R/W 1 SM4 R/W 1 SM3 R/W 1 SM2 R/W 1 SM1 R/W 1 SM0 R/W 1 Rewrite this register while operation is stopped (ICCR EN=0). The following describes the functions of the 7-bit slave address mask register (ISMK) bits. [Bit 15] ENSB (7-bit slave address enable bit) This bit is the 7-bit slave address enable bit. 0 7-bit slave address disabled 1 7-bit slave address enabled [Bits 14 to 8] 7-bit slave address mask bits These bits mask the bits of the 7-bit slave address register (ISBA). 0 This bit not used for comparison of slave addresses 1 This bit used for comparison of slave addresses Set this bit to enable transmission of an acknowledge to a 7-bit slave address in a particular space. Each of the SM6 to SM0 bits of ISMK corresponds to one bit of the ISBA address. If the value of each of the SM6 to SM0 bit is "1", the ISBA address becomes valid; if it is "0", the ISBA address becomes invalid. Example: If ISBA address is 0010111B and ISMK address is 1111100B: The slave address is in the space from 0010100B to 0010111B. Rewrite this register while the interface is stopped (ICCR EN=0). Note: An address is masked after the interface is enabled. An address is also masked when a slave address is set again. 356 CHAPTER 13 I2C INTERFACE 13.2.8 Data Register (IADR) This section describes the configuration and functions of the data register (IADR). ■ Data Register (IADR) Figure 13.2-12 shows the bit configuration of the data register (IADR). Figure 13.2-12 Bit Configuration of the Data Register (IADR) 7 Address : 00009DH D7 R/W Initial value→ 0 6 5 4 3 2 1 0 D6 R/W 0 D5 R/W 0 D4 R/W 0 D3 R/W 0 D2 R/W 0 D1 R/W 0 D0 R/W 0 The following describes the functions of the data register (IADR) bits. [Bits 7 to 0] D7 to D0 (Data bits) Bits D7 to D0 are a data register used for serial transfer. Data is transferred from the MSB. Since the writing side of this register has double buffers, write data is loaded into the register for serial transfer during transfer of each byte while the bus is being used (BB=1). Since, during reading, data is directly read from the register for serial transfer, receive data is valid only while the INT bit is set. 357 CHAPTER 13 I2C INTERFACE 13.2.9 Clock Disable Register (IDBL) This section describes the configuration and functions of the clock disable register (IDBL). ■ Clock Disable Register (IDBL) Figure 13.2-13 shows the bit configuration of the clock disable register (IDBL). Figure 13.2-13 Bit Configuration of the Clock Disable Register (IDBL) Address : 00009FH Initial value→ 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - DBL R/W 0 [Bit 0] DBL (Clock disable bit) This bit specifies whether to supply or stop supply of the operating clock for the I2C interface. This bit can be used in low-power mode. 0 Supplies the clock for I2C. 1 Stops supply of the clock for I2C. The I2C line is opened. Note: When the bit is set to "1", I2C immediately stops while even sending. 358 CHAPTER 13 I2C INTERFACE 13.3 I2C Interface Operation The I2C bus consists of two bidirectional bus lines used for communication: one serial data line (SDA) and one serial clock line (SCL). The I2C interface has two corresponding open-drain I/O pins (SDA and SCL), enabling wired logic. ■ START condition Write "1" to the MSS bit while the bus is open (IBSR BB=0, IBCR MSS=0) to place the I2C interface in master mode and to generate a START condition. Write "1" to the MSS bit while the bus is idle (MSS=0, BB=0) to generate a START condition and send the IDAR register value. To generate a repeated START condition, write "1" to the SCC bit while the interface is in master mode or processing an interrupt. Write "1" to the MSS bit while the bus is being used (IBSR BB=1 and TRX=0, IBCR MSS=0 and INT=0) to cause the interface to start transmission after waiting for the bus to be released. If, during this time, the interface in slave mode is receiving a write access, it starts transmission after the transfer is completed. Then the interface releases the bus. If the interface is sending slave data, it does not start transmission even though the bus has been released. To use this feature, it is important to check the following: • Whether the interface is specified as a slave (IBCR MSS=0, IBSR AAS=1) • Whether data byte transmission is normal (IBCR MSS=1) or not (IBSR AL=1) when the next interrupt is received Writing "1" to the MMS or SCC bit in any other state is ignored. ■ STOP condition Write "0" to the MSS bit in master mode (IBCR MSS=1, INT=1) to generate a STOP condition and to place the interface in slave mode. Writing "0" to the MSS bit in any other state is irrelevant. After the MSS bit is cleared, the interface tries to generate a STOP condition. However, a STOP condition will not be generated if the SDL line is driven to "L" by another device, in which case an interrupt is generated after the next byte is transferred. 359 CHAPTER 13 I2C INTERFACE ■ Slave Address Detection In slave mode, BB=1 is set after a START condition is generated. The receive data from the master device is stored in the IDAR register. ❍ When a 7-bit slave address is enabled (ISMK ENSB=1) After 8-bit data is received, the IDAR and ISBA register values are compared. However, the bits masked in the ISMK register are not compared. If the comparison result is a match, the ASS bit is set to "1", an acknowledge is returned to the master, and the value of Bit 0 of the receive data is inverted and stored in the TRX bit. ❍ When a 10-bit slave address is enabled (ITMK ENTB=1) If the header section of a 10-bit address {11110,TA0,TA0,write} is detected, an acknowledge is returned to the master and the value of the last bit of the receive data is inverted and stored in the TRX bit. No interrupt occurs at this time. Then, the next received byte data and the low-order byte of the ITBA register are compared. The bits masked in the ITMK register, however, are not compared. If the result is a match, the ASS bit is set to "1" and an acknowledge is returned to the master. An interrupt occurs at this time. If the address specification as a slave has been made and a repeated START condition is detected, the ASS bit is set to "1" and an interrupt occurs after the header section of a 10-bit address {11110,TA0,TA1,read} is received. The interface has two independent registers: a 10-bit address register (ITBA) and a 7-bit address register (ISBA). If both registers are enabled (ISMK ENSB=1, ITMK ENTB=1), an acknowledge can be returned to both 10-bit and 7-bit addresses. The receive slave address length can be checked using the RAL bit of ITMK register. The RAL bit is valid while ASS=1. ■ Slave Address Mask The slave address mask registers (ITMK/ISMK) can mask each of the bits of slave address registers. A bit set to "1" in the mask register is compared while a bit set to "0" is not compared. This feature allows an acknowledge to be returned to multiple slave addresses. A receive slave address can be recognized by reading the ITBA register (when a 10-bit address is received, RAL=1) or the ISBA register (when a 7-bit address is received, RAL=0) while ASS=1. If all mask registers are cleared, the interface can be used as the bus monitor for a slave address. However, the interface cannot be used as a real bus monitor because it returns an acknowledge to any slave address. 360 CHAPTER 13 I2C INTERFACE ■ Slave Addressing In master mode, BB=1 and TRX=1 are set after a START condition is generated and the IDAR register value is sent starting with the MSB. After address data is sent and an acknowledge is received from a slave device, Bit 0 of the send data (Bit 0 of the IDAR register after transmission) is inverted and stored in the TRX bit. The acknowledge from the slave is stored in the LRB bit of the IBSR register. This operation is also performed for a repeated START condition. Two bytes are sent for a 10-bit slave address during write access. The first byte data consists of the header section of a 10-bit address {11110,A9,A8,0} and the second byte data consists of the low-order bits of the 10-bit address {A7,A6,A5,A4,A3,A2,A1,A0}. The series of transmissions described above places the slave device in the read access state and generates a repeated START condition as well as the header section of the 10-bit address {11110,A9,A8,1} that will be used for read access. • 7-bit slave, write access: START condition A6,A5,A4,A3,A2,A1,A0,0 • 7-bit slave, read access: START condition A6,A5,A4,A3,A2,A1,A0,1 • 10-bit slave, write access: START condition 11110,A9,A8,0,A7,A6,A5, A4,A3,A2,A1,A0 • 10-bit slave, read access: START condition 11110,A9,A8,1,A7,A6, A5,A4,A3,A2, A1,A0 Repeated start: 11110,A9,A8,1 ■ Arbitration Arbitration occurs if, during sending in master mode, data is also sent by other master devices. Arbitration lost is recognized if the local device’s transmission data is "1" and the level on the SDA line is set to "L". Then, AL=1 is set. The AL bit is also set if a START condition is detected in the first bit of the data and neither a START nor a STOP condition can be generated for the same reason. If arbitration lost is detected, the MSS and TRX bits are cleared and the device immediately enters slave mode and returns an acknowledge when it receives the device’s own slave address. ■ Acknowledge The receiving device sends an acknowledge to the sending device. The ACK bit (IBCR) sets whether an acknowledge should be returned when data is received. If, during data transmission in slave mode (read access from other masters), an acknowledge is not returned from the master, the TRX bit is cleared to "0" and the device enters receive mode. This allows the master to generate a STOP condition when the slave opens the SCL line. In master mode, read the LRB bit (IBSR) to check for an acknowledge from the slave. 361 CHAPTER 13 I2C INTERFACE ■ Bus Error A bus error is recognized and the I2C interface is stopped if: • A violation of the basic convention on the I2C bus during data transfer (including the Ack bit) is detected. • A stop condition in master mode is detected. • A violation of the basic convention on the I2C bus while the bus is idle is detected. ■ Other items ❍ Addressing after arbitration lost occurs After arbitration lost occurs, check whether or not the local device is addressed using software. When arbitration lost occurs, the device becomes a slave in terms of hardware. However, after one-byte transfer is completed, both the CLK and DATA lines are pulled to "L". Thus, if the device is not addressed, immediately open the CLK and DATA lines. If the device is addressed, open the CLK and DATA lines after preparing for slave transmission or reception. All of these things must be processed using software. ❍ Interrupt condition when one-byte transfer is completed Since the I2C bus has only one interrupt, an interrupt source is generated when one-byte transfer is completed or when an interrupt condition is met. Since multiple interrupt conditions must be checked using one interrupt, each of the flags must be checked by the interrupt routine. The following lists the interrupt conditions used when onebyte transfer is completed: • The device is a bus master. • The device is an addressed slave. • A general call address is received. • Arbitration lost occurs. ❍ Arbitration lost and interrupt source When arbitration lost is detected, an interrupt source is generated, not immediately but after one-byte transfer is completed. When arbitration lost is detected, the device becomes a slave in terms of hardware. However, in slave mode, a total of nine clocks must be output before an interrupt source can be generated. Thus, since an interrupt source is not immediately generated, no processing can be performed after arbitration lost occurs. 362 CHAPTER 13 I2C INTERFACE Note: After "0" is written to the MMS bit, some time is required before a STOP condition is generated. If you disable the I2C interface (DBL=1: TDAR or EN=0: ICCR) before a STOP condition is generated, the operation is immediately stopped and an illegal clock is generated on the SCL line. To disable the I2C interface, first check for generation of a STOP condition (BB=0: TBSR) and then disable the operation (DBL=1: IDAR or EN=0: ICCR). If, during transmission in master mode, an illegal clock is generated on the SCL line due to noise or for some other reason, the transmission bit counter of the I2C interface may run quickly, causing the slave to hang while "L" has appeared on the SDA line in the ACK cycle. An error (AL=1, BER=1) does not occur for such an illegal clock. If this situation occurs, perform the following error processing: 1. A communication error can be assumed if LRB=1 when MSS=1, TRX=1, INT=1. 2. Set EN to "0" and then set EN to "1" to cause SCL to generate one clock on a pseudo basis. This action causes the slave to release the bus. The period from the time EN is set to "0" until EN is set to "1" must be long enough for the slave to recognize it as a clock (about as long as the H period of a transmission clock). 3. Since the IBSR and IBCR are cleared when EN is set to "0", perform retransmission processing from the START condition. No STOP condition is generated at this point if BSS is set to "0". Insert an interval equal to or longer than n × 7 × tCPP between the point at which EN is set to "1" and the point at which MSS is set to "1" (START condition). Example: High-speed mode: 6 × 7 × 30.3=about 1.273 µs Standard mode: 27 × 7 × 30.3=about 5.727 µs Since BER, if set, is not cleared even if EN is set to "0", first clear it and then resend it. 363 CHAPTER 13 I2C INTERFACE 13.4 Operation Flowcharts This section provides flowcharts for the following types of operation: • Slave address and data transfer • Receive data • Interrupt processing ■ Example of Slave Address and Data Transfer Figure 13.4-1 Slave Address and Data Transfer Flowchart 7-bit slave addressing Transfer data Start Start BER bit clear (set) Interface enable EN=1 Slave address in write access IDAR=S. address <<1+RW MSS=1 INT=0 IDAR = Byte data INT=0 N INT=1? INT=1? Y Y Y BER=1? BER=1? Y Restart and transfer due to check of AAS Bus error ACK? (LRB=0?) Restart and transfer due to check of AAS AL=1? N N N Y Preparing for data transfer The slave does not generate ACK, but generates a repeated START condition or STOP condition. 364 Y N N AL=1? N ACK? (LRB=0?) N Y Transfer of last byte Y N Transfer completed Generates repeated START condition or STOP condition. CHAPTER 13 I2C INTERFACE ■ Example of Receive Data Figure 13.4-2 Flowchart for Receive Data Start Slave address in read access Clear the ACK bit if data is the last read data from the slave. INT=1? N Y BER=1? Y Bus error Restart N N Transfer of last byte Y Transfer completed Generates repeated START condition or STOP condition. 365 CHAPTER 13 I2C INTERFACE ■ Interrupt Processing Figure 13.4-3 Interrupt Processing Flowchart START Y INT=1? Receive interrupt from another module Y N BER=1? Y Bus error Restart N GCA=1? Y N N Y Failure of transfer Retry AAS=1? General call detected in slave mode Y AL=1? AL=1? LRB=1? Start to transfer new data upon next interrupt. If required, change ACK bit. ADT=1? Y No ACK from slave. Generate STOP condition or repeated START condition. N N TRX=1? Arbitration lost Retransfer N N Y Y TRX=1? Y Y N N Write next send data to IDAR. If required, change ACK bit. Write next send data to IDAR. Write next send data to IDAR. If required, change ACK bit. Clear INT bit. End of ISR 366 Write next send data to IDAR. Or clear MSS bit. CHAPTER 14 DMA CONTROLLER (DMAC) This chapter describes the DMA controller (DMAC), the configuration and functions of registers, and DMAC operation. 14.1 Overview of the DMA Controller (DMAC) 14.2 DMA Controller (DMAC) Registers 14.3 DMA Controller (DMAC) Operation 14.4 Operation Flowcharts 14.5 Data Bus 14.6 DMA External Interface 367 CHAPTER 14 DMA CONTROLLER (DMAC) 14.1 Overview of the DMA Controller (DMAC) The DMA controller (DMAC) is a module that implements DMA (Direct Memory Access) transfer on FR family devices. When this module is used to control DMA transfer, various kinds of data can be transferred at high speed without bypassing the CPU, enhancing system performance. ■ Hardware Configuration The DMA controller (DMAC) consists mainly of the following blocks: • Independent DMA channel × 5 channels • 5-channel access control circuit • 32-bit address registers (reload specifiable, two registers for each channel) • 16-bit rotation count register (reload specifiable, one register for each channel) • 4-bit block rotation register (one for each channel) • External transfer request input pins: DREQ0, DREQ1, and DREQ2 (for ch0, 1, and 2 only) • External transfer request acceptance output pins:DACK0, DACK1, and DACK2 (for ch0, 1, and 2 only) • DMA end output pins: DEOP0, DEOP1, and DEOP2 (for ch0, 1, and 2 only) • Fly-by transfer (memory to I/O and memory to memory) (for ch0, 1, and 2 only) • 2-cycle transfer ■ Main Functions The following are the main functions related to data transfer by the DMA controller (DMAC): ❍ Priority (ch0>ch1>ch2>ch3>ch4) • Data can be transferred independently over multiple channels (5 channels) ❍ Channel priority rotation ❍ DMAC start sources 368 • External dedicated pin input (edge detection/level detection for ch0, 1, and 2 only) • Built-in peripheral requests (shared interrupt requests, including external interrupts) • Software request (register write) CHAPTER 14 DMA CONTROLLER (DMAC) ❍ Transfer mode • Demand transfer, burst transfer, step transfer, and block transfer • Addressing mode: 32-bit full addressing (increment/decrement/fixed) The address increment/decrement range is from -255 to +255. • Data types: Byte, halfword, and word length • Single shot/reload selectable ■ Block Diagram Figure 14.1-1 is a block diagram of the DMA controller (DMAC). Figure 14.1-1 Block Diagram of the DMA Controller (DMAC) Counter DMA transfer request to the bus controller Selector Write back Buffer DTC 2-stage register DTCR DMA activation source selection circuit & request acceptance control Peripheral activation request/stop input External pin activation request/stop input Counter Bus control unit ERIR,EDIR BLK register DDNO register State transition circuit TYPE.MOD,WS Selector DSAD 2-stage register To interrupt controller IRQ[4:0] Peripheral interrupt clear MCLREQ SADM,SASZ[7:0] SADR Write back Selector address Counter buffer Access Counter buffer DMA control Address counter To bus controller DDNO Priority circuit Selector Bus control unit Write Read/write control Selector Read DSS[3:0] X-bus Buffer DDAD 2-stage register DADM,DASZ[7:0] DADR Write back 369 CHAPTER 14 DMA CONTROLLER (DMAC) 14.2 DMA Controller (DMAC) Registers This section describes the configuration and functions of the registers used by the DMA controller (DMAC). ■ DMA Controller (DMAC) registers Figure 14.2-1 shows the registers used by the DMA controller (DMAC). Figure 14.2-1 DMA Controller (DMAC) Registers (bit) 31 370 ch0 Control/Status Register A DMACA0 00000200H ch0 Control/Status Register B DMACB0 00000204H ch1 Control/Status Register A DMACA1 00000208H ch1 Control/Status Register B DMACB1 0000020CH ch2 Control/Status Register A DMACA2 00000210H ch2 Control/Status Register B DMACB2 00000214H ch3 Control/Status Register A DMACA3 00000218H ch3 Control/Status Register B DMACB3 0000021CH ch4 Control/Status Register A DMACA4 00000220H ch4 Control/Status Register B DMACB4 00000224H All-channel control register DMACR 00000240H ch0 Transfer source address register DMASA0 00001000H ch0 Transfer destination address register DMADA0 00001004H ch1 Transfer source address register DMASA1 00001008H ch1 Transfer destination address register DMADA1 0000100CH ch2 Transfer source address register DMASA2 00001010H ch2 Transfer destination address register DMADA2 00001014H ch3 Transfer source address register DMASA3 00001018H ch3 Transfer destination address register DMADA3 0000101CH ch4 Transfer source address register DMASA4 00001020H ch4 Transfer destination address register DMADA4 00001024H 24 23 16 15 08 07 00 CHAPTER 14 DMA CONTROLLER (DMAC) ■ Notes on Setting Registers When the DMA controller (DMAC) is set, some bits need to be set while DMA is stopped. If they are set while DMA is in progress (during transfer), correct operation cannot be guaranteed. An asterisk following a bit when its function is described later indicates that the operation of the bit is affected if it is set during DMAC transfer. Rewrite this bit while DMAC transfer is stopped (start is disabled or temporarily stopped). If the bit is set while DMA transfer start is disabled (when DMAE of DMACR=0, or DENB of DMACA=0), the setting takes effect when start is enabled. If the bit is set while DMA transfer is temporarily stopped (DMAH[3:0] of DMAC not equal to 0000 or PAUS of DMACA=1), the setting takes effect when temporary stopping is canceled. 371 CHAPTER 14 DMA CONTROLLER (DMAC) 14.2.1 Control/Status Registers A (DMACA0 to DMACA4) Control/status registers A (DMACA0 to DMACA4) control the operation of the DMAC channels. There is a separate register for each channel. This section describes the configuration and functions of control/status registers A (DMACA0 to DMACA4). ■ Control/Status Registers A (DMACA0 to DMACA4) Figure 14.2-2 shows the bit configuration of control/status registers A (DMACA0 to DMACA4). Figure 14.2-2 Bit Configuration of Control/Status Registers A (DMACA0 to DMACA4) bit 31 30 29 28 27 DENB PAUS STRG bit 15 14 13 26 25 24 23 IS[4:0] 12 11 10 22 21 20 19 DDNO[3:0] 9 8 7 6 5 18 17 16 BLK[3:0] 4 3 2 1 0 DTC[15:0] (Initial value: 00000000_0000XXXX_XXXXXXXX_XXXXXXXX bit) The following describes the functions of the bits of control/status registers A (DMACA0 to DMACA4). [Bit 31] DENB (Dma ENaBle): DMA operation enable bit This bit, which corresponds to a transfer channel, is used to enable and disable DMA transfer. The activated channel starts DMA transfer when a transfer request is generated and accepted. All transfer requests that are generated for a deactivated channel are disabled. When the transfer on an activated channel reaches the specified count, this bit is set to "0" and transfer stops. The transfer can be forced to stop by writing "0" to this bit. Be sure to stop a transfer forcibly ("0" write) only after temporarily stopping DMA using the PUAS bit [Bit30 of DMACA]. If the transfer is forced to stop without first temporarily stopping DMA, DMA stops but the transferred data cannot be guaranteed. Check whether DMA is stopped using the DSS[2:0] bits [Bit18 to 16 of DMACB]. DENB Function 0 Disables operation of DMA on the corresponding channel (initial value). 1 Enables operation of DMA on the corresponding channel. • If a stop request is accepted during reset: Initialized to "0". • This bit is readable and writable. If the operation of all channels is disabled by Bit15 (DMAE bit) of the DMAC all-channel control register (DMACR), writing "1" to this bit is disabled and the stopped state is maintained. If the operation is disabled by the above bit while it is enabled by this bit, "0" is written to this bit and the transfer is stopped (forced stop). 372 CHAPTER 14 DMA CONTROLLER (DMAC) [Bit 30] PAUS (PAUSe)*: Temporary stop instruction This bit temporarily stops DMA transfer on the corresponding channel. If this bit is set, DMA transfer is not performed before this bit is cleared (While DMA is stopped, the DSS bits are 1xx. If this bit is set before starting, DMA transfer continues to be temporarily stopped. To temporarily stop DMA transfer after it has started (during operation), stop the operation of all DMAs (DMAH[3:0] of DMACR not equal to 0000), write "1" to this bit, and then restart operation by setting (DMAH[3:0] of DMACR=0000). The reason is that, if the bit is written during operation, the Bit31 DENB operation enable bit is affected. New transfer requests that occur while this bit is set are accepted, but no transfer starts before this bit is cleared (See "14.3.9 Operation from Starting to End/Stopping"). PAUS Function 0 Disable operation of the corresponding channel DMA (initial value) 1 Enable operation of the corresponding channel DMA • When reset: Initialized to "0". • This bit is readable and writable. [Bit 29] STRG (Software TRiGger): Transfer request This bit generates a DMA transfer request for the corresponding channel. If "1" is written to this bit, a transfer request is generated when write operation to the register is completed and transfer on the corresponding channel is started. However, if the corresponding channel is not activated, operations on this bit are disabled. If starting by a write operation to the DMAE bit and a transfer request occurring due to this bit are simultaneous, the transfer request is enabled and transfer is started. If writing of "1" to the PAUS bit and a transfer request occurring due to this bit are simultaneous, the transfer request is enabled, but DMA transfer is not started before "0" is written to the PAUS bit. STRG Function 0 Disabled 1 DMA starting request • When reset: Initialized to "0". • The read value is always "0". • Only a read value of "1" is valid. If "0" is read, operation is not affected. 373 CHAPTER 14 DMA CONTROLLER (DMAC) [Bits 28 to 24] IS4 to IS0 (Input Select)*: Transfer source selection These bits select the source of a transfer request. The settings and sources are listed in Table 14.2-1. For a software transfer request by the STRG bit function, set IS=00000. Table 14.2-1 Settings for Transfer Request Sources IS Function 00000 Software start (STRG bit) 00001 Setting disabled 01101 Setting disabled 01110 External pin "H" level or 01111 External pin "L" level or 10000 UART0 (receiving complete) 10001 UART1 (receiving complete) 10010 UART2 (receiving complete) 10011 UART0 (sending complete) 10100 UART1 (sending complete) 10101 UART2 (sending complete) 10110 External interrupt 0* 10111 External interrupt 1* 11000 Reload timer 0* 11001 Reload timer 1* 11010 Reload timer 2* 11011 External interrupt 2* 11100 External interrupt 3* 11101 External interrupt 4* 11110 External interrupt 5* 11111 A/D edge edge *: DMA transfer function by interrupt request signal cannot be used (Only MB91306R/307R). • When reset: Initialized to "00000". • These bits are readable and writable. 374 CHAPTER 14 DMA CONTROLLER (DMAC) Notes: • If DMA start resulting from an interrupt from a peripheral function is set (IS=1xxxx), disable interrupts from the selected peripheral function with the ICR register. • If demand transfer mode is selected, only IS[4:0]=01110, 01111 can be set. Starting by other sources is disabled. • External request input (DREQx) is valid only for ch0, ch1, and ch2. External request input cannot be selected for ch3 and ch4. Whether level detection or edge detection is used is determined by the mode setting. Level detection is selected for demand transfer. For all other cases, edge detection is selected. • To activate DMA transfer by an external interrupt, set the clock divide ratio of CLKB to CLKP to 1:2 or 1:1. Examples: CLKB = 66 MHz and CLKP = 33 MHz CLKB = 33 MHz and CLKP = 33 MHz [Bits 23 to 20] DDNO3 to DDNO0 (direct access number)*: Fly-by function for built-in peripherals These bits specify the built-in peripheral of the transfer destination/source used by the corresponding channel. Table 14.2-2 Settings of the Direct Access Number IS Function 0000 Setting disabled 0001 Reserved 0010 Reserved 0011 Reserved 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Setting disabled • When reset: Initialized to "0000". • These bits are readable and writable. 375 CHAPTER 14 DMA CONTROLLER (DMAC) Note: This function is not supported by the MB91307 series. Any data written is ignored. [Bits 19 to 16] BLK3 to BLK0 (BLocK size): Block size specification These bits specify the block size for block transfer on the corresponding channel. The value specified by these bits becomes the number of words in one transfer unit (more exactly, the repetition count of the data width setting). If block transfer will not be performed, set 01H (size 1). This register value is ignored during demand transfer. The size becomes 1. BLK XXXX Function Block size of the corresponding channel • When reset: Not initialized. • These bits are readable and writable. • If "0" is specified for all bits, the block size becomes 16 words. • During reading, the block size is always read (reload value). [Bits 15 to 00] DTC (Dma Terminal Count register)*: Transfer count register The DTC register stores the transfer count. Each register has 16-bit length. All registers have a dedicated reload register. When the register is used for a channel that is enabled to reload the transfer count register, the initial value is automatically written back to the register when the transfer is completed. DTC XXXX Function Transfer count for the corresponding channel When DMA transfer is started, data in this register is stored in the counter buffer of the DMAdedicated transfer counter and is decremented by 1 (subtraction) after each transfer unit. When DMA transfer is completed, the contents of the counter buffer are written back to this register and then DMA ends. Thus, the transfer count value during DMA operation cannot be read. • When reset: Not initialized. • These bits are readable and writable. Always access DTC using halfword length or word length. • During reading, the count value is read. The reload value cannot be read. 376 CHAPTER 14 DMA CONTROLLER (DMAC) 14.2.2 Control/Status Registers B (DMACB0 to DMACB4) Control/status registers B (DMACB0 to DMACB4) control the operation of each DMAC channel and exist independently for each channel. This section describes the configuration of control/status registers B (DMACB0 to DMACB4) and their functions. ■ Control/Status Register B (DMACB0 to DMACB4) Figure 14.2-3 shows the bit configuration of control/status registers B (DMACB0 to DMACB4). Figure 14.2-3 Bit Configuration of Control/Status Registers B (DMACB0 to DMACB4) bit bit 31 30 29 28 TYPE[1:0] MOD[1:0] 15 13 14 12 27 26 WS[1:0] 11 10 25 24 23 22 21 20 19 18 SADM DADM DTCR SADR DADR ERIE EDIE 9 8 7 6 SASZ[7:0] 5 4 3 17 16 DSS[2:0] 2 1 0 DASZ[7:0] (Initial value: 00000000_00000000_XXXXXXXX_XXXXXXXX bit) [Bits 31, 30] TYPE (TYPE)*: Transfer type setting These bits are the transfer type setting bits and set the type of operation for the corresponding channel. • 2-cycle transfer mode: In this mode, the transfer source address (DMASA) and transfer destination address (DMADA) are set and transfer is performed by repeating the read operation and write operation for the number of times specified by the transfer count. All areas can be specified as a transfer source or transfer destination (32-bit address). • Fly-by transfer mode: In this mode, external ↔ external transfer is performed in one cycle by setting a memory address as the transfer destination address (DMADA). Be sure to specify an external area for the memory address. Table 14.2-3 Settings for the Transfer Types TYPE Function 00 2-cycle transfer (initial value) 01 Fly-by: Memory → I/O transfer 10 Fly-by: I/O → memory transfer 11 Setting disabled • When reset: Initialized to "00". • These bits are readable and writable. 377 CHAPTER 14 DMA CONTROLLER (DMAC) [Bits 29, 28] MODE (MODE)*: Transfer mode setting These bits are the transfer mode setting bits and set the operating mode of the corresponding channel. Table 14.2-4 Settings for Transfer Modes MOD Function 00 Block/step transfer mode 01 Burst transfer mode 10 Demand transfer mode 11 Setting disabled • When reset: Initialized to "00". • These bits are readable and writable. [Bits 27, 26] WS (Word Size)*: Transfer data width selection These bits are the transfer data width selection bits and are used to select the transfer data width of the corresponding channel. Transfer operations are repeated in units of the data width specified in this register for as many times as the specified count. Table 14.2-5 Selection of the Transfer Data Width WS Function 00 Byte-width transfer (initial value) 01 Halfword-width transfer 10 Word-width transfer 11 Setting disabled • When reset: Initialized to "00". • These bits are readable and writable. 378 CHAPTER 14 DMA CONTROLLER (DMAC) [Bit 25] SADM (Source-ADdr. Count-Mode select)*: Transfer source address count mode specification This bit specifies the address processing of the transfer source address of the corresponding channel for each transfer operation. An address increment is added or an address decrement is subtracted after each transfer operation according to the specified transfer source address count width (SASZ). When the transfer is completed, the next access address is written to the corresponding address register (DMASA). As a result, the transfer source address register is not updated until DMA transfer is completed. To make the address always the same, specify this register for increment or decrement and make the address count width equal to "0". SADM Function 0 Increments transfer source address. (initial value) 1 Decrements the transfer source address. • When reset: Initialized to "0". • This bit is readable and writable. [Bit 24] DADM (Destination-ADdr. Count-Mode select)*: Transfer destination address count mode specification This bit specifies the address processing for the transfer destination address of the corresponding channel in each transfer operation. An address increment is added or an address decrement is subtracted after each transfer operation according to the specified transfer destination address count width (DASZ). When the transfer is completed, the next access address is written to the corresponding address register (DMADA). As a result, the transfer destination address register is not updated until the DMA transfer is completed. To make the address always the same, specify this register for increment or decrement and make the address count width equal to "0". DADM Function 0 Increments the transfer source address. (initial value) 1 Decrements the transfer source address. • When reset: Initialized to "0". • This bit is readable and writable. 379 CHAPTER 14 DMA CONTROLLER (DMAC) [Bit 23] DTCR (DTC-reg. Reload)*: Transfer count register reload specification This bit controls reloading of the transfer count register for the corresponding channel. If reload operation is enabled by this bit, the count register value is restored to its initial value after the transfer is completed and then waiting starts for new transfer requests. If this bit is "1", the DENB bit is not cleared. DENB=0 or DMAE=0 must be set to stop the transfer. In either case, the transfer is forcibly stopped. If reloading of the counter is disabled, a single shot operation occurs. In single shot operation, operation stops after the transfer is completed even if reload is specified in the address register. The DENB bit is also cleared in this case. DTCR Function 0 Disables transfer count register reloading (initial value) 1 Enables transfer count register reloading. • When reset: Initialized to "0". • This bit is readable and writable. [Bit 22] SADR (Source-ADdr.-reg. Reload)*: Transfer source address register reload specification This bit controls reloading of the transfer source address register for the corresponding channel. If this bit enables the reload operation, the transfer source address register value is restored to its initial value after the transfer is completed. If reloading of the counter is disabled, a single shot operation occurs. In single shot operation, operation stops after the transfer is completed even if reload is specified in the address register. The address register value also stops in this case while the initial value is being reloaded. If this bit disables the reload operation, the address register value when the transfer is completed is the address to be accessed next to the final address. When address increment is specified, the next address is an incremented address. SADR Function 0 Disables transfer source address register reloading. (initial value) 1 Enables transfer source address register reloading. • When reset: Initialized to "0". • This bit is readable and writable. 380 CHAPTER 14 DMA CONTROLLER (DMAC) [Bit 21] DADR (Dest.-ADdr.-reg. Reload)*: Transfer destination address register reload specification This bit controls reloading of the transfer source address register for the corresponding channel. If this bit enables reloading, the transfer source address register value is restored to its initial value after the transfer is completed. The details of other functions are the same as those described for Bit22 (SADR). DADR Function 0 Disables transfer destination address register reloading. (initial value) 1 Enables transfer destination address register reloading. • When reset: Initialized to "0". • This bit is readable and writable. [Bit 20] ERIE (ERror Interrupt Enable)*: Error interrupt output enable This bit controls the occurrence of an interrupt for termination after an error occurs. The nature of the error that occurred is indicated by DSS2 to "0". Note that an interrupt occurs only for specific termination causes and not for all termination causes (Refer to bits DSS2 to DSS0, which are Bits 18 to 16). ERIE Function 0 Disables error interrupt request output. (initial value) 1 Enables error interrupt request output. • When reset: Initialized to "0". • This bit is readable and writable. [Bit 19] EDIE (EnD Interrupt Enable)*: End interrupt output enable This bit controls the occurrence of an interrupt for normal termination. EDIE Function 0 Disables end interrupt request output. (initial value) 1 Enables end interrupt request output. • When reset: Initialized to "0". • This bit is readable and writable. 381 CHAPTER 14 DMA CONTROLLER (DMAC) [Bits 18 to 16] DSS2 to DSS0 (DMA Stop Status)*: Transfer stop source indication These bits indicate a code (end code) of 3 bits that indicates the source of stopping or termination of DMA transfer on the corresponding channel. For a list of end codes, see Table 14.2-6. Table 14.2-6 End Codes DSS Function Interrupt 000 Initial value None x01 Address error (underflow/overflow) Error x10 Transfer stop request Error x11 Normal end End 1xx DMA stopped temporarily (due, for example, to DMAH, PAUS bit, and an interrupt) Obey the lowest-order 2 bits. A transfer stop request is set only when it is requested by a peripheral device or the external pin DSTP function is used. The Interrupt column indicates the type of interrupts that can occur. • When reset: Initialized to "000". • These bits can be cleared by writing "000" to them. • These bits are readable and writable. Note, however, that the only valid written value is "000". [Bits 15 to 8] SASZ (Source Addr count SiZe)*: Transfer source specification address count size These bits specify the increment or decrement for the transfer source address (DMASA) of the corresponding channel for each transfer operation. The value set by these bits becomes the address increment/decrement for each transfer unit. The address increment/decrement conforms to the instruction in the transfer source address count mode (SADM). SASZ XXXX Function Specify the increment/decrement width of the transfer source address. 0 to 255 • When reset: Not initialized • These bits are readable and writable. [Bits 7 to 0] DASZ (Des Addr count size)*: Transfer destination specification address count size These bits specify the increment or decrement for the transfer destination address (DMADA) of the corresponding channel for each transfer operation. The value set by these bits becomes the address increment/decrement for each transfer unit. The address increment/ decrement conforms to the instruction in the transfer destination address count mode (DADM). DASZ Function XXXX Specify the increment/decrement width of the transfer destination address. 0 to 255 • When reset: Not initialized • These bits are readable and writable. 382 CHAPTER 14 DMA CONTROLLER (DMAC) 14.2.3 Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to DMASA4/DMADA0 to DMADA4) The transfer source/transfer destination address setting registers (DMASA0 to DMASA4/DMADA0 to DMADA4) control the operation of the DMAC channels. There is a separate register for each channel. This section describes the configuration and functions of the transfer source/transfer destination address setting registers (DMASA0 to DMASA4/DMADA0 to DMADA4). ■ Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to DMASA4/DMADA0 to DMADA4) The transfer source/transfer destination address setting registers (DMASA0 to DMASA4/ DMADA0 to DMADA4) are a group of registers that store the transfer source/transfer destination addresses. Each register is 32 bits. Figure 14.2-4 shows the bit configuration of the transfer source/transfer destination address setting registers (DMASA0 to DMASA4/DMADA0 to DMADA4). Figure 14.2-4 Bit Configuration of the Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to DMASA4/DMADA0 to DMADA4) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DMASA[31:16] bit 15 14 13 12 11 10 9 8 7 DMASA[15:0] (Initial value: XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX bit) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DMADA[31:16] bit 15 14 13 12 11 10 9 8 7 DMADA[16:0] (Initial value: XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX bit) The following describes the functions of the bits of each transfer source/transfer destination address setting register (DMASA0 to DMASA4/DMADA0 to DMADA4). 383 CHAPTER 14 DMA CONTROLLER (DMAC) [Bits 31 to 0] DMADA (DMA Destination Addr)*: Transfer destination address setting These bits set the transfer destination address. If DMA transfer is activated, data in this register is stored in the counter buffer of the DMAdedicated address counter and then the address is calculated according to the settings for the transfer operation. When the DMA transfer is completed, the contents of the counter buffer are written back to this register and then DMA ends. Thus, the address counter value during DMA operation cannot be read. All registers have a dedicated reload register. When the register is used for a channel that is enabled for reloading of the transfer source/transfer destination address register, the initial value is automatically written back to the register when the transfer is completed. Other address registers are not affected. • When reset: Not initialized. • These bits are readable and writable. For this register, be sure to access these bits as 32bit data. • If these bits are read during transfer, the address before the transfer is read. If they are read after transfer, the next access address is read. Because the reload value cannot be read, it is not possible to read the transfer address in real time. Note: Do not set any of the DMAC’s registers using this register. DMA transfer is not possible for the DMAC’s registers themselves. 384 CHAPTER 14 DMA CONTROLLER (DMAC) 14.2.4 DMAC All-Channel Control Register (DMACR) The DMAC all-channel control register (DMACR) controls the operation of the all five DMAC channels. Be sure to access this register using byte length. This section describes the configuration and functions of the DMAC all-channel control register (DMACR). ■ DMAC All-Channel Control Register (DMACR) Figure 14.2-5 shows the bit configuration of the DMAC all-channel control register (DMACR). Figure 14.2-5 Bit Configuration of the DMAC All-Channel Control Register (DMACR) bit bit 31 30 29 28 27 26 25 DMAE - - PM01 15 14 13 12 11 10 9 - - - - - - - 24 23 22 21 20 19 18 17 16 - - - - - - - - 8 7 6 5 4 3 2 1 0 - - - - - - - - - DMAH[3:0] (Initial value: 0XX00000_XXXXXXXX_XXXXXXXX_XXXXXXXX bit) The following describes the functions of the DMAC all-channel control register (DMACR) bits. [Bit 31] DMAE (DMA Enable): DMA operation enable This bit controls the operation of all DMA channels. If DMA operation is disabled with this bit, transfer operations on all channels are disabled regardless of the start/stop settings for each channel and the operating status. Any channel carrying out transfer cancels the requests and stops transfer at a block boundary. All start operations on each channel in a disabled state are disabled. If this bit enables DMA operation, start/stop operations are enabled for all channels. Simply enabling DMA operation with this bit does not activate each channel. DMA operation can be forced to stop by writing "0" to this bit. However, be sure to force stopping ("0" write) only after temporarily stopping DMA using the DMAH[3:0] bits [Bit27 to 24 of DMACR]. If forced stopping is carried out without first temporarily stopping DMA, DMA stops, but the transfer data cannot be guaranteed. Check whether DMA is stopped using the DSS[2:0] bits [Bit18 to 16 of DMACB]. DMAE Function 0 Disables DMA transfer on all channels. (initial value) 1 Enables DMA transfer on all channels. • When reset: Initialized to "0". • This bit is readable and writable. 385 CHAPTER 14 DMA CONTROLLER (DMAC) [Bit 28] PM01 (Priority mode ch0,1 robine): Channel priority rotation This bit is set to alternate priority for each transfer between Channel0 and Channel1. PM01 Function 0 Fixes the priority. (ch0 > ch1)(initial value) 1 Alternates priority. (ch1 > ch0) • When reset: Initialized to "0". • This bit is readable and writable. [Bits 27 to 24] DMAH (DMA Halt): DMA temporary stop These bits control temporary stopping of all DMA channels. If these bits are set, DMA transfer is not performed on any channel before these bits are cleared. When DMA transfer is activated after these bits are set, all channels remain temporarily stopped. Transfer requests that occur on channels for which DMA transfer is enabled (DENB=1) while these bits are set are all enabled. The transfer can be started by clearing all these bits. DMAH 0000 Other than 0000 Function Enables the DMA operation on all channels. (initial value) Temporarily stops DMA operation on all channels. • When reset: Initialized to "0". • These bits are readable and writable. [Bits 30, 29, and 23 to 0] (Reserved): Reserved bits These bits are reserved. • 386 A read value is undefined. CHAPTER 14 DMA CONTROLLER (DMAC) 14.2.5 Other Functions The MB91307 series has the DACK, DEOP, and DREQ pins, which can be used for external transfer. These pins can also be used as general-purpose ports. ■ Pin Function of the DACK, and DEOP, and DREQ pins To use the DACK, DEOP, or DREQ pins for external transfer, a switch must be made from the port function to the DMA pin function. To make the switch, set the PFR register. 387 CHAPTER 14 DMA CONTROLLER (DMAC) 14.3 DMA Controller (DMAC) Operation A DMA controller (DMAC) is built into all FR family devices. The FR family DMAC is a multi-functional DMAC that controls data transfer at high speed without the use of CPU instructions. This section describes the operation of the DMAC. ■ Principal Operations • Functions can be set for each transfer channel independently. • Once starting has been enabled, a channel starts transfer operation only after a specified transfer request has been detected. • After a transfer request is detected, a DMA transfer request is output to the bus controller and the bus right is acquired by the bus controller before the transfer is started. • The transfer is carried out as a sequence conforming to the mode settings made independently for the channel being used. ■ Transfer Mode Each DMA channel performs transfer according to the transfer mode set by the MOD[1:0] bits of its DMACB register. ❍ Block/step transfer Only a single block transfer unit is transferred in response to one transfer request. DMA then stops requesting the bus controller for transfer until the next transfer request is received. The block transfer unit is the specified block size (BLK[3:0] of DMACA). ❍ Burst transfer Transfer in response to one transfer request is carried out continuously for the number of times in the specified transfer count. The specified transfer count is the transfer count (BLK[3:0] of DMACA X DTC[15:0] of DMACA) X block size. ❍ Demand transfer The specified transfer count in a demand transfer is the specified transfer count (DTC[15:0] of DMACA). The block size is always "1" and the register value is ignored. 388 CHAPTER 14 DMA CONTROLLER (DMAC) ■ Transfer Type ❍ 2-cycle transfer (normal transfer) The DMA controller operates using as its unit of operation a read operation and a write operation. Data is read from an address in the transfer source register and then written to another address in the transfer destination register. ❍ Fly-by transfer (memory → I/O) The DMA controller operates using as its unit of operation a read operation. If DMA transfer is performed when fly-by transfer is set, DMA issues a fly-by transfer (read) request to the bus controller and the bus controller lets the external interface carry out the fly-by transfer (read). ❍ Fly-by transfer (I/O → memory) The DMA controller operates using as its unit of operation a write operation. Otherwise, operation is the same as fly-by transfer (memory → I/O) operation. Access areas used for MB91307 series fly-by transfer must be external areas. ■ Transfer Address The following types of addressing are available and can be set independently for each channel transfer source and transfer destination. The method for specifying the address setting register (DMASA/DMADA) for a 2-cycle transfer and the method for a fly-by transfer are different. ❍ Specifying the address for a 2-cycle transfer The value read from a register (DMASA/DMADA) in which an address has been set in advance is used as the address for access. After receiving a transfer request, DMA stores the address from the register in the temporary storage buffer and then starts transfer. After each transfer (access) operation, the next access address is generated (increment/ decrement/fixed selectable) by the address counter and then written to the temporary storage buffer. Because the contents of the temporary storage buffer are written back to the register (DMASA/DMADA) after each block transfer unit is completed, the address register (DMASA/ DMADA) value is updated after each block transfer unit is completed, making it impossible to determine the address in real time during transfer. ❍ Specifying the address for a fly-by transfer In a fly-by transfer, the value read from the transfer destination address register (DMADA) is used as the address for access. The transfer source address register (DMASA) is ignored. Be sure to specify an external area as the address to be set. After receiving a transfer request, DMA stores the address from the register in the temporary storage buffer and then starts transfer. After each transfer (access) operation, the next access address is generated (increment/ decrement/fixed selectable) by the address counter and then written to the temporary storage buffer. Because the contents of this temporary storage buffer are written back to the register (DMADA) after each block transfer unit is completed, the address register (DMADA) value is updated after each block transfer unit is completed, making it impossible to determine the address in real time during transfer. 389 CHAPTER 14 DMA CONTROLLER (DMAC) ■ Transfer Count and Transfer End ❍ Transfer count The transfer count register is decremented (-1) after each block transfer unit is completed. When the transfer count register becomes "0", counting for the specified transfer ends, and the transfer stops with the end code displayed or is reactivated *. Like the address register, the transfer count register is updated only after each block transfer unit. *: If transfer count register reloading is disabled, the transfer ends. If reloading is enabled, the register is initialized and then waits for transfer (DTCR of DMACB) ❍ Transfer end Listed below are the sources for transfer end. When transfer ends, a source is indicated as the end code (DSS[2:0] of DMACB). • End of the specified transfer count (DMACA:BLK[3:0] x DMACA:DTC[15:0]) => Normal end • A transfer stop request from a peripheral circuit or the external pin (DSTP) occurred => Error • An address error occurred => Error • A reset occurred => Reset The transfer stop source is indicated (DSS) and the transfer end interrupt or error interrupt for the end source is generated. 390 CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.1 Setting a Transfer Request The following three types of transfer requests are provided to activate DMA transfer: • External transfer request pin • Built-in peripheral request • Software request Software requests can always be used regardless of the settings of other requests. ■ External Transfer Request Pin A transfer request is generated by input to the input pin prepared for a channel. The MB91307 series supports channels 0 to 3 (DREQ0, 1, and 2). If the input is valid at this point, the following sources are selected depending on the settings for the transfer type and the start source: ❍ Edge detection If the transfer type is block, step, or burst transfer, select edge detection: • Falling edge detection: Set with the transfer source selection register. When IS[4:0] of DMACA=01110. • Rising edge detection: Set with the transfer source selection register. When IS[4:0] of DMACA=01111. ❍ Level detection If the transfer type is demand transfer, select level detection: • "H" level detection: Set with the transfer source selection register. When IS[4:0] of DMACA=01110. • "L" level detection: Set with the transfer source selection register. When IS[4:0] of DMACA=01111. ■ Built-in Peripheral Request A transfer request is generated by an interrupt from the built-in peripheral circuit. For each channel, set the peripheral’s interrupt by which a transfer request is generated (When IS[4:0] of DMACA=1xxxx.) The built-in peripheral request cannot be used together with an external transfer request. Notes: • Because an interrupt request used in a transfer request seems like an interrupt request to the CPU, disable interrupts from the interrupt controller (ICR register). • For built-in peripheral circuit, the DMA transfer via the external interrupt and the interrupt request signal of the reload timer cannot be started (MB91306R/307R only). ■ Software Request A transfer request is generated by writing to the trigger bit of a register (STRG of DMACA). If a software request occurs together with a start (transfer enable) request, the transfer is started by immediate output of a DMA transfer request to the bus controller. 391 CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.2 Transfer Sequence The transfer type and the transfer mode that determine, for example, the operation sequence after DMA transfer has started can be set independently (Settings for TYPE[1:0] and MOD[1:0] of DMACB). ■ Selection of the Transfer Sequence The following sequence can be selected with a register setting: • Burst 2-cycle transfer • Demand 2-cycle transfer • Block/step 2-cycle transfer • Burst fly-by transfer • Demand fly-by transfer • Block/step fly-by transfer ❍ Burst 2-cycle transfer In a burst 2-cycle transfer, as many transfers as specified by the transfer count are performed continuously for one transfer source. For a 2-cycle transfer, all 32-bit areas can be specified using a transfer source/transfer destination address. A peripheral transfer request, software transfer request, or external pin (DREQ) edge input detection request can be selected as the transfer source. Transfer source addressing Direction Transfer destination addressing All 32-bit areas specifiable → All 32-bit areas specifiable (Table of specifiable transfer addresses) The following are some features of a burst transfer: When one transfer request is received, transfer is performed continuously until the transfer count register reaches 0. The transfer count is the transfer count × block size (BLK[3:0] of DMACA × DTC[15:0] of DMACA). Another request occurring during transfer is ignored. If the reload function of the transfer count register is enabled, the next request is accepted after transfer ends. If a transfer request for another channel with a higher priority is received during transfer, the channel is switched at the boundary of the block transfer unit. Processing resumes only after the transfer request for the other channel is cleared. 392 CHAPTER 14 DMA CONTROLLER (DMAC) Transfer request ( edge) Bus operation CPU SA Transfer count DA SA 4 DA 3 SA DA 2 SA DA CPU 0 1 Transfer end (Example of burst transfer for a start on an external pin rising edge, number of blocks =1, and transfer count = 4) ❍ Burst fly-by transfer A burst fly-by transfer has the same features as a 2-cycle transfer except that the transfer area can only be external areas, and the transfer unit is read (memory → I/O) or write (I/O → memory) only. Transfer source addressing Direction Transfer destination addressing Specification not required (invalid) None External area (Table of specifiable transfer addresses) ■ Demand Transfer 2-Cycle Transfer A demand transfer sequence is generated only if "H" level or "L" level of an external pin is selected as a transfer request. Select the level with IS[3:0] of DMACA. The following are some features of a continuous transfer: • Each transfer operation of a transfer request is checked. While the external input level is within the range of the specified transfer request levels, transfer is performed continuously without the request being cleared. If the external input changes, the request is cleared and the transfer stops at the transfer boundary. This operation is repeated for the number of times specified by the transfer count. • Otherwise, operations are the same as those of a burst transfer. Transfer request ("H" level) Bus operation Transfer count CPU SA DA 3 SA 2 DA CPU SA DA 1 0 Transfer end (Example of demand transfer for a start with the external pin at "H" level, number of blocks = 1, and transfer count = 3) 393 CHAPTER 14 DMA CONTROLLER (DMAC) Transfer source address Direction Transfer destination address External area → External area External area → Built-in IO External area → Built-in RAM Built-in IO → External area Built-in RAM → External area (Table of specifiable transfer addresses) For a demand transfer, be sure to set an external area address for the transfer source or transfer destination or both. Since DMA transfer is adjusted to the external bus timing in demand transfer mode, access to external areas is always needed. ❍ Demand transfer fly-by transfer A demand transfer fly-by transfer has the same features as a 2-cycle transfer except that the transfer area can only be external areas, and the transfer unit is read (memory → I/O) or write (I/O → memory) only. Transfer source addressing Direction Transfer destination addressing All 32-bit areas specifiable → All 32-bit areas specifiable (Table of specifiable transfer addresses) ❍ Step/block transfer 2-cycle transfer For a step/block transfer (Transfer for each transfer request is performed as many times as the specified block count), all 32-bit areas can be specified as the transfer source/transfer destination address. Transfer source addressing Direction Transfer destination addressing All 32-bit areas specifiable → All 32-bit areas specifiable (Table of specifiable transfer addresses) [Step transfer] If 1 is set as the block size, a step transfer sequence is generated. The following are some features of a step transfer: • If a transfer request is received, the transfer request is cleared after one transfer operation and then the transfer is stopped (The DMA transfer request to the bus controller is canceled). • Another request occurring during transfer is ignored. 394 CHAPTER 14 DMA CONTROLLER (DMAC) • If a transfer request for another channel with a higher priority is received during transfer, the channel is switched after the transfer is stopped and then restarted. Priority in a step transfer is valid only if transfer requests occur simultaneously. [Block transfer] If any value other than "1" is specified as the block size, a block transfer sequence is generated. The following are some features of a block transfer: • The block transfer has the same features as those of a step transfer except that one transfer unit consists of multiple transfer cycle counts (number of blocks). Transfer request ( edge) Bus operation CPU Number of blocks Transfer count SA DA SA 2 DA CPU 1 DA 2 0 2 SA SA DA 1 1 Transfer end (Example of block transfer example for a start for an external pin on a rising edge, number of blocks = 2, and transfer count = 2) ❍ Step/block transfer 2-cycle transfer fly-by transfer This transfer has the same features as those of a 2-cycle transfer except that the transfer area can only be external areas, and the transfer unit is read (memory → I/O) or write (I/O → memory) only. Transfer source addressing Direction Transfer destination addressing Specification not required (invalid) None External area (Table of specifiable transfer addresses) 395 CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.3 General Aspects of DMA Transfer This section describes the block size for DMA transfers and the reload operation. ■ Block Size • The unit and increment for transfer data is a set of (the number set in the block size specification register × data width) data. • Since the amount of data transferred in one transfer cycle is determined by the value specified as the data width, one transfer unit is consists of the number of transfer cycles for the specified block size. • If a transfer request with a higher priority is received during transfer or if a temporary stop request for a transfer occurs, the transfer stops only at the transfer unit boundary, whether or not the transfer is a block transfer. This arrangement makes it possible to protect data for which division or temporary stopping is not desirable. However, if the block size is large, response time increases. • Transfer stops immediately only when a reset occurs, in which case the data being transferred cannot be guaranteed. ■ Reload Operation In this module, the following three types of reloading can be set for each channel: ❍ Transfer count register reloading After transfer is performed the specified number of times, the initial value is set in the transfer count register again and waiting for a start request starts. Set this type of reloading when the entire transfer sequence is to be performed repeatedly. If reload is not specified, the count register value remains "0" after the transfer is performed the specified number of times and no further transfer is performed. ❍ Transfer source address register reloading After transfer is performed the specified number of times, the initial value is set in the transfer source address register again. Set this type of reloading when transfer is to be repeated from a fixed area in the transfer source address area. If reload is not specified, the transfer source address register value after the transfer is performed the specified number of times becomes the next address. Use this type when the address area is not fixed. ❍ Transfer destination address register reloading After transfer is performed the specified number of times, the initial value is set in the transfer destination address register again. Set this type of reloading when transfer is to be repeated to a fixed area in the transfer destination address area. (The processing hereafter is the same as described in "Transfer source address register reloading" above.) 396 CHAPTER 14 DMA CONTROLLER (DMAC) • If only reloading of the transfer source/transfer destination register is enabled, restart after transfer is performed the specified number of times is not implemented and only the values of each address register are set. ❍ Special examples of operating mode and the reload operation • If transfer is performed in continuous transfer mode by external pin input level detection and transfer count register reloading is used, transfer continues by reloading even though transfer ends during continuous input. Also in this case, an end code is set. • If it is preferable that processing stops when data transfer ends and starts after input is detected again, do not specify reload. • For a transfer in burst, block, or step transfer mode, transfer stops temporarily after reload when data transfer ends. Transfer does not start until new transfer request input is detected. 397 CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.4 Addressing Mode Specify the transfer destination/transfer source address independently for each transfer channel. ■ Address Register Specifications The following two methods are provided to specify an address register. The method specified depends on the transfer sequence. • In 2-cycle transfer mode, set the transfer source address in the transfer source address setting register (DMASA) and the transfer destination address in the transfer destination address setting register (DMADA). • In fly-by transfer mode, specify the memory address in the transfer source address setting register (DMASA). In this case, the value in the transfer destination address setting register (DMADA) is ignored. ■ Features of the Address Register This register has the maximum 32-bit length. With 32-bit length, all space in the memory map can be accessed. ■ Function of the Address Register • The address register is read in each access operation and the read value is sent to the address bus. • At the same time, the address for the next access is calculated by the address counter and the address register is updated using the calculated address. • For address calculation, increment or decrement is selected independently for each channel, transfer destination, and transfer source. The address increment/decrement width is specified by the address count size register (SASZ/DASZ of DMACB). • If reloading is not enabled, the address resulting from the address calculation of the last address remains in the address register when the transfer ends. • If reloading is enabled, the initial value of the address is reloaded. Notes: • If an overflow or underflow occurs as a result of 32-bit length full address calculation, an address error is detected and transfer on the relevant channel is stopped. Refer to "Table 14.2-6 End Codes" for details. (Control Status Register B, DSS [2:0] bit) • Do not set any of the DMAC’s registers as the address register. • For demand transfer, be sure to set an address in an external area for the transfer source, transfer destination, or both. • Do not let the DMAC transfer data to any of the DMAC’s registers. 398 CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.5 Data Types Select the data length (data width) transferred in one transfer operation from the following: • Byte • Halfword • Word ■ Data Length (Data width) Since the word boundary specification is also observed in DMA transfer, different low-order bits are ignored if an address with a different data length is specified for the transfer destination/ transfer source address. • Byte: The actual access address and the addressing match. • Halfword: The actual access address has 2-byte length starting with "0" as the lowestorder bit. • Word: The actual access address has a 4-byte length starting with "00" as the lowestorder bits. If the lowest-order bits in the transfer source address and transfer destination address are different, the addresses as set are output on the internal address bus. However, each transfer target on the bus is accessed after the addresses are corrected according to the above rules. 399 CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.6 Transfer Count Control Specify the transfer count within the range of the maximum 16-bit length (1 to 65536). ■ Transfer Count Control Set the transfer count value in the transfer count register (DTC of DMACA). The register value is stored in the temporary storage buffer when the transfer starts and is decremented by the transfer counter. When the counter value becomes "0", end of transfer end for the specified count is detected, and the transfer on the channel is stopped or waiting for a restart request starts (when reload is specified). The following are some features of the group of transfer count registers: • Each register has 16-bit length. • All registers have a dedicated reload register. • If transfer is activated when the register value is "0", transfer is performed 65536 times. ■ Reload Operation 400 • The reload operation can be used only if reloading is enabled in a register that allows reloading. • When transfer is activated, the initial value of the count register is saved in the reload register. • If the transfer counter counts down to "0", end of transfer is reported and the initial value is read from the reload register and written to the count register. CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.7 CPU Control When a DMA transfer request is accepted, DMA issues a transfer request to the bus controller. The bus controller passes the right to use the internal bus to DMA at a break in bus operation and DMA transfer starts. ■ DMA Transfer and Interrupts • During DMA transfer, interrupts are generally not accepted until the transfer ends. • If a DMA transfer request occurs during interrupt processing, the transfer request is accepted and interrupt processing is stopped until the transfer is completed. • If, as an exception, an NMI request or an interrupt request with a higher level than the hold suppress level set by the interrupt controller occurs, DMAC temporarily cancels the transfer request via the bus controller at a transfer unit boundary (one block) to temporarily stop the transfer until the interrupt request is cleared. In the meantime, the transfer request is retained internally. After the interrupt request is cleared, DMAC issues a transfer request to the bus controller to acquire the right to use the bus and then restarts DMA transfer. ■ Suppressing DMA When an interrupt source with a higher priority occurs during DMA transfer, an FR family device interrupts the DMA transfer and branches to the relevant interrupt routine. This feature is valid as long as there are any interrupt requests. When all interrupt sources are cleared, the suppression feature no longer works and the DMA transfer is restarted by the interrupt processing routine. Thus, if you want to suppress restart of DMA transfer after clearing interrupt sources in the interrupt source processing routine at a level that interrupts DMA transfer, use the DMA suppress function. The DMA suppress function can be activated by writing any value other than "0" to the DMAH[3:0] bits of the DMA all-channel control register and can be stopped by writing "0" to these bits. This function is mainly used in the interrupt processing routines. Before the interrupt sources in an interrupt processing routine are cleared, the DMA suppress register is incremented by "1". If this is done, then no DMA transfer is performed. After interrupt processing, decrement the DMAH[3:0] bits by "1" before returning. If multiple interrupts have occurred, DMA transfer continues to be suppressed since the DMAH[3:0] bits are not "0" yet. If a single interrupt has occurred, the DMAH[3:0] bits become 0. DMA requests are then enabled immediately. Notes: • Since the register has only four bits, this function cannot be used for multiple interrupts exceeding 15 levels. • Be sure to assign the priority of the DMA tasks at a level that is at least 15 levels higher than other interrupt levels. 401 CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.8 Hold Arbitration When a device is operating in external bus extended mode, an external hold function can be used. The relationship between external hold requests and DMA transfer requests by this module when the hold function can be used is described below. ■ DMA Transfer Request during External Hold The device is externally held. When an external bus area is accessed by DMA transfer, DMA transfer is temporarily stopped. When the external hold is released, DMA transfer is restarted. ■ External Hold Request During DMA Transfer The device is externally held. When an external bus area is accessed by DMA transfer, DMA transfer is temporarily stopped. When the external hold is released, DMA transfer is restarted. ■ Simultaneous Occurrence of a DMA Transfer Request and an External Hold Request The device is externally held and internal DMA transfer is started. When an external bus area is accessed by DMA transfer, DMA transfer is temporarily stopped. When the external hold is released, DMA transfer is restarted. 402 CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.9 Operation from Starting to End/Stopping Starting of DMA transfer is controlled independently for each channel, but before transfer starts, the operation of all channels needs to be enabled. This section describes operation from starting to end/stopping. ■ Operation Start ❍ Enabling operation for all channels Before activating each DMAC channel, operation for all channels needs to be enabled in advance with the DMA operation enable bit (DMAE of DMACR). All start settings and transfer requests that occurred before operation is enabled are invalid. ❍ Starting transfer The transfer operation can be started by the operation enable bit of the control register for each channel. If a transfer request to an activated channel is accepted, the DMA transfer operation is started in the specified mode. ❍ Starting from a temporary stop If a temporary stop occurs before starting with channel-by-channel or all-channel control, the temporary stopped state is maintained even though the transfer operation is started. If transfer requests occur in the meantime, they are accepted and retained. When temporary stopping is released, transfer is started. ■ Transfer Request Acceptance and Transfer • Sampling for transfer requests set for each channel starts after starting. • If edge detection is selected for the external pin start source and a transfer request is detected, the request is retained within DMAC until the clear conditions are met (when the external pin start source is selected for block, step, or burst transfer). If level detection or peripheral interrupt start is selected for the external pin start source, DMAC continues the transfer until all transfer requests are cleared. When they are cleared, DMAC stops the transfer after one transfer unit (demand transfer or peripheral interrupt start). Since peripheral interrupts are handled as level detection, use interrupt clear by DMA to handle the interrupts. Transfer requests are always accepted while other channel requests are being accepted and transfer performed. The channel that will be used for transfer is determined for each transfer unit after priority has been checked. For built-in peripheral circuit, the DMA transfer via the external interrupt and the interrupt request signal of the reload timer cannot be started (MB91306R/307R only). 403 CHAPTER 14 DMA CONTROLLER (DMAC) ■ Clearing Peripheral Interrupts by DMA This DMA has a function that clears peripheral interrupts. This function works when peripheral interrupt is selected as the DMA start source (when IS[4:0]=1xxxx). Peripheral interrupts are cleared only for the set start sources. That is, only the peripheral functions set by IS[4:0] are cleared. The timing for clearing an interrupt depends on the transfer mode (See Section "14.4 Operation Flowcharts"). • Block/step transfer: If block transfer is selected, a clear signal is generated after one block (step) transfer. • Burst transfer: If burst transfer is selected, a clear signal is generated after transfer is performed the specified number of times. • Demand transfer: Since only start requests from external pins are supported in demand transfer, no clear signal is generated. ■ Temporary Stopping DMA transfer is stopped in the following cases: ❍ Setting of temporary stopping by writing to the control register (Set independently for each channel or all channels simultaneously) If temporary stopping is set using the temporary stop bit, transfer on the corresponding channel is stopped until release of temporary stopping is set again. You can check the DSS bits for temporary stopping. • When all channels are stopped temporarily at once To stop all DMA channels temporarily, set any value other than "0000" in DMAH[3:0] of DMACR. To release temporary stopping, set "0000" in the register. • When temporary stopping is determined on a channel-by-channel basis To stop the DMA channels on a channel-by-channel basis, set any value other than "0000" in DMAH[3:0] of DMACR to temporarily stop all channels, instruct temporary stopping for each channel by setting PAUS=1 of DMACA, and then release temporary stopping of all channels by setting 0000 in DMAH[3:0] of DMACR. To release temporary stopping of each channel, set PAUS=0. ❍ NMI/hold suppress level interrupt processing If an NMI request or an interrupt request with a higher level than the hold suppress level occurs, all channels on which transfer is in progress are stopped at the boundary of the transfer unit and 2 the bus right is returned to give priority to NMI/interrupt processing. Transfer interrupts accepted during NMI/interrupt processing are retained, initiating a wait for completion of NMI processing. Channels for which requests are retained restart transfer after NMI/interrupt processing is completed. 404 CHAPTER 14 DMA CONTROLLER (DMAC) ■ Operation End/Stopping The end of DMA transfer is controlled independently for each channel. It is also possible to disable operation for all channels at once. ❍ Transfer end If reloading is disabled, transfer is stopped, "Normal end" is displayed as the end code, and all transfer requests are disabled after the transfer count register becomes 0 (Clear the DENB bit of DMACA). If reloading is enabled, the initial value is reloaded, "Normal end" is displayed as the end code, and a wait for transfer requests starts after the transfer count register becomes 0 (Do not clear the DENB bit of DMACA). ❍ Disabling all channels If the operation of all channels is disabled with the DMA operation enable bit DMAE, all DMAC operations, including operations on active channels, are stopped. Then, even if the operation of all channels is enabled again, no transfer is performed unless a channel is restarted. In this case, no interrupt whatever occurs. ■ Stopping Due To an Error In addition to normal end after transfer for the number of times specified, stopping as the result of various types of errors and the forced stopping are provided. ❍ Transfer stop requests from peripheral circuits Depending on the peripheral circuit that outputs a transfer request, a transfer stop request is issued when an error is detected (Example: Error when data is received at or sent from a communications system peripheral). The DMAC, when it receives such a transfer stop request, displays "Transfer stop request" as the end code and stops the transfer on the corresponding channel. IS Function Transfer stop request 00000 Software start (STRG bit) None 01111 10000 External pin "L" level or edge Yes 10010 10011 None 11111 For details of the conditions under which a transfer stop request is generated, see "12.2.5 DRCL Register". 405 CHAPTER 14 DMA CONTROLLER (DMAC) ■ Occurrence of an Address Error If inappropriate addressing, as shown below in parenthesis, occurs in an addressing mode, an address error is detected (if an overflow or underflow occurs in the address counter when a 32bit address is specified). If an address error is detected, "An address error occurred" is displayed as the end code and transfer on the corresponding channel is stopped. 406 CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.10 DMAC Interrupt Control Independent of peripheral interrupts that become transfer requests, interrupts can also be output for each DMAC channel. ■ DMAC Interrupt Control The following interrupts can be output for each DMAC channel: • Transfer end interrupt: Occurs only when operation ends normally. • Error interrupt: Transfer stop request due to a peripheral circuit (error due to a peripheral) • Error interrupt: Occurrence of address error (error due to software) All of these interrupts are output according to the meaning of the end code. An interrupt request can be cleared by writing "000" to DSS2 to "0" (end code) of DMACS. Be sure to clear the end code by writing "000" before restarting. If reloading is enabled, the transfer is automatically restarted. At this point, however, the end code is not cleared and is retained until a new end code is written when the next transfer ends. Since only one end source can be displayed in an end code, the result after considering the order of priority is displayed when multiple sources occur simultaneously. The interrupt that occurs at this point conforms to the displayed end code. The following shows the priority for displaying end codes (in order of decreasing priority): • Reset • Clearing by writing "000" • Peripheral stop request or external pin input (DSTP) stop request • Normal end • Stopping when address error detected • Channel selection and control ■ DMA Transfer during Sleep • The DMAC can also operate in sleep mode. • If you anticipate operations during sleep mode, note the following: • • Since the CPU is stopped, DMAC registers cannot be rewritten. Make settings before sleep mode is entered. • The sleep mode is released by an interrupt. Thus, if a peripheral interrupt is selected as the DMAC start source, interrupts must be disabled by the interrupt controller. If you do not want to release sleep mode with a DMAC end interrupt, disable these interrupts. 407 CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.11 Channel Selection and Control Up to five channels can be simultaneously set as transfer channels. In general, an independent function can be set for each channel. ■ Priority Among Channels Since DMA transfer is possible only on one channel at a time, priority must be set for the channels. Two modes, fixed and rotation, are provided as the priority settings and can be selected for each channel group (described later). ❍ Fixed mode The order of priority is fixed by channel number, with priority decreasing from channel 0 to channel 4: (ch0 > ch1 > ch2 > ch3 > ch4) If a transfer request with a higher priority is received during a transfer, the transfer channel becomes the channel with the higher priority when the transfer for the transfer unit (number set in the block size specification register × data width) ends. When higher priority transfer is completed, transfer is restarted on the previous channel. ch0 transfer request ch1 transfer request Bus operation CPU Transfer ch SA DA ch1 SA DA ch0 SA DA ch0 SA DA CPU ch1 ch0 transfer end ch1 transfer end ❍ Rotation mode (ch.0 to ch.1 only) When operation is enabled, the initial states have the same order that they would have in fixed mode, but at the end of each transfer operation, the priority of the channels is reversed. Thus, if more than one transfer request is output at the same time, the channel is switched after each transfer unit. This mode is effective when continuous or burst transfer is set. ch0 transfer request ch1 transfer request Bus operation Transfer ch ch0 transfer end ch1 transfer end 408 CPU SA DA ch1 SA DA ch0 SA DA ch1 SA DA ch0 CPU CHAPTER 14 DMA CONTROLLER (DMAC) ■ Channel Group The order of priority is set as shown in the following table. MODE Priority Remarks Fixed ch0 > ch1 − ch0 > ch1 Rotation ch0 < ch1 The initial state is the top row. If transfer occurs for the top row, the priority is reversed. 409 CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.12 Supplement on External Pin and Internal Operation Timing This section provides supplementary information about external pins and internal operation timing. ■ Minimum Effective Pulse Width of the DREQ pin Input Only channels 0, 1, and 2 are applicable for the MB91307 series. In all transfer modes for burst, step, block, and demand transfers, the minimum width required is five system clock cycles (5 cycles of the DMA operating clock CLKB). Note: DACK output does not indicate acceptance of DREQ input. DREQ input is always accepted if DMA is enabled but transfer has not started. Therefore, it is not necessary to retain DREQ input until DACK output is asserted (except in demand transfer mode). ■ Negate Timing of the DREQ Pin Input when a Demand Transfer Request is Stopped ❍ For 2-cycle transfer For a demand transfer, be sure to set an address in an external area for the transfer source, the transfer destination, or both. • If the transfer type is external ↔ external: Negate before the last sense timing of the clock in the "L" section of the external write strobe pin output when accessing the transfer source for the last DMA transfer. If DREQ is negated later than this, a DMA request may be sensed, resulting in negation until the next transfer. • If the transfer type is external ↔ internal: Negate before the last sense timing of the clock in the "L" section of the external RD pin output when accessing the transfer source for the last DMA transfer. If DREQ is negated later than this, a DMA request may be sensed, resulting in negation until the next transfer. Bus operation Area External D bus CPU SA DA SA DA *1 *2 *1 *2 CPU *1: External *2: Internal SA DA SA DA *1 *2 *1 *2 DACK DEOP RD WR DREQ (H level) (Negate timing example of the DREQ pin input for 2-cycle external transfer => internal transfer) 410 CHAPTER 14 DMA CONTROLLER (DMAC) • If the transfer is internal ↔ external: Negate before the last sense timing of the clock in the "L" section of the external write strobe pin output when accessing the transfer source for the last DMA transfer. If DREQ is negated later than this, a DMA request may be sensed, resulting in negation until the next transfer. ❍ For fly-by (read/write) transfer For a demand transfer, be sure to set an address in an external area for the transfer destination. • For fly-by (read) transfer: Negate while in the "L" section of the external RD pin output when accessing the transfer source for the last DMA transfer (section where DACK=L & RD=L). If DREQ is negated later than this, the negation may continue until the next transfer. • For fly-by (write) transfer: Negate while in the "L" section of the external WR pin output when accessing the transfer source for the last DMA transfer (section where DACK=L & RD=L). If DREQ is negated later than this, the negation may continue until the next transfer. Bus operation CPU Area External D bus DA DA DA DA * * * * CPU * : External DA * DA * DA * DA * DACK DEOP RD WR DREQ (H level) (Negate timing example of the DREQ pin input for fly-by (write) transfer) ■ Timing of the DREQ Pin Input for Continuing Transfer over the Same Channel ❍ For burst, step, block, and demand transfers Operation in which transfer is continued over the same channel by the DREQ pin input cannot be guaranteed. If DREQ is reasserted at the fastest timing to clear requests retained internally after the transfer ends, at least one system clock cycle (one CLK output cycle) is provided to detect transfer requests for other channels. If, as a result, a transfer request for another channel with a higher priority is detected, transfer on that channel will be started. Even if DREQ is reasserted earlier, it is ignored because the transfer has not been completed. If no transfer requests for other channels occur, transfer over the same channel is restarted by reasserting DREQ when the DACK pin output is asserted. ■ Timing of DACK Pin Output The DACK output of this DMAC indicates that transfer with respect to an accepted transfer request is being performed. The output of DACK is basically synchronized with the address output of external bus access timing. To use DACK output, it is necessary to enable the DACK output with a port. 411 CHAPTER 14 DMA CONTROLLER (DMAC) ■ Timing of the DEOP Pin Output • The DEOP of this DMA indicates that DMA transfer for the specified number of times of the accepted channel has been completed. • DEOP is output when access to an external area of the last transfer block starts. Thus, if any value other than "1" is set (block transfer mode) as the block size, DEOP is output when the last data of the last block is transferred. In this case, the acceptance of the next DREQ is already started even during transfer (before DEOP output) if the DACK pin output is asserted. • The DEOP output is synchronized with external bus access timing. However, if the transfer source/transfer destination is internal access, DEOP is not output. To use DEOP output, it is necessary to enable the DEOP output using the port register. ■ Timing of the DSTP Pin Input • In all transfer modes of burst, step, block, and demand transfers, a width of at least 5 system clock cycles (=1/2θ, 5 cycles of the DMA operating clock CLKB) are needed. • As with DREQ, we recommend that you use DSTP input timing in synchronization with external access (Use the DACK output and the signal decoded by RD or WR). • Use the pin input to force DMA transfer to stop. Although transfer can be forced to stop by using this pin input, the status register (DSS[2:0] of DMACB) indicates "Transfer stop request" and is handled as an error. If interrupts are enabled, interrupts will occur. • Since this function is shared with the DEOP pin, both functions cannot be used. Set switching of functions with the port register. ■ If an External Pin Transfer Request is Reentered During Transfer ❍ For burst, step, and block transfers While the DACK signal is asserted within the DMAC, the next transfer request, if it is entered, is disabled. However, since operation of the external bus control unit and operation of the DMAC are not completely synchronous, the circuit must be initialized to create DREQ pin input using DACK and DEOP output to enable transfer requests by using DREQ input. ❍ For a demand transfer If reloading of the transfer count register is specified when transfer for as many transfers as specified has been completed, another transfer request is accepted. ■ If Another Transfer Request Occurs During Block Transfer No request is detected before the transfer of the specified blocks is completed. At the block boundaries, transfer requests accepted at that time are evaluated and then transfer on the channel with the highest priority is performed. ■ Transfer Between External I/O and External Memory As targets of transfer by the DMAC, external I/O and external memory are not distinguished. Specify an external I/O as a fixed external address. To perform fly-by transfer, set the address of external memory in the transfer destination address register. For external I/O, use DACK output and the signal decoded by the read signal RD or write signal WRx pin. 412 CHAPTER 14 DMA CONTROLLER (DMAC) ■ AC Characteristics of DMAC DREQ pin input, DACK pin output, and DEOP pin output are provided as the external pins related to the DMAC,. Output timing is synchronized with external bus access (refer to the AC standard for the DMAC on the Data sheet). 413 CHAPTER 14 DMA CONTROLLER (DMAC) 14.4 Operation Flowcharts This section contains operation flowcharts for the following transfer modes: • Block transfer • Burst transfer • Demand transfer ■ Block Transfer Figure 14.4-1 shows the flowchart for block transfer. Figure 14.4-1 Operation Flowchart for Block Transfer DMA stop DENB=>0 DENB=1 Reload enable Activation request wait Activation request Load the initial address, transfer count, and number of blocks Calculate the address for transfer source address access One-time access for fly-by Calculate the address for transfer destination address access Number of blocks - 1 BLK=0 Transfer count - 1 Write back the address, transfer count, and number of blocks Only when the peripheral interrupt activation source is selected Interrupt clear Interrupt cleared DTC=0 DMA transfer end Block transfer - Can be activated by all activation sources (selection). - Can access all areas. - The number of blocks can be set. - Interrupt clear is issued when transfer of the specified number of blocks is completed. - The DMA interrupt is issued when transfer for the number of times specified is completed. 414 DMA interrupted CHAPTER 14 DMA CONTROLLER (DMAC) ■ Burst Transfer Figure 14.4-2 shows the operation flowchart for burst transfer. Figure 14.4-2 Operation Flowchart for Burst Transfer DMA stop DENB=>0 DENB=1 Reload enable Activation request wait Activation request Load the initial address, transfer count, and number of blocks Calculate the address for transfer source address access One-time access for fly-by Calculate the address for transfer destination address access Number of blocks - 1 BLK=0 Transfer count - 1 DTC=0 Write back the address, transfer count, and number of blocks Only when the peripheral interrupt activation source is selected Interrupt cleared Interrupt clear DMA transfer end DMA interrupted Burst transfer - Can be activated by all activation sources (selection). - Can access all areas. - The number of blocks can be set. - Interrupt clear and the DMA interrupt are issued when transfer for the number of times specified is completed. 415 CHAPTER 14 DMA CONTROLLER (DMAC) ■ Demand Transfer Figure 14.4-3 shows the operation flowchart for demand transfer. Figure 14.4-3 Operation Flowchart for Demand Transfer DMA stop DENB=>0 None Reload enable DENB=1 Activation request wait Activation request Load the initial address, transfer count, and number of blocks Calculate the address for transfer source address access One-time access for fly-by Calculate the address for transfer destination address access Number of blocks - 1 Write back the address, transfer count, and number of blocks DTC=0 Interrupt clear DMA transfer end Only when the peripheral interrupt activation source is selected Interrupt cleared DMA interrupted Demand transfer - Only requests from the external pin (DREQ) are accepted. Activation by other sources is disabled. - Access to an external area is required (since access to an external area becomes the next activation source). - The number of blocks is always 1, regardless of the settings. - Interrupt clear and the DMA interrupt are issued when transfer for the number of times specified is completed. 416 CHAPTER 14 DMA CONTROLLER (DMAC) 14.5 Data Bus This section shows the flow of data during 2-cycle transfer and fly-by transfer. ■ Flow of Data During 2-Cycle Transfer Figure 14.5-1 shows examples of six types of transfer during 2-cycle transfer. Figure 14.5-1 Examples of 2-Cycle Transfer (Continued on next page) CPU Read cycle I-bus D-bus X-bus Bus controller Data buffer MB91xxx D-bus F-bus RAM DMAC Write cycle I-bus X-bus Bus controller Data buffer External bus I/F DMAC CPU MB91xxx External bus I/F External area → external area transfer F-bus I/O RAM I/O CPU Read cycle I-bus X-bus Bus controller D-bus Data buffer MB91xxx X-bus Bus controller D-bus Data buffer F-bus RAM DMAC Write cycle I-bus External bus I/F DMAC CPU MB91xxx External bus I/F External area → internal RAM area transfer F-bus I/O RAM I/O X-bus Bus controller D-bus Data buffer F-bus RAM DMAC Write cycle I-bus CPU Read cycle I-bus CPU MB91xxx DMAC External bus I/F MB91xxx X-bus Bus controller D-bus Data buffer External bus I/F External area → built-in I/O area transfer F-bus I/O RAM I/O 417 CHAPTER 14 DMA CONTROLLER (DMAC) X-bus Bus controller DMAC Write cycle I-bus CPU CPU Read cycle I-bus D-bus MB91xxx DMAC External bus I/F MB91xxx X-bus Bus controller D-bus F-bus RAM External bus I/F Built-in I/O area → internal RAM area transfer F-bus I/O RAM I/O X-bus Bus controller DMAC Write cycle I-bus CPU CPU Read cycle I-bus D-bus MB91xxx DMAC External bus I/F MB91xxx X-bus Bus controller D-bus F-bus RAM External bus I/F Internal RAM area → external area transfer F-bus I/O RAM I/O X-bus Bus controller F-bus RAM 418 DMAC Write cycle I-bus CPU CPU Read cycle I-bus D-bus MB91xxx DMAC External bus I/F MB91xxx X-bus Bus controller D-bus F-bus I/O RAM I/O External bus I/F Internal RAM area → built-in I/O area transfer CHAPTER 14 DMA CONTROLLER (DMAC) ■ Flow of Data During Fly-By Transfer Figure 14.5-2 shows examples of two types of transfer during fly-by transfer. Figure 14.5-2 Examples of Fly-By Transfer DMAC CPU Read cycle I-bus D-bus X-bus Bus controller memory MB91xxx External bus I/F Fly-by transfer (memory to I/O) F-bus I/O write by RD or DACK I/O RAM Memory read by RD or CSx I/O Fly-by transfer by SDRAM disabled CPU D-bus X-bus Bus controller memory DMAC Read cycle I-bus I/O read by WR0/1 or DACK F-bus RAM Memory write by WR0/1 or CSx I/O I/O MB91xxx External bus I/F Fly-by transfer (I/O to memory) Fly-by transfer by SDRAM disabled 419 CHAPTER 14 DMA CONTROLLER (DMAC) 14.6 DMA External Interface This section provides operation timing charts for the DMA external interface. ■ DMA External Interface Pins DMA channels 0 to 2 have the following DMA-dedicated pins (DREQ, DACK, and DEOP): • DREQ: DMA transfer request input pin for demand transfer. A transfer is requested with an input. • DACK: This pin becomes active ("L" output) when DMA accesses an external area via the external interface. • DEOP: This pin becomes active ("L" output) in synchronization with the last access to complete DMA transfer. The IORD and IOWR signals become active under the following conditions: 420 • IORD: This signal becomes active when the direction I/O -> memory is selected for fly-by transfer. • IOWR: This signal becomes active when the direction memory -> I/O is selected for fly-by transfer. CHAPTER 14 DMA CONTROLLER (DMAC) 14.6.1 Examples of DMA External Interface Operation (Simplified Waveforms) This section provides the following three timing charts as examples of DMA external interface operation (simplified waveforms): • 2-cycle transfer • Fly-by transfer (I/O → memory) • Fly-by transfer (memory → I/O) ■ 2-Cycle Transfer (for external → external transfer and transfer count = 2) Figure 14.6-1 Timing Chart for 2-Cycle Transfer A24 to A0 #RD1 #WR1 #RD2 #WR2 RD WE,WR0/1 The write signal depends on the external bus interface settings. DEOP DACK CS1 1st read 1st write 2nd read 2nd write ■ Fly-By Transfer (for I/O → memory and transfer count = 3) Figure 14.6-2 Timing Chart for Fly-By Transfer (I/O → Memory) A24 to A0 CPU 1# 2 3 RD WE,WR0/1 The write signal depends on the external bus interface settings. IORD DEOP DACK CS1 CPU read 1st fly-by 2nd fly-by 3rd fly-by 421 CHAPTER 14 DMA CONTROLLER (DMAC) ■ Fly-By Transfer (for memory → I/O and transfer count = 3) Figure 14.6-3 Timing Chart for Fly-By Transfer (Memory → I/O) A24 to A0 CP #1 #2 #3 RD The write signal depends on the external bus interface settings. WE,WR0/1 IOWR DEOP DACK CS1 CPU read 422 1st fly-by 2nd fly-by 3rd fly-by CHAPTER 14 DMA CONTROLLER (DMAC) 14.6.2 Input Timing of the DREQx Pin The DREQx pin is a DMA start request signal. If the pin is also used as a port, enable the DREQ input using the PFR register. This section shows the input timing of the DREQx pin. ■ Timing of Transfer Other Than Demand Transfer For transfer other than demand transfer, set the DMA start source to edge detection. Although there is no rule for rise/fall timing, use three or more clock cycles as the holding time the DREQ signal. To make another transfer request, enter the request after the DMA transfer is completed (make a request after DEOP is output). If a request is made before DEOP is output, it may be ignored. Figure 14.6-4 shows the timing chart for transfer other than demand transfer. Figure 14.6-4 Timing Chart for Transfer Other Than the Demand Transfer When a DREQx edge is requested (for 2-cycle transfer) MCLK DREQ A24 to 0 #RD1 #WR1 #RD2 #WR2 RD WE,WR0/1 DEOP CPU operation MAD transfer CPU The write signal depends on the external bus interface settings. 3 or more cycles The next request must be after DEOP output 423 CHAPTER 14 DMA CONTROLLER (DMAC) ■ Timing of Demand Transfer For demand transfer, set the DMA start source to level detection. Although there is no rule for starting, synchronize with RD/WR of the DMA transfer when stopping a transfer. The sense timing is the rise of MCLK in the final external access. Figure 14.6-5 shows the timing chart for demand transfer. Figure 14.6-5 Timing Chart for Demand Transfer When a DREQx level is requested (for 2-cycle transfer) MCLK DREQ A24 to 0 #RD1 #WR1 #RD2 #WR2 RD WE,WR0/1 CPU operation DMA transfer CPU The write signal depends on the external bus interface settings. Sense point of the 3rd transfer request Note: In this case, because 2-cycle transfer is used and the transfer source and transfer destination are an external area, negate from the fall of #RD2 to before the final MCLK rise of #WR2 to stop the two DMA transfer operations. 424 CHAPTER 14 DMA CONTROLLER (DMAC) 14.6.3 FR30 Compatible Mode of DACK(DEOP) FR30 compatible mode of DACK makes the DACK timing identical to the timing of DMA used in FR30 devices. This section provides the timing charts for the DACK(DEOP) pin in FR30 compatible mode for the following examples of transfer mode setting: • 2-cycle transfer mode • Fly-by transfer mode ■ Transfer Mode Settings Set the transfer mode using the PFR register corresponding to the DACK pin. When setting PFR, match the transfer mode (2-cycle transfer/fly-by transfer) of the corresponding DMA channel. Note: If 2-cycle transfer is set in FR30 compatible mode, the transfer is synchronized with RD or WE. To use WE, enable WE by setting 0x1x for TYPE3 to TYPE0 of the external interface ACR register. When WR0 and WR1 are enabled (TYPE3 to TYPE0=0x0x), FR30 compatible mode cannot be used. ❍ 2-cycle transfer mode Figure 14.6-6 shows the timing chart in 2-cycle transfer mode. Figure 14.6-6 Timing Chart in 2-Cycle Transfer Mode RD UUB/ULB WE DACK (AKxx=111) * DACK (AKxx=001) * Same timing as the chip select 2-cycle transfer setting disabled DACK (AKxx=110) * DACK (AKxx=100) * DACK (AKxx=010) * * : Akxx is the setting in the PFR register that corresponds to the DMA channel. 425 CHAPTER 14 DMA CONTROLLER (DMAC) ❍ Fly-by transfer mode Figure 14.6-7 shows the timing chart in fly-by transfer mode. Figure 14.6-7 Timing Chart in Fly-By Transfer Mode RD UUB/ULB WE IORD IOWR DACK (AKxx=111) * Same timing as the chip select DACK (AKxx=001) * DACK (AKxx=110) * Fly-by transfer setting disabled DACK (AKxx=100) * Fly-by transfer setting disabled DACK (AKxx=010) * Fly-by transfer setting disabled memory to I/O I/O to memory memory to I/O I/O to memory * : Akxx is the setting in the PFR register that corresponds to the DMA channel. Note: The timing of DEOP is the same as the timing of DACK because the DEOP timing is synchronized with the settings of each DACK. 426 CHAPTER 15 BIT SEARCH MODULE This chapter describes the bit search module, the configuration and functions of registers, and bit search module operation. 15.1 Overview of the Bit Search Module 15.2 Bit Search Module Registers 15.3 Bit Search Module Operation 427 CHAPTER 15 BIT SEARCH MODULE 15.1 Overview of the Bit Search Module The bit search module searches for "0", "1", or any points of change for data written to the input register and then returns the detected bit locations. ■ Block Diagram of the Bit Search Module Figure 15.1-1 is a block diagram of the bit search module. Figure 15.1-1 Block Diagram of the Bit Search Module D-bus Input latch Address decoder Detection mode 1 detection data coding Bit search circuit Detection result 428 CHAPTER 15 BIT SEARCH MODULE 15.2 Bit Search Module Registers This section describes the registers used by the bit search module. ■ Bit Search Module Registers Figure 15.2-1 shows the bit search module registers Figure 15.2-1 Bit Search Module Register 31 0 Address: 000003F0H Address: 000003F4H Address: 000003F8H Address: 000003FCH BSD0 BSD1 BSDC BSRR 0 detection data register 1 detection data register Change point detection data register Detection result register ■ 0 Detection Data Register (BSD0) Shown below is the configuration of the "0" detection data register (BSD0). 31 0 000003F0H Read/write→ W Initial value→ Undefined • "0" detection is performed for the written data. • The initial value after a reset is undefined. • The read value is undefined. • Use a 32-bit length data transfer instruction for data transfer. Do not use 8-bit or 16-bit length data transfer instructions. ■ 1 Detection Data Register (BSD1) Shown below is the configuration of the 1 detection data register (BSD1). 31 0 000003F4H Read/write→ R/W Initial value→ Undefined Use a 32-bit length data transfer instruction for data transfer. Do not use 8-bit or 16-bit length data transfer instructions. 429 CHAPTER 15 BIT SEARCH MODULE ❍ Writing "1" detection is performed for the written data. ❍ Reading • Save data of the internal state of the bit search module is read. This register is used to save and restore the original state when the bit search module is used by, for example, an interrupt handler. • Even though data is written to the "0" detection or change point detection data register, data can be saved and restored only by using the "1" detection data register. • The initial value after a reset is undefined. ■ Change Point Detection Data Register (BSDC) Shown below is the configuration of the change point detection data register (BSDC). 31 0 000003F8H Read/write→ W Initial value→ Undefined • Point of change are detected in the written value. • The initial value after a reset is undefined. • The read value is undefined. • Use a 32-bit length data transfer instruction for data transfer. Do not use 8-bit or 16-bit length data transfer instructions. ■ Detection Result Register (BSRR) The result of "0" detection, "1" detection, or change point detection is read. Which detection result is to be read is determined by the data register that has been written to last. Shown below is the configuration of the detection result register (BSRR). 31 000003FCH Read/write→ R Initial value→ Undefined 430 0 CHAPTER 15 BIT SEARCH MODULE 15.3 Bit Search Module Operation The bit search module performs the following three operations: • 0 detection • 1 detection • Change point detection ■ 0 Detection The bit search module scans data written to the "0" detection data register from the MSB to LSB and returns the location where the first "0" is detected. The detection result can be obtained by reading the detection result register. The relationship between the detected location and the return value is given in Table 15.3-1. If a "0" is not found (that is, the value is FFFFFFFFH), 32 is returned as the search result. [Execution example] Write data 11111111111111111111000000000000B 11111000010010011110000010101010B 10000000000000101010101010101010B 11111111111111111111111111111111B Read value (decimal) (FFFFF000H) (F849E0AAH) (8002AAAAH) (FFFFFFFFH) → 20 →5 →1 → 32 ■ 1 Detection The bit search module scans data written to the 1 detection data register from the MSB to LSB and returns the location where the first "1" is detected. The detection result can be obtained by reading the detection result register. The relationship between the detected location and the return value is given in Table 15.3-1. If a "1" is not found (that is, the value is 00000000H), 32 is returned as the search result. [Execution example] Write data 00100000000000000000000000000000B 00000001001000110100010101100111B 00000000000000111111111111111111B 00000000000000000000000000000001B 00000000000000000000000000000000B Read value (decimal) (20000000H) (01234567H) (0003FFFFH) (00000001H) (00000000H) →2 →7 → 14 → 31 → 32 431 CHAPTER 15 BIT SEARCH MODULE ■ Change Point Detection The bit search module scans data written to the change point detection data register from bit 30 to the LSB for comparison with the MSB value. The first location where a value that is different from that of the MSB is detected is returned. The detection result can be obtained by reading the detection result register. The relationship between the detected location and the return value is given in Table 15.3-1. If a change point is not detected, 32 is returned. In change point detection, "0" is never returned as a result. [Execution example] Write data Read value (decimal) 00100000000000000000000000000000B 00000001001000110100010101100111B 00000000000000111111111111111111B 00000000000000000000000000000001B 00000000000000000000000000000000B 11111111111111111111000000000000B 11111000010010011110000010101010B 10000000000000101010101010101010B 11111111111111111111111111111111B (20000000H) (01234567H) (0003FFFFH) (00000001H) 00000000H) FFFFF000H) F849E0AAH) 8002AAAAH) (FFFFFFFFH) →2 →7 → 14 → 31 → 32 → 20 →5 →1 → 32 Table 15.3-1 Bit Locations and Return Values (decimal) Detected bit location Return value Detected bit location Return value Detected bit location Return value Detected bit location Return value 31 0 23 8 15 16 7 24 30 1 22 9 14 17 6 25 29 2 21 10 13 18 5 26 28 3 20 11 12 19 4 27 27 4 19 12 11 20 3 28 26 5 18 13 10 21 2 29 25 6 17 14 9 22 1 30 24 7 16 15 8 23 0 31 Not found 32 432 CHAPTER 15 BIT SEARCH MODULE ■ Save/Restore Processing If it is necessary to save and restore the internal state of the bit search module, such as when the bit search module is used in an interrupt handler, use the following procedure: 1. Read the detection data register and save its contents (save). 2. Use the bit search module. 3. Write the data saved in 1) to the 1 detection data register (restore). With the above operation, the value obtained when the detection result register is read the next time corresponds to the value written to the bit search module before 1). If the data register written to last is the 0 detection or change point detection register, the value is restored correctly with the above procedure. 433 CHAPTER 15 BIT SEARCH MODULE 434 APPENDIX This appendix consists of the following parts: I/O map, interrupt vector, pin states in the CPU state, notes on using a little endian area, and instruction lists. The appendix contains detailed information that could not be included in the main text and reference material for programming. APPENDIX A I/O MAP APPENDIX B INTERRUPT VECTOR APPENDIX C PIN STATE IN EACH CPU STATE APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA APPENDIX E INSTRUCTION LISTS 435 APPENDIX A I/O MAP APPENDIX A I/O MAP Table A-1 shows the correspondence between the memory space area and the peripheral resource registers. ■ I/O Map [Reading the table] address 000000H +0 PDR0[R/W] XXXXXXXX register +1 +2 +3 block PDR1[R/W] PDR2[R/W] PDR3[R/W] T-unit XXXXXXXX XXXXXXXX XXXXXXXX Port Data Register Read/write attribute Initial value of register after reset Register name (column 1 of the register is at address 4n, column 2 is at address 4n+2...) Leftmost register address (For word-length access, column 1 of the register becomes the MSB of the data) Note: The initial values of bits in a register are indicated as follows: 1: Initial value "1" 0: Initial value "0" X: Initial value "X" -: A physical register does not exist at the location. 436 APPENDIX A I/O MAP Table A-1 I/O Map (1/9) register address block +0 +1 +2 +3 000000H − − PDR2 [R/W] XXXXXXXX - 000004H − − PDR6 [R/W] XXXXXXXX PDR7 [R/W] -------X 000008H PDR8 [R/W] --X--XXX PDR9 [R/W] XXXXXXX- PDRA [R/W] XXXXXXXX PDRB [R/W] XXXXXXXX PDRI [R/W] ---XXXXX PDRJ [R/W] XXXXXXXX − 00000CH 000010H T-unit Port Data Register PDRG [R/W] -----XXX PDRH [R/W] XXX00XXX 000018H to 00001CH − 000020H to 00003CH − R-bus Port Data Register Reserved 000040H EIRR [R/W] 00000000 ENIR [R/W] 00000000 ELVR [R/W] 00000000 Ext int 000044H DICR [R/W] ------0 HRCL [R/W, R] 0--11111 − DLYI/I-unit TMRLR [W] XXXXXXXX XXXXXXXX TMR [R] XXXXXXXX XXXXXXXX 00004CH − TMCSR [R, R/W] ----0000 00000000 000050H TMRLR [W] XXXXXXXX XXXXXXXX TMR [R] XXXXXXXX XXXXXXXX 000054H − TMCSR [R, R/W] ----0000 00000000 000058H TMRLR [W] XXXXXXXX XXXXXXXX TMR [R] XXXXXXXX XXXXXXXX Reload Timer 2 00005CH − TMCSR [R, R/W] ----0000 00000000 − 000048H 000060H 000064H 000068H SSR [R/W, R] 00001-00 SIDR/SODR [R,W] XXXXXXXX UTIM [R] (UTIMR [W]) 00000000 00000000 SSR [R/W, R] 00001-00 SIDR/SODR [R,W] XXXXXXXX Reload Timer 0 Reload Timer 1 SCR [R/W] 00000100 SMR [R/W, W] 00--0-0- UART0 DRCL [W] -------- UTIMC [R/W] 0--00001 U-TIMER 0 SCR [R/W] 00000100 SMR [R/W, W] 00--0-0- UART1 437 APPENDIX A I/O MAP Table A-1 I/O Map (2/9) register address block +0 00006CH 000070H +1 UTIM [R] (UTIMR [W]) 00000000 00000000 SSR [R/W, R] 00001-00 SIDR/SODR [R,W] XXXXXXXX 000074H UTIM [R] (UTIMR [W]) 00000000 00000000 000078H ADCR [R] XXXXXXXX XXXXXXXX +2 +3 DRCL [W] -------- UTIMC [R/W] 0--00001 U-TIMER 1 SCR [R/W] 00000100 SMR [R/W, W] 00--0-0- UART2 DRCL [W] -------- UTIMC [R/W] 0--00001 U-TIMER 2 ADCS [R/W] 00000000 00000000 A/D Converter sequential comparison 00007CH − Reserved 000080H − Reserved 000084H − Reserved 000088H − Reserved 00008CH − Reserved 000090H − Reserved 000094H IBCR [W, R/W] 00000000 IBSR [R] 00000000 000098H ITMK [R, R/W] 00----11 11111111 00009CH − ITBA [R/W] ------00 00000000 IDAR [R/W] 00000000 ISMK [R/W] 01111111 ISBA [R/W] 0000000 ICCR [W, R/W] 0-011111 IDBL [R/W] -------0 I2C interface 0000A0H − Reserved 0000A4H − Reserved 0000A8H − Reserved 0000ACH − Reserved 0000B0H − Reserved 000200H DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000204H DMACB0 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000208H DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 00020CH DMACB1 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000210H DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 438 DMAC APPENDIX A I/O MAP Table A-1 I/O Map (3/9) register address block +0 +1 +2 +3 000214H DMACB2 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000218H DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 00021CH DMACB3 [R/W] 0000000 00000000 XXXXXXXX XXXXXXXX 000220H DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000224H DMACB4 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000228H − 00022CH to 00023CH − Reserved 000240H DMACR [R/W] 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX DMAC 000244H to 000274H − Reserved 000278H − Reserved 00027CH − Reserved 000280H to 0002FCH − Reserved 000300H − Reserved 000304H 000308H to 0003E0H 0003E4H 0003E8H to 0003ECH ISIZE [R/W] ------00 − − − Instruction Cache Reserved ICHCR [R/W] 0-000000 − DMAC Instruction Cache Reserved 439 APPENDIX A I/O MAP Table A-1 I/O Map (4/9) register address block +0 +1 +2 +3 0003F0H BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F4H BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8H BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FCH BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000400H DDRG [R/W] ----000 DDRH [R/W] 00011000 DDRI [R/W] --000000 000404H − 000408H − 00040CH − 000410H PFRG [R/W] ----0000 PFRH [R/W] 0000000− 000418H − 00041CH − 000420H to 00043CH − DDRJ [R/W] 00000000 R-bus Port Direction Register PFRI [R/W] --00-00- 000414H Bit Search Module − R-bus Port Function Register Reserved 000440H ICR00 [R, R/W] ---11111 ICR01 [R, R/W] ---11111 ICR02 [R, R/W] ---11111 ICR03 [R, R/W] ---11111 000444H ICR04 [R, R/W] ---11111 ICR05 [R, R/W] ---11111 ICR06 [R, R/W] ---11111 ICR07 [R, R/W] ---11111 000448H ICR08 [R, R/W] ---11111 ICR09 [R, R/W] ---11111 ICR10 [R, R/W] ---11111 ICR11 [R, R/W] ---11111 00044CH ICR12 [R, R/W] ---11111 ICR13 [R, R/W] ---11111 ICR14 [R, R/W] ---11111 ICR15 [R, R/W] ---11111 000450H ICR16 [R, R/W] ---11111 ICR17 [R, R/W] ---11111 ICR18 [R, R/W] ---11111 ICR19 [R, R/W] ---11111 000454H ICR20 [R, R/W] ---11111 ICR21[R, R/W] ---11111 ICR22 [R, R/W] ---11111 ICR23 [R, R/W] ---11111 000458H ICR24 [R, R/W] ---11111 ICR25 [R, R/W] ---11111 ICR26 [R, R/W] ---11111 ICR27 [R, R/W] ---11111 00045CH ICR28 [R, R/W] ---11111 ICR29 [R, R/W] ---11111 ICR30 [R, R/W] ---11111 ICR31 [R, R/W] ---11111 440 Interrupt Control unit APPENDIX A I/O MAP Table A-1 I/O Map (5/9) register address block +0 +1 +2 +3 000460H ICR32 [R, R/W] ---11111 ICR33 [R, R/W] ---11111 ICR34 [R, R/W] ---11111 ICR35 [R, R/W] ---11111 000464H ICR36 [R, R/W] ---11111 ICR37 [R, R/W] ---11111 ICR38 [R, R/W] ---11111 ICR39 [R, R/W] ---11111 000468H ICR40 [R, R/W] ---11111 ICR41 [R, R/W] ---11111 ICR42 [R, R/W] ---11111 ICR43 [R, R/W] ---11111 00046CH ICR44 [R, R/W] ---11111 ICR45 [R, R/W] ---11111 ICR46 [R, R/W] ---11111 ICR47 [R, R/W] ---11111 000470H to 00047CH − Interrupt Control unit 000480H RSRR [R/W] 10000000 (**) STCR [R/W] 00110011 (**) TBCR [R/W] 00XXXX00 (*) CTBR [W] XXXXXXXX 000484H CLKR [R/W] 00000000 (*) WPR [W] XXXXXXXX DIVR0 [R/W] 00000011 (*) DIVR1 [R/W] 00000000 (*) 000488H − 00048CH to 0005FCH − − − DDR2 [R/W] 00000000 − 000604H − − DDR6 [R/W] 00000000 DDR7 [R/W] -------0 000608H DDR8 [R/W] --0--000 DDR9 [R/W] 00000000 DDRA [R/W] 00000000 DDRB [R/W] 00000000 − 000610H − 000614H − − PFR6 [R/W] 11111111 PFR7 [R/W] -------1 000618H PFR8 [R/W] --1--0-- PFR9 [R/W] 0-001101 PFRA [R/W] 11111111 PFRB1 [R/W] 00000000 00061CH PFRB2 [R/W] 00------ 000620H − 000624H − 000628H to 00063FH − Clock Control unit Reserved 000600H 00060CH Interrupt Control unit T-unit Port Direction Register T-unit Port Function Register Reserved 441 APPENDIX A I/O MAP Table A-1 I/O Map (6/9) register address block +0 +1 +2 +3 000640H ASR0 [R/W] 00000000 00000000 (*) ACR0 [R/W] 1111XX00 00000000 (*) 000644H ASR1 [R/W] XXXXXXXX XXXXXXXX (*) ACR1 [R/W] XXXXXXXX XXXXXXXX (*) 000648H ASR2 [R/W] XXXXXXXX XXXXXXXX (*) ACR2 [R/W] XXXXXXXX XXXXXXXX (*) 00064CH ASR3 [R/W] XXXXXXXX XXXXXXXX (*) ACR3 [R/W] XXXXXXXX XXXXXXXX (*) 000650H ASR4 [R/W] XXXXXXXX XXXXXXXX (*) ACR4 [R/W] XXXXXXXX XXXXXXXX (*) 000654H ASR5 [R/W] XXXXXXXX XXXXXXXX (*) ACR5 [R/W] XXXXXXXX XXXXXXXX (*) 000658H ASR6 [R/W] XXXXXXXX XXXXXXXX (*) ACR6 [R/W] XXXXXXXX XXXXXXXX (*) 00065CH ASR7 [R/W] XXXXXXXX XXXXXXXX (*) ACR7 [R/W] XXXXXXXX XXXXXXXX (*) 000660H AWR0 [R/W] 011111111 11111111 (*) AWR1 [R/W] XXXXXXXX XXXXXXXX (*) 000660H AWR2 [R/W] XXXXXXXX XXXXXXXX (*) AWR3 [R/W] XXXXXXXX XXXXXXXX (*) 000668H AWR4 [R/W] XXXXXXXX XXXXXXXX (*) AWR5 [R/W] XXXXXXXX XXXXXXXX (*) 00066CH AWR6 [R/W] XXXXXXXX XXXXXXXX (*) AWR7 [R/W] XXXXXXXX XXXXXXXX (*) 000670H − 000674H − 000678H IOWR0 [R/W] XXXXXXXX IOWR1 [R/W] XXXXXXXX CSER [R/W] 000000001 CHER [R/W] 11111111 000684H − 000684H to 0007F8H − 0007FCH 442 T-unit IOWR2 [R/W] XXXXXXXX − − TCR [R/W] 00000000 − 00067CH 000680H T-unit − MODR [R/W] XXXXXXXX Reserved − − − APPENDIX A I/O MAP Table A-1 I/O Map (7/9) register address block +0 +1 000800H to 000AFCH +2 +3 − Reserved 000B00H ESTS0 [R/W] X0000000 ESTS1 [R/W] XXXXXXXX ESTS2 [R] 1XXXXXXX − 000B04H ECTL0 [R/W] 0X000000 ECTL1 [R/W] 00000000 ECTL2 [W] 000X0000 ECTL3 [R/W] 00X00X11 000B08H ECNT0 [W] XXXXXXXX ECNT1 [W] XXXXXXXX EUSA [W] XXX00000 EDTC [W] 0000XXXX 000B0CH EWPT [R] 00000000 00000000 − 000B10H EDTR0 [W] XXXXXXXX XXXXXXXX EDTR1 [W] XXXXXXXX XXXXXXXX 000B14H to 000B1CH − 000B20H EIA0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B24H EIA1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B28H EIA2 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B2CH EIA3 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B30H EIA4 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B34H EIA5 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B38H EIA6 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B3CH EIA7 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B40H EDTA [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B44H EDTM [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B48H EOA0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DSU DSU 443 APPENDIX A I/O MAP Table A-1 I/O Map (8/9) register address block +0 +1 +2 +3 000B4CH EOA1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B50H EPCR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B54H EPSR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B58H EIAM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B5CH EIAM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX − 000B60H EOAM0/EODM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX − 000B64H EOAM1/EODM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX − 000B68H EOD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX − 000B6CH EOD1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX − 000B70H to 000FFCH − Reserved 001000H DMASA0 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 001004H DMADA0 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 001008H DMASA1 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 00100CH DMADA1 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 001010H DMASA2 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 001014H DMADA2 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 001018H DMASA3 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 00101CH DMADA3 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 001020H DMASA4 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 444 DSU DMAC DMAC APPENDIX A I/O MAP Table A-1 I/O Map (9/9) register address block +0 001024H +1 +2 DMADA4 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX +3 DMAC *1: Do not execute any RMW instructions for a register that has a write-dedicated bit. *2: If not otherwise specified, do not perform write access to a block indicated Reserved or to a read-only register. *3: Data in an area marked Reserved or (-) is undefined. *4: RMW system instruction (RMW: Read modify write) AND : Rj, @Ri OR : Rj, @Ri EOR : Rj, @Ri ANDH : Rj, @Ri OR : HRj, @Ri EORH : Rj, @Ri ANDB : Rj, @Ri ORB : Rj, @Ri EORB : Rj, @Ri BANDL : #u4, @Ri BORL : #u4, @Ri BEORL : #u4, @Ri BANDH : #u4, @Ri BORH : #u4, @Ri BEORH : #u4, @Ri 445 APPENDIX B INTERRUPT VECTOR APPENDIX B INTERRUPT VECTOR Table B-1 shows the interrupt vector table, which gives the interrupt source and interrupt vector/interrupt control register allocations for the MB91307 series. ■ Interrupt Vectors Table B-1 Interrupt Vectors (1/4) Interrupt number Decimal Hexadecimal Interrupt level Reset 0 00 − 3FCH 000FFFFCH Mode vector 1 01 − 3F8H 000FFFF8H Reserved for system 2 02 − 3F4H 000FFFF4H Reserved for system 3 03 − 3F0H 000FFFF0H Reserved for system 4 04 − 3ECH 000FFFECH Reserved for system 5 05 − 3E8H 000FFFE8H Reserved for system 6 06 − 3E4H 000FFFE4H No-coprocessor trap 7 07 − 3E0H 000FFFE0H Coprocessor error trap 8 08 − 3DCH 000FFFDCH INTE instruction 9 09 − 3D8H 000FFFD8H Instruction break exception 10 0A − 3D4H 000FFFD4H Operand break trap 11 0B − 3D0H 000FFFD0H Step trace trap 12 0C − 3CCH 000FFFCCH NMI request (tool) 13 0D − 3C8H 000FFFC8H Undefined instruction exception 14 0E − 3C4H 000FFFC4H NMI request 15 0F 15(FH), fixed 3C0H 000FFFC0H External Interrupt 0 16 10 ICR00 3BCH 000FFFBCH External Interrupt 1 17 11 ICR01 3B8H 000FFFB8H External Interrupt 2 18 12 ICR02 3B4H 000FFFB4H External Interrupt 3 19 13 ICR03 3B0H 000FFFB0H External Interrupt 4 20 14 ICR04 3ACH 000FFFACH External Interrupt 5 21 15 ICR05 3A8H 000FFFA8H Interrupt source 446 Offset TBR default address APPENDIX B INTERRUPT VECTOR Table B-1 Interrupt Vectors (2/4) Interrupt number Decimal Hexadecimal Interrupt level External Interrupt 6 22 16 ICR06 3A4H 000FFFA4H External Interrupt 7 23 17 ICR07 3A0H 000FFFA0H Reload Timer 0 24 18 ICR08 39CH 000FFF9CH Reload Timer 1 25 19 ICR09 398H 000FFF98H Reload Timer 2 26 1A ICR10 394H 000FFF94H UART0 (reception completed) 27 1B ICR11 390H 000FFF90H UART1 (reception completed) 28 1C ICR12 38CH 000FFF8CH UART2 (reception completed) 29 1D ICR13 388H 000FFF88H UART0 (transmission completed) 30 1E ICR14 384H 000FFF84H UART1 (transmission completed) 31 1F ICR15 380H 000FFF80H UART2 (transmission completed) 32 20 ICR16 37CH 000FFF7CH DMAC0 (end, error) 33 21 ICR17 378H 000FFF78H DMAC1 (end, error) 34 22 ICR18 374H 000FFF74H DMAC2 (end, error) 35 23 ICR19 370H 000FFF70H DMAC3 (end, error) 36 24 ICR20 36CH 000FFF6CH DMAC4 (end, error) 37 25 ICR21 368H 000FFF68H A/D 38 26 ICR22 364H 000FFF64H I2C 39 27 ICR23 360H 000FFF60H Reserved for system 40 28 ICR24 35CH 000FFF5CH Reserved for system 41 29 ICR25 358H 000FFF58H Reserved for system 42 2A ICR26 354H 000FFF54H Reserved for system 43 2B ICR27 350H 000FFF50H U-TIMER0 44 2C ICR28 34CH 000FFF4CH U-TIMER1 45 2D ICR29 348H 000FFF48H U-TIMER2 46 2E ICR30 344H 000FFF44H Time base timer overflow 47 2F ICR31 340H 000FFF40H Reserved for system 48 30 ICR32 33CH 000FFF3CH Reserved for system 49 31 ICR33 338H 000FFF38H Reserved for system 50 32 ICR34 334H 000FFF34H Interrupt source Offset TBR default address 447 APPENDIX B INTERRUPT VECTOR Table B-1 Interrupt Vectors (3/4) Interrupt number Decimal Hexadecimal Interrupt level Reserved for system 51 33 ICR35 330H 000FFF30H Reserved for system 52 34 ICR36 32CH 000FFF2CH Reserved for system 53 35 ICR37 328H 000FFF28H Reserved for system 54 36 ICR38 324H 000FFF24H Reserved for system 55 37 ICR39 320H 000FFF20H Reserved for system 56 38 ICR40 31CH 000FFF1CH Reserved for system 57 39 ICR41 318H 000FFF18H Reserved for system 58 3A ICR42 314H 000FFF14H Reserved for system 59 3B ICR43 310H 000FFF10H Reserved for system 60 3C ICR44 30CH 000FFF0CH Reserved for system 61 3D ICR45 308H 000FFF08H Reserved for system 62 3E ICR46 304H 000FFF04H Delayed interrupt source bit 63 3F ICR47 300H 000FFF00H Reserved for system (used by REALOS) 64 40 − 2FCH 000FFEFCH Reserved for system (used by REALOS) 65 41 − 2F8H 000FFEF8H Reserved for system 66 42 − 2F4H 000FFEF4H Reserved for system 67 43 − 2F0H 000FFEF0H Reserved for system 68 44 − 2ECH 000FFEECH Reserved for system 69 45 − 2E8H 000FFEE8H Reserved for system 70 46 − 2E4H 000FFEE4H Reserved for system 71 47 − 2E0H 000FFEE0H Reserved for system 72 48 − 2DCH 000FFEDCH Reserved for system 73 49 − 2D8H 000FFED8H Reserved for system 74 4A − 2D4H 000FFED4H Reserved for system 75 4B − 2D0H 000FFED0H Reserved for system 76 4C − 2CCH 000FFECCH Reserved for system 77 4D − 2C8H 000FFEC8H Reserved for system 78 4E − 2C4H 000FFEC4H Reserved for system 79 4F − 2C0H 000FFEC0H Interrupt source 448 Offset TBR default address APPENDIX B INTERRUPT VECTOR Table B-1 Interrupt Vectors (4/4) Interrupt number Interrupt source Decimal Hexadecimal 80 to 255 50 to FF Used in INT instruction Interrupt level Offset TBR default address − 2BCH to 000H 000FFEBCH to 000FFC00H Notes: • The ICR is a register set in the interrupt controller that sets the interrupt level for each interrupt request. The ICR is provided to support each interrupt request. • The TBR is a register that indicates the first address of the EIT vector table. • The vector address can be obtained by adding the offset value defined for each TBR and EIT source to the address. • REALOS/FR uses the 0x40 and 0x41 interrupts for system code. Reference: The 1 KB area from the address indicated by the TBR is the vector area for EIT. The size of each vector is 4 bytes and the relation between the vector number and vector address can be represented as follows: vctadr = TBR + vctofs =TBR + (3FCH-4 × vct) vctadr: Vector address vctofs: Vector offset vct: Vector number 449 APPENDIX C PIN STATE IN EACH CPU STATE APPENDIX C PIN STATE IN EACH CPU STATE Table C-1 to Table C-2 the pin states in each CPU state. ■ Meaning of Terms in the Pin State Table Terms related to the pin state have the following meanings: • Input ready Means that the input function can be used. • Input 0 fixed Means that external input is cut off at the input gate following the pin and "0" is sent inside. • Output Hi-Z Means that the pin drive transistor is disabled and the pin is set to high impedance. • Output retained Means that the state output just before a mode is entered is output as is. That is, if any built-in peripheral with output is active, the output is determined by the built-in peripheral. For output as a port, the output is retained. • Preceding state retained Means that the state output just before a mode is entered is output as is. Also means input ready if the state is the input state. 450 APPENDIX C PIN STATE IN EACH CPU STATE ■ Pin State Table Table C-1 Pin States in External Bus 16-Bit Mode (1/3) When stopped Pin name Function Sleep mode HIZ=0 P20 to P27 D16 to D23 − D24 to D31 − A0 to A7 − A8 to A15 P60 to P67 A16 to A23 P70 A24 P85 WR1/ULB − WR0/UUB − RD P82 BRQ P: Preceding state retained F: BRQ input P81 BGRNT P: Preceding state retained F: H output P80 RDY P: Preceding state retained F: RDY input Output retained or Hi-Z Output retained or Hi-Z Address output retained Address output retained P: Preceding state retained F: Address output P: Preceding state retained F: Address output P: Preceding state retained F: H output Preceding state retained for both P and F Preceding state retained Preceding state retained − CS0 PA1 to PA7 CS1 to CS7 P: Preceding state retained F: CS output P90 SYSCLK P: Preceding state retained F: SYSCLK output P91 − P: Preceding state retained P92 MCLK P: Preceding state retained F: MCLK output P93 − Preceding state retained P94 LBA AS P: Preceding state retained F: LBA/AS output HIZ=1 Open bus (BGRNT) When initialized (INIT) Hardware standby Remarks Output Hi-Z/ input ready Mode vector address output *2 Output Hi-Z H output Preceding state retained Output Hi-Z/ Input 0 fixed Preceding state retained for both P and F BRQ input L output Output Hi-Z/ input ready Output Hi-Z/ Input 0 fixed P: Preceding state retained F: RDY input Preceding state retained H output Output Hi-Z CLK output *3 Output Hi-Z/ input ready Preceding state retained for both P and F CLK output *3 P: Preceding state retained Output Hi-Z/ input ready Output Hi-Z 451 APPENDIX C PIN STATE IN EACH CPU STATE Table C-1 Pin States in External Bus 16-Bit Mode (2/3) When stopped Pin name Function Sleep mode HIZ=0 452 P95 BAA P96 − P97 WE PB0 DREQ0 PB1 DACK0 PB2 DEOP0/ DSTP0 PB3 DREQ1 PB4 DACK1 PB5 DEOP1/ DSTP1 PB6 IOWR PB7 IORD PG0 DREQ2 PG1 DACK2 PH0 SI2 PH1 SO2 PH2 SC2 PH3 TOT0 PH4 TOT1 PH5 TOT2 PH6 SDA PH7 SCL PI0 SI0 PI1 SO0 PI2 SC0 PI3 SI1 PI4 SO1 PI5 SC1 PJ0 INT0 PJ1 INT1 PJ2 INT2 PJ3 INT3 HIZ=1 P: Preceding state retained F: BAA output Preceding state retained Open bus (BGRNT) When initialized (INIT) Output Hi-Z P: Preceding state retained Preceding state retained for both P and F Output Hi-Z Output Hi-Z/ input 0 fixed Output Hi-Z/ input 0 fixed Output Hi-Z/ input ready Preceding state retained Hardware standby Preceding state retained Preceding state retained Preceding state/input ready *1 Output Hi-Z/ input ready *1 Remarks APPENDIX C PIN STATE IN EACH CPU STATE Table C-1 Pin States in External Bus 16-Bit Mode (3/3) When stopped Pin name Function Sleep mode HIZ=0 PJ4 INT4/TIN0 PJ5 INT5/TIN1 PJ6 INT6/TIN2 PJ7 INT7/ATG Preceding state retained Preceding state/input ready *1 HIZ=1 Output Hi-Z/ input ready *1 Open bus (BGRNT) Preceding state retained When initialized (INIT) Hardware standby Output Hi-Z/ input ready Output Hi-Z/ input ready Remarks *1: The input is ready when the output is in the Hi-Z state. This pin is used for returning from the stop state. *2: The output immediately after power-on is undefined. *3: The output is at the L level while the L level is input at INIT pin. Note: P indicates that general-purpose port is selected. F indicates that the specified function is selected. 453 APPENDIX C PIN STATE IN EACH CPU STATE Table C-2 Pin States in External Bus 8-Bit Mode (1/3) When stopped Pin name Function Sleep mode HIZ=0 P20 to P27 D16 to D23 Preceding state retained D24 to D31 − A0 to A7 − A8 to A15 P60 to P67 A16 to A23 P70 A24 P85 WR1/ULB − WR0/UUB − RD P82 BRQ P: Preceding state retained F: BRQ input P81 BGRNT P: Preceding state retained F: H output P80 RDY P: Preceding state retained F: RDY input − CS0 Preceding state retained PA1 to PA7 CS1 to CS7 P: Preceding state retained F: CS output P90 SYSCLK P: Preceding state retained F: SYSCLK output P91 − P: Preceding state retained P92 MCLK P: Preceding state retained F: MCLK output P93 − Preceding state retained 454 LBA AS Preceding state retained Preceding state retained Output retained or Hi-Z − P94 HIZ=1 Open bus (BGRNT) Address output retained Address output retained P: Preceding state retained F: Address output P: Preceding state retained F: Address output P: Preceding state retained F: H output Preceding state retained for both P and F Preceding state retained P: Preceding state retained F: LBA/AS output When initialized (INIT) Hardware standby Output Hi-Z/ input ready H output Output *2 Output Hi-Z H output Preceding state retained BRQ input Preceding state retained for both P and F Output Hi-Z/ input 0 fixed L output Output Hi-Z/ input ready P: Preceding state retained F: RDY input Preceding state retained H output Output Hi-Z CLK output *3 Output Hi-Z/ input ready Preceding state retained for both P and F CLK output *3 P: Preceding state retained F: RDY input Output Hi-Z/ input ready Output Hi-Z Output Hi-Z/ input 0 fixed Remarks APPENDIX C PIN STATE IN EACH CPU STATE Table C-2 Pin States in External Bus 8-Bit Mode (2/3) When stopped Pin name Function Sleep mode HIZ=0 P95 BAA P96 − P97 WE PB0 DREQ0 PB1 DACK0 PB2 DEOP0/ DSTP0 PB3 DREQ1 PB4 DACK1 PB5 DEOP1/ DSTP1 PB6 IOWR PB7 IORD PG0 DREQ2 PG1 DACK2 PH0 SI2 PH1 SO2 PH2 SC2 PH3 TOT0 PH4 TOT1 PH5 TOT2 PH6 SDA PH7 SCL PI0 SI0 PI1 SO0 PI2 SC0 PI3 SI1 PI4 SO1 PI5 SC1 HIZ=1 P: Preceding state retained F: BAA output Preceding state retained Open bus (BGRNT) When initialized (INIT) Hardware standby Remarks Output Hi-Z Preceding state retained for both P and F P: Preceding state retained F: RDY input P: Preceding state retained F: WE output Output Hi-Z Output Hi-Z/ input 0 fixed Output Hi-Z/ input 0 fixed Output Hi-Z/ input ready Preceding state retained Preceding state retained Preceding state retained Output Hi-Z/ input ready 455 APPENDIX C PIN STATE IN EACH CPU STATE Table C-2 Pin States in External Bus 8-Bit Mode (3/3) When stopped Pin name Function Sleep mode HIZ=0 PJ0 INT0 PJ1 INT1 PJ2 INT2 PJ3 INT3 PJ4 INT4/TIN0 PJ5 INT5/TIN1 PJ6 INT6/TIN2 PJ7 INT7/ATG Preceding state retained Preceding state/input ready *1 HIZ=1 Output Hi-Z/ input ready *1 Open bus (BGRNT) When initialized (INIT) Hardware standby Preceding state retained Output Hi-Z/ input ready Output Hi-Z/ input ready Remarks *1: The input is ready when the output is in the Hi-Z state. This pin is used for returning from the stop state. *2: The output immediately after power-on is undefined. *3: The output is at the L level while the L level is input at INIT pin. Note: P indicates that general-purpose port is selected. F indicates that the specified function is selected. 456 APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA This section provides notes on the use of a little endian area classified with the following items: These items are not supported by the MB91307 series. D.1 C Compiler (fcc911) D.2 Assembler (fasm911) D.3 Linker (flnk911) D.4 Debugger (sim911, eml911, mon911) 457 APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA D.1 C Compiler (fcc911) Note that when programming is done in the C language, behavior cannot be guaranteed if the following operations are performed for a little endian area: • Allocation of a variable with an initial value • Structure assignment • Operations other than character string arrangement using a character string manipulation function • Specification of the -K lib option when a character string manipulation function is used • Use of the double type or long double type • Allocation of a stack to a little endian area ■ Allocation of a Variable with an Initial Value Allocation of a variable with an initial value to a little endian area is not allowed. No compiler has a function that generates the initial value of a little endian area. Although it is possible to allocate a variable to a little endian area, an initial value cannot be set. Include processing at the beginning of a program that sets an initial value. [Example] Setting an initial value for the variable little_data in a little endian area extern int little_data; void little_init(void){ little_data = Initial value; } void main(void) little_init(); ... } ■ Structure Assignment When a structure is assigned to another structure, the compiler selects the optimal transfer method (byte, halfword, or word). Thus, if structure assignment is performed between a structure variable allocated to an ordinary area and a structure variable allocated to a little endian area, a correct result cannot be obtained. It is therefore necessary to assign each member in the structure. 458 APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA [Example] Assigning a structure to the structure variable little_st in a little endian area struct tag { char c; int i; } normal_st; extern struct tag little_st; #define STRMOVE(DEST,SRC) DEST.c=SRC.c;DEST.i=SRC.i; void main(void) { STRMOVE(little_st,normal_st); } Since the allocation of the members of a structure is different from compiler to compiler, the allocation of members by one compiler will be different from the allocation by another compiler. If the allocation method is different, it is not possible to obtain the correct result even the method described above is used. If the allocation of members of a structure varies, do not allocate any structure variable to a little endian area. ■ Operations Other Than the String Arrangement Using a String Manipulation Function Since character string manipulation functions provided as a standard library perform their processing in bytes, correct results cannot be obtained if processing using a character string manipulation function is performed in an area with a type other than the char type, unsigned char type, or signed char type allocated within a little endian area. Do not perform processing such as that described above. [Example of incorrect coding] Transfer of word data using memcpy int big = 0x01020304; /* Big endian area */ extern int little; /* Little endian area */ memcpy(&little,&big,4); /* Transfer using memcpy */ The result of the above code is shown below, and, as the result of transferring word data, is an error. 01 (Big endian area) 02 03 04 → memcpy 01 (Correct result) 04 (Little endian area) 02 03 03 02 04 01 459 APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA ■ Specification of the -K lib Option When Using a String Manipulation Function If the -K lib option is specified, the compiler performs inline expansion for some of the string manipulation functions. At this point, processing may be changed to processing using halfwords or words as a way to select the optimal processing. If processing is changed in this manner, processing on a little endian area will not be performed correctly. Do not specify the -K lib option when performing processing for a little endian area that uses a string manipulation function. Also, do not specify the -O4 option and -K speed option, each of which includes the -K lib option. ■ Use of the Double Type or Long Double Type Access to double type or long double type data is performed by accessing one high-order word or one low-order word. Thus, when a double type or long double type variable allocated to a little endian area is accessed, correct results cannot be obtained. The assignment of variables of the same type allocated to a little endian area can be done, but as a result of optimization, the assignment of variables may be replaced by the assignment of constants. Do not allocate double type and long double type variables to a little endian area. [Example of incorrect coding] Transfer of data of the double type double big = 1.0; /* Big endian area */ extern int little; /* Little endian area */ little = big;; /* Transfer of double type data */ The result of the above code is shown below, and as the result of transferring double type data, is an error. 3f f0 (Big endian area) 00 00 00 00 00 00 → (Correct result) 00 00 (Little endian area) f0 3f 00 00 00 00 00 00 00 f0 3f 00 00 00 ■ Allocation of a Stack to a Little Endian Area If some of the stacks are allocated to a little endian area, behavior cannot be guaranteed. 460 APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA D.2 Assembler (fasm911) The following items regarding little endian areas need to be noted when the FR series assembly language is used for programming: • Section • Data access ■ Section A little endian area is primarily intended to be used for data exchange with CPUs with little endian lines. Consequently, define a little endian area as a data section without an initial value. If a code, stack, or data section with an initial value is specified in a little endian area, the MB91307 series access operation cannot be guaranteed. [Example] /* Section definition of a correct little endian area */ .SECTION Little_Area, DATA, ALIGN=4 Little_Word: .RES.W 1 Little_Half: .RES.H 1 Little_Byte: .RES.B 1 461 APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA ■ Data Access When data in a little endian area is accessed, the data values can be coded without awareness of the endian method used. However, access to data in a little endian area must be performed using the same size as the data size. [Example] LDI LDI #0x01020304, r0 #Little_Word, r1 LDI LDI #0x0102, r2 #Little_Half, r3 LDI LDI #0x01, r4 #Little_Byte, r5 /* Access 32-bit data using the ST instruction (or the LD instruction). */ ST r0, @r1 /* Access 16-bit data using the STH instruction (or the LDH instruction). */ STH r2, @r3 /* Access 8-bit data using the STB instruction (or the LDB instruction). */ STB r4, @r5 If data is accessed with the MB91307 series using a size that is different from the data size, the data values cannot be guaranteed. For example, if two consecutive 16-bit data items are accessed using a 32-bit access instruction, the data value cannot be guaranteed. 462 APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA D.3 Linker (flnk911) The following items related to section allocation for linking need to be noted when a program that uses a little endian area is used: • Restriction on section types • Lack of error detection ■ Restriction on Section Types Only data sections without an initial value can be allocated to a little endian area. If a data section, stack section, or code section with an initial value is allocated to a little endian area, program operation cannot be guaranteed because arithmetic processing, such as an address resolution, is performed internally by the linker using the big endian method. ■ Lack of Error Detection Since the linker does not recognize little endian areas, the linker does not issue an error message if allocation violating the above restriction is performed. Use the linker only after carefully studying the sections that will be allocated to little endian areas. 463 APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA D.4 Debugger (sim911, eml911, mon911) This section provides notes on using a simulator debugger or emulator debugger/ monitor debugger. ■ Simulator Debugger There is no memory space specification command that can indicate a little endian area. As a result, memory management commands and instructions executed to manage memory are handled as if they were big endian. ■ Emulator Debugger/Monitor Debugger Note that, if a little endian area is accessed using the following commands, the data values are not handled as normal values: ❍ The set memory, show memory, enter, examine, and set watch commands When floating-point (single or double) data is processed, the specified value is neither set nor displayed. ❍ The search memory command When halfword or word data is searched, the specified value is not used in the search. ❍ Line assembly and disassembly (including the disassembly display in the source window) Normal instruction codes can neither be set nor displayed. Do not allocate any instruction codes to a little endian area. ❍ The call and show call commands If a stack area is placed in a little endian area, normal operation cannot be expected. Do not allocate a stack area to a little endian area. 464 APPENDIX E INSTRUCTION LISTS APPENDIX E INSTRUCTION LISTS This section provides lists of the FR family instructions. E.1 How to Read the Instruction Lists E.2 FR Family Instruction Lists 465 APPENDIX E INSTRUCTION LISTS E.1 How to Read the Instruction Lists Before the lists are presented, the following items are explained to make the lists easier to understand: • How to read the instruction lists • Addressing mode symbols • Instruction format ■ How to Read the Instruction Lists Mnemonic Type OP CYCLE NZVC Operation Remarks - ADD *ADD Rj, Rj #s5, Rj , , A C , , AG A4 , , 1 1 , , CCCC CCCC , , Ri + Rj → Rj Ri + s5 → Ri , , 1. 2. 3. 4. 5. 6. 7. 1. Instruction name. • An asterisk (*) indicates an extended instruction that is not contained in the CPU specifications and is obtained by extension of or addition to the assembler. 2. Symbols indicating addressing modes that can be specified for the operand. • For the meaning of symbols, see "■Addressing Mode Symbols". 3. Instruction format. 4. Instruction code in hexadecimal notation. 5. Number of machine cycles. • a: Memory access cycle that may be extended by the Ready function. • b: Memory access cycle that may be extended by the Ready function. However, the cycle is interlocked if a direct instruction references a register intended for an LD operation, increasing the number of execution cycles by 1. • c: Interlocked if the direct instruction is an instruction that reads or writes to R15, SSP, or USP, or an instruction in instruction format A. The number of execution cycles increases by 1 or 2. • d: Interlocked if the direct instruction references MDH/MDL. The number of execution cycles increases to 2. • The minimum for a, b, c, and d is 1 cycle. 6. Indicates a flag change. • Flag change C: Change -: No change 0: Clear 1: Set • Flag meaning N: Negative flag Z: Zero flag V: Overflow flag C: Carry flag 7. Instruction operation. 466 APPENDIX E INSTRUCTION LISTS ■ Addressing Mode Symbols Table E.1-1 Explanation of Addressing Mode Symbols (1/2) Symbol Meaning Ri Register direct (R0 to R15, AC, FP, SP) Rj Register direct (R0 to R15, AC, FP, SP) R13 Register direct (R13, AC) Ps Register direct (program status register) Rs Register direct (TBR, RP, SSP, USP, MDH, MDL) CRi Register direct (CR0 to CR15) CRj Register direct (CR0 to CR15) #i8 Unsigned 8-bit immediate (-128 to 255) Note: -128 to -1 is handled as 128 to 255. #i20 Unsigned 20-bit immediate (-0X80000b to 0XFFFFF) Note: -0X7FFFF to -1 is handled as 0X7FFFF to 0XFFFFF. #i32 Unsigned 32-bit immediate (-0X80000000 to 0XFFFFFFFF) Note: -0X80000000 to -1 is handled as 0X80000000 to 0XFFFFFFFF. #s5 Signed 5-bit immediate (-16 to 15) #s10 Signed 10-bit immediate (-512 to 508, multiples of 4 only) #u4 Unsigned 4-bit immediate (0 to 15) #u5 Unsigned 5-bit immediate (0 to 31) #u8 Unsigned 8-bit immediate (0 to 255) #u10 Unsigned 10-bit immediate (0 to 1020, multiples of 4 only) @dir8 Unsigned 8-bit direct address (0 to 0XFF) @dir9 Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only) @dir10 Unsigned 10-bit direct address (0 to 0X3FC, multiples of 4 only) label9 Signed 9-bit branch address (-0X100 to 0XFC, multiples of 2 only) label12 Signed 12-bit branch address (-0X800 to 0X7FC, multiples of 2 only) label20 Signed 20-bit branch address (-0X80000 to 0X7FFFF) label32 Signed 32-bit branch address (-0X80000000 to 0X7FFFFFFF) @Ri Register indirect (R0 to R15, AC, FP, SP) @Rj Register indirect (R0 to R15, AC, FP, SP) @(R13,Rj) Register relative indirect (Rj: R0 to R15, AC, FP, SP) @(R14,disp10) Register relative indirect (disp10: -0X200 to 0X1FC, multiples of 4 only) @(R14,disp9) Register relative indirect (disp9: -0X100 to 0XFE multiples of 2 only) 467 APPENDIX E INSTRUCTION LISTS Table E.1-1 Explanation of Addressing Mode Symbols (2/2) Symbol Meaning @(R14,disp8) Register relative indirect (disp8: -0X80 to 0X7F) @(R15,udisp6) Register relative indirect (udisp6: 0 to 60, multiples of 4 only) @Ri+ Register indirect with post-increment (R0 to R15, AC, FP, SP) @R13+ Register indirect with post-increment (R13, AC) @SP+ Stack pop @-SP Stack push (reglist) Register list 468 APPENDIX E INSTRUCTION LISTS ■ Instruction Format Table E.1-2 Instruction Format Type Instruction format MSB LSB 16 bit A B OP Rj Ri 8 4 4 OP i8/o8 Ri 4 8 4 C OP u4/m4 Ri 8 4 4 ADD, ADDN, CMP, LSL, LSR, ASR C’ D OP s5/u5 Ri 7 5 4 OP u8/rel8/dir/ reglist 8 8 E F OP SUB-OP Ri 8 4 4 OP rel11 5 11 469 APPENDIX E INSTRUCTION LISTS E.2 FR Family Instruction Lists The FR family instruction lists are presented in the order listed below. ■ FR Family Instruction Lists Table E.2-1 Add-Subtract Instructions Table E.2-2 Compare Instructions Table E.2-3 Logic Instructions Table E.2-4 Bit Manipulation Instructions Table E.2-5 Multiply Instructions Table E.2-6 Shift Instructions Table E.2-7 Immediate Set/16-bit/32-bit Immediate Transfer Instructions Table E.2-8 Memory Load Instructions Table E.2-9 Memory Store Instructions Table E.2-10 Register-to-Register Transfer Instructions Table E.2-11 Normal Branch (No Delay) Instructions Table E.2-12 Delayed Branch Instructions Table E.2-13 Other Instructions Table E.2-14 20-Bit Normal Branch Macro Instructions Table E.2-15 20-Bit Delayed Branch Macro Instructions Table E.2-16 32-Bit Normal Branch Macro Instructions Table E.2-17 32-Bit Delayed Branch Macro Instructions Table E.2-18 Direct Addressing Instructions Table E.2-19 Resource Instructions Table E.2-20 Coprocessor Control Instructions 470 APPENDIX E INSTRUCTION LISTS ■ Add-Subtract Instructions Table E.2-1 Add-Subtract Instructions Mnemonic Type OP CYCLE NZVC Rj, Ri A A6 1 CCCC Ri + Rj → Ri *ADD #s5, Ri C’ A4 1 CCCC Ri + s5 → Ri The assembler treats the highest-order bit as the sign. ADD C A4 1 CCCC Ri + extu(i4) → Ri Zero extension ADD2 #u4, Ris C A5 1 CCCC Ri + extu(i4) → Ri Minus extension ADDC Rj, Ri A A7 1 CCCC Ri + Rj + c → Ri Addition with carry ADDN Rj, Ri A A2 1 ---- Ri + Rj → Ri *ADDN #s5, Ri C’ A0 1 ---- Ri + s5 → Ri The assembler treats the highest-order bit as the sign. ADDN #u4, Ri C A0 1 ---- Ri + extu(i4) → Ri Zero extension ADDN2 #u4, Ri C A1 1 ---- Ri + extu(i4) → Ri Minus extension SUB Rj, Ri A AC 1 CCCC Ri - Rj → Ri SUBC Rj, Ri A AD 1 CCCC Ri - Rj - c → Ri SUBN Rj, Ri A AE 1 ---- ADD #u4, Ri Operation Remarks Addition with carry Ri - Rj → Ri ■ Compare Instructions Table E.2-2 Compare Instructions Mnemonic Type OP CYCLE NZVC Rj, Ri A AA 1 CCCC Ri + Rj *CMP #s5, Ri C’ A8 1 CCCC Ri + s5 The assembler treats the highest-order bit as the sign. CMP #u4, Ri C A8 1 CCCC Ri + extu(i4) Zero extension CMP2 #u4, Ri C A9 1 CCCC Ri + extu(i4) Minus extension CMP Operation Remarks 471 APPENDIX E INSTRUCTION LISTS ■ Logic Instructions Table E.2-3 Logic Instructions Mnemonic Type OP CYCLE NZVC Operation Remarks AND Rj, Ri A 82 1 CC-- Ri &= Rj Word AND Rj, @Ri A 84 1+2a CC-- (Ri) &= Rj Word ANDH Rj, @Ri A 85 1+2a CC-- (Ri) &= Rj Halfword ANDB Rj, @Ri A 86 1+2a CC-- (Ri) &= Rj Byte OR Rj, Ri A 92 1 CC-- Ri | = Rj Word OR Rj, @Ri A 94 1+2a CC-- (Ri) | = Rj Word ORH Rj, @Ri A 95 1+2a CC-- (Ri) | = Rj Halfword ORB Rj, @Ri A 96 1+2a CC-- (Ri) | = Rj Byte EOR Rj, Ri A 9A 1 CC-- Ri ^ = Rj Word EOR Rj, @Ri A 9C 1+2a CC-- (Ri) ^ = Rj Word EORH Rj, @Ri A 9D 1+2a CC-- (Ri) ^ = Rj Halfword EORB Rj, @Ri A 9E 1+2a CC-- (Ri) ^ = Rj Byte 472 APPENDIX E INSTRUCTION LISTS ■ Bit Manipulation Instructions Table E.2-4 Bit Manipulation Instructions Mnemonic Type OP CYCLE NZVC #u4, @Ri C 80 1+2a ---- (Ri)&=(0xF0+u4) Low-order 4 bits are manipulated. BANDH #u4, @Ri C 81 1+2a ---- (Ri)&=((u4<<4)+0x0F) High-order 4 bits are manipulated. ---- (Ri)&=u8 BANDL Operation Remarks *BAND #u8, @Ri*1 BORL #u4, @Ri C 90 1+2a ---- (Ri) | = u4 Low-order 4 bits are manipulated. BORLH #u4, @Ri C 91 1+2a ---- (Ri) | = (u4<<4) High-order 4 bits are manipulated. ---- (Ri) | = u8 *BOR #u8, @Ri*2 BEORL #u4, @Ri C 98 1+2a ---- (Ri) ^ = u4 Low-order 4 bits are manipulated. BEORH #u4, @Ri C 99 1+2a ---- (Ri) ^ = (u4<<4) High-order 4 bits are manipulated. ---- (Ri) ^ = u8 *BEOR #u8, @Ri*3 BTSTL #u4, @Ri C 88 2+a 0C-- (Ri) & u4 Low-order 4 bits are manipulated. BTSTH #u4, @Ri C 89 2+a CC-- (Ri) & (u4<<4) High-order 4 bits are manipulated. *1: The assembler generates BANDL if the bit is set at u8&0x0F, and BANDH if the bit is set at u8&0xF0. In some cases, both BANDL and BANDH may be generated. *2: The assembler generates BORL if the bit is set at u8&0x0F, and BORH if the bit is set at u8&0xF0. In some cases, both BORL and BORH are generated. *3: The assembler generates BEORL if the bit is set at u8&0x0F, and BEORH if the bit is set at u8&0xF0. In some cases, both BEORL and BEORH are generated. 473 APPENDIX E INSTRUCTION LISTS ■ Multiply Instructions Table E.2-5 Multiply Instructions Mnemonic Type OP CYCLE NZVC Operation Remarks MUL Rj,Ri A AF 5 CCC- Ri * Rj → MDH,MDL 32bit*32bit=64bit MULU Rj,Ri A AB 5 CCC- Ri * Rj → MDH,MDL No sign MULH Rj,Ri A BF 3 CC-- Ri * Rj → MDL 16bit*16bit=32bit MULUH Rj,Ri A BB 3 CC-- Ri * Rj → MDL No sign DIV0S Ri E 97-4 1 ---- Step operation DIV0U Ri E 97-5 1 ---- 32bit/32bit=32bit DIV1 Ri E 97-6 d -C-C DIV2 Ri*3 E 97-7 1 -C-C DIV3 E 9F-6 1 ---- DIV4S E 9F-7 1 ---- *DIV Ri*1 36 -C-C MDL / Ri → MDL, MDL % Ri → MDH *DIVU Ri*2 33 -C-C MDL / Ri → MDL, MDL % Ri → MDH *1: DIV0S, DIV1 × 32, DIV2, DIV3, or DIV4S is generated. The instruction code length becomes 72 bytes. *2: DIV0U or DIV1 × 32 is generated. The instruction code length becomes 66 bytes. *3: Be sure to place a DIV3 instruction after a DIV2 instruction. 474 APPENDIX E INSTRUCTION LISTS ■ Shift Instructions Table E.2-6 Shift Instructions Mnemonic Type OP CYCLE NZVC Operation LSL Rj, Ri A B6 1 CC-C Ri << Rj → Ri *LSL #u5, Ri (u5:0-31) C’ B4 1 CC-C Ri << u5 → Ri LSL #u4, Ri C B4 1 CC-C Ri << u4 → Ri LSL2 #u4, Ri C B5 1 CC-C Ri <<(u4+16) → Ri LSR Rj, Ri A B2 1 CC-C Ri >> Rj → Ri *LSR #u5, Ri (u5:0-31) C’ B0 1 CC-C Ri >> u5 → Ri LSR #u4, Ri C B0 1 CC-C Ri >> u4 → Ri LSR2 #u4, Ri C B1 1 CC-C Ri >>(u4+16) → Ri ASR Rj, Ri A BA 1 CC-C Ri >> Rj → Ri *ASR #u5, Ri (u5:0-31) C’ B8 1 CC-C Ri >> u5 → Ri ASR #u4, Ri C B8 1 CC-C Ri >> u4 → Ri ASR2 #u4, Ri C B9 1 CC-C Ri >>(u4+16) → Ri Remarks Logical shift Logical shift Arithmetic shift ■ Immediate Set/16-bit/32-bit Immediate Transfer Instructions Table E.2-7 Immediate Set/16-bit/32-bit Immediate Transfer Instructions Mnemonic Type OP CYCLE NZVC LDI:32 #i32, Ri E 9F-8 3 ---- i32 → Ri LDI:20 #i20, Ri C 9B 2 ---- i20 → Ri High-order 12 bits are zero-extended. LDI:8 B C0 1 ---- i8 → Ri High-order 24 bits are zeroextended. #i8, Ri *LDI # {i8 | i20 | i32} ,Ri*1 Operation Remarks {i8 | i20 | i32} → Ri *1: If the immediate data is represented as absolute values, the assembler selects automatically from i8, i20, and i32. If immediate data contains a relative value or external reference symbol, i32 is selected. 475 APPENDIX E INSTRUCTION LISTS ■ Memory Load Instructions Table E.2-8 Memory Load Instructions Mnemonic Type OP CYCLE NZVC Operation Remarks LD @Rj, Ri A 04 b ---- (Rj) → Ri LD @(R13,Rj), Ri A 00 b ---- (R13+Rj) → Ri LD @(R14,disp10), Ri B 20 b ---- (R14+disp10) → Ri LD @(R15,udisp6), Ri C 03 b ---- (R15+udisp6) → Ri LD @R15+, Ri E 07-0 b ---- (R15) → Ri,R15+=4 LD @R15+, Rs E 07-8 b ---- (R15) → Rs, R15+=4 LD @R15+, PS E 07-9 1+a+b CCCC (R15) → PS, R15+=4 LDUH @Rj, Ri A 05 b ---- (Rj) →Ri Zero extension LDUH @(R13,Rj), Ri A 01 b ---- (R13+Rj) →Ri Zero extension LDUH @(R14,disp9), Ri B 40 b ---- (R14+disp9) →Ri Zero extension LDUB @Rj, Ri A 06 b ---- (Rj) →Ri Zero extension LDUB @(R13,Rj), Ri A 02 b ---- (R13+Rj) →Ri Zero extension LDUB @(R14,disp8), Ri B 60 b ---- (R14+disp8) →Ri Zero extension Rs: Special register * *: Special register Rs: TBR, RP, USP, SSP, MDH, and MDL Note: In the o8 and o4 fields of the hardware specifications, the assembler calculates values and sets them as shown below: disp10/4 → o8, disp9/2 → o8, disp8 → o8; disp10, disp9, and disp8 have a sign. udisp6/4 → o4; udisp6 has no sign. 476 APPENDIX E INSTRUCTION LISTS ■ Memory Store Instructions Table E.2-9 Memory Store Instructions Mnemonic Type OP CYCLE NZVC Operation Remarks ST Ri, @Rj A 14 a ---- Ri → (Rj) Word ST Ri, @(R13,Rj) A 10 a ---- Ri → (R13+Rj) Word ST Ri, @(R14,disp10) B 30 a ---- Ri → (R14+disp10) Word ST Ri, @(R15,udisp6) C 13 a ---- Ri → (R15+udisp6) ST Ri, @-R15 E 17-0 a ---- R15-=4,Ri → (R15) ST Rs, @-R15 E 17-8 a ---- R15-=4, Rs → (R15) ST PS, @-R15 E 17-9 a ---- R15-=4, PS → (R15) Rs: Special register * STH Ri, @Rj A 15 a ---- Ri → (Rj) Halfword STH Ri, @(R13,Rj) A 11 a ---- Ri → (R13+Rj) Halfword STH Ri, @(R14,disp9) B 50 a ---- Ri → (R14+disp9) Halfword STB Ri, @Rj A 16 a ---- Ri → (Rj) Byte STB Ri, @(R13,Rj) A 12 a ---- Ri → (R13+Rj) Byte STB Ri, @(R14,disp8) B 70 a ---- Ri → (R14+disp8) Byte *: Special register Rs: TBR, RP, USP, SSP, MDH, and MDL Notes: In the o8 and o4 fields of the hardware specifications, the assembler calculates values and sets them as shown below: disp10/4 → o8, disp9/2 → o8, disp8 → o8; disp10, disp9, and disp8 have a sign. disp6/4 → o4; udisp6 has no sign. ■ Register-to-Register Transfer Instructions Table E.2-10 Register-to-Register Transfer Instructions Mnemonic Type OP CYCLE NZVC Operation Remarks MOV Rj, Ri A 8B 1 ---- Rj → Ri Transfer between generalpurpose registers MOV Rs, Ri A B7 1 ---- Rs → Ri Rs: Special register * MOV Ri, Rs A B3 1 ---- Ri → Rs Rs: Special register * MOV PS, Ri E 17-1 1 ---- PS → Ri MOV Ri, PS E 07-1 c CCCC Ri → PS *: Special register Rs: TBR, RP, USP, SSP, MDH, and MDL 477 APPENDIX E INSTRUCTION LISTS ■ Normal Branch (No Delay) Instructions Table E.2-11 Normal Branch (No Delay) Instructions Mnemonic Type OP CYCLE NZVC E 97-0 2 ---- Ri → PC CALL label12 F D0 2 ---- PC+2→RP , PC+2+(label12-PC-2)→PC CALL @Ri E 97-1 2 ---- PC+2→RP ,Ri→PC RET E 97-2 2 ---- RP → PC D AC 3+3a CCCC INTE E 9F-3 3+3a RETI E 97-3 2+2a CCCC JMP INT @Ri #u8 Operation Remarks Return SSP-=4,PS → (SSP), SSP-=4,PC+2 → (SSP), 0→ I flag,0→ S flag, (TBR+0x3FC-u8x4)→ PC SSP-=4,PS → (SSP), SSP-=4,PC+2 → (SSP), 0→ S flag, (TBR+0x3D8) →PC For emulator (R15) → PC,R15-=4, (R15) → PS,R15-=4 BRA label9 D E0 2 ---- PC+2+(label9-PC-2) →PC BNO label9 D E1 1 ---- No branch BEQ label9 D E2 2/1 ---- if(Z==1) then PC+2+(label9-PC-2) →PC BNE label9 D E3 2/1 ---- s/Z==0 BC label9 D E4 2/1 ---- s/C==1 BNC label9 D E5 2/1 ---- s/C==0 BN label9 D E6 2/1 ---- s/N==1 BP label9 D E7 2/1 ---- s/N==0 BV label9 D E8 2/1 ---- s/V==1 BNV label9 D E9 2/1 ---- s/V==0 BLT label9 D EA 2/1 ---- s/V xor N==1 BGE label9 D EB 2/1 ---- s/V xor N==0 BLE label9 D EC 2/1 ---- s/(V xor N) or Z==1 BGT label9 D ED 2/1 ---- s/(V xor N) or Z==0 BLS label9 D EE 2/1 ---- s/C or Z==1 BHI label9 D EF 2/1 ---- s/C or Z==0 Notes: • "2/1" under CYCLE indicates 2 when branching occurs and "1" when branching does not occur. • In the rel11 and rel8 fields of the hardware specifications, the assembler calculates values and sets them as shown below: (label12-PC-2)/2→ rel11, (label9-PC-2)/2→ rel8; label12 and label9 have a sign. • To execute the RETI instruction, the S flag must be "0". 478 APPENDIX E INSTRUCTION LISTS ■ Delayed Branch Instructions Table E.2-12 Delayed Branch Instructions Mnemonic Type OP CYCLE NZVC E 9F-0 1 ---- Ri → PC CALL:D label12 F D8 1 ---- PC+4 → RP , PC+2+(label12-PC-2) → PC CALL:D @Ri E 9F-1 1 ---- PC+4 → RP ,Ri → PC RET:D E 9F-2 1 ---- RP → PC JMP:D @Ri Operation BRA:D label9 D F0 1 ---- PC+2+(label9-PC-2) →PC BNO:D label9 D F1 1 ---- No branch BEQ:D label9 D F2 1 ---- if(Z==1) then PC+2+(label9-PC-2) →PC BNE:D label9 D F3 1 ---- s/Z==0 BC:D label9 D F4 1 ---- s/C==1 BNC:D label9 D F5 1 ---- s/C==0 BN:D label9 D F6 1 ---- s/N==1 BP:D label9 D F7 1 ---- s/N==0 BV:D label9 D F8 1 ---- s/V==1 BNV:D label9 D F9 1 ---- s/V==0 BLT:D label9 D FA 1 ---- s/V xor N==1 BGE:D label9 D FB 1 ---- s/V xor N==0 BLE:D label9 D FC 1 ---- s/(V xor N) or Z==1 BGT:D label9 D FD 1 ---- s/(V xor N) or Z==0 BLS:D label9 D FE 1 ---- s/C or Z==1 BHI:D label9 D FF 1 ---- s/C or Z==0 Remarks Return Notes: • In the rel11 and rel8 fields of the hardware specifications, the assembler calculates values and sets them as shown below: (label12-PC-2)/2 → rel11, (label9-PC-2)/2 → rel8; label12 and label9 have a sign. • A delayed branch always occurs after the next instruction (delay slot) is executed. • Instructions that can be placed in the delay slot are all 1-cycle, a-, b-, c-, and d-cycle instructions. Multicycle instructions cannot be placed in the delay slot. 479 APPENDIX E INSTRUCTION LISTS ■ Other Instructions Table E.2-13 Other Instructions Mnemonic Type OP CYCLE NZVC NOP E 9F-A 1 ---- ANDCCR #u8 D 83 c CCCC CCR and u8 → CCR ORCCR #u8 D 93 c CCCC CCR or u8→ CCR STILM #u8 D 87 1 ---- i8 → ILM ILM immediate set D A3 1 ---- R15 += s10 ADD SP instruction EXTSB Ri E 97-8 1 ---- Sign extension 8 → 32bit EXTUB Ri E 97-9 1 ---- Zero extension 8 → 32bit EXTSH Ri E 97-A 1 ---- Sign extension 16 → 32bit EXTUH Ri E 97-B 1 ---- Zero extension 16 → 32bit LDM0 (reglist) D 8C ---- (R15) → reglist, R15 increment Load multi R0-R7 LDM1 (reglist) D 8D ---- (R15) → reglist, R15 increment Load multi R8-R15 *LDM (reglist)*2 ---- (R15) → reglist, R15 increment Load multi R0-R15 STM0 (reglist) D 8E ---- R15 decrement, reglist → (R15) Store multi R0-R7 STM1 (reglist) D 8F ---- R15 decrement, reglist → (R15) Store multi R8-R15 *STM (reglist)*3 ---- R15 decrement, reglist → (R15) Store multi R0-R15 ADDSP #s10 *1 Operation Remarks No change ENTER #u10*4 D 0F 1+a ---- R14 → (R15 - 4), R15 - 4 → R14, R15 - u10 → R15 Entry processing of a function LEAVE E 9F-9 b ---- R14 + 4 → R15, (R15 - 4) → R14 Exit processing of a function A 8A 2a ---- Ri → TEMP (Rj) → Ri TEMP → (Rj) For semaphore management Byte data XCHB @Rj, Ri *1: For s10, the assembler calculates s10/4 and then changes to s8 to set a value. s10 has a sign. *2: If any of R0 to R7 is specified in reglist, LDM0 is generated. If any of R8 to R15 is generated, LDM1 is generated. In some cases, both LDM0 and LDM1 are generated. *3: If any of R0 to R7 is specified in reglist, STM0 is generated. If any of R8 to R15 is generated, STM1 is generated. In some cases, both STM0 and STM1 are generated. *4: For u10, the assembler calculates u10/4 and then changes to u8 to set a value. u10 has a sign. Notes: • The number of execution cycles of LDM0(reglist) and LDM1(reglist) can be calculated as a×(n-1)+b+1 cycles if the number of specified registers is n. • The number of execution cycles of STM0(reglist) and STM1(reglist) can be calculated as a×n+1 cycles if the number of specified registers is n. 480 APPENDIX E INSTRUCTION LISTS ■ 20-Bit Normal Branch Macro Instructions Table E.2-14 20-Bit Normal Branch Macro Instructions Mnemonic Operation Remarks *CALL20 label20,Ri Address of the next instruction → RP, label20 → PC Ri: Temporary register (See Reference 1) *BRA20 label20,Ri label20 → PC Ri: Temporary register (See Reference 2) *BEQ20 label20,Ri if(Z==1) then label20 → PC Ri: Temporary register (See Reference 3) *BNE20 label20,Ri s/Z==0 *BC20 label20,Ri s/C==1 *BNC20 label20,Ri s/C==0 *BN20 label20,Ri s/N==1 *BP20 label20,Ri s/N==0 *BV20 label20,Ri s/V==1 *BNV20 label20,Ri s/V==0 *BLT20 label20,Ri s/V xor N==1 *BGE20 label20,Ri s/V xor N==0 *BLE20 label20,Ri s/(V xor N) or Z==1 *BGT20 label20,Ri s/(V xor N) or Z==0 *BLS20 label20,Ri s/C or Z==1 *BHI20 label20,Ri s/C or Z==0 [Reference 1] CALL20 1) If label20-PC-2 is between -0x800 and +0x7fe, create an instruction as shown below: CALL label12 2) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below: LDI:20 #label20,Ri CALL @Ri [Reference 2] BRA20 1) If label20-PC-2 is between -0x100 and +0xfe, create an instruction as shown below: BRA label9 2) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below: LDI:20 #label20,Ri JMP @Ri [Reference 3] Bcc20 1) If label20-PC-2 is between -0x100 and +0xfe, create an instruction as shown below: Bcc label9 2) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below: Bxcc false xcc is the opposite condition of cc. LDI:20 #label20,Ri JMP @Ri false: 481 APPENDIX E INSTRUCTION LISTS ■ 20-Bit Delayed Branch Macro Instructions Table E.2-15 20-Bit Delayed Branch Macro Instructions Mnemonic Operation Remarks *CALL20:D label20,Ri Address of the next instruction → RP, label20 → PC Ri: Temporary register (See Reference 1) *BRA20:D label20,Ri label20 → PC Ri: Temporary register (See Reference 2) *BEQ20:D label20,Ri if(Z==1) then label20 → PC Ri: Temporary register (See Reference 3) *BNE20:D label20,Ri s/Z==0 *BC20:D label20,Ri s/C==1 *BNC20:D label20,Ri s/C==0 *BN20:D label20,Ri s/N==1 *BP20:D label20,Ri s/N==0 *BV20:D label20,Ri s/V==1 *BNV20:D label20,Ri s/V==0 *BLT20:D label20,Ri s/V xor N==1 *BGE20:D label20,Ri s/V xor N==0 *BLE20:D label20,Ri s/(V xor N) or Z==1 *BGT20:D label20,Ri s/(V xor N) or Z==0 *BLS20:D label20,Ri s/C or Z==1 *BHI20:D label20,Ri s/C or Z==0 [Reference 1] CALL20:D 1) If label20-PC-2 is between -0x800 and +0x7fe, create an instruction as shown below: CALL:D label12 2) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below: LDI:20 #label20,Ri CALL:D @Ri [Reference 2] BRA20 1) If label20-PC-2 is between -0x100 and +0xfe, create an instruction as shown below: BRA :D label9 2) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below: LDI:20 #label20,Ri JMP:D @Ri [Reference 3] Bcc20:D 1) If label20-PC-2 is between -0x100 and +0xfe, create an instruction as shown below: Bcc:D label9 2) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below: Bxcc false xcc is the opposite condition of cc. LDI:20 #label20,Ri JMP:D @Ri false: 482 APPENDIX E INSTRUCTION LISTS ■ 32-Bit Normal Branch Macro Instructions Table E.2-16 32-Bit Normal Branch Macro Instructions Mnemonic Operation Remarks *CALL32 label32,Ri Address of the next instruction → RP, label20 → PC Ri: Temporary register (See Reference 1) *BRA32 label32,Ri label32 → PC Ri: Temporary register (See Reference 2) *BEQ32 label32,Ri if(Z==1) then label20 → PC Ri: Temporary register (See Reference 3) *BNE32 label32,Ri s/Z==0 *BC32 label32,Ri s/C==1 *BNC32 label32,Ri s/C==0 *BN32 label32,Ri s/N==1 *BP32 label32,Ri s/N==0 *BV32 label32,Ri s/V==1 *BNV32 label32,Ri s/V==0 *BLT32 label32,Ri s/V xor N==1 *BGE32 label32,Ri s/V xor N==0 *BLE32 label32,Ri s/(V xor N) or Z==1 *BGT32 label32,Ri s/(V xor N) or Z==0 *BLS32 label32,Ri s/C or Z==1 *BHI32 label32,Ri s/C or Z==0 [Reference 1] CALL32 1) If label32-PC-2 is between -0x800 and +0x7fe, create an instruction as shown below: CALL label12 2) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below: LDI:32 #label32,Ri CALL @Ri [Reference 2] BRA32 1) If label32-PC-2 is between -0x100 and +0xfe, create an instruction as shown below: BRA label9 2) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below: LDI:32 #label32,Ri JMP @Ri [Reference 3] Bcc32 1) If label32-PC-2 is between -0x100 and +0xfe, create an instruction as shown below: Bcc label9 2) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below: Bxcc false xcc is the opposite condition of cc. LDI:32 #label32,Ri JMP @Ri32 false: 483 APPENDIX E INSTRUCTION LISTS ■ 32-Bit Delayed Branch Macro Instructions Table E.2-17 32-Bit Delayed Branch Macro Instructions Mnemonic Operation Remarks *CALL32:D label32,Ri Address of the next instruction → RP, label20 → PC Ri: Temporary register (See Reference 1) *BRA32:D label32,Ri label32 → PC Ri: Temporary register (See Reference 2) *BEQ32:D label32,Ri if(Z==1) then label20 → PC Ri: Temporary register (See Reference 3) *BNE32:D label32,Ri s/Z==0 *BC32:D label32,Ri s/C==1 *BNC32:D label32,Ri s/C==0 *BN32:D label32,Ri s/N==1 *BP32:D label32,Ri s/N==0 *BV32:D label32,Ri s/V==1 *BNV32:D label32,Ri s/V==0 *BLT32:D label32,Ri s/V xor N==1 *BGE32:D label32,Ri s/V xor N==0 *BLE32:D label32,Ri s/(V xor N) or Z==1 *BGT32:D label32,Ri s/(V xor N) or Z==0 *BLS32:D label32,Ri s/C or Z==1 *BHI32:D label32,Ri s/C or Z==0 [Reference 1] CALL32:D 1) If label32-PC-2 is between -0x800 and +0x7fe, create an instruction as shown below: CALL:D label12 2) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below: LDI:32 #label32,Ri CALL:D @Ri [Reference 2] BRA32:D 1) If label32-PC-2 is between -0x100 and +0xfe, create an instruction as shown below: BRA:D label9 2) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below: LDI:32 #label32,Ri JMP:D @Ri [Reference 3] Bcc32:D 1) If label32-PC-2 is between -0x100 and +0xfe, create an instruction as shown below: Bcc:D label9 2) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below: Bxcc false xcc is the opposite condition of cc. LDI:32 #label32,Ri JMP:D @Ri32 false: 484 APPENDIX E INSTRUCTION LISTS ■ Direct Addressing Instructions Table E.2-18 Direct Addressing Instructions Mnemonic Type OP CYCLE NZVC DMOV @dir10, R13 D 08 b ---- (dir10) → R13 Word DMOV R13, D 18 a ---- R13 → (dir10) Word DMOV @dir10, @R13+ D 0C 2a ---- (dir10) → (R13),R13+=4 Word DMOV @R13+, @dir10 D 1C 2a ---- (R13) → (dir10),R13+=4 Word DMOV @dir10, @-R15 D 0B 2a ---- R15-=4,(R15) → (dir10) Word DMOV @R15+, @dir10 D 1B 2a ---- (R15) → (dir10),R15+=4 Word DMOVH @dir9, R13 D 09 b ---- (dir9) → R13 Halfword DMOVH R13, D 19 a ---- R13 → (dir9) Halfword DMOVH @dir9, @R13+ D 0D 2a ---- (dir9) → (R13),R13+=2 Halfword DMOVH @R13+, @dir9 D 1D 2a ---- (R13) → (dir9),R13+=2 Halfword DMOVB @dir8, R13 D 0A b ---- (dir8) → R13 Byte DMOVB R13, D 1A a ---- R13 → (dir8) Byte DMOVB @dir8, @R13+ D 0E 2a ---- (dir8) → (R13),R13++ Byte DMOVB @R13+, @dir8 D 1E 2a ---- (R13) → (dir8),R13++ Byte @dir10 @dir9 @dir8 Operation Remarks Note: In the dir8, dir9, and dir10 fields, the assembler calculates values and sets them as shown below: dir8 → dir, dir9/2 → dir, dir10/4 → dir; dir8, dir9, and dir10 have no sign. ■ Resource Instructions Table E.2-19 Resource Instructions Mnemonic Type OP CYCLE NZVC Operation Remarks LDRES @Ri+, #u4 C BC a ---- (Ri) → u4 resource Ri+=4 u4: Channel number STRES #u4, @Ri+ C BD a ---- u4 resource → (Ri) Ri+=4 u4: Channel number Note: Because the resource with the channel number is not installed in the MB91307 series, these instructions cannot be used. 485 APPENDIX E INSTRUCTION LISTS ■ Coprocessor Control Instructions Table E.2-20 Coprocessor Control Instructions Mnemonic Type OP CYCLE NZVC Operation COPOP #u4, #u8, CRj, CRi E 9F-C 2+a ---- Operation instruction COPLD #u4, #u8, Rj, CRi E 9F-D 1+2a ---- Rj → CRi COPST #u4, #u8, CRj, Ri E 9F-E 1+2a ---- CRj → Ri COPSV #u4, #u8, CRj, Ri E 9F-F 1+2a ---- CRj → Ri Remarks No error trap Notes: • {CRi | CRj}:= CR0 | CR1 | CR2 | CR3 | CR4 | CR5 | CR6 | CR7 | CR8 | CR9 | CR10 | CR11 | CR12 | CR13 |CR14 | CR15 u4:= Channel specified u8:= Channel specified • Since the MB91307 series has no coprocessor, this instruction cannot be used. 486 INDEX INDEX The index follows on the next page. This is listed in alphabetic order. 487 INDEX Index Numerics A 0 Detection 0 Detection ..................................................... 431 0 Detection Data Register 0 Detection Data Register (BSD0) .................... 429 1 Detection 1 Detection ..................................................... 431 1 Detection Data Register 1 Detection Data Register (BSD1) .................... 429 10-bit Slave Address Mask Register 10-bit Slave Address Mask Register (ITMK) ..... 353 10-bit Slave Address Register 10-bit Slave Address Register (ITBA) ............... 352 16-bit Reload Register Bit Configuration of the 16-bit Reload Register (TMRLR) .......................................... 246 16-bit Reload Timer 16-bit Reload Timer Registers .......................... 241 Overview of the 16-bit Reload Timer ................ 240 Precautions on Using the 16-bit Reload Timer ... 253 16-bit Timer Register Bit Configuration of the 16-bit Timer Register (TMR) ......................................................... 245 20-Bit Delayed Branch Macro Instructions 20-Bit Delayed Branch Macro Instructions ........ 482 20-Bit Normal Branch Macro Instructions 20-Bit Normal Branch Macro Instructions ......... 481 2-Cycle Transfer 2-Cycle Transfer (External→I/O)...................... 221 2-Cycle Transfer (for external →external transfer and transfer count=2) ................................ 421 2-Cycle Transfer (I/O→External)...................... 222 2-Cycle Transfer (Internal RAM→External I/O,RAM) ......................................................... 220 Demand Transfer 2-Cycle Transfer ................... 393 Flow of Data During 2-Cycle Transfer .............. 417 32-Bit Delayed Branch Macro Instructions 32-Bit Delayed Branch Macro Instructions ........ 484 32-Bit Normal Branch Macro Instructions 32-Bit Normal Branch Macro Instructions ......... 483 7-bit Slave Address Mask Register 7-bit Slave Address Mask Register (ISMK) ....... 356 7-bit Slave Address Register 7-bit Slave Address Register (ISBA) ................. 355 A/D Control Status Register A/D Control Status Register (ADCS) .................297 A/D Converter A/D Converter .....................................................4 A/D Converter Registers...................................296 Precautions on Using the A/D Converter ............307 AC Characteristics AC Characteristics of DMAC............................413 Access Burst Access Operation ....................................207 Byte Access.....................................................190 Data Access.......................................................66 Halfword Access..............................................188 Program Access .................................................66 Word Access ...................................................187 Acknowledge Acknowledge ..................................................361 ACR Configuration of Area Configuration Registers 0 to 7 (ACR0 to ACR7) ................................152 ADCR Data Register (ADCR) .....................................302 ADCS A/D Control Status Register (ADCS) .................297 Add Add-Subtract Instructions .................................471 Address Error Occurrence of an Address Error ........................406 Address Register Address Register Specifications ........................398 Features of the Address Register .......................398 Function of the Address Register .......................398 Address Setting Registers Transfer Source/Transfer Destination Address Setting Registers (DMASA0 toDMASA4/DMADA0 to DMADA4) .....................................383 Addressing Mode Addressing Mode Symbols ...............................467 Arbitration Arbitration ......................................................361 Architecture Internal Architecture ..........................................41 Area Configuration Registers Configuration of Area Configuration Registers 0 to 7 (ACR0 to ACR7) ................................152 488 INDEX Area Select Registers Functions of Bits in the Area Select Registers (ASR0 to ASR7) .................................151 area select registers Configuration of area select registers 0 to 7 (ASR0 to ASR7) .................................150 Area Wait Registers Configuration of the Area Wait Registers (AWR0 to AWR7) ..............................158 ASR Configuration of area select registers 0 to 7 (ASR0 to ASR7) .................................150 Functions of Bits in the Area Select Registers (ASR0 to ASR7) .................................151 Auto-Wait Cycle Timing Auto-Wait Cycle Timing ..................................199 AWR Configuration of the Area Wait Registers (AWR0 to AWR7) ..............................158 B Base Clock Division Setting Register Base Clock Division Setting Register 0 (DIVR0) ..........................................................120 Base Clock Division Setting Register 1 (DIVR1) ..........................................................122 Basic Block Diagram Basic Block Diagram of the I/O Port..................228 Basic Timing Basic Timing (For Successive Accesses) ............194 Baud Rate Calculation of Baud Rate ..................................261 Baud Rates Example of Setting U-TIMER Baud Rates and Reload Values ....................................334 Big Endian Differences between Little Endian and Big Endian ..........................................................182 Bit Manipulation Instructions Bit Manipulation Instructions ............................473 Bit Ordering Bit Ordering ......................................................65 Bit Search Module Bit Search Module (Used by REALOS) .................3 Bit Search Module Registers .............................429 Block Diagram of the Bit Search Module ...........428 Block Diagram Basic Block Diagram of the I/O Port..................228 Block Diagram ...................6, 107, 146, 240, 256, 279, 295, 311, 337, 369 Block Diagram of the Bit Search Module ...........428 Block Diagram of the Delayed Interrupt Module ..........................................................274 Block Diagram of the External Interrupt and NMI Controller................................... 264 Block Size Block Size ...................................................... 396 Block Transfer Block Transfer ................................................ 414 If Another Transfer Request Occurs During Block Transfer.................................... 412 Branch Normal Branch (No Delay) Instructions............. 478 Branch Instruction Limitations on Branch Instruction with Delay Slot ........................................................... 70 Operation of Branch Instruction with Delay Slot ........................................................... 69 Operation of Branch Instruction without Delay Slot ........................................................... 72 Branch Instructions Branch Instructions with Delay Slot .................... 68 Branch Instructions without Delay Slot................ 68 Delayed Branch Instructions ............................. 479 Branch Macro Instructions 20-Bit Delayed Branch Macro Instructions......... 482 20-Bit Normal Branch Macro Instructions.......... 481 32-Bit Delayed Branch Macro Instructions......... 484 32-Bit Normal Branch Macro Instructions.......... 483 BSD 0 Detection Data Register (BSD0)..................... 429 1 Detection Data Register (BSD1)..................... 429 BSDC Change Point Detection Data Register (BSDC) ......................................................... 430 BSRR Detection Result Register (BSRR)..................... 430 Built-in DC-DC Regulator Built-in DC-DC Regulator (MB91307B,MB91V307B only) ............ 33 Built-in Peripheral Built-in Peripheral Request............................... 391 Built-in RAM Built-in RAM ...................................................... 3 Built-in RAM Area in the Memory Space ............ 37 Burst Access Burst Access Operation .................................... 207 Burst Transfer Burst Transfer ................................................. 415 Bus Access External Bus Access ........................................ 179 Bus Control Register Bus Control Register (IBCR) ............................ 343 Bus Error Bus Error ........................................................ 362 Bus Interface Bus Interface ....................................................... 2 489 INDEX Ordinary Bus Interface..................................... 193 Bus Modes Bus Modes...................................................... 139 Bus Right Releasing the Bus Right ................................... 223 Bus Status Register Bus Status Register (IBSR) .............................. 340 Bus Width Data Bus Width....................................... 178, 184 Relationship between Data Bus Width and Control Signal.................................... 175 Byte Access Byte Access .................................................... 190 Byte Control Operation Timing of the WE + Byte Control Type ......................................................... 195 Byte Ordering Byte Ordering ................................................... 65 C Cache Enable Register Configuration of the Cache Enable Register (CHER) ......................................................... 170 Functions of Bits in the Cache Enable Register (CHER) ............................................. 170 Cache Size Register Configuration of Cache Size Register (ISIZE)...... 49 Cancellation Request Hold Request Cancellation Request Sequence .... 292 Cascade Mode Cascade Mode................................................. 262 Change Point Detection Change Point Detection ................................... 432 Change Point Detection Data Register Change Point Detection Data Register (BSDC) ......................................................... 430 Channel Group Channel Group................................................ 409 CHER Configuration of the Cache Enable Register (CHER) ......................................................... 170 Functions of Bits in the Cache Enable Register (CHER) ............................................. 170 Chip Select Area Example of Setting the Chip Select Area ........... 174 Chip Select Enable Register Configuration of the Chip Select Enable Register (CSER) ............................................. 168 Functions of Bits in the Chip Select Enable Register (CSER) ............................................. 168 Circuit Input-output Circuit Types ................................. 18 490 Clear Sequence Hardware Standby Clear Sequence (MB91307B) ...........................................................93 Operation Initialization Reset (RST) Clear Sequence ...........................................................92 Setting Initialization Reset (INIT) Clear Sequence ...........................................................92 CLKB CPU Clock (CLKB) .........................................104 CLKB Clock Precautions on Dividing the CLKB Clock ..........124 CLKP Peripheral Clock (CLKP)..................................104 CLKR Clock Source Control Register (CLKR) .............116 CLKS SDRAM Clock (CLKS)....................................105 CLKT External Bus Clock (CLKT)..............................105 Clock Clock Division.................................................106 Clock Generation Control ...................................98 CPU Clock (CLKB) .........................................104 External Bus Clock (CLKT)..............................105 External Clock Mode .......................................102 Internal Clock Operation ..................................247 Operation of the Input Pin Function (in Internal Clock Mode) .....................249 Peripheral Clock (CLKP)..................................104 Precautions on Dividing the CLKB Clock ..........124 SDRAM Clock (CLKS)....................................105 Selecting a Clock for the UART ........................323 Source Clock .....................................................98 Clock Control Register Clock Control Register (ICCR) .........................350 Clock Disable Register Clock Disable Register (IDBL) .........................358 Clock Division Clock Division.................................................106 Clock Generation Clock Generation Control ...................................98 Clock Source Control Register Clock Source Control Register (CLKR) .............116 Communication End of Communication.....................................328 Start of Communication....................................328 Compare Instructions Compare Instructions .......................................471 Continuous Conversion Mode Continuous Conversion Mode ...........................303 Control Registers Control Registers .............................................291 INDEX Control Status Register Bit Configuration of the Control Status Register (TMCSR) ...........................................242 Bit Functions of the Control Status Register (TMCSR) ..........................................................242 Control/Status Register Control/Status Register B (DMACB0 to DMACB4) ..........................................................377 Control/Status Registers Control/Status Registers A (DMACA0 to DMACA4) ..........................................................372 Conversion Data Protection Conversion Data Protection Function .................305 Conversion Mode Continuous Conversion Mode ...........................303 Single-shot Conversion Mode ...........................303 Stop Conversion Mode .....................................304 Coprocessor Coprocessor Error Trap ......................................87 coprocessor No-coprocessor Trap ..........................................87 Coprocessor Control Instructions Coprocessor Control Instructions.......................486 Coprocessor Error Trap Coprocessor Error Trap ......................................87 Counter Operating States of the Counter .........................252 CPU CPU Clock (CLKB) .........................................104 FR CPU ..............................................................2 CPU Clock CPU Clock (CLKB) .........................................104 CSER Configuration of the Chip Select Enable Register (CSER) ..............................................168 Functions of Bits in the Chip Select Enable Register (CSER) ..............................................168 CTBR Time Base Counter Clear Register (CTBR) ........115 D DACK Pin Function of the DACK,and DEOP,and DREQ pins ..........................................................387 DACK Pin Timing of DACK Pin Output ............................411 Data Access Data Access.......................................................66 Data Bus Data Bus Width .......................................178, 184 Data Direction Registers Configuration of the Data Direction Registers (DDR) ..........................................................231 Data Format Transfer Data Format ............................... 325, 327 Data Length Data Length (Data width) ................................. 399 Data Register Data Register (ADCR) ..................................... 302 Data Register (IADR) ...................................... 357 Data width Data Length (Data width) ................................. 399 DC-DC Regulator Built-in DC-DC Regulator (MB91307B,MB91V307B only) ............ 33 DDR Configuration of the Data Direction Registers (DDR) ......................................................... 231 Debugger Emulator Debugger/Monitor Debugger.............. 464 Simulator Debugger ......................................... 464 debugger Notes about debugger......................................... 30 Dedicated Registers List of Dedicated Registers ................................. 57 Delay Normal Branch (No Delay) Instructions............. 478 Operation Timing for the CS Delay Setting ........ 203 Delay Slot Branch Instructions with Delay Slot .................... 68 Branch Instructions without Delay Slot................ 68 Limitations on Branch Instruction with Delay Slot ........................................................... 70 Operation of Branch Instruction with Delay Slot ........................................................... 69 Operation of Branch Instruction without Delay Slot ........................................................... 72 Precaution on Delay Slot .................................... 87 Delayed Branch Instructions Delayed Branch Instructions ............................. 479 Delayed Branch Macro Instructions 20-Bit Delayed Branch Macro Instructions......... 482 32-Bit Delayed Branch Macro Instructions......... 484 Delayed Interrupt Control Register Delayed Interrupt Control Register (DICR) ........ 275 Delayed Interrupt Module Block Diagram of the Delayed Interrupt Module ......................................................... 274 Delayed Interrupt Module Registers .................. 275 Demand Transfer Demand Transfer ............................................. 416 Demand Transfer 2-Cycle Transfer.................... 393 Negate Timing of the DREQ Pin Input when a Demand Transfer Request is Stopped ......................................................... 410 Timing of Demand Transfer ............................. 424 491 INDEX Timing of Transfer Other Than Demand Transfer ......................................................... 423 DEOP Pin Function of the DACK,and DEOP,and DREQ pins ......................................................... 387 DEOP Pin Timing of the DEOP Pin Output ....................... 412 Detecting Detecting the start bit....................................... 326 Detection 0 Detection ..................................................... 431 1 Detection ..................................................... 431 Change Point Detection ................................... 432 Lack of Error Detection ................................... 463 Slave Address Detection .................................. 360 Detection Result Register Detection Result Register (BSRR) .................... 430 Device Initialization Reset (Device Initialization) ............................... 88 Device States Device States .................................................. 130 DICR Delayed Interrupt Control Register (DICR)........ 275 DLYI Bit of DICR........................................... 276 Dimensions Dimensions of the FPT-120P-M21........................ 7 Direct Addressing Instructions Direct Addressing Instructions.......................... 485 DIVR Base Clock Division Setting Register 0 (DIVR0) ......................................................... 120 Base Clock Division Setting Register 1 (DIVR1) ......................................................... 122 DLYI Bit DLYI Bit of DICR........................................... 276 DMA Clearing Peripheral Interrupts by DMA ............. 404 DMA Access Operation ................................... 215 DMA External Interface Pins............................ 420 DMA Fly-By Transfer (I/O→Memory) ............. 216 DMA Fly-By Transfer (Memory→I/O) ............. 218 DMA Transfer during Sleep ............................. 407 Operation Timing for DMA Fly-By Transfer (I/O→Memory).................................. 205 Operation Timing for DMA Fly-By Transfer (Memory→I/O).................................. 206 Suppressing DMA ........................................... 401 DMA Controller DMA Controller (DMAC) registers................... 370 DMAC (DMA Controller).................................... 3 DMA Transfer DMA Transfer and Interrupts ........................... 401 DMA Transfer Request during External Hold .... 402 External Hold Request During DMA Transfer.... 402 492 Simultaneous Occurrence of a DMA Transfer Request and an External Hold Request ..............402 DMAC AC Characteristics of DMAC............................413 Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR2)............................165 DMA Controller (DMAC) registers ...................370 DMAC (DMA Controller) ....................................3 DMAC Interrupt Control ..................................407 Functions of Bits in the I/O Wait Registers for DMAC (IOWR0 to IOWR2)............................165 DMAC All-Channel Control Register DMAC All-Channel Control Register (DMACR) .........................................................385 DMACA Control/Status Registers A (DMACA0 to DMACA4) .........................................................372 DMACB Control/Status Register B (DMACB0 to DMACB4) .........................................................377 DMACR DMAC All-Channel Control Register (DMACR) .........................................................385 DMADA Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to DMASA4/ DMADA0 to DMADA4) .....................383 DMASA Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to DMASA4/ DMADA0 to DMADA4) .....................383 Double Type Use of the Double Type or Long Double Type .........................................................460 DRCL DRCL Register ................................................322 DREQ Pin Negate Timing of the DREQ Pin Input when a Demand Transfer Request is Stopped .........................................................410 Timing of the DREQ Pin Input for Continuing Transfer over the Same Channel ...........411 DREQ pin Minimum Effective Pulse Width of the DREQ pin Input ............................410 DREQ pins Pin Function of the DACK,and DEOP,and DREQ pins .........................................................387 DSTP Pin Timing of the DSTP Pin Input...........................412 INDEX E Effective Pulse Width Minimum Effective Pulse Width of the DREQ pin Input ..................................................410 EIRR External Interrupt Source Register (EIRR: External Interrupt Request Register) ..................267 EIT EIT (Exception,Interrupt,and Trap)......................73 EIT Causes........................................................73 EIT Interrupt Levels ...........................................74 EIT Operations ..................................................84 EIT Vector Table ...............................................78 Priority of EIT Causes to Be Accepted .................82 Return from EIT ................................................73 ELVR External Interrupt Request Level Setting Register (ELVR: External Level Register)..........268 Emulator Emulator Debugger/Monitor Debugger ..............464 ENable Interrupt Request Register Interrupt Enable Register (ENIR: ENable Interrupt Request Register) ................................266 End Operation End/Stopping ...................................405 ENIR Interrupt Enable Register (ENIR: ENable Interrupt Request Register) ................................266 Error Bus Error ........................................................362 Coprocessor Error Trap ......................................87 Lack of Error Detection ....................................463 Occurrence of an Address Error.........................406 Stopping Due To an Error .................................405 Exception EIT (Exception,Interrupt,and Trap)......................73 Operation of Undefined Instruction Exception ......86 External Bus External Bus Access.........................................179 External Bus Clock External Bus Clock (CLKT)..............................105 External Clock Mode External Clock Mode........................................102 External Devices Example of Connection with External Devices ..........................................................181 Examples of Connection with External Devices ..........................................................185 External Event Count External Event Count Operation ........................250 External Hold Simultaneous Occurrence of a DMA Transfer Request and an External Hold Request ..............402 External I/O 2-Cycle Transfer (Internal RAM→External I/O,RAM) ......................................................... 220 Transfer Between External I/O and External Memory ......................................................... 412 External Interrupt Block Diagram of the External Interrupt and NMI Controller................................... 264 External Interrupt and NMI Controller Registers ......................................................... 265 External Interrupt Request Level ....................... 270 Operating Procedure for an External Interrupt .... 269 Operation of an External Interrupt ..................... 269 External Interrupt Request Level Setting Register External Interrupt Request Level Setting Register (ELVR: External Level Register) ......... 268 External Interrupt Request Register External Interrupt Source Register (EIRR: External Interrupt Request Register) ..... 267 External Interrupt Source Register External Interrupt Source Register (EIRR: External Interrupt Request Register) ..... 267 External Level Register External Interrupt Request Level Setting Register (ELVR: External Level Register) ......... 268 External Memory Transfer Between External I/O and External Memory ......................................................... 412 External Transfer Request External Transfer Request Pin........................... 391 External Wait With External Wait .......................................... 210 Without External Wait ..................................... 209 External Wait Cycle Timing External Wait Cycle Timing ............................. 200 F Flag I Flag................................................................ 75 Flags Occurrence of Interrupts and Timing for Setting Flags ......................................................... 329 Fly-By Transfer DMA Fly-By Transfer (I/O→Memory).............. 216 DMA Fly-By Transfer (Memory→I/O).............. 218 Flow of Data During Fly-By Transfer ................ 419 Fly-By Transfer (for I/O →memory and transfer count=3) ................................ 421 Fly-By Transfer (for memory →I/O and transfer count=3) ................................ 422 Operation Timing for DMA Fly-By Transfer (I/O→Memory) .................................. 205 Operation Timing for DMA Fly-By Transfer (Memory→I/O) .................................. 206 493 INDEX FPT-120P-M21 Dimensions of the FPT-120P-M21........................ 7 FR FR CPU.............................................................. 2 FR Family FR Family Instruction Lists .............................. 470 G General-purpose Registers General-purpose Registers.................................. 64 H Halfword Access Halfword Access ............................................. 188 Hardware Configuration Hardware Configuration........................... 291, 368 Hardware Standby Hardware Standby after Power-on (MB91307B,MB91V307B only)............ 33 Hardware Standby Clear Sequence (MB91307B) ........................................................... 93 Hardware Standby State ................................... 132 HST Pin Input (Hardware Standby Pin) (MB91307B only) ................................ 91 Hardware Standby Mode Hardware Standby Mode.................................. 138 Hardware Standby State Hardware Standby State ................................... 132 Hold Request Hold Request Cancellation Request Sequence ......................................................... 292 Hold Request Cancel Request Hold Request Cancellation Request (HRLC: Hold Request Cancel Request)............. 289 Hold Request Cancellation Request Hold Request Cancellation Request (HRLC: Hold Request Cancel Request)............. 289 Hold Request Cancellation Request Level Setting Register Hold Request Cancellation Request Level Setting Register (HRCL) ..................... 284 HRCL Hold Request Cancellation Request Level Setting Register (HRCL) ..................... 284 HRLC Hold Request Cancellation Request (HRLC: Hold Request Cancel Request)............. 289 HST HST Pin Input (Hardware Standby Pin) (MB91307B only) ................................ 91 494 I I Flag I Flag ................................................................75 I/O Map I/O Map ..........................................................436 I/O Pins I/O Pins...........................................................147 I/O Port Basic Block Diagram of the I/O Port..................228 I/O Port Modes ................................................229 I/O Ports I/O Ports .............................................................5 I/O Wait Registers Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR2)............................165 Functions of Bits in the I/O Wait Registers for DMAC (IOWR0 to IOWR2)............................165 2 I C Interface I2C Interface........................................................4 I2C Interface Registers .....................................338 IADR Data Register (IADR).......................................357 IBCR Bus Control Register (IBCR) ............................343 IBSR Bus Status Register (IBSR) ...............................340 ICCR Clock Control Register (ICCR) .........................350 ICHCR Instruction Cache Control Register (ICHCR) ........50 ICR Configuration of Interrupt Control Register (ICR) ...........................................................76 Interrupt Control Register (ICR)........................282 Mapping of Interrupt Control Register (ICR) ........76 IDBL Clock Disable Register (IDBL) .........................358 ILM Interrupt Level Mask (ILM) Register ...................75 Immediate Set Immediate Set/16-bit/32-bit Immediate Transfer Instructions ........................................475 Immediate Transfer Instructions Immediate Set/16-bit/32-bit Immediate Transfer Instructions ........................................475 INIT INIT Pin Input (Settings Initialization Reset Pin) ...........................................................90 Setting Initialization Reset (INIT) Clear Sequence ...........................................................92 Settings Initialization Reset (INIT) ......................89 Settings Initialization Reset (INIT) State ............133 INDEX Initial Value Allocation of a Variable with an Initial Value .....458 Initialization Initialization ....................................................328 Operation Initialization Reset (RST) State ..........133 Reset (Device Initialization)................................88 Settings Initialization Reset (INIT) State ............133 Initialization Reset INIT Pin Input (Settings Initialization Reset Pin) ............................................................90 Operation Initialization Reset (RST) ....................89 Operation Initialization Reset (RST) Clear Sequence ............................................................92 Setting Initialization Reset (INIT) Clear Sequence ............................................................92 Settings Initialization Reset (INIT) ......................89 Input-output Circuit Input-output Circuit Types ..................................18 Instruction FR Family Instruction Lists...............................470 How to Read the Instruction Lists......................466 Instruction Format............................................469 Limitations on Branch Instruction with Delay Slot ............................................................70 Operation of Branch Instruction with Delay Slot ............................................................69 Operation of Branch Instruction without Delay Slot ............................................................72 Operation of INT Instruction ...............................85 Operation of INTE Instruction.............................85 Operation of RETI Instruction .............................87 Operation of Undefined Instruction Exception ......86 Instruction Cache Area That Can Be Cached in the Instruction Cache ............................................................45 Configuration of Instruction Cache ......................46 Instruction Cache .................................................3 Instruction Cache Status in Each Operating Mode V .........................................................52 Instruction Cache Tags .......................................47 Updating Entries in the Instruction Cache.............53 Instruction Cache Control Register Instruction Cache Control Register (ICHCR) ........50 Instructions 20-Bit Delayed Branch Macro Instructions .........482 20-Bit Normal Branch Macro Instructions ..........481 32-Bit Delayed Branch Macro Instructions .........484 32-Bit Normal Branch Macro Instructions ..........483 Add-Subtract Instructions .................................471 Bit Manipulation Instructions ............................473 Branch Instructions with Delay Slot.....................68 Branch Instructions without Delay Slot ................68 Compare Instructions .......................................471 Coprocessor Control Instructions.......................486 Delayed Branch Instructions .............................479 Direct Addressing Instructions ..........................485 Immediate Set/16-bit/32-bit Immediate Transfer Instructions ........................................ 475 Logic Instructions ............................................ 472 Memory Load Instructions................................ 476 Memory Store Instructions ............................... 477 Multiply Instructions........................................ 474 Normal Branch (No Delay) Instructions............. 478 Other Instructions ............................................ 480 Overview of Instructions .................................... 43 Register-to-Register Transfer Instructions .......... 477 Resource Instructions ....................................... 485 Shift Instructions ............................................. 475 INT Instruction Operation of INT Instruction .............................. 85 INTE Instruction Operation of INTE Instruction ............................ 85 Interface Bus Interface ....................................................... 2 I2C Interface ....................................................... 4 I2C Interface Registers ..................................... 338 Ordinary Bus Interface ..................................... 193 Internal Architecture Internal Architecture .......................................... 41 Internal Clock Internal Clock Operation .................................. 247 Operation of the Input Pin Function (in Internal Clock Mode) ..................... 249 Internal RAM 2-Cycle Transfer (Internal RAM→External I/O,RAM) ......................................................... 220 Interrupt Block Diagram of the External Interrupt and NMI Controller................................... 264 DMAC Interrupt Control .................................. 407 EIT (Exception,Interrupt,and Trap) ..................... 73 EIT Interrupt Levels........................................... 74 External Interrupt and NMI Controller Registers ......................................................... 265 External Interrupt Request Level ....................... 270 Interrupt Level Mask (ILM) Register................... 75 Interrupt Number ............................................. 276 Interrupt Processing ......................................... 366 Interrupt Stack................................................... 77 Level Mask for Interrupt and NMI ...................... 75 Operating Procedure for an External Interrupt ......................................................... 269 Operation of an External Interrupt ..................... 269 Interrupt Control Register Configuration of Interrupt Control Register (ICR) ........................................................... 76 Interrupt Control Register (ICR) ....................... 282 Mapping of Interrupt Control Register (ICR)........ 76 Interrupt Controller Hardware Configuration of the Interrupt Controller ......................................................... 278 495 INDEX Interrupt Controller.............................................. 4 Interrupt Controller Registers ........................... 280 Interrupt Enable Register Interrupt Enable Register (ENIR: ENable Interrupt Request Register) ............................... 266 Interrupt Level Mask Interrupt Level Mask (ILM) Register .................. 75 Interrupt Vectors Interrupt Vectors ............................................. 446 Interrupts Clearing Peripheral Interrupts by DMA ............. 404 DMA Transfer and Interrupts ........................... 401 Occurrence of Interrupts and Timing for Setting Flags ......................................................... 329 Interval Timers Other Interval Timers .......................................... 4 IOWR Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR2) ........................... 165 Functions of Bits in the I/O Wait Registers for DMAC (IOWR0 to IOWR2) ........................... 165 ISBA 7-bit Slave Address Register (ISBA) ................. 355 ISIZE Configuration of Cache Size Register (ISIZE)...... 49 ISMK 7-bit Slave Address Mask Register (ISMK) ....... 356 ITBA 10-bit Slave Address Register (ITBA) ............... 352 ITMK 10-bit Slave Address Mask Register (ITMK) ..... 353 K -K lib Option Specification of the -K lib Option When Using a String Manipulation Function............ 460 L Latch up Preventing a Latch up ........................................ 24 Level Mask Interrupt Level Mask (ILM) Register .................. 75 Level Mask for Interrupt and NMI ...................... 75 Little Endian Allocation of a Stack to a Little Endian Area ..... 460 Differences between Little Endian and Big Endian ......................................................... 182 Restrictions on the Little Endian Area ............... 182 Load Memory Load Instructions ............................... 476 Logic Instructions Logic Instructions............................................ 472 496 Long Double Type Use of the Double Type or Long Double Type....460 Low-power Modes Low-power Modes ...................................130, 134 M Mask Interrupt Level Mask (ILM) Register ...................75 Level Mask for Interrupt and NMI.......................75 Slave Address Mask .........................................360 MB91306R Precautions on turning on and off the power supplies (MB91306R,MB91307R only) ...............34 MB91307 MB91307 Series ..................................................5 MB91307B Built-in DC-DC Regulator (MB91307B,MB91V307B only) ............33 Hardware Standby after Power-on (MB91307B,MB91V307B only) ............33 Hardware Standby Clear Sequence (MB91307B) ...........................................................93 HST Pin Input (Hardware Standby Pin) (MB91307B only).................................91 Pin Layout of the MB91307B ...............................8 MB91307R Pin Layout of the MB91307R ...............................9 Precautions on turning on and off the power supplies (MB91306R,MB91307R only) ...............34 MB91V307B Built-in DC-DC Regulator (MB91307B,MB91V307B only) ............33 Hardware Standby after Power-on (MB91307B,MB91V307B only) ............33 MDH Multiply and Divide Registers (MDH/MDL) ........59 MDL Multiply and Divide Registers (MDH/MDL) ........59 Memory Built-in RAM Area in the Memory Space ............37 Memory Load Instructions ................................476 Memory Store Instructions................................477 Memory Load Instructions Memory Load Instructions ................................476 Memory Map Memory Map...............................................36, 67 Memory Space Built-in RAM Area in the Memory Space ............37 Memory Store Instructions Memory Store Instructions................................477 Minimum Effective Pulse Width Minimum Effective Pulse Width of the DREQ pin Input ............................410 INDEX Mode Addressing Mode Symbols ...............................467 Cascade Mode .................................................262 Continuous Conversion Mode ...........................303 External Clock Mode........................................102 Hardware Standby Mode ..................................138 Instruction Cache Status in Each Operating Mode ............................................................52 Mode Settings..................................................140 Operation of the Input Pin Function (in Internal Clock Mode) .....................249 Precautions on Using STOP Mode.......................34 Return from Standby Mode (Sleep/Stop) ............290 Self-induced Oscillation Mode ..........................101 Single-shot Conversion Mode ...........................303 Sleep Mode .....................................................134 Stop Conversion Mode .....................................304 Stop Mode.......................................................136 Transfer Mode .................................................388 Transfer Mode Settings.....................................425 Mode Register Functions of Bits in the Mode Register (MODR) ..........................................................140 Modes I/O Port Modes ................................................229 Low-power Modes ...................................130, 134 Operating Modes .............................................323 MODR Functions of Bits in the Mode Register (MODR) ..........................................................140 Monitor Emulator Debugger/Monitor Debugger ..............464 Multiply and Divide Registers Multiply and Divide Registers (MDH/MDL) ........59 Multiply Instructions Multiply Instructions ........................................474 Multiply-by Rate PLL Multiply-by Rate ......................................100 N Negate Timing Negate Timing of the DREQ Pin Input when a Demand Transfer Request is Stopped ..........................................................410 NMI Block Diagram of the External Interrupt and NMI Controller ...................................264 External Interrupt and NMI Controller Registers ..........................................................265 Level Mask for Interrupt and NMI .......................75 NMI........................................................270, 288 Operation of User Interrupt/NMI .........................84 NMI Controller Block Diagram of the External Interrupt and NMI Controller ...................................264 NMI Controller Registers External Interrupt and NMI Controller Registers ......................................................... 265 No-coprocessor Trap No-coprocessor Trap.......................................... 87 Normal Branch Normal Branch (No Delay) Instructions............. 478 Normal Branch Macro Instructions 20-Bit Normal Branch Macro Instructions.......... 481 32-Bit Normal Branch Macro Instructions.......... 483 Normal Reset Normal Reset Operation ..................................... 96 O Operating Mode Instruction Cache Status in Each Operating Mode ........................................................... 52 Operating Modes Operating Modes ..................................... 139, 323 Operating States Operating States of the Counter......................... 252 Operation Initialization Reset Operation Initialization Reset (RST).................... 89 Operation Initialization Reset (RST) Clear Sequence ........................................................... 92 Operation Initialization Reset (RST) State.......... 133 Operation Timing Operation Timing for DMA Fly-By Transfer (I/O→Memory) .................................. 205 Operation Timing for DMA Fly-By Transfer (Memory→I/O) .................................. 206 Operation Timing for Synchronous Write Enable Output ............................................... 201 Operation Timing for the CS Delay Setting ........ 203 Operation Timing for the CS→RD/WE Setup and RD/WE→CS Hold Settings ................. 204 Operation Timing of Read→Write .................... 197 Operation Timing of the WE + Byte Control Type ......................................................... 195 Option Specification of the -K lib Option When Using a String Manipulation Function ............ 460 Ordering Bit Ordering ...................................................... 65 Byte Ordering ................................................... 65 Ordinary Bus Interface Ordinary Bus Interface ..................................... 193 Oscillation Processing of Source Oscillation Input after Power-on ........................................................... 33 Oscillation Mode Self-induced Oscillation Mode.......................... 101 497 INDEX Oscillation Stabilization Wait Oscillation Stabilization Wait Reset (RST) Status ......................................................... 132 Oscillation Stabilization Wait RUN State .......... 132 Sources of an Oscillation Stabilization Wait......... 94 Oscillation Stabilization Wait Reset Oscillation Stabilization Wait Reset (RST) Status ......................................................... 132 Oscillation Stabilization Wait RUN State Oscillation Stabilization Wait RUN State .......... 132 Oscillation Stabilization Wait Time Selecting an Oscillation Stabilization Wait Time .. 95 Other Instructions Other Instructions............................................ 480 P PC Program Counter (PC) ....................................... 57 PDR Configuration of the Port Data Registers (PDR) ......................................................... 230 Peripheral Built-in Peripheral Request .............................. 391 Clearing Peripheral Interrupts by DMA ............. 404 Peripheral Clock Peripheral Clock (CLKP) ................................. 104 PFR Configuration of the Port Function Registers (PFR) ......................................................... 232 Function of the Port Function Registers (PFR) ......................................................... 233 Pin Functions Description of Pin Functions .............................. 10 Pin Layout Pin Layout of the MB91307B............................... 8 Pin Layout of the MB91307R............................... 9 Pin State Table Meaning of Terms in the Pin State Table ........... 450 Pin State Table................................................ 451 Pin/Timing Control Register Configuration of the Pin/Timing Control Register (TCR) ............................................... 171 Functions of Bits in the Pin/Timing Control Register (TCR) ............................................... 171 Pins Handling of Pins ............................................... 24 pins Pin Function of the DACK,and DEOP,and DREQ pins ......................................................... 387 PLL PLL Multiply-by Rate...................................... 100 PLL Operation Enable ....................................... 99 498 Port Data Registers Configuration of the Port Data Registers (PDR) .........................................................230 Port Function Registers Configuration of the Port Function Registers (PFR) .........................................................232 Function of the Port Function Registers (PFR) ....233 power supplies Precautions on turning on and off the power supplies (MB91306R,MB91307R only) ...............34 Power-on Hardware Standby after Power-on (MB91307B,MB91V307B only) ............33 Processing after Power-on ..................................33 Processing of Source Oscillation Input after Power-on ...........................................................33 Prefetch Prefetch Operation ...........................................212 Principal Operations Principal Operations.........................................388 Priority Priority Among Channels .................................408 Priority Decision..............................................285 Priority of EIT Causes to Be Accepted .................82 Priority of State Transition Requests ..................133 Procedure Operating Procedure for an External Interrupt.....269 Procedure for Setting a Register ........................225 Setup Procedure.................................................54 Processing Save/Restore Processing ...................................433 Program Access Program Access .................................................66 Program Counter Program Counter (PC) ........................................57 Program Status Program Status (PS) Register ..............................60 Protection Conversion Data Protection Function.................305 PS Program Status (PS) Register ..............................60 Pulse Width Minimum Effective Pulse Width of the DREQ pin Input ............................410 R RAM 2-Cycle Transfer (Internal RAM→External I/O,RAM) .........................................................220 Built-in RAM ......................................................3 Built-in RAM Area in the Memory Space ............37 REALOS Bit Search Module (Used by REALOS) .................3 INDEX Reload Timer (including One Channel for REALOS) ..............................................................3 Receive Data Example of Receive Data..................................365 Receive Operation Receive Operation............................................325 Register Interrupt Level Mask (ILM) Register ...................75 Program Status (PS) Register ..............................60 Register-to-Register Transfer Instructions Register-to-Register Transfer Instructions ..........477 Regulator Built-in DC-DC Regulator (MB91307B,MB91V307B only) ............33 Reload Operation Reload Operation .....................................396, 400 Reload Register Reload Register (UTIMR).................................257 Reload Timer 16-bit Reload Timer Registers ...........................241 Overview of the 16-bit Reload Timer .................240 Precautions on Using the 16-bit Reload Timer ....253 Reload Timer (including One Channel for REALOS) ..............................................................3 Reload Values Example of Setting U-TIMER Baud Rates and Reload Values ....................................334 Reset INIT Pin Input (Settings Initialization Reset Pin) ............................................................90 Normal Reset Operation .....................................96 Operation Initialization Reset (RST) ....................89 Operation Initialization Reset (RST) Clear Sequence ............................................................92 Operation Initialization Reset (RST) State ..........133 Oscillation Stabilization Wait Reset (RST) Status ..........................................................132 Reset (Device Initialization)................................88 Setting Initialization Reset (INIT) Clear Sequence ............................................................92 Settings Initialization Reset (INIT) ......................89 Settings Initialization Reset (INIT) State ............133 Software Reset (STCR: SRST Bit Writing) ..........90 Synchronous Reset Operation..............................96 Watchdog Reset .................................................91 Resource Instructions Resource Instructions .......................................485 Restore Processing Save/Restore Processing ...................................433 RETI Instruction Operation of RETI Instruction .............................87 Return Pointer Return Pointer (RP)............................................58 RP Return Pointer (RP) ........................................... 58 RSRR Reset Source Register/Watchdog Timer Control Register (RSRR)................................. 108 RST Operation Initialization Reset (RST).................... 89 Operation Initialization Reset (RST) Clear Sequence ........................................................... 92 Operation Initialization Reset (RST) State.......... 133 Oscillation Stabilization Wait Reset (RST) Status ......................................................... 132 RUN State Oscillation Stabilization Wait RUN State........... 132 RUN State (Normal Operation) ......................... 131 S Save Save/Restore Processing................................... 433 SCR Serial Control Register (SCR) ........................... 315 SDRAM Clock SDRAM Clock (CLKS) ................................... 105 Section Section ........................................................... 461 Section Types Restriction on Section Types ............................ 463 Self-induced Oscillation Mode Self-induced Oscillation Mode.......................... 101 Send Operation Send Operation................................................ 325 Serial Control Register Serial Control Register (SCR) ........................... 315 Serial Input Data Register Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) ................................ 318 Serial Mode Register Serial Mode Register (SMR)............................. 313 Serial Output Data Register Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) ................................ 318 Serial Status Register Serial Status Register (SSR) ............................. 319 Setting Initialization Reset Setting Initialization Reset (INIT) Clear Sequence ........................................................... 92 Settings Initialization Reset INIT Pin Input (Settings Initialization Reset Pin) ........................................................... 90 Settings Initialization Reset (INIT) ...................... 89 Settings Initialization Reset (INIT) State............ 133 Shift Instructions Shift Instructions ............................................. 475 499 INDEX SIDR Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) ................................ 318 Simulator Simulator Debugger......................................... 464 Single-shot Conversion Mode Single-shot Conversion Mode........................... 303 Slave Address Example of Slave Address and Data Transfer..... 364 Slave Address Detection .................................. 360 Slave Address Mask ........................................ 360 Slave Addressing Slave Addressing............................................. 361 Sleep DMA Transfer during Sleep ............................. 407 Return from Standby Mode (Sleep/Stop) ........... 290 Sleep Mode Sleep Mode..................................................... 134 Sleep State Sleep State...................................................... 131 SMR Serial Mode Register (SMR) ............................ 313 SODR Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) ................................ 318 Software Request Software Request ............................................ 391 Software Reset Software Reset (STCR: SRST Bit Writing).......... 90 Source Clock Source Clock .................................................... 98 Source Oscillation Processing of Source Oscillation Input after Power-on ........................................................... 33 Specifications Overview of Specifications ................................ 46 SRST Software Reset (STCR: SRST Bit Writing).......... 90 SSP System Stack Pointer (SSP).......................... 58, 77 SSR Serial Status Register (SSR) ............................. 319 Stack Allocation of a Stack to a Little Endian Area ..... 460 Interrupt Stack .................................................. 77 Standby Hardware Standby after Power-on (MB91307B,MB91V307B only)............ 33 Hardware Standby Clear Sequence (MB91307B) ........................................................... 93 Hardware Standby Mode.................................. 138 Hardware Standby State ................................... 132 Return from Standby ....................................... 269 500 Standby Control Register Standby Control Register (STCR)......................110 Standby Mode Return from Standby Mode (Sleep/Stop) ............290 START condition START condition.............................................359 State Hardware Standby State ...................................132 Operation Initialization Reset (RST) State ..........133 Oscillation Stabilization Wait RUN State ...........132 RUN State (Normal Operation) .........................131 Settings Initialization Reset (INIT) State ............133 Sleep State ......................................................131 Stop State........................................................131 State Transition Priority of State Transition Requests ..................133 Status Oscillation Stabilization Wait Reset (RST) Status .........................................................132 STCR Software Reset (STCR: SRST Bit Writing) ..........90 Standby Control Register (STCR)......................110 Step Trace Trap Operation of Step Trace Trap ..............................86 Stop Return from Standby Mode (Sleep/Stop) ............290 STOP condition STOP condition ...............................................359 Stop Conversion Mode Stop Conversion Mode .....................................304 STOP Mode Precautions on Using STOP Mode.......................34 Stop Mode Stop Mode.......................................................136 Stop State Stop State........................................................131 Stopping Operation End/Stopping ...................................405 Stopping Due To an Error .................................405 Store Memory Store Instructions................................477 String Operations Other Than the String Arrangement Using a String Manipulation Function ............459 Specification of the -K lib Option When Using a String Manipulation Function ............460 String Arrangement Operations Other Than the String Arrangement Using a String Manipulation Function ............459 String Manipulation Operations Other Than the String Arrangement Using a String Manipulation Function ............459 Specification of the -K lib Option When Using a String Manipulation Function ........................460 INDEX Structure Assignment Structure Assignment .......................................458 Subtract Instructions Add-Subtract Instructions .................................471 Successive Accesses Basic Timing (For Successive Accesses) ............194 Symbols Addressing Mode Symbols ...............................467 Synchronous Reset Synchronous Reset Operation..............................96 Synchronous Write Operation Timing for Synchronous Write Enable Output................................................201 System Stack Pointer System Stack Pointer (SSP) ..........................58, 77 T Table Base Register Table Base Register (TBR) ...........................58, 78 Tags Instruction Cache Tags .......................................47 TBCR Time Base Counter Control Register (TBCR) .....113 TBR Table Base Register (TBR) ...........................58, 78 TCR Configuration of the Pin/Timing Control Register (TCR) ................................................171 Functions of Bits in the Pin/Timing Control Register (TCR) ................................................171 Temporary Stopping Temporary Stopping.........................................404 Time Base Counter Time Base Counter...........................................127 Time Base Counter Clear Register Time Base Counter Clear Register (CTBR) ........115 Time Base Counter Control Register Time Base Counter Control Register (TBCR) .....113 Time Base Timer Time Base Timer .............................................128 TMCSR Bit Configuration of the Control Status Register (TMCSR) ...........................................242 Bit Functions of the Control Status Register (TMCSR) ..........................................................242 TMR Bit Configuration of the 16-bit Timer Register (TMR) ..........................................................245 TMRLR Bit Configuration of the 16-bit Reload Register (TMRLR)...........................................246 Transfer 2-Cycle Transfer (External→I/O) ......................221 2-Cycle Transfer (for external →external transfer and transfer count=2) ................................ 421 2-Cycle Transfer (I/O→External) ...................... 222 2-Cycle Transfer (Internal RAM→External I/O,RAM) ......................................................... 220 Block Transfer ................................................ 414 Burst Transfer ................................................. 415 Demand Transfer ............................................. 416 Demand Transfer 2-Cycle Transfer.................... 393 DMA Fly-By Transfer (I/O→Memory).............. 216 DMA Fly-By Transfer (Memory→I/O).............. 218 DMA Transfer and Interrupts............................ 401 DMA Transfer during Sleep ............................. 407 DMA Transfer Request during External Hold..... 402 Example of Slave Address and Data Transfer ..... 364 External Hold Request During DMA Transfer .... 402 External Transfer Request Pin........................... 391 Flow of Data During 2-Cycle Transfer............... 417 Flow of Data During Fly-By Transfer ................ 419 Fly-By Transfer (for I/O →memory and transfer count=3) ................................ 421 Fly-By Transfer (for memory →I/O and transfer count=3) ................................ 422 If an External Pin Transfer Request is Reentered During Transfer .................................. 412 If Another Transfer Request Occurs During Block Transfer ............................................. 412 Operation Timing for DMA Fly-By Transfer (I/O→Memory) .................................. 205 Operation Timing for DMA Fly-By Transfer (Memory→I/O) .................................. 206 Selection of the Transfer Sequence.................... 392 Simultaneous Occurrence of a DMA Transfer Request and an External Hold Request .............. 402 Timing of the DREQ Pin Input for Continuing Transfer over the Same Channel........... 411 Timing of Transfer Other Than Demand Transfer ......................................................... 423 Transfer Address ............................................. 389 Transfer Between External I/O and External Memory ......................................................... 412 Transfer Count and Transfer End ...................... 390 Transfer Count Control .................................... 400 Transfer Data Format ............................... 325, 327 Transfer Mode................................................. 388 Transfer Request Acceptance and Transfer......... 403 Transfer Type.................................................. 389 Transfer Count Control Transfer Count Control .................................... 400 Transfer Destination Address Setting Registers Transfer Source/Transfer Destination Address Setting Registers (DMASA0 toDMASA4/DMADA0 to DMADA4) ..................................... 383 Transfer Instructions Immediate Set/16-bit/32-bit Immediate Transfer Instructions ........................................ 475 501 INDEX Register-to-Register Transfer Instructions.......... 477 Transfer Mode Transfer Mode ................................................ 388 Transfer Mode Settings.................................... 425 Transfer Request If an External Pin Transfer Request is Reentered During Transfer.................................. 412 If Another Transfer Request Occurs During Block Transfer............................................. 412 Transfer Source Transfer Source/Transfer Destination Address Setting Registers (DMASA0 toDMASA4/DMADA0 to DMADA4)..................................... 383 Trap Coprocessor Error Trap...................................... 87 EIT (Exception,Interrupt,and Trap) ..................... 73 No-coprocessor Trap ......................................... 87 Operation of Step Trace Trap ............................. 86 UTIM U-TIMER (UTIM) ...........................................257 UTIMC Precautions on the U-TIMER Control Register (UTIMC) ...........................................260 U-TIMER Control Register (UTIMC)................258 U-TIMER Example of Setting U-TIMER Baud Rates and Reload Values ....................................334 Overview of the U-TIMER ...............................256 U-TIMER (UTIM) ...........................................257 U-TIMER Registers .........................................257 U-TIMER Control Register Precautions on the U-TIMER Control Register (UTIMC) ...........................................260 U-TIMER Control Register (UTIMC)................258 UTIMR Reload Register (UTIMR) ................................257 U V UART Example of Using the UART............................ 332 Selecting a Clock for the UART ....................... 323 UART ................................................................ 4 UART Registers.............................................. 312 Undefined Instruction Exception Operation of Undefined Instruction Exception ..... 86 Underflow Operation Underflow Operation ....................................... 248 User Interrupt Operation of User Interrupt/NMI ........................ 84 User Program Initializing a User Program................................. 38 User Stack Pointer User Stack Pointer (USP) ................................... 59 USP User Stack Pointer (USP) ................................... 59 Variable Allocation of a Variable with an Initial Value .....458 Vector Table EIT Vector Table ...............................................78 502 W Wait Cycle Timing Auto-Wait Cycle Timing ..................................199 External Wait Cycle Timing..............................200 Watchdog Reset Watchdog Reset.................................................91 Watchdog Reset Postpone Register Watchdog Reset Postpone Register (WPR).........119 Word Access Word Access ...................................................187 WPR Watchdog Reset Postpone Register (WPR).........119 CM71-10111-6E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL FR60 32-BIT MICROCONTROLLER MB91307 Series HARDWARE MANUAL March 2006 the 6th edition Published FUJITSU LIMITED Edited Business Promotion Dept. Electronic Devices