The following document contains information on Cypress products. FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM71-10121-3E FR60 32-BIT MICROCONTROLLER MB91350A Series HARDWARE MANUAL FR60 32-BIT MICROCONTROLLER MB91350A Series HARDWARE MANUAL Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. FUJITSU LIMITED CONTENTS ■ Objectives and Intended Reader The MB91350A series is one of the FR60 family of microcontrollers. The FR60 family of microcontrollers is based on the FR30/40 family of CPUs, which use a 32-bit high-performance RISC CPU as the core CPU. The FR60 family offers enhanced bus access. The MB91350A series is a single-chip microcontroller with built-in peripheral resources. The MB91350A series is ideal for embedded control applications that require high-performance or high-speed CPU processing. This manual is intended for engineers who will develop products using the MB91350A series and describes the functions and operations of the MB91350A series. Read this manual thoroughly. For more information on instructions, see the "Instructions Manual". Note : FR, which is an abbreviation of FUJITSU RISC controller, is a product of FUJITSU LIMITED. ■ Trademark The company names and brand names herein are the trademarks or registered trademarks of their respective owners. ■ License Purchase of Fujitsu I2C components conveys a licence under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. ■ Organization of This Manual This manual consists of the following 19 chapters and an appendix. CHAPTER 1 OVERVIEW This chapter provides basic information required to understand the MB91350A series. It covers features and dimensions, and presents a block diagram of the MB91350A series. CHAPTER 2 HANDLING THE DEVICE This chapter provides precautions on handling the device. CHAPTER 3 CPU AND CONTROL UNITS This chapter provides basic information required to understand the MB91350A series core CPU functions. It covers architecture, specifications, and instructions. CHAPTER 4 EXTERNAL BUS INTERFACE This chapter describes basic items related to the external bus interface, register configuration/functions, bus operation, bus timing, and procedures for setting the registers. CHAPTER 5 I/O PORT This chapter describes the I/O ports and the configuration and functions of registers. i CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers This chapter outlines the 8/16-bit up/down counter/timer and U-TIMER and explains the configuration and functions of the registers and timer operations. CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER This chapter outlines the 16-bit free-running timer and 16-bit reload timer and explains the configuration and functions of the registers and timer operations. CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER This chapter gives an outline of the PPG (Programmable Pulse Generator) timer and explains the register configuration and functions and the timer operations. CHAPTER 9 INTERRUPT CONTROLLER This chapter describes the overview of the interrupt controller, the configuration and functions of registers, and interrupt controller operation. CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER This chapter outlines the external interrupt/NMI controller and explains the configuration and functions of the registers and operations of the external interrupt/NMI controller. CHAPTER 11 REALOS-RELATED HARDWARE This chapter outlines the delayed interrupt module and bit search module, and explains the configuration and functions of registers and operations. CHAPTER 12 A/D CONVERTER This chapter outlines the A/D converter and explains the configuration and functions of registers and the A/D converter operations. CHAPTER 13 8-BIT D/A CONVERTER This chapter gives an overview of the 8-bit D/A converter, register configuration and functions, and 8bit D/A converter operation. CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE MODULE This chapter outlines the UART, SIO, input capture, and output compare, and explains the configuration and functions of registers. It also explains UART, SIO, input capture, and output compare operations. CHAPTER 15 I2C INTERFACE This chapter describes the overview of the I2C interface, the configuration and functions of registers, and I2C interface operation. CHAPTER 16 DMA CONTROLLER (DMAC) This chapter describes the overview of the DMAC, the configuration and functions of registers, and DMAC operation. CHAPTER 17 FLASH MEMORY This chapter provides an outline of flash memory and explains its register configuration, register functions, and operations. CHAPTER 18 MB91F355A/F353A/F356B/F357B SERIAL PROGRAMMING CONNECTION This chapter describes the serial onboard writing connection (Fujitsu standard) using the AF220/AF210/ AF120/AF110 Flash Microcontroller Programmer by Yokogawa Digital Computer Corporation. ii CHAPTER 19 DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS This chapter outlines a function that restricts access to data internal RAM and instruction internal RAM. It also explains the configuration and functions of registers and internal RAM operations. APPENDIX This appendix consists of the following parts: I/O map, interrupt vectors, pin state for each CPU state, and the instruction lists. iii • • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Copyright ©2003-2007 FUJITSU LIMITED All rights reserved iv CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 OVERVIEW ................................................................................................... 1 Features .............................................................................................................................................. 2 Block Diagram .................................................................................................................................... 7 Package Dimensions .......................................................................................................................... 9 Pin Layout ......................................................................................................................................... 11 List of Pin Functions ......................................................................................................................... 13 Input-output Circuit Forms ................................................................................................................ 27 CHAPTER 2 HANDLING THE DEVICE .......................................................................... 31 2.1 Precautions on Handling the Device ................................................................................................. 2.2 Precautions on Using the Little-Endian Area .................................................................................... 2.2.1 C Compiler (fcc911) ..................................................................................................................... 2.2.2 Assembler (fasm911) .................................................................................................................. 2.2.3 Linker (flnk911) ............................................................................................................................ 2.2.4 Debuggers (sim911, eml911, and mon911) ................................................................................ CHAPTER 3 3.1 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.4 3.5 3.6 3.6.1 3.6.2 3.7 3.7.1 3.7.2 3.7.3 3.7.4 3.7.5 3.7.6 3.7.7 3.7.8 3.8 3.8.1 3.8.2 3.9 3.9.1 32 37 38 41 42 43 CPU AND CONTROL UNITS ..................................................................... 45 Memory Space .................................................................................................................................. Internal Architecture .......................................................................................................................... Internal Architecture .................................................................................................................... Overview of Instructions .............................................................................................................. Programming Model ......................................................................................................................... General-Purpose Registers ......................................................................................................... Dedicated Registers .................................................................................................................... Data Configuration ............................................................................................................................ Memory Map ..................................................................................................................................... Branch Instructions ........................................................................................................................... Operations with a Delay Slot ....................................................................................................... Operation without Delay Slot ....................................................................................................... EIT (Exception, Interrupt, and Trap) ................................................................................................. EIT Interrupt Levels ..................................................................................................................... ICR (Interrupt Control Register) ................................................................................................... SSP (System Stack Pointer) ........................................................................................................ Interrupt Stack ............................................................................................................................. TBR (Table Base Register) ......................................................................................................... EIT Vector Table .......................................................................................................................... Multiple EIT Processing ............................................................................................................... Operations ................................................................................................................................... Operating Modes .............................................................................................................................. Bus Modes ................................................................................................................................... Mode Settings .............................................................................................................................. Reset (Device Initialization) .............................................................................................................. Reset Levels ................................................................................................................................ v 46 49 50 53 55 56 57 64 66 67 68 71 72 73 75 77 78 79 80 84 86 90 91 92 94 95 3.9.2 Reset Sources ............................................................................................................................. 96 3.9.3 Reset Sequence .......................................................................................................................... 98 3.9.4 Oscillation Stabilization Wait Time .............................................................................................. 99 3.9.5 Reset Operation Modes ............................................................................................................. 102 3.10 Clock Generation Control ............................................................................................................... 104 3.10.1 PLL Controls .............................................................................................................................. 105 3.10.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time .................................................... 106 3.10.3 Clock Distribution ....................................................................................................................... 108 3.10.4 Clock Division ............................................................................................................................ 110 3.10.5 Block Diagram of Clock Generation Controller .......................................................................... 111 3.10.6 Register of Clock Generation Controller .................................................................................... 112 3.10.7 Peripheral Circuits of Clock Controller ....................................................................................... 129 3.11 Device State Control ....................................................................................................................... 133 3.11.1 Device States and State Transitions ......................................................................................... 134 3.11.2 Low-power Consumption Modes ............................................................................................... 138 3.12 Watch Timer ................................................................................................................................... 143 3.13 Main Clock Oscillation Stabilization Wait Timer .............................................................................. 149 3.14 Peripheral Stop Control .................................................................................................................. 155 CHAPTER 4 4.1 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.5 4.6 4.7 4.8 4.9 4.10 CHAPTER 5 5.1 5.2 162 167 168 169 175 181 183 184 186 188 189 190 197 201 205 215 218 222 228 230 I/O PORT .................................................................................................. 231 Overview of the I/O Port ................................................................................................................. 232 I/O Port Registers ........................................................................................................................... 234 CHAPTER 6 6.1 EXTERNAL BUS INTERFACE ................................................................ 161 Overview of the External Bus Interface .......................................................................................... External Bus Interface Registers .................................................................................................... ASR0 to ASR3 (Area Select Register) ...................................................................................... ACR0 to ACR7 (Area Configuration Registers) ......................................................................... AWR0 to AWR3 (Area Wait Register) ....................................................................................... IOWR0 to IOWR3 (I/O Wait Registers for DMAC) ..................................................................... Chip Select Enable Register (CSER) ........................................................................................ TCR (Terminal and Timing Control Register) ............................................................................ Setting Example of the Chip Select Area ........................................................................................ Byte Ordering (Endian) and Bus Access ........................................................................................ Relationship Between Data Bus Widths and Control Signals .................................................... Big Endian Bus Access ............................................................................................................. Little Endian Bus Access ........................................................................................................... External Access ......................................................................................................................... Ordinary Bus Interface .................................................................................................................... Address/data Multiplex Interface .................................................................................................... Prefetch Operation .......................................................................................................................... DMA Access Operation .................................................................................................................. Bus Arbitration ................................................................................................................................ Procedure for Setting a Register .................................................................................................... 8/16-bit Up/Down Counters/Timer and U-Timers ................................. 245 8/16-bit Up/Down Counters/Timers ................................................................................................ 246 vi 6.1.1 Overview of 8/16-bit Up/Down Counters/Timers ....................................................................... 6.1.2 8/16-bit Up/Down Counters/Timer Registers ............................................................................. 6.1.3 Operation of the 8/16-bit Up/Down Counters/Timers ................................................................ 6.2 U-TIMER ......................................................................................................................................... 6.2.1 Overview of the U-TIMER .......................................................................................................... 6.2.2 U-TIMER Registers ................................................................................................................... 6.2.3 Operation of the U-TIMER ......................................................................................................... CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER ............. 277 7.1 16-bit Free-Running Timer .............................................................................................................. 7.1.1 Structure of the 16-bit Free-Running Timer ............................................................................... 7.1.2 16-bit Free-Running Timer Registers ........................................................................................ 7.1.3 Operation of the 16-bit Free-Running Timer .............................................................................. 7.2 16-bit Reload Timer ........................................................................................................................ 7.2.1 Structure of the 16-bit Reload Timer ......................................................................................... 7.2.2 16-bit Reload Timer Register ..................................................................................................... 7.2.3 Operation of the 16-bit Reload Register .................................................................................... CHAPTER 8 278 279 280 284 286 287 289 292 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER ...................... 297 8.1 Overview of the PPG Timer ............................................................................................................ 8.2 PPG Timer Registers ...................................................................................................................... 8.2.1 Control Status Register ............................................................................................................. 8.2.2 PPG Cycle Setting Register (PCSR) ......................................................................................... 8.2.3 PPG Duty Setting Register (PDUT) ........................................................................................... 8.2.4 PPG Timer Register (PTMR) ..................................................................................................... 8.2.5 General Control Register 10 ...................................................................................................... 8.2.6 General Control Register 20 ...................................................................................................... 8.3 Operation of the PPG Timer ........................................................................................................... 8.3.1 Timing Charts for PWM Operation ............................................................................................ 8.3.2 Timing Charts for One-Shot Operation ...................................................................................... 8.3.3 Interrupt Sources and Timing Chart (with PPG output set for ordinary polarity) ........................ 8.3.4 Examples of Methods of All-L and All-H PPG Output ................................................................ 8.3.5 Activation of Multiple Channels Using the General Control Register ........................................ CHAPTER 9 247 252 259 268 269 270 275 298 302 303 307 308 309 310 313 314 315 317 318 319 320 INTERRUPT CONTROLLER ................................................................... 323 9.1 Overview of the Interrupt Controller ................................................................................................ 9.2 Interrupt Controller Registers .......................................................................................................... 9.2.1 Interrupt Control Register (ICR) ................................................................................................. 9.2.2 Hold request cancellation request register (HRCL) ................................................................... 9.3 Operation of the Interrupt Controller ............................................................................................... 324 328 329 331 332 CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER ............................... 341 10.1 Overview of the External Interrupt and NMI Controller ................................................................... 10.2 External Interrupt and NMI Controller Registers ............................................................................. 10.2.1 Enable Interrupt Request Register (ENIRn) .............................................................................. 10.2.2 External Interrupt Request Register (EIRRn) ............................................................................ 10.2.3 External Level Register (ELVRn) ............................................................................................... vii 342 344 345 346 347 10.3 Operation of the External Interrupt and NMI Controller .................................................................. 348 CHAPTER 11 REALOS-RELATED HARDWARE .......................................................... 351 11.1 Delayed Interrupt Module ............................................................................................................... 11.1.1 Overview of the Delayed Interrupt Module ................................................................................ 11.1.2 Delayed Interrupt Module Registers .......................................................................................... 11.1.3 Operation of the Delayed Interrupt Module ............................................................................... 11.2 Bit Search Module .......................................................................................................................... 11.2.1 Overview of the Bit Search Module ........................................................................................... 11.2.2 Bit Search Module Registers ..................................................................................................... 11.2.3 Operation of the Bit Search Module .......................................................................................... 352 353 354 355 356 357 358 360 CHAPTER 12 A/D CONVERTER .................................................................................... 363 12.1 Overview of the A/D Converter ....................................................................................................... 12.2 A/D Converter Registers ................................................................................................................. 12.2.1 Control Status Register (ADCS1) .............................................................................................. 12.2.2 Control Status Register (ADCS2) .............................................................................................. 12.2.3 Conversion Time Setting Register (ADCT) ................................................................................ 12.2.4 Data Registers (ADTHx and ADTLx) ......................................................................................... 12.3 Operation of the A/D Converter ...................................................................................................... 364 366 367 370 373 375 376 CHAPTER 13 8-BIT D/A CONVERTER .......................................................................... 379 13.1 13.2 13.3 Overview of the 8-bit D/A Converter ............................................................................................... 380 8-bit D/A Converter Register ........................................................................................................... 382 8-bit D/A Converter Operation ........................................................................................................ 384 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE MODULE ...................................................... 385 14.1 UART .............................................................................................................................................. 14.1.1 Features of the UART ................................................................................................................ 14.1.2 UART Registers ......................................................................................................................... 14.1.3 Operation of the UART .............................................................................................................. 14.1.4 Example of using the UART ...................................................................................................... 14.2 Serial I/O Interface (SIO) ................................................................................................................ 14.2.1 Overview of the Serial I/O Interface (SIO) ................................................................................. 14.2.2 Serial I/O Interface Registers .................................................................................................... 14.2.3 Operation of the Serial I/O Interface (SIO) ................................................................................ 14.3 Input Capture Module ..................................................................................................................... 14.3.1 Overview of the Input Capture Module ...................................................................................... 14.3.2 Input Capture Module Registers ................................................................................................ 14.3.3 Input Capture Operation ............................................................................................................ 14.4 Output Compare ............................................................................................................................. 14.4.1 Features of the Output Compare Module .................................................................................. 14.4.2 Output Compare Module Registers ........................................................................................... 14.4.3 Operation of the Output Compare Module ................................................................................ viii 386 387 390 399 407 410 411 413 419 425 426 428 430 431 432 434 437 CHAPTER 15 I2C INTERFACE ....................................................................................... 439 15.1 Overview of the I2C Interface .......................................................................................................... 15.2 I2C Interface Registers ................................................................................................................... 15.2.1 Bus Status Register (IBSR) ....................................................................................................... 15.2.2 Bus Control Register (IBCR) ..................................................................................................... 15.2.3 Clock Control Register (ICCR) .................................................................................................. 15.2.4 10-bit Slave Address Register (ITBA) ........................................................................................ 15.2.5 10-bit Slave Address Mask Register (ITMK) ............................................................................. 15.2.6 7-bit Slave Address Register (ISBA) ......................................................................................... 15.2.7 7-bit Slave Address Mask Register (ISMK) ............................................................................... 15.2.8 Data Register (IDAR) ................................................................................................................. 15.2.9 Clock Disable Register (IDBL) ................................................................................................... 15.3 Explanation of I2C Interface Operation ........................................................................................... 15.4 Operation Flowcharts ...................................................................................................................... 440 444 445 448 455 457 458 460 461 462 463 464 468 CHAPTER 16 DMA CONTROLLER (DMAC) .................................................................. 471 16.1 Overview ......................................................................................................................................... 16.2 Detailed Explanation of Registers ................................................................................................... 16.2.1 DMAC ch0 to ch4 Control/Status Registers A ........................................................................... 16.2.2 DMAC ch0 to ch4 Control/Status Registers B ........................................................................... 16.2.3 DMAC ch0 to ch4 Transfer Source/Transfer Destination Address Setting Registers ................ 16.2.4 DMAC ch0 to ch4 DMAC All-Channel Control Register ............................................................ 16.3 Explanation of Operation ................................................................................................................ 16.3.1 Overview of Operation ............................................................................................................... 16.3.2 Setting a Transfer Request ........................................................................................................ 16.3.3 Transfer Sequence .................................................................................................................... 16.3.4 General Aspects of DMA Transfer ............................................................................................. 16.3.5 Addressing Mode ....................................................................................................................... 16.3.6 Data Types ................................................................................................................................ 16.3.7 Transfer Count Control .............................................................................................................. 16.3.8 CPU Control .............................................................................................................................. 16.3.9 Hold Arbitration .......................................................................................................................... 16.3.10 Operation from Starting to End/Stopping ................................................................................... 16.3.11 Transfer Request Acceptance and Transfer .............................................................................. 16.3.12 Clearing Peripheral Interrupts by DMA ...................................................................................... 16.3.13 Temporary Stopping .................................................................................................................. 16.3.14 Operation End/Stopping ............................................................................................................ 16.3.15 Stopping Due To an Error .......................................................................................................... 16.3.16 DMAC Interrupt Control ............................................................................................................. 16.3.17 DMA Transfer during Sleep ....................................................................................................... 16.3.18 Channel Selection and Control .................................................................................................. 16.3.19 Supplement on External Pin and Internal Operation Timing ..................................................... 16.4 Operation Flowcharts ...................................................................................................................... 16.5 Data Path ........................................................................................................................................ 16.6 DMA External Interface ................................................................................................................... ix 472 475 476 482 488 490 492 493 496 497 501 503 504 505 506 507 508 509 510 511 512 513 514 515 516 518 522 525 529 CHAPTER 17 FLASH MEMORY ..................................................................................... 533 17.1 Outline of Flash Memory ................................................................................................................. 17.2 Flash Memory Registers ................................................................................................................. 17.2.1 Flash Control/Status Register (FLCR) (CPU mode) .................................................................. 17.2.2 Flash Memory Wait Register (FLWC) ........................................................................................ 17.3 Explanation of Flash Memory Operation ........................................................................................ 17.4 Automatic Algorithm of Flash Memory ............................................................................................ 17.4.1 Command Sequence ................................................................................................................. 17.4.2 Checking the Automatic Algorithm Operating Status ................................................................ 17.5 Writing to and Erasing Flash Memory ............................................................................................. 17.5.1 Read/Reset Status .................................................................................................................... 17.5.2 Data Writing ............................................................................................................................... 17.5.3 Data Erasure (Chip Erasure) ..................................................................................................... 17.5.4 Data Erasure (Sector Erasure) .................................................................................................. 17.5.5 Temporary Sector Erase Stop ................................................................................................... 17.5.6 Sector Erase Restart ................................................................................................................. 534 539 540 543 545 547 548 552 557 558 559 561 562 564 565 CHAPTER 18 MB91F355A/F353A/F356B/F357B SERIAL PROGRAMMING CONNECTION ................................................................................................................... 567 18.1 18.2 18.3 18.4 18.5 Basic Configuration of MB91F355A/F353A/F356B/F357B Serial Programming Connection ......... Pins Used for Fujitsu Standard Serial Onboard Writing .................................................................. Examples of Serial Programming Connection ................................................................................ System Configuration of Flash Microcontroller Programmer .......................................................... Other Precautionary Information ..................................................................................................... 568 569 570 572 573 CHAPTER 19 DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS .................................................... 575 19.1 19.2 19.3 Overview ......................................................................................................................................... 576 Explanation of Registers ................................................................................................................. 577 Explanation of Operation ................................................................................................................ 579 APPENDIX ......................................................................................................................... 581 APPENDIX A APPENDIX B APPENDIX C APPENDIX D I/O Map ................................................................................................................................ Interrupt Vector .................................................................................................................... Pin States in Each CPU State .............................................................................................. Instruction Lists .................................................................................................................... 582 594 597 603 INDEX................................................................................................................................... 619 x Main changes in this edition Page Changes (For details, refer to main body.) - - Products were changed. (MB91F353A/352A/353A → MB91F353A/351A/352A/353A) (MB91F35 → MB91F353A/351A/352A/353A) (MB91F35A → MB91F353A/351A/352A/353A) (MB91F355A/353A → MB91F353A/F355A/F356B/F357B) (MB91F355A/355A/354A → MB91F355A/355A/354A/F356B/F357B) - - "flash memories" were changed. (256 KB flash memories → 256K bytes/128K bytes flash memories) (512 KB flash memories → 512K bytes/256K bytes flash memories) - - The following terms were unified. (FR series → FR family) (FR30 series → FR30 family) 3 1.1 Features "Table 1.1-1 Internal Memory Details" was changed. (The column for MB91351A was added.) (The columns for MB91F356B and MB91F357B were added.) 5 1.1 Features "■ Other Features" was changed. (LQFP-176 (lead pitch 0.50 mm) → MB91F355A/F356B/F357B/355A/354A: LQFP-176 (lead pitch 0.50 mm)) 6 1.1 Features "Table 1.1-2 Comparison of Functions: Internal Memory (Products whose Memory Capacity is to be Extended and the Configuration of Memory are Currently under Study.)" was changed. (The column for MB91351A was added.) 1.2 Block Diagram "Figure 1.2-1 MB91F353A/353A/352A/351A Block Diagram" was changed. 7, 8 "Figure 1.2-2 MB91355A/354A/F355A/F356B/F357B Block Diagram" was changed. 12 1.4 Pin Layout "■ Pin layout of the MB91352A and MB91F353A (LQFP-120)" was deleted. 46 3.1 Memory Space "Figure 3.1-1 MB91F355A, MB91355A, MB91F353A, MB91353A and MB95F357B Memory Maps" was changed. (Internal ROM → Internal RAM) 47 "Figure 3.1-2 MB91351A Memory Map " was added. "Figure 3.1-3 MB91354A and MB91352A Memory Map" was changed. (Internal ROM → Internal RAM) 48 "Figure 3.1-4 MB91F356B Memory Map" was added. xi Page Changes (For details, refer to main body.) 48 3.1 Memory Space "■ Memory Map" was changed. (For the MB91V350A, a 512K-byte internal ROM area is used as emulation RAM for the MB91355A, F355A, 353A, and F353A memory map. In addition, the instruction internal RAM is extended from 8 KB to 16 KB. → For the MB91V350A, with the memory map of the MB91355A/F355A/353A/F353A/ F357B, the 512K bytes area of the internal ROM, and with the memory map of the MB91F356B, the 256K bytes area of the internal ROM, is the emulation RAM. In addition, internal RAM(Instruction) is extended from 8K bytes to16K bytes.) 174 4.2.2 ACR0 to ACR7 (Area Configuration Registers) "Notes:" was changed. "(Set both ASR and ACR at the same time using word access. When accessing ASR and ACR using half word, please set ACR after setting ASR.)" was added. 230 4.10 Procedure for Setting a Register "■ Procedure for Setting the External Bus Interface" was changed. 238 to 244 5.2 I/O Port Registers "Table 5.2-1 Initial Values and Functions of the Port Function Registers (PFRs)" was changed. ("*2" was deleted.) 246 6.1 8/16-bit Up/Down Counters/Timers "■ Overview of the 8/16-bit Up/Down Counters/Timers" was changed. (The MB91F355A/355A/354A/V350A→ The MB91F355A/355A/354A/ F356B/F357B) 271 6.2.2 U-TIMER Registers "■ Reload Register (UTIMR)" was changed. ("Note:" was added.) 275 6.2.3 Operation of the UTIMER "■ Calculation of Baud Rate" was changed. ("Note:" was added.) 348 10.3 Operation of the External Interrupt and NMI Controller "■ Operating Procedure for an External Interrupt" was changed. ("1. Terminal and general-purpose I/O port used as external interrupt input are set to input port." was added.) 384 13.3 8-bit D/A Converter Operation "Table 13.3-1 Logical Expressions for D/A Converter Output Voltage" was changed. (Values specified in DADR1 DADR2 DADR3 → Values specified in DADR0 DADR1 DADR2) 413, 414 14.2.2 Serial I/O Interface Registers "[Bits 15, 14, and 13] Shift clock selection bits (SMD2, SMD1, SMD0: Serial shift clock mode)" was changed. 450 15.2.2 Bus Control Register (IBCR) "[Bit 12] MSS (Master Slave Select)" was changed. ("Note:" was changed.) "■ Bus Control Register (IBCR)" was changed. ("Note:" was changed.) 451 to 454 479 16.2.1 DMAC ch0 to ch4 Control/Status Registers A "■ [Bits 28 to 24] IS4 to 0 (Input Select)*: Transfer Source Selection" was changed. xii Page 494 534 536 Changes (For details, refer to main body.) 16.3.1 Overview of Operation "● Fly-by transfer (I/O → memory)" was changed. 17.1 Outline of Flash Memory "Summary of 17.1 Outline of Flash Memory" was changed. 537, 538 (Access areas used for MB91350A fly-by transfer must be external areas. → Access areas used for MB91F355A/F356B/F357B/355A fly-by transfer must be external areas.) "Figure 17.1-3 Memory Map of MB91F356B Flash Memory" was added. "■ Sector Address Table of Flash Memory" was changed. 544 17.2.2 Flash Memory Wait Register (FLWC) "[Bits 2 to 0] WTC2, WTC1, and WTC0 (wait cycle bits)" was changed. 559 17.5.2 Data Writing "■ How to Specify Address" was changed. 568 18.1 Basic Configuration of MB91F355A/F353A/ F356B/F357B Serial Programming Connection "■ Basic Configuration of MB91F355A/F353A/F356B/F357B Serial Programming Connection" was changed. ("Either a program operating in single-chip mode or a program operating in internal ROM external bus mode is selected to write." was added.) 569 18.2 Pins Used for Fujitsu Standard Serial Onboard Writing "Table 18.2-1 Function of Pins Used for Fujitsu Standard Serial Onboard Writing" was changed. 573 18.5 Other Precautionary Information "● Oscillation Clock Frequency" was changed. (4.0 MHz and 12.0 MHz → 10.0 MHz and 12.5 MHz) "● Port State for Write Operations on Flash Memory" was changed. (reset state except → initial state in the single-chip mode except) 584 APPENDIX A I/O Map "Address 00009CH of Table A-1 I/O Map" was changed. ("*1" was added.) The vertical lines marked in the left side of the page show the changes. xiii xiv CHAPTER 1 OVERVIEW The FR family is a standard single-chip microcontroller that has a 32-bit high-performance RISC CPU as well as internal I/O resources and bus control configuration for embedded controllers that require high-performance or high-speed CPU processing. This model is an FR60 family model that is based on the FR30/40 family of CPUs, and offers enhanced bus access. The FR family is a single-chip microcontroller with built-in peripheral resources. 1.1 Features 1.2 Block Diagram 1.3 Package Dimensions 1.4 Pin Layout 1.5 List of Pin Functions 1.6 Input-output Circuit Forms 1 CHAPTER 1 OVERVIEW 1.1 Features This section describes the features of the FR60 family microcontrollers. ■ FR CPU Features • 32-bit RISC, load/store architecture, five stages pipeline • Maximum operating frequency of 50 MHz [PLL used: Oscillation at 12.5 MHz] • 16-bit fixed-length instructions (basic instructions), one instruction per cycle • Memory-to-memory transfer, bit processing, instructions including barrel shift, etc.--instructions appropriate for embedded applications • Function entry and exit instructions, multi load/store instructions of register content--instructions compatible with high-level languages • Register interlock function to facilitate assembly-language coding • Built-in multiplier/instruction-level support • Signed 32-bit multiplication: 5 cycles • Signed 16-bit multiplication: 3 cycles • Interrupts (saving of PC and PS): 6 cycles, 16 priority levels • Harvard architecture enabling simultaneous execution of both program access and data access • Instructions compatible with the FR family ■ Bus Interface • Maximum operating frequency of 25 MHz • 24-bit address full output (16M bytes space) capability (21-bit address full output (2M bytes space) capability: MB91F353A/351A/352A/353A) • 8/16-bit data output • Prefetch buffer installed • Use of unused data/address pins as general-purpose I/O ports • Totally independent 4-area chip select outputs that can be configured in units as small as 64K bytes • Supported interface for each type of memory SRAM and ROM/FLASH Page mode FLASHROM and page mode ROM interface • Basic bus cycle (2 cycles) • Automatic wait cycle generator that can be programmed for each area and can insert waits. • External wait cycle using RDY input • DMA support of fly-by transfer capable of wait control for independent I/O (The MB91F353A/351A/352A/353A does not support fly-by transfer.) 2 ■ Internal Memory Table 1.1-1 provides details about internal memory. Table 1.1-1 Internal Memory Details Memory MB91V350A MB91F355A MB91F356B MB91F357B MB91355A MB91354A MB91F353A MB91353A MB91352A MB91351A None 512K bytes 256K bytes 512K bytes 512K bytes 384K bytes 512K bytes 512K bytes 384K bytes 384K bytes Stack RAM 16K bytes 16K bytes 16K bytes 16K bytes 16K bytes 8K bytes 16K bytes 16K bytes 8K bytes 16K bytes Instruction RAM 16K bytes 8K bytes 8K bytes 8K bytes 8K bytes 8K bytes 8K bytes 8K bytes 8K bytes 8K bytes ROM ■ DMAC (DMA Controller) • Up to 5 channels can operate simultaneously (3 channels for external → external) • Three transfer sources (external pins, built-in peripherals, and software) • Selectability of activation source using software (activation can be from UART0, UART1, and UART2). • Addressing mode with 32-bit full address specifications (increase, decrease, fixed) • Transfer modes (demand transfer, burst transfer, step transfer, block transfer) • Fly-by transfer supported between external I/O and memory • Transfer data size that can be selected from 8, 16, and 32 bits • Multibyte transfer supported (defined by software) • DMAC descriptor I/O area (200 to 240H and 1000H to 1024H) (The MB91F353A/351A/352A/353A does not have an external interface.) External pin transfer is not supported. Demand transfer and fly-by transfer cannot be used. ■ Bit Search Module (Used by REALOS) • Searches for the position of the first bit varying between 1 and 0 in the MSB of a word ■ Various Timers • 16-bit reload timer; 4 channels (including 1 channel for REALOS) The internal clock can be selected using divide by 2, 8, or 32. (For ch3, divide by 64 or 128 can also be selected.) • 16-bit free-running timer; 1 channel Output compare: 8 channels (MB91F353A/351A/352A/353A: 2 channels) Input capture: 4 channels • 16-bit PPG timer: 6 channels (MB91F353A/351A/352A/353A: 3 channels) 3 CHAPTER 1 OVERVIEW ■ UART • UART full-duplex double buffer • 5 channels, (MB91F353A/351A/352A/353A: 4 channels) • Parity or no parity can be selected. • Either asynchronous (start-stop synchronization) or CLK synchronous communication can be selected. • Built-in timer for dedicated baud rates • An external clock can be used as the transfer clock. • Plentiful error detection functions (parity, frame, overrun) • 115 kbps supported • 8-bit data serial transfer • 3 channels, (MB91F353A/351A/352A/353A: 2 channels) • A shift clock can be selected from three internal types and one external type. • The shift direction can be switched between LSB and MSB. ■ SIO ■ Interrupt Controller • Total number of external interrupts: 17 (MB91F353A/351A/352A/353A: (9)) [One non-maskable interrupt pin and 16 (8) ordinary interrupt pins that can be used for wakeup in stop mode.] • Interrupts from internal peripherals • Priority level can be defined as programmable (16 levels) except for the unmaskable pin ■ D/A Converter • 8-bit resolution: 3 channels (MB91F353A/351A/352A/353A: 2 channels) ■ A/D Converter • 10-bit resolution: 12 channels (MB91F353A/351A/352A/353A: 8 channels) • Serial-parallel conversion type Conversion time: About 1.48 µs • Conversion modes (single conversion mode and continuous conversion mode) • Activation sources (software, external trigger, and peripheral interrupt) ■ Other Interval Timers and Counters • 8/16-bit up/down counter Note: The MB91F353A/351A/352A/353A supports only an 8-bit up/down counter. 4 • 16-bit timer (U-TIMER), 5 channels, (MB91F353A/351A/352A/353A: 4 channels) • Watchdog timer ■ I2C* Bus Interface (400 kbps Supported) • 1 channel master/slave send and receive - Arbitration function and clock synchronization function ■ I/O Ports • 3 V I/O ports (5 V input is supported for those ports that are also used for external interrupts (16 ports, MB91F353A/ 351A/352A/353A: 8 ports). • Up to 126 ports (MB91F353A/351A/352A/353A: Up to 84 ports) ■ Other Features • Internal oscillation circuit as a clock source provided. PLL multiplication can also be selected. • INIT is provided as a reset pin. (When the INIT pin is cleared, CPU operation starts immediately without waiting for oscillation to stabilize.) • Additionally, a watchdog timer reset and software resets are provided. • Stop mode and sleep mode supported as low-power consumption modes Low-power consumption operation using 32 kHz CPU operation enabled • Gear function • Built-in timebase timer • Package: MB91F355A/F356B/F357B/355A/354A: LQFP-176 (lead pitch 0.50 mm) MB91F353A/351A/352A/353A: LQFP-120 (lead pitch 0.50 mm) • CMOS technology: 0.35 µm • Supply voltage: 3.3 V (-0.3 V to +0.3 V) *: I2C license Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. 5 CHAPTER 1 OVERVIEW ■ Comparison of Functions Table 1.1-2 compares the functions of FR60 family microcontrollers. Table 1.1-2 Comparison of Functions: Internal Memory (Products whose Memory Capacity is to be Extended and the Configuration of Memory are Currently under Study.) MB91F355A MB91355A MB91F356B MB91F357B MB91354A MB91F353A MB91353A MB91352A MB91351A None 512K bytes 256K bytes 384K bytes 512K bytes 384K bytes 384K bytes Stack RAM 16K bytes 16K bytes 16K bytes 8K bytes 16K bytes 8K bytes 16K bytes Instruction RAM 16K bytes 8K bytes 8K bytes 8K bytes 8K bytes 8K bytes 8K bytes DMAC 5ch 5ch 5ch 5ch 5ch 5ch 5ch A/D input 12ch 12ch 12ch 12ch 8ch 8ch 8ch D/A input 3ch 3ch 3ch 3ch 2ch 2ch 2ch UART 5ch 5ch 5ch 5ch 4ch 4ch 4ch U-TIMER 5ch 5ch 5ch 5ch 4ch 4ch 4ch SIO 3ch 3ch 3ch 3ch 2ch 2ch 2ch External interrupt 16ch 16ch 16ch 16ch 8ch 8ch 8ch Free-running timer 1ch 1ch 1ch 1ch 1ch 1ch 1ch PPG 6ch 6ch 6ch 6ch 3ch 3ch 3ch Reload timer 4ch 4ch 4ch 4ch 4ch 4ch 4ch Input capture 4ch 4ch 4ch 4ch 4ch 4ch 4ch Output compare 8ch 8ch 8ch 8ch 2ch 2ch 2ch 8-bit up/down counter 2ch 2ch 2ch 2ch 1ch 1ch 1ch I2C 1ch 1ch 1ch 1ch 1ch 1ch 1ch Number of pins 279 176 176 176 120 120 120 Function ROM 6 MB91V350A 1.2 Block Diagram Figure 1.2-1 is a block diagram of the MB91F353A/353A/352A/351A. Figure 1.2-2 is a block diagram of the MB91355A/354A/F355A/F356B/F357B. ■ MB91F353A/353A/352A/351A Block Diagram Figure 1.2-1 MB91F353A/353A/352A/351A Block Diagram FR CPU Core 32 32 DMAC (5 channels) Bit search Stack RAM ROM/Flash A20 to 00 D31 to 16 Bus converter RAM (Instruction execution enabled) X0, X1 MD0 to 2 INIT X0A, X1A Clock control 32 32 32 16 adapter Watch timer 16 External interrupt (8 channels) SI0 to 7 SO0 to 7 SCK0 to 7 UART (4 channels) RD WR1, WR0 RDY BRQ BGRNT SYSCLK PORT Interrupt controller INT0 to 7 NMI External memory interface 16-bit PPG (3 channels) TRG0 to 4 PPG0, 2, 4 Reload timer (4 channels) Free-running timer U-TIMER (4 channels) SI6, 7 SO6, 7 SCK6, 7 PORT SIO (2 channels) FRCK Input capture (4 channels) IN0 to 3 Output compare (2 channels) OC0, 2 AN0 to 7 ATG AVRH, AVCC AVSS, AVRL DA0 to 1 DAVC, DAVS A/D (8 channels) I2C (1 channel) SDA SCL Up/down counter (1 channel) AIN0 BIN0 ZIN0 D/A (2 channels) MB91F353A MB91353A MB91352A MB91351A Flash 512K bytes 512K bytes 384K bytes 384K bytes RAM (Stack) 16K bytes 16K bytes 8K bytes 16K bytes RAM (Instruction execution enabled) 8K bytes 8K bytes 8K bytes 8K bytes ROM/Flash 7 CHAPTER 1 OVERVIEW ■ MB91355A/354A/F355A/F356B/F357B Block Diagram Figure 1.2-2 MB91355A/354A/F355A/F356B/F357B Block Diagram FR CPU Core 32 32 Bit search DMAC (5 channels) DREQ0 to 2 DACK0 to 2 EOP/DSTP to 2 IOWR IORD Stack RAM ROM/Flash 512KB (F356B only : 256 KB) RAM (Instruction execution enabled) X0, X1 MD0 to 2 Clock control INIT X0A, X1A 32 32 External memory interface 32 16 adapter RD WR1, WR0 RDY BRQ BGRNT SYSCLK Watch timer PORT 16 Interrupt controller 16-bit PPG (6 channels) INT0 to 15 NMI External interrupt (16 channels) SI0 to 4 SO0 to 4 SCK0 to 4 UART (5 channels) Reload timer (4 channels) U-TIMER (5 channels) SI5 to 7 SO5 to 7 SCK5 to 7 AN0 to 11 ATG AVRH, AVCC AVSS, AVRL DA0 to 2 DAVC, DAVS 8 A23 to 00 D31 to 16 Bus converter TRG0 to 5 PPG0 to 5 TOT0 to 3 Free-running timer FRCK Input capture (4 channels) IN0 to 3 Output compare (2 channels) SIO (3 channels) PORT OC0 to 7 A/D (12 channels) I2C (1 channel) SDA SCL D/A (3 channels) Up/down counter (1 channel) AIN0, 1 BIN0, 1 ZIN0, 1 MB91F355A MB91F356B MB91F357B MB91355A MB91354A ROM/Flash Flash 512K bytes Flash 256K bytes Flash 512K bytes 512K bytes 384K bytes RAM (Stack) 16K bytes 16K bytes 16K bytes 16K bytes 8K bytes RAM (Instruction execution enabled) 8K bytes 8K bytes 8K bytes 8K bytes 8K bytes 1.3 Package Dimensions Figure 1.3-1 and show the package dimensions. ■ MB91F355/354A/355A/F356B/F357B Package Dimensions (Reference Diagram) Consult your customer representative for the formal version. Figure 1.3-1 MB91F355/354A/355A/F356B/F357B Package Dimensions 176-pin plastic LQFP (FPT-176P-M02) 176-pin plastic LQFP (FPT-176P-M02) Lead pitch 0.50 mm Package width × package length 24.0 × 24.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 1.86g Code (Reference) P-LFQFP176-24×24-0.50 Note 1) * : Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness Note 3) Pins width do not include tie bar cutting remainder. 26.00±0.20(1.024±.008)SQ * 24.00±0.10(.945±.004)SQ 0.145±0.055 (.006±.002) 132 89 133 88 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 .059 –.004 0˚~8˚ (Mounting height) 0.10±0.10 (.004±.004) (Stand off) INDEX 176 45 "A" LEAD No. 1 44 0.50(.020) C 2003 FUJITSU LIMITED F176006S-c-4-6 0.22±0.05 (.009±.002) 0.08(.003) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) M Dimensions in mm (inches). Note: The values in parentheses are reference values. 9 CHAPTER 1 OVERVIEW ■ MB91F353A/351A/352A/353A Package Dimensions Figure 1.3-2 MB91F353A/351A/352A/353A Package Dimensions 120-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 16.0 × 16.0 mm Lead shape Gullwing Sealing method Plastic mold M ounting height 1.70 mm MAX Weight 0.88 g Code (Reference) P-LFQFP120-16×16-0.50 (FPT-120P-M21) 120-pin plastic LQFP (FPT-120P-M21) Note 1) * : These dimensions do not include resin protrusion. Resin protrusion is +0.25(.010) MAX(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 18.00±0.20(.709±.008)SQ +0.40 * 16.00 –0.10 .630 +.016 –.004 SQ 90 61 91 60 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 INDEX 0~8˚ 120 LEAD No. 1 30 0.50(.020) C 10 "A" 31 2002 FUJITSU LIMITED F120033S-c-4-4 0.22±0.05 (.009±.002) 0.08(.003) M 0.145 .006 +0.05 –0.03 +.002 –.001 0.60±0.15 (.024±.006) 0.10±0.05 (.004±.002) (Stand off) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values. 1.4 Pin Layout Figure 1.4-1 , Figure 1.4-2 show the FR60 family pin layouts. ■ Pin Layout of the MB91F355A/354A/355A/F356B/F357B The installed package is FPT-176P-M02. 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PG4/SO5 PG3/SI5 PG2/SCK4 PG1/SO4 PG0/SI4 PH5/SCK3 PH4/SO3 PH3/SI3 PH2/SCK2 PH1/SO2 PH0/SI2 PI5/SCK1 PI4/SO1 PI3/SI1 PI2/SCK0 PI1/SO0 PI0/SI0 VCC VSS PJ7/INT15 PJ6/INT14 PJ5/INT13 PJ4/INT12 PJ3/INT11 PJ2/INT10 PJ1/INT9 PJ0/INT8 PK7/INT7/ATG PK6/INT6/FRCK PK5/INT5 PK4/INT4 PK3/INT3 PK2/INT2 PK1/INT1 PK0/INT0 VCC VSS PL1/SCL PL0/SDA VSS PM5/SCK7/ZIN1/TRG5 PM4/SO7/BIN1/TRG4 PM3/SI7/AIN1/TRG3 PM2/SCK6/ZIN0/TRG2 Figure 1.4-1 Pin Layout of the MB91F355A/354A/355A/F356B/F357B MB91F355A/MB91355A/MB91354A/ MB91F356B/MB91F357B TOP VIEW (LQFP176) 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 PM1/SO6/BIN0/TRG1 PM0/SI6/AIN0/TRG0 PN5/PPG5 PN4/PPG4 PN3/PPG3 PN2/PPG2 PN1/PPG1 PN0/PPG0 VCC VSS PO7/OC7 PO6/OC6 PO5/OC5 PO4/OC4 PO3/OC3 PO2/OC2 PO1/OC1 PO0/OC0 PP3/TOT3 PP2/TOT2 PP1/TOT1 PP0/TOT0 VCC VSS AVSS/AVRL AVRH AVCC AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 DA2 DA1 DA0 DAVC DAVS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 P30/D24 P31/D25 P32/D26 P33/D27 P34/D28 P35/D29 P36/D30 P37/D31 VSS VCC P40/A00 P41/A01 P42/A02 P43/A03 P44/A04 P45/A05 P46/A06 P47/A07 P50/A08 P51/A09 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 VSS VCC P60/A16 P61/A17 P62/A18 P63/A19 P64/A20 P65/A21 P66/A22 P67/A23 PG5/SCK5 NMI X1A Vss X0A MD2 MD1 MD0 X0 Vcc X1 INIT Vss Vcc PC0/DREQ2 PC1/DACK2 PC2/DSTP2/DEOP2 PB0/DREQ0 PB1/DACK0 PB2/DSTP0/DEOP0 PB3/DREQ1 PB4/DACK1 PB5/DSTP1/DEOP1 PB6/IOWR PB7/IORD A0/CS0 PA1/CS1 PA2/CS2 PA3/CS3 VSS VCC P80/IN0/RDY P81/IN1/BGRNT P82/IN2/BRQ P83/RD P84/WR0 P85/IN3/WR1 P90/SYSCLK P91 P92/MCLK P93 P94/AS VSS VCC 11 CHAPTER 1 OVERVIEW ■ Pin Layout of the MB91F353A/351A/352A/353A The installed package is FPT-120P-M21. 91 92 93 94 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 95 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 MB91F353A/MB91351A/ MB91352A/MB91353A 10 11 12 13 14 15 16 TOP VIEW 17 18 19 20 21 22 23 24 (LQFP-120) 25 26 27 28 29 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P54/A12 P55/A13 P56/A14 P57/A15 P60/A16 P61/A17 P62/A18 P63/A19 P64/A20 VSS PL1/SCL PL0/SDA VSS VCC P80/IN0/RDY P81/IN1/BGRNT P82/IN2/BRQ P83/RD P84/WR0 P85/IN3/WR1 NMI MD2 MD1 MD0 INIT VCC X1 X0 VSS X0A 32 30 31 P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 P30/D24 P31/D25 P32/D26 P33/D27 P34/D28 P35/D29 P36/D30 P37/D31 P40/A00 VSS VCC P41/A01 P42/A02 P43/A03 P44/A04 P45/A05 P46/A06 P47/A07 P50/A08 P51/A09 P52/A10 P53/A11 119 120 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VSS AVSS/AVRL AVRH AVCC DAVC DAVS DA0 DA1 PH5/SCK3 PH4/SO3 PH3/SI3 PH2/SCK2 PH1/SO2 PH0/SI2 PO2/OC2 PO0/OC0 VSS VCC PI5/SCK1 PI4/SO1 PI3/SI1 PI2/SCK0 Figure 1.4-2 Pin Layout of the MB91F353A/351A/352A/353A 12 PI1/SO0 PI0/SI0 PK7/INT7/ATG PK6/INT6/FRCK PK5/INT5 PK4/INT4 PK3/INT3 PK2/INT2 PK1/INT1 PK0/INT0 PM5/SCK7 PM4/SO7/TRG4 PM3/SI7/TRG3 VCC VSS PM2/SCK6/ZIN0/TRG2 PM1/SO6/BIN0/TRG1 PM0/SI6/AIN0/TRG0 PN4/PPG4 PN2/PPG2 PN0/PPG0 PA3/CS3 PA2/CS2 PA1/CS1 PA0/CS0 P94/AS P93 P91 P90/SYSCLK X1A 1.5 List of Pin Functions Table 1.5-1 lists the functions of the pins. Table 1.5-2 lists the power supply and GND pins. See Figure 1.4-1 , Figure 1.4-2 for the pin layouts. ■ List of Pin Functions Table 1.5-1 Pin Functions (1 / 13) Pin number Pin name 176 pins 120 pins I/O circuit type D16 to D23 1 to 8 9 to 16 19 to 26 27 to 34 37 to 41 42 to 44 1 to 8 C Function Bits 16 to 23 of the external data bus. Valid only in external bus mode. P20 to P27 Can be used as a port in external bus 8-bit mode. D24 to D31 Bits 24 to 31 of the external data bus. Valid only in external bus mode. 9 to 16 C P30 to P37 Can be used as a port in single-chip mode. A00 to A07 Bits 0 to 7 of the external address bus. Valid only in external bus mode. 17,20 to 26 C P40 to P47 Can be used as a port in single-chip mode. A08 to A15 Bits 8 to 15 of the external address bus. Valid only in external bus mode. 27 to 34 C P50 to P57 Can be used as a port in single-chip mode. A16 to A20 Bits 16 to 20 of the external address bus. Valid only in external bus mode. 35 to 39 C P60 to P64 Can be used as a port in single-chip mode or when an external address bus is not used. A21 to A23 Bits 21 to 23 of the external address bus. Valid only in external bus mode. - C Can be used as a port in single-chip mode or when an external address bus is not used. P65 to P67 47, 48 106,105 DA0, DA1 - D/A converter output pin 49 - DA2 - D/A converter output pin 50 to 57 113 to 120 AN0 to AN7 G Analog input pin 58 to 61 - AN8 to AN11 G Analog input pin TOT0 to TOT3 67 to 70 - [TOT0 to TOT3] are reload timer output ports. This function is valid when timer output is enabled. D PP0 to PP3 [PP0 to PP3] are general-purpose I/O ports. This function is valid when the timer output function is disabled. 13 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Functions (2 / 13) Pin number Pin name 176 pins 120 pins I/O circuit type OC0 71 72 73 [OC0] is an output compare output pin. PO0 [PO0] is a general-purpose I/O port. This function can be used as a port when output compare output is not used. OC1 [OC1] is an output compare output pin. 97 D PO1 [PO1] is a general-purpose I/O port. This function can be used as a port when output compare output is not used. OC2 [OC2] is an output compare output pin. - D 98 D PO2 OC3 to OC7 74 to 78 - D PPG0 82 83 84 85 86 [PO3 to PO7] are general-purpose I/O ports. This function can be used as a port when output compare output is not used. [PPG0] is a PPG timer output pin. PN0 [PN0] is a general-purpose I/O port. This function can be used as a port when PPG timer output is not used. PPG1 [PPG1] is a PPG timer output pin. 70 D PN1 [PN1] is a general-purpose I/O port. This function can be used as a port when PPG timer output is not used. PPG2 [PPG2] is a PPG timer output pin. - D PN2 [PN2] is a general-purpose I/O port. This function can be used as a port when PPG timer output is not used. PPG3 [PPG3] is a PPG timer output pin. 71 D PN3 [PN3] is a general-purpose I/O port. This function can be used as a port when PPG timer output is not used. PPG4 [PPG4] is a PPG timer output pin. - D PN4 [PN4] is a general-purpose I/O port. This function can be used as a port when PPG timer output is not used. PPG5 [PPG5] is a PPG timer output pin. 72 D - D PN5 14 [PO2] is a general-purpose I/O port. This function can be used as a port when output compare output is not used. [OC3 to OC7] are output compare output pins. PO3 to PO7 81 Function [PN5] is a general-purpose I/O port. This function can be used as a port when PPG timer output is not used. Table 1.5-1 Pin Functions (3 / 13) Pin number Pin name 176 pins 120 pins I/O circuit type [SI6] is data input for serial I/O6. Since this input is always used when serial I/O6 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. SI6 AIN0 87 88 89 73 Function D [AIN0] is input for the up/down timer. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. TRG0 [TRG0] is external trigger input for PPG timer 0. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. PM0 [PM0] is a general-purpose I/O port. This function can be used as a port when serial I/O, up/ down timer, and PPG timer output are not used. SO6 [SO6] is data output from serial I/O6. This function is valid when data output from serial I/O6 is allowed. BIN0 [BIN0] is input for the up/down timer. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. 74 D TRG1 [TRG1] is external trigger input for PPG timer 1. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. PM1 [PM1] is a general-purpose I/O port. This function can be used as a port when serial I/O, up/ down timer, and PPG timer output are not used. SCK6 [SCK6] is clock I/O for serial I/O6. This function is valid when clock output from serial I/O6 is allowed or when external shift clock input is used. ZIN0 [ZIN0] is input for the up/down timer. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. 75 D TRG2 [TRG2] is external trigger input for PPG timer 2. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. PM2 [PM2] is a general-purpose I/O port. This function can be used as a port when serial I/O, up/ down timer, and PPG timer output are not used. 15 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Functions (4 / 13) Pin number Pin name 176 pins 120 pins I/O circuit type [SI7] is data input for serial I/O7. Since this input is always used when serial I/O7 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. SI7 AIN1* 90 78 D 16 [AIN1] is input for the up/down timer. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. *: The 120-pin version does not support this function. TRG3 [TRG3] is external trigger input for PPG timer 3. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. PM3 [PM3] is a general-purpose I/O port. This function can be used as a port when serial I/O, up/ down timer, and PPG timer output are not used. S07 [S07] is data output from serial I/O7. This function is valid when data output from serial I/O7 is allowed. BIN1* 91 Function 79 D [BIN1] is input for the up/down timer. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. * : The 120-pin version does not support this function. TRG4 [TRG4] is external trigger input for PPG timer 4. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. PM4 [PM4] is a general-purpose I/O port. This function can be used as a port when serial I/O, up/ down timer, and PPG timer output are not used. Table 1.5-1 Pin Functions (5 / 13) Pin number Pin name 176 pins 92 94 95 98 to 103 120 pins I/O circuit type Function SCK7 [SCK7] is clock I/O for serial I/O7. This function is valid when clock output from serial I/O7 is allowed or when external shift clock input is used. ZIN1* [ZIN1] is input for the up/down timer. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. *: The 120-pin version does not support this function. 80 D TRG5* [TRG5] is external trigger input for PPG timer 5. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. * : The 120-pin version does not support this function. PM5 [PM5] is a general-purpose I/O port. This function can be used as a port when serial I/O, up/ down timer, and PPG timer output are not used. SDA [SDA] is a DATA I/O pin for the I2C bus. This function is valid when the I2C is allowed to operate in standard mode. Output using the port must be stopped beforehand unless this operation is intended (open drain output). 42 F PL0 [PL0] is a general-purpose I/O port. This function can be used as a port when I2C operation is not allowed (open drain output). SCL [SCL] is a CLK I/O pin for the I2C bus. This function is valid when the I2C is allowed to operate in standard mode. Output using the port must be stopped beforehand unless this operation is intended (open drain output). F 41 PL1 [PL1] is a general-purpose I/O port. This function can be used as a port when I2C operation is not allowed (open drain output). INT0 to INT5 [INT0 to INT5] are external interrupt input. Since this input is always used when the corresponding external interrupt is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. 81 to 86 E PK0 to PK5 [PK0 to PK5] are general-purpose I/O ports. 17 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Functions (6 / 13) Pin number Pin name 176 pins 120 pins I/O circuit type [INT6] is external interrupt input. Since this input is always used when the corresponding external interrupt is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. INT6 104 87 E FRCK 105 106 to 113 [PK6] is a general-purpose I/O port. INT7 [INT7] is external interrupt input. Since this input is always used when the corresponding external interrupt is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. ATG [ATG] is external trigger for the A/D converter. Since this input is always used when it is selected as the source of A/D activation, output using the port must be stopped beforehand unless this operation is the intended operation. PK7 [PK7] is a general-purpose I/O port. E INT8 to INT15 E PJ0 to PJ7 117 89 D [SI0] is data input for UART0. Since this input is always used when UART0 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. PI0 [PI0] is a general-purpose I/O port. SO0 [SO0] is data output from UART0. This function is valid when UART0 data output is allowed. 90 D PI1 18 [INT8 to INT15] are external interrupt input. Since this input is always used when the corresponding external interrupt is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. [PJ0 to PJ7] are general-purpose I/O ports. SI0 116 [FRCK] is external clock input pin for the free-running timer. Since this input is always used when it is selected as external clock input for the free-running timer, output using the port must be stopped beforehand unless this operation is the intended operation. PK6 88 - Function [PI1] is a general-purpose I/O port. This function is valid when UART0 data output is not allowed. Table 1.5-1 Pin Functions (7 / 13) Pin number Pin name 176 pins 120 pins I/O circuit type [SCK0] is clock I/O for UART0. This function is valid when UART0 clock output is allowed or when external clock input is used. SCK0 118 119 120 91 D PI2 [PI2] is a general-purpose I/O port. This function is valid when UART0 clock output is not allowed or when external clock input is not used. SI1 [SI1] is data input for UART1. Since this input is always used when UART1 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. 92 D PI3 [PI3] is a general-purpose I/O port. SO1 [SO1] is data output from UART1. This function is valid when UART1 data output is allowed. 93 D PI4 122 123 94 D PI5 [PI5] is a general-purpose I/O port. This function is valid when UART1 clock output is not allowed or when external clock input is not used. SI2 [SI2] is data input for UART2. Since this input is always used when UART2 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. 99 D PH0 [PH0] is a general-purpose I/O port. SO2 [SO2] is data output from UART2. This function is valid when UART2 data output is allowed. 100 D PH1 101 [PH1] is a general-purpose I/O port. This function is valid when UART2 data output is not allowed or when external shift clock input is used. [SCK2] is clock I/O for UART2. This function is valid when UART2 clock output is allowed or when external clock input is used. SCK2 124 [PI4] is a general-purpose I/O port. This function is valid when UART1 data output is not allowed. [SCK1] is clock I/O for UART1. This function is valid when UART1 clock output is allowed or when external clock input is used. SCK1 121 Function D PH2 [PH2] is a general-purpose I/O port. This function is valid when UART2 clock output is not allowed or when external clock input is not used. 19 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Functions (8 / 13) Pin number Pin name 176 pins 120 pins I/O circuit type SI3 125 126 102 D [PH3] is a general-purpose I/O port. SO3 [SO3] is data output from UART3. This function is valid when UART3 data output is allowed. 103 D 129 104 D PH5 [PH5] is a general-purpose I/O port. This function is valid when UART3 clock output is not allowed or when external clock input is not used. SI4 [SI4] is data input for UART4. Since this input is always used when UART4 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. - D PG0 [PG0] is a general-purpose I/O port. SO4 [SO4] is data output from UART4. This function is valid when serial I/O4 data output is allowed. - D [PG1] is a general-purpose I/O port. This function is valid when serial I/O4 data output is not allowed. PG1 [SCK4] is clock I/O for UART4. This function is valid when serial I/O4 clock output is allowed or when external clock input is used. SCK4 130 131 - D PG2 [PG2] is a general-purpose I/O port This function is valid when serial I/O4 clock output is not allowed or when external clock input is not used. SI5 [SI5] is data input for serial I/O5. Since this input is always used when serial I/O5 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. - D PG3 20 [PH4] is a general-purpose I/O port. This function is valid when UART3 data output is not allowed. [SCK3] is clock I/O for UART3. This function is valid when UART3 clock output is allowed or when external clock input is used. SCK3 128 [SI3] is data input for UART3. Since this input is always used when UART3 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. PH3 PH4 127 Function [PG3] is a general-purpose I/O port. Table 1.5-1 Pin Functions (9 / 13) Pin number Pin name 176 pins 120 pins I/O circuit type [SO5] is data output from serial I/O5. This function is valid when serial I/O5 data output is allowed. SO5 132 - D [PG4] is a general-purpose I/O port. This function is valid when serial I/O5 data output is not allowed. PG4 [SCK5] is clock I/O for serial I/O5. This function is valid when serial I/O5 clock output is allowed or when external shift clock input is used. SCK5 133 Function - D [PG5] is a general-purpose I/O port. This function is valid when serial I/O5 clock output is not allowed or when external clock input is not used. PG5 134 51 NMI H NMI (non-maskable interrupt) input 135 61 X1A B Clock (oscillation) output (subclock) 137 60 X0A B Clock (oscillation) input (subclock) H [MD2 to MD0] are mode pins 2 to 0. These pins set the basic operating mode. Connect the pins to VCC or VSS. Input circuit type: • The production version (mask ROM version) is the "H" type. • The flash ROM version is the "J" type. 138 to 140 52 to 54 MD2 to MD0 J 141 58 X0 A Clock (oscillation) input (main clock) 143 57 X1 A Clock (oscillation) output (main clock) 144 55 INIT I External reset input DREQ2 147 - C PC0 [PC0] is a general-purpose I/O port. DACK2 148 - C PC1 [DREQ2] is DMA external transfer request input. Since this input is always used when it is selected as the source of DMA activation, output using the port must be stopped beforehand unless this operation is the intended operation. [DACK2] is DMA external transfer request acceptance output. This function is valid when DMA transfer request acceptance output is allowed. [PC1] is a general-purpose I/O port. This function is valid when DMA transfer request acceptance output is allowed. 21 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Functions (10 / 13) Pin number Pin name 176 pins 120 pins I/O circuit type [DEOP2] is DMA external transfer end output. This function is valid when DMA external transfer end output is allowed. DEOP2 149 - DSTP2 C DREQ0 - C PB0 - C [DEOP0] is DMA external transfer end output. This function is valid when DMA external transfer end output is allowed. DEOP0 - DSTP0 C DREQ1 - C PB3 22 [DSTP0] is DMA external transfer stop input. This function is valid when DMA external transfer stop input is allowed. [PB2] is a general-purpose I/O port. This function is valid when DMA external transfer end output and external transfer stop input are not allowed. PB2 153 [DACK0] is DMA external transfer request acceptance output. This function is valid when DMA transfer request acceptance output is allowed. [PB1] is a general-purpose I/O port. This function is valid when DMA transfer request acceptance output is not allowed. PB1 152 [DREQ0] is DMA external transfer request input. Since this input is always used when it is selected as the source of DMA activation, output using the port must be stopped beforehand unless this operation is the intended operation. [PB0] is a general-purpose I/O port. DACK0 151 [DSTP2] is DMA external transfer stop input. This function is valid when DMA external transfer stop input is allowed. [PC2] is a general-purpose I/O port. This function is valid when DMA external transfer end output and external transfer stop input are not allowed. PC2 150 Function [DREQ1] is DMA external transfer request input. Since this input is always used when it is selected as the source of DMA activation, output using the port must be stopped beforehand unless this operation is the intended operation. [PB3] is a general-purpose I/O port. Table 1.5-1 Pin Functions (11 / 13) Pin number Pin name 176 pins 120 pins I/O circuit type DACK1 154 - C [DEOP1] is DMA external transfer end output. This function is valid when DMA external transfer end output is allowed. DEOP1 - DSTP1 C [IOWR] is write strobe output for DMA fly-by transfer. This function is valid when write strobe output for DMA fly-by transfer is allowed. IOWR - C [PB6] is a general-purpose I/O port. This function is valid when write strobe output for DMA fly-by transfer is not allowed. PB6 [IORD] is read strobe output for DMA fly-by transfer. This function is valid when read strobe output for DMA flyby transfer is allowed. IORD 157 158 159 160 [DSTP1] is DMA external transfer stop input. This function is valid when DMA external transfer stop input is allowed. [PB5] is a general-purpose I/O port. This function is valid when DMA external transfer end output and external transfer stop input are not allowed. PB5 156 [DACK1] is DMA external transfer request acceptance output. This function is valid when DMA transfer request acceptance output is allowed. [PB4] is a general-purpose I/O port. This function is valid when DMA external transfer request acceptance output is not allowed. PB4 155 Function C PB7 [PB7] is a general-purpose I/O port. This function is valid when read strobe output for DMA flyby transfer is not allowed. CS0 [CS0] is chip select 0 output. This function is valid in external bus mode. C 66 PA0 [PA0] is a general-purpose I/O port. This function is valid in single-chip mode. CS1 [CS1] is chip select 1 output. This function is valid when chip select 1 output is allowed. C 67 PA1 [PA1] is a general-purpose I/O port. This function is valid when chip select 1 output is not allowed. CS2 [CS2] is chip select 2 output. This function is valid when chip select 2 output is allowed. C 68 PA2 [PA2] is a general-purpose I/O port. This function is valid when chip select 2 output is not allowed. 23 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Functions (12 / 13) Pin number Pin name 176 pins 120 pins I/O circuit type [CS3] is chip select 3 output. This function is valid when chip select 3 output is allowed. CS3 161 164 165 166 167 C 69 45 46 47 PA3 [PA3] is a general-purpose I/O port. This function is valid when chip select 3 output is not allowed. RDY [RDY] is external ready input. This function is valid when external ready input is allowed. IN0 [IN0] is an input capture input pin. Since this input is always used when it is selected for input capture input, output using the port must be stopped beforehand unless this operation is the intended operation. D P80 [P80] is a general-purpose I/O port. This function is valid when external ready input is not allowed. BGRNT [BGRNT] is external bus open acceptance output. The low level is output when the external bus is open. This function is valid when output is allowed. IN1 D [IN1] is an input capture input pin. Since this input is always used when it is selected for input capture input, output using the port must be stopped beforehand unless this operation is the intended operation. P81 [P81] is a general-purpose I/O port. This function is valid when external bus open acceptance is not allowed. BRQ [BRQ] is external bus open request input. Input to the high level [1] if you want to open the external bus. This function is valid when input is allowed. IN2 D [IN2] is an input capture input pin. Since this input is always used when it is selected for input capture input, output using the port must be stopped beforehand unless this operation is the intended operation. P82 [P82] is a general-purpose I/O port. This function is valid when external bus open request is not allowed. RD [RD] is external bus read strobe output. This function is valid in external bus mode. D 48 P83 24 Function [P80] is a general-purpose I/O port. This function is valid in single-chip mode. Table 1.5-1 Pin Functions (13 / 13) Pin number Pin name 176 pins 120 pins I/O circuit type [WR0] is external bus write strobe output. This function is valid in external bus mode. WR0 168 169 170 49 50 D P84 [P80] is a general-purpose I/O port. This function is valid in single-chip mode. WR1 [WR1] is external bus write strobe output. This function is valid when WR1 output in external bus mode is allowed. IN3 [IN3] is an input capture input pin. Since this input is always used when it is selected for input capture input, output using the port must be stopped beforehand unless this operation is the intended operation. D P85 [P85] is a general-purpose I/O port. This function is valid when external bus write enable output is not allowed. SYSCLK [SYSCLK] is system clock output. This function is valid when system clock output is allowed. A clock having the same frequency as the external bus operating frequency is output (stopped in stop mode). 62 C [P90] is a general-purpose I/O port. This function is valid when system clock output is not allowed. P90 171 63 P91 C [P91] is a general-purpose I/O port. C [MCLK] is memory clock output. This function is valid when memory clock output is allowed. A clock having the same frequency as the external bus operating frequency is output (stopped in sleep mode). MCLK 172 - [P92] is a general-purpose I/O port. This function is valid when memory clock output is not allowed. P92 173 64 P93 C [P93] is a general-purpose I/O port. [AS] is address strobe output. This function is valid when address strobe output is allowed. AS 174 Function C 65 P94 [P94] is a general-purpose I/O port. This function is valid when address load output is not allowed. *: These functions are not supported for the 120-pin version. 25 CHAPTER 1 OVERVIEW Table 1.5-2 Power Supply and GND Pins Pin number Pin name 176 pins 17,35,65,79,93,96,114, 136,145,162,175 18,40,43,59,76,9 6,112 VSS 18,36,66,80,97,115,142,14 6,163,176 19,44,56,77,95 VCC 26 Function 120 pins GND pins. Use the same potential for all pins. 3.3 V power supply pins. Use the same potential for all pins. 45 107 DAVS D/A converter GND pin 46 108 DAVC D/A converter power supply pin 62 109 AVCC A/D converter analog power supply pin 63 110 AVRH A/D converter reference power supply pin 64 111 AVSS/AVRL A/D converter analog GND pin 1.6 Input-output Circuit Forms This section describes the I/O circuit types listed in Table 1.6-1 . ■ Input-Output Circuit Types Table 1.6-1 Input-Output Circuit Types (1 / 3) Classification Circuit type Remarks • Oscillation feedback resistor for highspeed operation (main clock oscillation) : About 1 MΩ • Oscillation feedback resistor for lowspeed operation (subclock oscillation) : About 7 MΩ • • CMOS level output CMOS level input X1 Clock input A X0 Standby control X1A Clock input B X0A Standby control Pull-up control Digital output C Digital output With standby control With pull-up control Pull-up resistance = about 50 kΩ (Typ) IOL = 8 mA Digital input Standby control 27 CHAPTER 1 OVERVIEW Table 1.6-1 Input-Output Circuit Types (2 / 3) Classification Circuit type Remarks Pull-up control • • CMOS level output CMOS level hysteresis input Digital output With standby control With pull-up control Pull-up resistance = about 50 kΩ (Typ) Digital output IOL = 4 mA D Digital input Standby control • • CMOS level output CMOS level hysteresis input 5 V withstand voltage Digital output IOL = 4 mA E Digital output Digital input • • Digital output F Nch open-drain output CMOS level hysteresis input With standby control 5 V withstand voltage IOL = 15 mA Digital input Standby control Analog input with switches G Analog input Control 28 Table 1.6-1 Input-Output Circuit Types (3 / 3) Classification Circuit type Remarks • CMOS level hysteresis input • CMOS level hysteresis input H Digital input With pull-up resistor Pull-up resistance = about 50 kΩ (Typ) I Digital input • CMOS level input (flash memory products only) J Control signal Mode input Diffusion resistor 29 CHAPTER 1 OVERVIEW 30 CHAPTER 2 HANDLING THE DEVICE This chapter provides precautions on handling FR family microcontrollers. 2.1 Precautions on Handling the Device 2.2 Precautions on Using the Little-Endian Area 31 CHAPTER 2 HANDLING THE DEVICE 2.1 Precautions on Handling the Device This section contains information on the prevention of latch-ups, pin processing, handling of circuits, input at power-on and so on. ■ Preventing a Latch-up A latch-up can occur if, on a CMOS IC, a voltage higher than VCC or a voltage lower than VSS is applied to an input or output pin or a voltage higher than the rating is applied between VCC and VSS. A latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the maximum rating. ■ Unused Input Pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pull-up or pull-down resistor. ■ Power Supply Pins If more than one VCC or VSS pin exists, those that must be kept at the same potential are designed to be connected to one other inside the device to prevent malfunctions such as latch-up. Be sure to connect the pins to a power supply and ground external to the device to minimize undesired electromagnetic radiation, prevent strobe signal malfunctions due to an increase in ground level, and conform to the total output current rating. Given consideration to connecting the current supply source to Vcc and VSS of the device at the lowest impedance possible. It is also recommended that a ceramic capacitor of around 0.1 µF be connected between VCC and VSS at circuit points close to the device as a bypass capacitor. ■ Quartz Oscillation Circuit Noise near the X0, X1, X0A, and X1A pins may cause the device to malfunction. Design printed circuit boards so that X0 and X1, X0A and X1A, the quartz oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as near as possible to one another. In addition, it is strongly recommended that printed circuit board artwork that surrounds the X0, X1, X0A, and X1A pins with ground be used to make stable operation more likely. ■ Note on Using an External Clock When an external clock is used, use the X0 pin unless otherwise specify and supply a negative-phase clock to the X1 pin simultaneously. Do not use STOP mode (oscillation stop mode) for this operation because the X1 pin is disabled when H is output at STOP. Figure 2.1-1 Example of Using an External Clock (Normal Method) X0 X1 Note: STOP mode (oscillation stop mode) cannot be used. 32 ■ Note for the Case of Using No Subclock When the oscillator is not connect to the X0A,X1A pins, set the X0A pin to the pull-down operation and open the X1A pin. Figure 2.1-2 Setting for the Case of Using No Subclock X0A OPEN X1A MB91350A ■ Handling of NC and Open Pins NC and open pins must be left open. ■ Mode Pins (MD0 to MD2) These pins must be directly connected to VCC or VSS when they are used. Keep the pattern length between a mode pin on a printed circuit board and VCC or VSS as short as possible so that they can be connected at a low impedance. ■ Power-on At power-on, be sure to set the INIT pin to the low level. Also immediately after power-on, keep the INIT pin at the L level until the oscillator has reached the required frequency stability. (For initialization by INIT from the INIT pin, the oscillation stabilization wait time is set to the minimum value.) ■ Source Oscillation Input at Power-on At power-on, be sure to input a source clock until the oscillation stabilization wait time is cleared. ■ Note on Operating in PLL Clock Mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. ■ Setting the External Bus The MB91350A model type guarantees a 25 MHz external bus. If the base clock is set to 50 MHz without the DIVR1 (external bus base clock freq.-divide setting register) initial value being unchanged, the external bus will also be set to 50 MHz. When changing the base clock, first set the external bus so that it does not exceed 25 MHz and then change the base clock. ■ MCLK and SYSCLK The difference between MCLK and SYSCLK is that MCLK stops in sleep mode and stop mode whereas SYSCLK stops only in stop mode. Use MCLK or SYSCLK, whichever is appropriate. After initialization, MCLK is disabled (PORT) and SYSCLK is enabled. To use MCLK, you must set the port function register (PFR) to use MCLK. 33 CHAPTER 2 HANDLING THE DEVICE ■ Pull-up Control The AC specification will not be guaranteed if pull-up resistor is connected to pins that are used as external bus pins. In addition, ports for which pull-up resistor is connected will be disabled in stop mode with HIZ = 1 and for hardware standby. ■ Clock Controller When inputting the low level to INIT, allocate wait time to allow oscillation to stabilize. ■ Subclock Switching Immediately after switching the clock source to subclock mode from the main clock, insert at least one NOP instruction. (ldi (ldi stb nop #0x0b, r0) #_CLKR ,r12) r0, @r12 // sub-clock mode // Must insert NOP instruction ■ Bit Search Module Only word access is supported for the BSD0, BSD1, and BDSC registers. ■ D-bus Memory Because instruction fetch to the D-bus memory is not executed, do not set the code area in the D-bus memory. If instruction fetch to the D-bus memory is executed, incorrect data will be interpreted for the codes, causing a runaway condition. ■ Low-power Consumption Mode When sleep or stop mode is set, always read the same registers immediately after writing to the standby control register (STCR). Specifically, use the sequence given below. In addition, after returning from standby mode, set the I flag, ILM, and ICR to branch to the interrupt handler that causes the return. (ldi (ldi stb ldub ldub nop nop nop nop nop 34 #value_of_standby, r0) #_STCR, r12) r0, @r12 // set STOP/SLEEP bit @r12, r0 // Must read STCR @r12, r0 // after reading, go into standby mode // Must insert NOP * 5 ■ Prefetch When prefetch to an area set as little endian is allowed, restrict access to that area to word (32-bit) access. Access will be incorrect if byte or halfword access is allowed. ■ Accessing I/O Ports Only byte access is supported for port access. ■ Switching Shared Port Functions Use the port function register (PFR) to switch the pins that also serve as ports. To switch the bus pins, use the external bus setting. ■ Internal RAM The function that restricts internal RAM size operates immediately after a reset is cleared. Only 4K bytes can be used for data and another 4K bytes for program execution regardless of the amount of RAM installed for the device. To release the restriction function, rewrite the setting of the function. In addition, if the above setting would be rewritten, include at least one NOP instruction immediately after that processing. ■ Flash Memory In programming mode, flash memory cannot be used for interrupt vector tables (reset is enabled). ■ Notes of PS Register Since some instructions process the PS register first, interrupt processing routines can lead to breaks during debugging or updating of the PS register flag due to the following exceptions. Whichever the case, the program is designed to reprocess correctly after returning from EIT to ensure that operation before and after EIT conforms to specifications. 1 The following operations may occur when (a) user interrupt/NMI is received, (b) step execution is performed, (c) break occurs in a data event or emulator menu in an immediately preceding DIVOU/ DIVOS instruction. (1) D0 and D1 flags precede and are renewed. (2) EIT processing routine (user interruption, NMI or emulator) is executed. (3) After returning from EIT, DIVOU/DIVOS instructions are executed and the D0 and D1 flags are updated to the same value as (1). 2 When each ORCCR/STILM/MOV Ri and PS instruction is executed to permit interrupting with the user interruption and the NMI factor generated, the following operations are done. (1) The PS register precedes and is updated. (2) EIT processing routine (user interruption, NMI, or emulator) is executed. (3) After returning from EIT, the above instructions are executed and the PS register is updated to the same value as (1). 35 CHAPTER 2 HANDLING THE DEVICE ■ Precautions on the Debuggers ● Single-step execution of the RETI instruction In an environment where interrupts frequently occur, only the relevant interrupt processing routines are executed repeatedly during single-step execution. As a result, the main routines and programs that have a low interrupt level will not be executed. (For example, if the RETI is executed in single-step mode with timebase timer interrupts allowed, the break will always be at the beginning of the timebase routine.) For stages in which debugging of the relevant interrupt processing routines is not required, disable the relevant interrupts. ● Break function If the target address of a hardware break (including event breaks) is the address of the current system stack pointer or if the target address is set in an area that contains the stack pointer, a break will occur after one instruction is executed. This applies even when there is no data access instruction in the user program. To avoid the problem, do not set word access for the area that contains the address of the system stack pointer as a target of a hardware break (including event breaks). ● Internal ROM (flash memory and MASK ROM) Note the following points when using an evaluation chip: • Do not set the internal ROM area as the DMAC transfer destination. • If the internal ROM area is set as the DMAC transfer destination, the internal ROM area may be rewritten if a break occurs during DMAC transfer. (The internal ROM area can be set as the DMAC transfer source.) ● Concurrent occurrence of a software break (INTE instruction) and user interrupt or NMI If a software break and a user interrupt or NMI occur concurrently, the following problems occur in the debugger: • The debugger stops, indicating a point other than the break point set by the user. • After having stopped, the debugger does not correctly execute processing. If this problem occurs, use a hardware break in place of a software break. If you use a monitor debugger, avoid setting a break at the relevant point. ● About the operand break If there is a stack pointer in an area that is set as operand break of DSU, the system may cause malfunctions. Do not set the access for the area that contains the address of the system stack pointer as a target of a data event break. 36 2.2 Precautions on Using the Little-Endian Area This section provides precautions on using the little-endian area. ■ Precautions on Using the Little-Endian Area Note the precautions for the following items when using the little-endian area: • C compiler • Assembler • Linker • Debuggers 37 CHAPTER 2 HANDLING THE DEVICE 2.2.1 C Compiler (fcc911) When programming with the C language, operation will be unpredictable if the following operations are executed for the little-endian area: • Mapping of variables with initial values • Structure assignment • Manipulation of arrays other than character-type arrays using character string operation functions • Specification of the -K lib option when character string operation functions are being used • Use of the double type and long double type • Mapping of the stack to the little-endian area ■ Mapping of Variables with Initial Values Variables with initial values cannot be mapped to the little-endian area. The compiler does not have a function for generating little-endian initial values. Variables can be mapped to the little-endian area, but initial values cannot be set. Provide processing at the beginning of the program that sets initial values. Example: Setting an initial value for the variable little_data in the little-endian area extern int little_data; void little_init(void) { little_data = initial value; } void main(void) { little_init( ); ... } 38 ■ Structure Assignment When structures are assigned among structures, the compiler selects the optimum transfer method and executes transfer for each byte, halfword, and word. As a result, the correct result will not be obtained if structure assignment spans structure variables assigned to the regular area and structure variables assigned to the little-endian area. Assign the members of a structure individually. Example: Assigning a structure to the structure variable little_st in the little-endian area struct tag { char c; int i; } normal_st; extern struct tag little_st; #define STRMOVE(DEST,SRC) DEST.c=SRC.c;DEST.i=SRC.i; void main(void) { STRMOVE(little_st,normal_st); } In addition, mapping of the structure members depends on the compiler. If a different compiler was used to compile a structure, the members will be mapped differently. In this case, the correct result will not be obtained even though the method described above is used. If the mappings of the structure members do not match, do not map structure variables in the little-endian area. ■ Manipulation of Arrays Other than Character-type Arrays Using Character String Operation Functions Character string operation functions provided as a standard library are processed in byte units. As a result, the correct result will not be obtained if processing that uses character string operation functions is executed for areas that have a type other than char, unsigned char, or signed char mapped in the little-endian area. Do not execute this type of processing. Incorrect processing example: Transferring word data using memcpy int big = 0x01020304; extern int little; memcpy(&little,&big,4); /* Big-endian area */ /* Little-endian area */ /* Transfer using memcpy */ The result of the executing the above code is shown below. An error occurs when word data is transferred. (Big-endian area) (Little-endian area) 01 02 03 04 memcpy (Correct result) 04 03 02 01 01 02 03 04 39 CHAPTER 2 HANDLING THE DEVICE ■ Specification of the -K lib Option when Character String Operation Functions are Used When the -K lib option is specified, the compiler expands several character string operation functions inline. Because the compiler selects the optimum processing method at this time, processing may change for each halfword or word. If the processing changes, processing for the little-endian area will not be executed correctly. Do not specify the -K lib option when executing processing that uses character string operation functions for the little-endian area. In addition, do not specify the -O 4 or -K speed option that includes the -K lib option. ■ Use of the Double Type and Long Double Type In double type access, the high-order word is accessed. In long double type access, the low-order word is accessed. For this reason, the correct result will not be obtained when double type and long double type variables mapped in the little-endian area are accessed. Variables of the same type allocated in the little-endian area can be assigned among the variables. However, optimization can replace the assignment of these variables with an assignment of literals. Do not map double type and long double type variables in the little-endian area. Incorrect processing example: Transferring double type data double big = 1.0; extern int little; little = big; /* Big-endian area */ /* Little-endian area */ /* Transfer double type data */ The result of executing the above code is shown below. An error occurs when the double type data is transferred. (Big-endian area) 3f f0 (Little-endian area) 00 00 00 00 00 00 (Correct result) 00 00 f0 3f 00 00 00 00 00 00 00 00 00 00 f0 3f ■ Mapping of the Stack to the Little-endian Area Operation will be unpredictable if part or all of the stack is mapped to the little-endian area. 40 2.2.2 Assembler (fasm911) Note the following points regarding the little-endian area when programming with the FR assembly language: ■ Sections Since the main purpose of the little-endian area is to exchange data with little-endian system CPUs, define the little-endian area as a data section without initial values. Access by the MB91101 will be unpredictable if a code, stack, or data section with initial values is specified in the little-endian area. Example: /* Correct section definitions of the little-endian area */ .SECTION Little_Area, DATA, ALIGN=4 Little_Word: .RES.W 1 Little_Half: .RES.H 1 Little_Byte: .RES.B 1 ■ Accessing Data When data in the little-endian area is accessed, the data values can be coded without having to take the byte ordering into consideration. However, when accessing data in the little-endian area, access it using the data size. Example: LDI LDI #0x01020304, r0 #Little_Word, r1 LDI LDI #0x0102, r2 #Little_Half, r3 LDI LDI #0x01, r4 #Little_Byte, r5 /* Using the ST instruction (or LD instruction) to access 32-bit data*/ ST r0, @r1 /* Using the STH instruction (or LDH instruction) to access 16-bit data*/ STH r2, @r3 /* Using the STB instruction (or LDB instruction) to access 8-bit data*/ STB r4, @r5 The data values will be unpredictable if the MB91350A model type is used to access data using a size that is not the data size. For example, the data values will be unpredictable if a 32-bit access instruction is used to access two consecutive 16-bit data items at one time. 41 CHAPTER 2 HANDLING THE DEVICE 2.2.3 Linker (flnk911) When creating programs that use the little-endian area, note the following points regarding section mapping at link time: ■ Restriction on Section Types Only data sections without initial values can be mapped in the little-endian area. If a data section with initial values, a stack section, or a code section is mapped in the little-endian area, arithmetic operations such as address decisions will be executed internally in the linker using the bigendian method, causing program operation that is unpredictable. ■ Non-detection of Errors Because the linker does not recognize the little-endian area, an error message may not be posted if the restriction described above is not observed. When using the linker, be careful of the contents for the sections mapped into the little-endian area. 42 2.2.4 Debuggers (sim911, eml911, and mon911) When creating programs that use the little-endian area, note the following points regarding the debuggers: ■ Simulator Debugger There is no memory space specification command for displaying the little-endian area. Therefore, when memory operator commands or instructions that manipulate memory are executed, the area is handled as a big-endian area. ■ Emulator and Monitor Debuggers Note that the data will not be handled using its correct values when the following commands are used to access the little-endian area: • set memory, show memory, enter, examine, and set watch commands When floating-point (single or double) data is handled, setting or display of the specified values will not be possible. • search memory command When a search uses halfword or word data, execution of the search with the specified values will not be possible. • Line/reverse assembly (including display of reverse assembly in the source window) Setting or display of the correct instruction codes will not be possible. (Do not map instruction codes in the little-endian area.) • call and show call commands Operation will be unpredictable if the stack area is mapped in the little-endian area. (Do not map the stack area in the little-endian area.) 43 CHAPTER 2 HANDLING THE DEVICE 44 CHAPTER 3 CPU AND CONTROL UNITS This chapter provides basic information required to understand the core CPU functions of FR family microcontrollers. It covers architecture, specifications, and instructions. 3.1 Memory Space 3.2 Internal Architecture 3.3 Programming Model 3.4 Data Configuration 3.5 Memory Map 3.6 Branch Instructions 3.7 EIT (Exception, Interrupt, and Trap) 3.8 Operating Modes 3.9 Reset (Device Initialization) 3.10 Clock Generation Control 3.11 Device State Control 3.12 Watch Timer 3.13 Main Clock Oscillation Stabilization Wait Timer 3.14 Peripheral Stop Control 45 CHAPTER 3 CPU AND CONTROL UNITS 3.1 Memory Space FR family microcontrollers have a logical address space of 4 GB (232 addresses). The CPU accesses this space linearly. ■ Direct Addressing Area The areas in the address space listed below are used for input-output. These areas called the direct addressing area. The address of an operand can be directly specified in an instruction. The size of the direct addressing area varies according to the size of data to be accessed: • Byte data access: 000H to 0FFH • Halfword data access: 000H to 1FFH • Word data access: 000H to 3FFH ■ Memory Map Figure 3.1-1 to Figure 3.1-4 show the memory spaces of FR family microcontrollers. Figure 3.1-1 MB91F355A, MB91355A, MB91F353A, MB91353A and MB95F357B Memory Maps 0000 0000H Single-chip mode Internal ROM external bus mode I/O I/O External ROM external bus mode I/O Direct addressing area Reference to I/O map 0000 0400H 0001 0000H 0003 E000H 0004 0000H 0004 4000H 0005 0000H I/O I/O I/O Access not allowed Internal RAM (8 KB) (Instruction) Internal RAM (16 KB) (Data) Access not allowed Internal RAM (8 KB) (Instruction) Internal RAM (16 KB) (Data) Access not allowed Access not allowed Internal RAM (8 KB) (Instruction) Internal RAM (16 KB) (Data) Access not allowed Access not allowed External area 0008 0000H Internal ROM (512 KB) Internal ROM (512 KB) Access not allowed External area 0010 0000H FFFF FFFFH 46 External area Figure 3.1-2 MB91351A Memory Map 0000 0000H Single-chip mode Internal ROM external bus mode External ROM external bus mode I/O I/O I/O Direct addressing area I/O I/O I/O Reference to I/O map Access not allowed Internal RAM (8 KB) (Instruction) Internal RAM (16 KB) (Data) Access not allowed Internal RAM (8 KB) (Instruction) Internal RAM (16 KB) (Data) Access not allowed Access not allowed Internal RAM (8 KB) (Instruction) Internal RAM (16 KB) (Data) Access not allowed 0000 0400H 0001 0000H 0003 E000H 0004 0000H 0004 4000H 0005 0000H 0008 0000H Access not allowed 000A 0000H External area Access not allowed Internal ROM (384 KB) Internal ROM (384 KB) Access not allowed External area External area 0010 0000H FFFF FFFFH Figure 3.1-3 MB91354A and MB91352A Memory Map 0000 0000H Single-chip mode Internal ROM external bus mode External ROM external bus mode I/O I/O I/O Direct addressing area I/O I/O I/O Reference to I/O map Access not allowed Internal RAM (8 KB) (Instruction) Internal RAM (8 KB) (Data) Access not allowed Internal RAM (8 KB) (Instruction) Internal RAM (8 KB) (Data) Access not allowed Access not allowed Internal RAM (8 KB) (Instruction) Internal RAM (16 KB) (Data) Access not allowed 0000 0400H 0001 0000H 0003 E000H 0004 0000H 0004 2000H 0005 0000H 0008 0000H Access not allowed 000A 0000H External area Access not allowed Internal ROM (384 KB) Internal ROM (384 KB) Access not allowed External area External area 0010 0000H FFFF FFFFH 47 CHAPTER 3 CPU AND CONTROL UNITS Figure 3.1-4 MB91F356B Memory Map 0000 0000H Single-chip mode Internal ROM external bus mode External ROM external bus mode I/O I/O I/O Direct addressing area I/O I/O I/O Reference to I/O map Access not allowed Internal RAM (8 KB) (Instruction) Internal RAM (16 KB) (Data) Access not allowed Internal RAM (8 KB) (Instruction) Internal RAM (16 KB) (Data) Access not allowed External area Access not allowed Internal RAM (8 KB) (Instruction) Internal RAM (16 KB) (Data) Access not allowed 0000 0400H 0001 0000H 0003 E000H 0004 0000H 0004 4000H 0005 0000H 0008 0000H 000C 0000H Access not allowed Access not allowed Internal ROM (256 KB) Internal ROM (256 KB) Access not allowed External area External area 0010 0000H FFFF FFFFH 48 • Each mode setting is determined based on the mode vector fetch after INIT negate. (For details about setting the modes, see Section "3.8.2 Mode Settings".) • For the MB91V350A, with the memory map of the MB91355A/F355A/353A/F353A/F357B, the 512K bytes area of the internal ROM, and with the memory map of the MB91F356B, the 256K bytes area of the internal ROM, is the emulation RAM. In addition, internal RAM(Instruction) is extended from 8K bytes to16K bytes. • The available internal RAM area is restricted as soon as a reset is cleared. If the available area setting would be rewritten, include at least one NOP instruction immediately after that processing. 3.2 Internal Architecture This section describes the structure of the internal architecture and instructions of the FR family microcontrollers. ■ Overview of Internal Architecture The FR family CPUs employ RISC architecture to create a high-performance core with instructions that provide high-level functions for embedded applications. 49 CHAPTER 3 CPU AND CONTROL UNITS 3.2.1 Internal Architecture This section describes the features and structure of the internal architecture. ■ Features of the Internal Architecture • RISC architecture used Basic instruction: One instruction per cycle • 32-bit architecture General-purpose register: 32 bits x 16 • 4 GB linear memory space • Multiplier installed 32-bit by 32-bit multiplication: 5 cycles 16-bit by 16-bit multiplication: 3 cycles • Enhanced interrupt processing function Quick response speed: 6 cycles Support of multiple interrupts Level mask function: 16 levels • Enhanced instructions for I/O operations Memory-to-memory transfer instruction Bit-processing instructions • Efficient code Basic instruction word length: 16 bits • Low-power consumption Sleep and stop modes Gear function 50 ■ Structure of the Internal Architecture The FR CPU uses the Harvard architecture, in which the instruction bus and data buses are independent of each other. A 32-bit ↔ 16-bit bus converter is connected to the 32-bit bus (F-bus) to provide an interface between the CPU and peripheral resources. A Harvard ↔ Princeton bus converter is connected to the I-bus and D-bus to provide an interface between the CPU and the bus controller. Figure 3.2-1 shows the structure of the internal architecture. Figure 3.2-1 Structure of the Internal Architecture FRex CPU D-bus I-bus 32 I address Harvard External address 32 24 I data D address 32 Data RAM D data 32-bit 16-bit Princeton bus converter 32 Address 32 Data 32 External data 16 Bus converter R-bus 16 Peripheral resources F-bus Internal I/O Bus converter 51 CHAPTER 3 CPU AND CONTROL UNITS ■ CPU The CPU is a compact implementation of the 32-bit RISC FR architecture. Five instruction pipelines are used to execute one instruction per cycle. A pipeline consists of the following stages: Figure 3.2-2 shows the structure of the instruction pipeline. • Instruction fetch (IF): Outputs an instruction address to fetch an instruction. • Instruction decode (ID): Decodes a fetched instruction. Also reads a register. • Execution (EX): Executes an arithmetic operation. • Memory access (MA): Performs a load or store access to memory. • Write-back (WB): Writes an operation result (or loaded memory data) to a register. Figure 3.2-2 Structure of the Instruction Pipeline CLK Instruction 1 WB Instruction 2 MA WB Instruction 3 EX MA WB Instruction 4 ID EX MA WB Instruction 5 IF ID EX MA WB IF ID EX MA Instruction 6 WB Instructions are never executed randomly. If Instruction A enters a pipeline before Instruction B, it always reaches the write-back stage before Instruction B. In general, one instruction is executed per cycle. However, multiple cycles are required to execute a load/ store instruction with a memory wait, a branch instruction without a delay slot, or a multiple-cycle instruction. The execution of instructions slows down if the instructions are not supplied fast enough. ■ 32-bit/16-bit Bus Converter The 32-bit/16-bit bus converter provides an interface between the F-bus accessed at high-speed with a 32bit width and the R-bus accessed with a 16-bit width. This converter enables data access to the built-in peripheral circuits from the CPU. If the CPU performs a 32-bit width access to the R-bus, this bus converter converts the access into two 16bit width accesses. Some of the built-in peripheral circuits have limitations on the access bus width. ■ Harvard/Princeton Bus Converter The Harvard/Princeton bus converter coordinates CPU instruction access and data access, and provides a smooth interface with the external buses. The CPU has a Harvard architecture with separate buses for instructions and data. On the other hand, the bus controller that performs control of external buses has a Princeton architecture with a single bus. The Harvard/Princeton bus converter assigns priorities to instruction and data accesses from the CPU to control accesses to the bus controller. This function allows the order of external bus accesses to be permanently optimized. 52 3.2.2 Overview of Instructions The FR supports the general RISC instruction set as well as logical operation, bit manipulation, and direct addressing instructions optimized for embedded applications. For the instruction set, see the APPENDIX D "Instruction Lists". Each instruction is 16-bit long (except for some instructions are 32- or 48-bit long), resulting in superior efficiency of memory use. An instruction set is classified into the following function groups: • Arithmetic operation • Load and store • Branch • Logical operation and bit manipulation • Direct addressing • Other ■ Arithmetic Operation Arithmetic operation instructions include standard arithmetic operation instructions (addition, subtraction, and comparison) and shift instructions (logical shift and arithmetic operation shift). The addition and subtraction instructions include an operation with carries for use with multiple-word-length operations and an operation that does not change flag values, a convenience in address calculations. Furthermore, 32-bit-by-32-bit and 16-bit-by-16-bit multiplication instructions and a 32-bit-by-32-bit step division instruction are provided. Additionally, an immediate data transfer instruction that sets immediate data in a register and a register-toregister transfer instruction are provided. An arithmetic operation instruction is executed using the general-purpose registers and the multiplication and division registers in the CPU. ■ Load and Store Load and store instructions read and write to external memory. They are also used to read and write to a peripheral circuit (I/O) on the chip. Load and store instructions have three access lengths: byte, halfword, and word. In addition to indirect memory addressing via general registers, indirect memory addressing via registers with displacements and via registers with register incrementing or decrementing are provided for some instructions. ■ Branch The branch group includes branch, call, interrupt, and return instructions. Some branch instructions have delay slots while others do not. These may be optimized according to the application. The branch instructions are described in detail later. 53 CHAPTER 3 CPU AND CONTROL UNITS ■ Logical Operation and Bit Manipulation Logical operation instructions perform the AND, OR, and EOR logical operations between general-purpose registers or a general-purpose register and memory (and I/O). Bit manipulation instructions directly manipulate the contents of memory (and I/O). They access memory using general register indirect addressing. ■ Direct Addressing Direct addressing instructions are used for access between an I/O and a general-purpose register or between an I/O and the memory. High-speed and high-efficiency access can be achieved since an I/O address is directly specified in an instruction instead of using register indirect addressing. Indirect memory addressing via registers with register incrementing or decrementing are provided for some instructions. ■ Other Types of Instructions Other types of instructions include instructions that provide flag setting, stack manipulation, sign/zero extension, and other functions in the PS register. Also, function entry and exit instructions that support high-level languages and register multi-load/store instructions are provided. 54 3.3 Programming Model This section describes the programming model, general-purpose registers, and dedicated registers of the FR family microcontrollers. ■ Basic Programming Model Figure 3.3-1 shows the FR family basic programming model. Figure 3.3-1 Basic Programming Model 32 bits [Initial value] R0 XXXX XXXX H R1 General-purpose register R12 R13 AC R14 R15 Program counter PC Program status PS Table base register TBR Return pointer RP System stack pointer SSP User stack pointer USP XXXX XXXX H FP 0000 0000 H SP ILM SCR CCR Multiply and divide registers MDH MDL 55 CHAPTER 3 CPU AND CONTROL UNITS 3.3.1 General-Purpose Registers Registers R0 to R15 are general-purpose registers. They are used as the accumulator for various arithmetic operations and as pointers for memory access. ■ General-Purpose Registers Figure 3.3-2 shows the configuration of the general-purpose registers. Figure 3.3-2 Configuration of General-Purpose Registers 32 bits [Initial value] R0 XXXX XXXXH R1 R12 R13 R14 AC FP XXXX XXXXH R15 SP 0000 0000H Since it is assumed that the following registers of the 16 registers will be used for specific applications, some of the instructions have been enhanced accordingly: • R13: Virtual accumulator • R14: Frame pointer • R15: Stack pointer The initial value after a reset is not defined for R0 to R14. For R15, the initial value is 00000000H (SSP value). 56 3.3.2 Dedicated Registers The dedicated registers are used for specific applications. FR family microcontrollers provide the following dedicated registers: • PS (Program Status) • CCR (Condition Code Register) • SCR (System Condition Code Register) • ILM • PC (Program Counter) • TBR (Table Base Register) • RP (Return Pointer) • SSP (System Stack Pointer) • USP (User Stack Pointer) • Multiply & Divide register ■ PS (Program Status) The program status (PS) register holds the program status and consists of three parts: ILM, SCR, and CCR. In the figure, all the undefined bits are reserved. During reading, "0" is always read. This register cannot be written. The configuration of the program status (PS) register is shown below: Bit location 31 20 16 ILM 10 8 7 SCR 0 CCR 57 CHAPTER 3 CPU AND CONTROL UNITS ■ CCR (Condition Code Register) The configuration of the condition code register (CCR) is shown below: 7 6 5 4 3 2 1 0 [Initial value] - - S I N Z V C --00XXXXB [Bit 5] Stack flag This bit specifies the stack pointer to be used as R15. Value Description 0 The system stack pointer (SSP) is used as R15. When an EIT occurs, this bit is automatically set to "0". (Note that the value saved on the stack is the value before it is cleared.) 1 The user stack pointer (USP) is used as R15. • Reset clears this bit to "0". • Set this bit to "0" when executing a RETI instruction. [Bit 4] Interrupt enable flag This bit enables or disables a user interrupt request. Value • Description 0 User interrupt disabled. When the INT instruction is executed, this bit is cleared to "0". (Note that the value saved on the stack is the value before it is cleared.) 1 User interrupt enabled. The mask processing of a user interrupt request is controlled by the value held in ILM. Reset clears this bit to "0". [Bit 3] Negative flag This bit indicates the sign when the operation result is regarded as an integer represented by its 2's complement. Value • 58 Description 0 Indicates that the operation result is a positive value. 1 Indicates that the operation result is a negative value. The initial value after reset is undefined. [Bit 2] Zero flag This bit indicates whether the operation result is "0". Value • Description 0 Indicates that the operation result is not "0". 1 Indicates that the operation result is "0". The initial value after reset is undefined. [Bit 1] Overflow flag This bit indicates whether an overflow has occurred as a result of the operation when the operand using the operation is regarded as an integer represented by its 2's complement. Value • Description 0 Indicates that the operation result did not cause an overflow. 1 Indicates that the operation result caused an overflow. The initial value after reset is undefined. [Bit 0] Carry flag This bit indicates whether a carry or a borrow has occurred from the most significant bit in the operation. Value • Description 0 Indicates that no carry or borrow has occurred. 1 Indicates that a carry or borrow has occurred. The initial value after reset is undefined. 59 CHAPTER 3 CPU AND CONTROL UNITS ■ SCR (System Condition Code Register) The configuration of the system condition code register (SCR) is shown below: 10 9 8 [Initial value] D1 D0 T XX0B [Bits 10 and 9] Step division flag These bits hold the intermediate data when step division is executed. Do not change these bits during step division. To execute other processing during a step division, save and restore the value of the PS register to ensure that the step division is restarted. • The initial value after reset is undefined. • When the DIVOS instruction is executed, the multiplicand and divisor are accessed and this flag is set. • When the DIV0U instruction is executed, this flag is cleared. • DIV0S/DIV0U command and user interruption/NMI simultaneous receipt; Do not perform any process desiring D0/D1 bit of the PS resister before the EIT branch in the EIT process routine. • When a halt caused by break, step, etc. occurs right before the DIV0S/DIV0U command, the D0/D1 bit of the PS register may not display a valid value. Calculation result, however, will be valid after recovery. [Bit 8] Step trace trap flag This bit specifies whether the step trace trap is to be enabled. Value 60 Description 0 The step trace trap is disabled. 1 The step trace trap is enabled. All user NMIs and user interrupts are prohibited. • Reset initializes this bit to "0". • The step trace trap function is also used by emulators. When being used by an emulator, this function cannot be used in a user program. ■ ILM The configuration of the ILM register is shown below: 20 19 18 17 16 [Initial value] ILM4 ILM3 ILM2 ILM1 ILM0 01111B The interrupt level mask (ILM) register holds an interrupt level mask value. The value held in ILM is used as a level mask. An interrupt request to the CPU is accepted only when its interrupt level is higher than the level indicated in this ILM. The highest level is 0 (00000B), and the lowest level is 31 (11111B). The program setting range is limited. • When the original value is between 16 and 31: A new value between 16 and 31 can be set. If an instruction that sets a value between 0 and 15 is executed, the specified value plus 16 is transferred. • When the original value is between 0 and 15: Any value between 0 and 31 can be set. Reset initializes this bit to 15 (01111B). ■ PC (Program Counter) The configuration of the program counter (PC) register is shown below: 31 0 [Initial value] XXXXXXXXH PC [Bits 31 to 0] These are the bits of the program counter that indicates the address of the instruction being executed. Bit 0 is set to "0" when the PC is updated after an instruction is executed. Bit 0 can become "1" only if the branch address is an odd number address. However, even if the branch address is an odd number address, bit 0 is invalid and therefore the instruction should be placed at an address for multiple of two. The initial value after reset is undefined. ■ TBR (Table Base Register) The configuration of the table base register (TBR) is shown below: 31 TBR 0 [Initial value] 000FFC00H The table base register holds the first address of the vector table to be used during EIT processing. The initial value after reset is 000FFC00H. 61 CHAPTER 3 CPU AND CONTROL UNITS ■ RP (Return Pointer) The configuration of the return pointer (RP) register is shown below: 31 0 [Initial value] XXXXXXXXH RP The return pointer holds the address returned from a subroutine. When a CALL instruction is executed, the PC value is transferred to this RP. When a RET instruction is executed, the RP contents are transferred to PC. The initial value after reset is undefined. ■ SSP (System Stack Pointer) The configuration of the system stack pointer (SSP) register is shown below: 31 0 [Initial value] 00000000H SSP SSP is the system stack pointer. SSP functions as R15 when the S flag is "0". SSP can also be specified explicitly. This register is also used as a stack pointer that specifies the stack on which the PS and PC contents are to be saved if an EIT occurs. The initial value after reset is 00000000H. ■ USP (User Stack Pointer) The configuration of the user stack pointer (USP) register is shown below: 31 USP USP is the user stack pointer USP functions as R15 when the S flag is "1". USP can also be specified explicitly. The initial value after reset is undefined. This register cannot be used by the RETI instruction. 62 0 [Initial value] XXXXXXXXH ■ Multiply & Divide Register The configuration of the multiply & divide register is shown below: 31 0 MDH MDL The multiply and divide registers are 32-bit long. The initial value after reset is undefined. • When multiplication is executed For a 32-bit-by-32-bit multiplication, the 64-bit long operation result is stored in the multiply and divide registers as follows: MDH: High-order 32 bits MDL: Low-order 32 bits For a 16-bit-by-16-bit multiplication, the result is stored as follows: MDH: Undefined MDL: 32-bit result • When division is executed At the start of calculation, the dividend is stored in MDL. If a DIV0S/DIV0U, DIV1, DIV2, DIV3, or DIV4S instruction is executed for a division, the result is stored in MDL and MDH as follows: MDH: Remainder MDL: Quotient 63 CHAPTER 3 CPU AND CONTROL UNITS 3.4 Data Configuration This section describes the data structure in FR family microcontrollers. ■ Bit Ordering FR family microcontrollers use the little endian method for bit ordering. Figure 3.4-1 shows the data configuration in bit ordering. Figure 3.4-1 Data Configuration in Bit Ordering bit 31 29 30 27 28 25 26 23 24 21 22 19 20 17 18 15 16 13 14 11 12 9 10 7 8 5 6 3 4 MSB 2 0 LSB ■ Byte Ordering FR family microcontrollers use the big endian method for byte ordering. Figure 3.4-2 shows the data configuration in byte ordering. Figure 3.4-2 Data Configuration in Byte Ordering Memory MSB bit 31 23 15 7 LSB 0 10101010 11001100 11111111 00010001 bit 7 Address n 0 10101010 Address (n+1) 11001100 Address (n+2) 11111111 Address (n+3) 00010001 64 1 ■ Word Alignment ● Program access An FR family program must be placed at an address that is a multiple of 2. Bit 0 of the PC is set to "0" if the PC is updated when an instruction is executed. Bit 0 can be set to "1" only if an odd-number address is specified as the branch address. If Bit 0 is set to "1", however, Bit 0 is invalid and an instruction must be placed at the address that is a multiple of 2. No odd-number address exception exists. ● Data access When FR family data is accessed, forced alignment is applied as described below to the address based on the width. Word access: An address must be a multiple of 4. (The lowest-order 2 bits are forcibly set to "00".) Halfword access: An address must be a multiple of 2. (The lowest-order bit is forcibly set to "0".) Byte access: - During word or halfword data access, some of the bits in the result of calculating an effective address are forcibly set to "0". For example, in @(R13, Ri) addressing mode, the register before addition is used without change in the calculation (even if the lowest-order bit is "1") and the low-order bits are masked. A register before calculation is not masked. [Example] LD @(R13, R2), R0 R13 00002222H R2 00000003H +) Addition result 00002225H Lower 2 bits forcibly masked Address pin 00002224H 65 CHAPTER 3 CPU AND CONTROL UNITS 3.5 Memory Map This section describes the memory maps of the FR family microcontrollers. ■ Memory Map The address space is 32 bits linear. Figure 3.5-1 shows the memory map. Figure 3.5-1 Memory Map 0000 0000H Byte data 0000 0100H Halfword data Direct addressing area 0000 0200H Word data 0000 0400H 000F FC00H Vector table initial area 000F FFFFH FFFF FFFFH ● Direct addressing area The following areas in the address space are the areas for I/O. When direct addressing is used in these areas, an operand address can be directly specified in an instruction. The size of an address area for which an address can be directly specified varies is determined by the data length as follows: • Byte data (8 bits): 000H to 0FFH • Halfword data (16 bits): 000H to 1FFH • Word data (32 bits): 000H to 3FFH ● Vector table initial area The area from 000FFC00H to 000FFFFFH is the initial EIT vector table area. You can place the vector table that will be used during EIT processing at any address by rewriting the TBR. Initialization by a reset places the table at this address. 66 3.6 Branch Instructions This section describes the branch instructions used in the FR family microcontrollers. ■ Overview of Branch Instructions In the FR family microcontrollers, both operations with and without a delay slot can be specified for the branch instructions. 67 CHAPTER 3 CPU AND CONTROL UNITS 3.6.1 Operations with a Delay Slot This section describes operation when operations with a delay slot are specified for a branch instruction. ■ Branch Instructions with Delay Slot Instructions written as follows perform a branch operation with a delay slot: JMP:D @Ri CALL:D label12 CALL:D @Ri RET:D BRA:D label9 BNO:D label9 BEQ:D label9 BNE:D label9 BC:D label9 BNC:D label9 BN:D label9 BP:D label9 BV:D label9 BNV:D label9 BLT:D label9 BGE:D label9 BLE:D label9 BGT:D label9 BLS:D label9 BHI:D label9 ■ Operation with Delay Slot In an operation with a delay slot, the instruction immediately following the branch instruction (this is called the delay slot) is executed, then the instruction at the branch destination is executed. Since an instruction in the delay slot is executed before the branch operation, the apparent execution speed is one cycle. However, a NOP instruction must be placed in the delay slot if there is no valid instruction put there. [Example] ; List of instructions ADD R1, BRA:D LABEL MOV R2, R3, R2, ; ; Branch instruction R3, ; Delay slot ... Executed before branch @R4 ; Branch destination ... LABEL : ST If a conditional branch instruction is used, an instruction placed in the delay slot is executed whether or not the condition for branching is met. If a delay branch instruction is used, the order of execution for some instructions seems to be reversed. However, this occurs only for updating the PC and the instructions are executed in the specified order for other operations (register update and reference, etc.) The following is a concrete example. 1) Ri referred by the JMP:D @Ri / CALL:D @Ri instruction is not affected even though Ri is updated by the instruction in the delay slot. 68 [Example] LDI:32 #Label, JMP:D @R0 LDI:8 #0, R0 R0 ; Branch to Label ; No effect on the branch destination address ... 2) RP referred by the RET:D instruction is not affected even though RP is updated by the instruction in the delay slot. [Example] RET:D MOV R8, RP ; Branch to address defined beforehand in RP ; No effect on the return operation ... 3) The flag referred by the Bcc:D rel instruction is not affected by the instruction in the delay slot. [Example] ADD #1, BC:D ANDCCR R0 ; Flag change Overflow ; Branch to execution result of above instruction #0 ; This flag update is not referred by the above branch instruction. ... 4) If RP is referred by an instruction in the delay slot of the CALL:D instruction, the data that has been updated by the CALL:D instruction is read. [Example] CALL:D Label MOV RP, R0 ; Updating RP and branching ; Transferring RP, execution result of above CALL:D ... ■ Limitations on Operation with Delay Slot ● Instructions that can be placed in the delay slot Only an instruction meeting the following conditions can be executed in the delay slot. • One-cycle instruction • Instruction other than a branch instruction • Instruction whose operation is not affected even though the order is changed A one-cycle instruction is an instruction denoted in the Number of Cycles column in the list of instructions as 1, a, b, c, and d. 69 CHAPTER 3 CPU AND CONTROL UNITS ● Step trace trap A step trace trap does not occur between the execution of a branch instruction with a delay slot and the delay slot. ● Interrupt NMI An interrupt /NMI is not accepted between the execution of a branch instruction with a delay slot and the delay slot. ● Undefined instruction exception An undefined instruction exception does not occur if there is an undefined instruction in the delay slot. If an undefined instruction is in the delay slot, it operates as a NOP instruction. 70 3.6.2 Operation without Delay Slot This section describes operation when operations without a delay slot are specified for a branch instruction. ■ Instructions not Using a Delay Slot The instructions below execute branch operations without a delay slot: JMP @Ri CALL label12 CALL @Ri RET BRA label9 BNO label9 BEQ label9 BNE label9 BC label9 BNC label9 BN label9 BP label9 BV label9 BNV label9 BLT label9 BGE label9 BLE label9 BGT label9 BLS label9 BHI label9 ■ Operation without Delay Slot In an operation without a delay slot, the instruction is executed by the order of the list. Instruction immediately after the instruction is not executed before branch. [Example] ; List of instructions ADD R1, R2, ; BRA LABEL ; Branch instruction (without a delay slot) MOV R2, R3, ; Not executed R3, @R4 ; Branch destination ... LABEL : ST A branch instruction without a delay slot is executed in two cycles if a branch occurs and in one cycle if no branch occurs. Since no appropriate instruction can be placed in the delay slot, branch instructions without a delay slot result in more efficient instruction codes than branch instructions with a delay slot and with NOP specified. For both optimal execution speed and code efficiency, select an operation with a delay slot if a valid instruction can be placed in the delay slot; otherwise, select an operation without a delay slot. 71 CHAPTER 3 CPU AND CONTROL UNITS 3.7 EIT (Exception, Interrupt, and Trap) EIT, a generic term for exception, interrupt, and trap, refers to suspending program execution if an event occurs during execution and then executing another program. An exception is an event that occurs related to the execution context. Execution restarts from the instruction that caused the exception. An interrupt is an event that occurs independently of execution context. The event is caused by hardware. A trap is an event that occurs related to the execution context. Some traps, such as system calls, are specified in a program. Execution restarts from the instruction following the one that caused the trap. ■ Features of EIT • Multiple interrupts support • Level masking function (15 levels available to the user) • Trap instruction (INT) • Emulator activation EIT (hardware/software) ■ EIT Causes The following are causes of EIT: • Reset • User interrupt (internal resource, external interrupt) • NMI • Delayed interrupt • Undefined instruction exception • Trap instruction (INT) • Trap instruction (INTE) • Step trace trap • No-coprocessor trap • Coprocessor error trap Note: Restrictions apply to EIT regarding the delay slot of branch instructions. See Section "3.6 Branch Instructions" for more information. ■ Return from EIT • 72 RETI instruction 3.7.1 EIT Interrupt Levels The interrupt levels are 0 to 31 and are managed with five bits. ■ EIT Interrupt Levels Table 3.7-1 shows the allocation of the levels. Table 3.7-1 Interrupt Levels Level Binary Decimal 00000 ... ... 00011 0 ... ... 3 (Reserved for system) ... ... (Reserved for system) 00100 4 INTE instruction Step trace trap 00101 ... ... 01110 5 ... ... 14 (Reserved for system) ... ... (Reserved for system) 01111 15 NMI (for user) 10000 10001 ... ... 11110 11111 16 17 ... ... 30 31 Interrupt Interrupt ... ... Interrupt - If the original ILM value is between 16 and 31, a program cannot set a value in this ILM range. User interrupts prohibited if ILM is set Interrupts prohibited if ICR is set Operation is possible for levels 16 to 31. The interrupt level does not affect an undefined instruction exception, no-coprocessor trap, coprocessor error trap, or an INT instruction. It does not change the ILM, either. 73 CHAPTER 3 CPU AND CONTROL UNITS ■ I Flag A flag that specifies whether an interrupt is permitted or prohibited. This flag is provided as Bit 4 of the PS register. Value Description 0 Interrupts prohibited Cleared to "0" if the INT instruction is executed. (Note that a value saved on the stack is the value before it is cleared.) 1 Interrupts permitted The mask processing of an interrupt request is controlled by the value in the ILM register. ■ Interrupt Level Mask (ILM) Register A PS register (Bits 20 to 16) that holds an interrupt level mask value. The CPU accepts only an interrupt request sent to it with an interrupt level higher than the level indicated by the ILM. The highest level is 0 (00000B) and the lowest level is 31 (11111B). Values that can be set by a program have a limit. If the original value is between 16 and 31, the new value must be between 16 and 31. If an instruction that sets a value between 0 and 15 is executed, the specified value plus 16 is transferred. If the original value is between 0 and 15, any value between 0 and 31 may be set. Use the STILM instruction to specify an arbitrary value. ■ Level Mask for Interrupt and NMI If an NMI or interrupt request occurs, the interrupt level (Table 3.7-1 ) of the interrupt source is compared with the level mask value held in the ILM. A request meeting the following condition is masked and is not accepted: Interrupt level of cause ≥ Level mask value 74 3.7.2 ICR (Interrupt Control Register) The interrupt control register (ICR: Interrupt Control Register), located in the interrupt controller, sets the level of an interrupt request. An ICR is provided for each of the interrupt request inputs. The ICR is mapped on the I/O space and is accessed from the CPU through a bus. ■ Configuration of Interrupt Control Register (ICR) The following shows the configuration of the interrupt control register (ICR) bits. 7 6 5 4 3 2 1 0 - - - ICR4 R ICR3 R/W ICR2 R/W ICR1 R/W ICR0 R/W [Initial value] ---111111B [Bit 4] ICR4 ICR4 is always set to "1". [Bits 3 to 0] ICR3 to 0 These bits are the low-order 4 bits of the interrupt level for the corresponding interrupt source. They can be read and written to. Together with Bit 4, a value between 16 and 31 can be set in the ICR. ■ Mapping of Interrupt Control Register (ICR) Table 3.7-2 shows the relationship between interrupt sources, interrupt control register, and interrupt vectors. Table 3.7-2 Interrupt Sources, Interrupt Control Registers, and Interrupt Vectors Interrupt control register Interrupt source Corresponding interrupt vector Number Number Address Address Hexadecimal Decimal IRQ00 ICR00 00000440H 10H 16 TBR + 3BCH IRQ01 ICR01 00000441H 11H 17 TBR + 3B8H IRQ02 ICR02 00000442H 12H 18 TBR + 3B4H ... ... ... ... ... ... ... ... ... ... ... ... IRQ45 ICR45 0000046DH 3DH 61 TBR + 308H IRQ46 ICR46 0000046EH 3EH 62 TBR + 304H IRQ47 ICR47 0000046FH 3FH 63 TBR + 300H 75 CHAPTER 3 CPU AND CONTROL UNITS Table 3.7-2 Interrupt Sources, Interrupt Control Registers, and Interrupt Vectors Interrupt control register Interrupt source Corresponding interrupt vector Number Number Address Address Hexadecimal TBR initial value: 000F FC00H Note: See "CHAPTER 9 INTERRUPT CONTROLLER". 76 Decimal 3.7.3 SSP (System Stack Pointer) SSP (System Stack Pointer) is used to point to the stack to save and restore data when EIT is accepted or a return operation occurs. ■ System Stack Pointer (SSP) The configuration of the SSP register is shown below: 31... SSP ...0 [Initial value] 00000000H Eight is subtracted from the register value during EIT processing and eight is added to the register value during the return operation from EIT that occurs when the RETI instruction is executed. The system stack pointer (SSP) is initialized to 00000000H by a reset. The SSP is also used as general-purpose register R15 if the S flag in the CCR is set to "0". 77 CHAPTER 3 CPU AND CONTROL UNITS 3.7.4 Interrupt Stack The PC and PS values are saved and restored using the area pointed to by the SSP. After an interrupt, the PC is stored at the address pointed to by the SSP and the PS is stored at the address SSP + 4. ■ Interrupt Stack Figure 3.7-1 shows an example of an interrupt stack. Figure 3.7-1 Interrupt Stack [Before interrupt] SSP 80000000H [After interrupt] SSP 7FFFFFF8H Memory 80000000H 7FFFFFFCH 7FFFFFF8H 78 80000000H 7FFFFFFCH 7FFFFFF8H PS PC 3.7.5 TBR (Table Base Register) TBR (Table Base Register) indicates the beginning address of the vector table for EIT. ■ Table Base Register (TBR) The configuration of the TBR register is shown below: 31... TBR ...0 [Initial value] 000FFC00H Obtain a vector address by adding to the TBR the offset value predetermined for an EIT cause. The table base register (TBR) is initialized to 000FFC00H by a reset. 79 CHAPTER 3 CPU AND CONTROL UNITS 3.7.6 EIT Vector Table A 1K bytes area from the address indicated in the table base register (TBR) is the vector area for EIT. ■ EIT Vector Table The size for each vector is 4 bytes. The relationship between a vector number and a vector address can be expressed as follows: vctadr = TBR + vctofs = TBR + (3FC H - 4 x vct) vctadr: Vector address vctofs: Vector offset vct: Vector number The low-order two bits of the addition result are always handled as 00. The area from 000FFC00H to 000FFFFFH is the initial area for the vector table upon reset. Special functions are allocated to some of the vectors. Table 3.7-3 shows the vector table on the architecture. Table 3.7-3 Vector Table (1 / 4) Interrupt number Interrupt source Interrupt level Offset Default address of TBR Decimal Hexadecimal Reset *1 0 00 - 3FCH 000FFFFCH Mode vector *1 1 01 - 3F8H 000FFFF8H Reserved for system 2 02 - 3F4H 000FFFF4H Reserved for system 3 03 - 3F0H 000FFFF0H Reserved for system 4 04 - 3ECH 000FFFECH Reserved for system 5 05 - 3E8H 000FFFE8H Reserved for system 6 06 - 3E4H 000FFFE4H No-coprocessor trap 7 07 - 3E0H 000FFFE0H Coprocessor error trap 8 08 - 3DCH 000FFFDCH INTE instruction 9 09 - 3D8H 000FFFD8H Instruction break exception 10 0A - 3D4H 000FFFD4H Operand break trap 11 0B - 3D0H 000FFFD0H Step trace trap 12 0C - 3CCH 000FFFCCH 80 Table 3.7-3 Vector Table (2 / 4) Interrupt number Interrupt source Interrupt level Offset Default address of TBR Decimal Hexadecimal NMI request (tool) 13 0D - 3C8H 000FFFC8H Undefined instruction exception 14 0E - 3C4H 000FFFC4H NMI request 15 0F Fixed to 15(FH) 3C0H 000FFFC0H External Interrupt 0 16 10 ICR00 3BCH 000FFFBCH External Interrupt 1 17 11 ICR01 3B8H 000FFFB8H External Interrupt 2 18 12 ICR02 3B4H 000FFFB4H External Interrupt 3 19 13 ICR03 3B0H 000FFFB0H External Interrupt 4 20 14 ICR04 3ACH 000FFFACH External Interrupt 5 21 15 ICR05 3A8H 000FFFA8H External Interrupt 6 22 16 ICR06 3A4H 000FFFA4H External Interrupt 7 23 17 ICR07 3A0H 000FFFA0H Reload Timer 0 24 18 ICR08 39CH 000FFF9CH Reload Timer 1 25 19 ICR09 398H 000FFF98H Reload Timer 2 26 1A ICR10 394H 000FFF94H Maskable interrupt source *2 27 1B ICR11 390H 000FFF90H Maskable interrupt source *2 28 1C ICR12 38CH 000FFF8CH Maskable interrupt source *2 29 1D ICR13 388H 000FFF88H Maskable interrupt source *2 30 1E ICR14 384H 000FFF84H Maskable interrupt source *2 31 1F ICR15 380H 000FFF80H Maskable interrupt source *2 32 20 ICR16 37CH 000FFF7CH Maskable interrupt source *2 33 21 ICR17 378H 000FFF78H Maskable interrupt source *2 34 22 ICR18 374H 000FFF74H Maskable interrupt source *2 35 23 ICR19 370H 000FFF70H Maskable interrupt source *2 36 24 ICR20 36CH 000FFF6CH Maskable interrupt source *2 37 25 ICR21 368H 000FFF68H Maskable interrupt source *2 38 26 ICR22 364H 000FFF64H 81 CHAPTER 3 CPU AND CONTROL UNITS Table 3.7-3 Vector Table (3 / 4) Interrupt number Interrupt source Interrupt level Offset Default address of TBR Decimal Hexadecimal Maskable interrupt source *2 39 27 ICR23 360H 000FFF60H Maskable interrupt source *2 40 28 ICR24 35CH 000FFF5CH Maskable interrupt source *2 41 29 ICR25 358H 000FFF58H Maskable interrupt source *2 42 2A ICR26 354H 000FFF54H Maskable interrupt source *2 43 2B ICR27 350H 000FFF50H Maskable interrupt source *2 44 2C ICR28 34CH 000FFF4CH Maskable interrupt source *2 45 2D ICR29 348H 000FFF48H Maskable interrupt source *2 46 2E ICR30 344H 000FFF44H Timebase timer overflow 47 2F ICR31 340H 000FFF40H Maskable interrupt source *2 48 30 ICR32 33CH 000FFF3CH Maskable interrupt source *2 49 31 ICR33 338H 000FFF38H Maskable interrupt source *2 50 32 ICR34 334H 000FFF34H Maskable interrupt source *2 51 33 ICR35 330H 000FFF30H Maskable interrupt source *2 52 34 ICR36 32CH 000FFF2CH Maskable interrupt source *2 53 35 ICR37 328H 000FFF28H Maskable interrupt source *2 54 36 ICR38 324H 000FFF24H Maskable interrupt source *2 55 37 ICR39 320H 000FFF20H Maskable interrupt source *2 56 38 ICR40 31CH 000FFF1CH Maskable interrupt source *2 57 39 ICR41 318H 000FFF18H Maskable interrupt source *2 58 3A ICR42 314H 000FFF14H Maskable interrupt source *2 59 3B ICR43 310H 000FFF10H Maskable interrupt source *2 60 3C ICR44 30CH 000FFF0CH Maskable interrupt source *2 61 3D ICR45 308H 000FFF08H Maskable interrupt source *2 62 3E ICR46 304H 000FFF04H Delayed interrupt source bit 63 3F ICR47 300H 000FFF00H Reserved for system (used in REALOS) 64 40 - 2FCH 000FFEFCH 82 Table 3.7-3 Vector Table (4 / 4) Interrupt number Interrupt source Interrupt level Offset Default address of TBR Decimal Hexadecimal Reserved for system (used in REALOS) 65 41 - 2F8H 000FFEF8H Reserved for system 66 42 - 2F4H 000FFEF4H Reserved for system 67 43 - 2F0H 000FFEF0H Reserved for system 68 44 - 2ECH 000FFEECH Reserved for system 69 45 - 2E8H 000FFEE8H Reserved for system 70 46 - 2E4H 000FFEE4H Reserved for system 71 47 - 2E0H 000FFEE0H Reserved for system 72 48 - 2DCH 000FFEDCH Reserved for system 73 49 - 2D8H 000FFED8H Reserved for system 74 4A - 2D4H 000FFED4H Reserved for system 75 4B - 2D0H 000FFED0H Reserved for system 76 4C - 2CCH 000FFECCH Reserved for system 77 4D - 2C8H 000FFEC8H Reserved for system 78 4E - 2C4H 000FFEC4H Reserved for system 79 4F - 2C0H 000FFEC0H 80 50 2BCH 000FFEBCH … … 255 FF Used in INT instruction - … … 000H 000FFC00H *1: Even though the TBR value is changed, the reset vector and the mode vector are always fixed addresses. 000FFFFCH and 000FFFF8H are used. *2: The maskable interrupt source is defined for each model. For the vector table for this model type, see "APPENDIX B Interrupt Vector". 83 CHAPTER 3 CPU AND CONTROL UNITS 3.7.7 Multiple EIT Processing If multiple EIT causes occur at the same time, the CPU repeats the operation of selecting and accepting one of the EIT causes, executing the EIT sequence, and then detecting EIT causes again. If there are no more EIT causes be accepted while the CPU is detecting EIT causes, the CPU executes the handler instruction of the last accepted EIT cause. As a result, the order of executing handlers for multiple EIT causes that occur at the same time is determined according to the following two elements: 1. Priority of EIT causes to be accepted 2. How other causes can be masked when one cause is accepted ■ Priority of EIT Causes to Be Accepted The priority of EIT causes to be accepted is the order of causes for which the EIT sequence is to be executed (that is, saving the PS and PC, updating the PC, and masking other causes, if required). The handler of a cause accepted earlier is not necessarily executed earlier. Table 3.7-4 lists the acceptance priority of EIT causes. Table 3.7-4 Priority of EIT Causes to Be Accepted and Masking of Other Causes Priority of acceptance Cause Masking of other causes 1 Reset Other causes are abandoned. 2 Undefined instruction exception Canceled 3 INT instruction I flag=0 4 No-coprocessor trap Coprocessor error trap - 5 User interrupt ILM=level of cause accepted 6 NMI (for users) ILM=15 7 (INTE instruction) ILM=4 * 8 NMI (for emulators) ILM=4 9 Step trace trap ILM=4 10 INTE instruction ILM=4 *: The priority is 6 only if the INTE instruction and the NMI for emulators occur at the same time. (This model type uses NMI for emulators for breaks occurring because of data access.) 84 In consideration of masking other causes after an EIT cause is accepted, the handlers of EIT causes that occur at the same time are executed in the order shown in Table 3.7-5 . Table 3.7-5 Order of Executing EIT Handlers Order of executing handlers Cause 1 Reset *1 2 Undefined instruction exception 3 Step trace trap *2 4 INTE instruction *2 5 NMI (for users) 6 INT instruction 7 User interrupt 8 No-coprocessor trap, coprocessor error trap *1: Other causes are abandoned. *2: If the INTE instruction is executed in steps, only a step trace trap EIT occurs. An INTE cause is ignored. Figure 3.7-2 shows an example of multiple EIT processing. Figure 3.7-2 Multiple EIT Processing Main routine Priority NMI handler INT instruction handler (1) Executed first (High) NMI occurring (Low) INT instruction executed (2) Executed next 85 CHAPTER 3 CPU AND CONTROL UNITS 3.7.8 Operations This section describes the operation of FR family microcontrollers. In the following, it is assumed that the transfer source PC indicates the address of the instruction that detected an EIT cause. In addition, "address of the next instruction" means that the instruction that detected EIT is as follows: • If LDI is 32: PC + 6 • If LDI is 20 and COPOP, COPLD, COPST, and COPSV are used: PC + 4 • Other instructions: PC + 2 ■ Operation of User Interrupt/NMI If an interrupt request for a user interrupt or a user NMI occurs, whether the request can be accepted is determined with the following procedure: [Determining whether an interrupt request can be accepted] 1. Compare the interrupt levels of requests that have occurred simultaneously and select the request with the highest level (the smallest value). As levels to be compared, the value held in the corresponding ICR is used for a maskable interrupt and a predetermined constant is used for an NMI. 2. If multiple interrupt requests with the same level occur, select the interrupt request with the smallest interrupt number. 3. Mask and do no accept an interrupt request with an interrupt level greater than or equal to the level mask value. Go to Step 4) if the interrupt level is less than the level mask value. 4. Mask and do not accept the selected interrupt request if it is maskable and the I flag is set to 0. Go to Step 5) if the I flag is "1". If the selected interrupt request is an NMI, go to Step 5) regardless of the I flag value. 5. If the above conditions are met, the interrupt request is accepted at a break in the instruction processing. If a user interrupt or NMI request is accepted when EIT requests are detected, the CPU operates as follows, using an interrupt number corresponding to the accepted interrupt request. Note: The parentheses in [Operation] indicate an address pointed to by the register. [Operation] 1. SSP-4 → SSP 2. PS → (SSP) 3. SSP-4 → SSP 4. Address of next instruction → (SSP) 5. Interrupt level of accepted request → ILM 6. "0" → S flag 7. (TBR + Vector offset of accepted interrupt request) → PC After the interrupt sequence was finished, the CPU performs the detection of new EIT before processing the lead instruction of the handler. If an acceptable EIT is detected at this time, the CPU enters the EIT process sequence. Executing the ORCCR,STILM and MOV Ri,PS command to allow interruptions when user interruption or NMI factors have been occurred may executes above commands twice before and after the interrupt 86 handler. There is no problem of operation, however, because the same values are set twice for the registers in the CPU. Do not perform any process desiring the contents of the PS resister before the EIT branch in the EIT process routine. ■ Operation of INT Instruction INT#u8: A branch to the interrupt handler for the vector indicated by u8 generation. [Operation] 1. SSP-4 → SSP 2. PS → (SSP) 3. SSP-4 → SSP 4. PC + 2 → (SSP) 5. "0" → I flag 6. "0" → S flag 7. (TBR + 3FCH-4 x u8) → PC ■ Operation of INTE Instruction INTE: A branch to the interrupt handler for the vector indicated by vector number #9 generation. [Operation] 1. SSP-4 → SSP 2. PS → (SSP) 3. SSP-4 → SSP 4. PC + 2 → (SSP) 5. "00100" → ILM 6. "0" → S flag 7. (TBR+3D8H) → PC Do not use the INTE instruction in the processing routine of the INTE instruction or a step trace trap. During step execution, no EIT due to INTE generates. 87 CHAPTER 3 CPU AND CONTROL UNITS ■ Operation of Step Trace Trap Set the T flag in the SCR of the PS to enable the step trace function. A trap and a break then occur every time an instruction is executed. [Step trace trap detection conditions] 1. T flag =1 2. There is no delayed branch instruction. 3. A processing routine other than the INTE instruction or a step trace trap is in progress. 4. If the above conditions are met, a break occurs between instruction operations. [Operation] 1. SSP-4 → SSP 2. PS → (SSP) 3. SSP-4 → SSP 4. Address of next instruction → (SSP) 5. "00100" → ILM 6. "0" → S flag 7. (TBR+3CCH) → PC Set the T flag to enable the step trace trap to prohibit a user NMI and a user interrupt. No EIT occurs due to the INTE instruction. In FR family microcontrollers, a trap occurs for the instruction that follows the instruction that set the T flag. ■ Operation of Undefined Instruction Exception If, during instruction decode, an undefined instruction is detected, an undefined instruction exception occurs. [Undefined instruction exception detection conditions] 1. An undefined instruction is detected during instruction decode. 2. The instruction is not located in the delay slot (it does not immediately follow the delayed branch instruction). 3. If the above conditions are met, an undefined instruction exception and a break occur. [Operation] 1. SSP-4 → SSP 2. PS → (SSP) 3. SSP-4 → SSP 4. PC → (SSP) 5. "0" → S flag 6. (TBR+3C4H) → PC The PC value to be saved is the address of an instruction that detected an undefined instruction exception. 88 ■ No-coprocessor Trap If a coprocessor instruction using a coprocessor that is not installed is executed, a no-coprocessor trap occurs. [Operation] 1. SSP-4 → SSP 2. PS → (SSP) 3. SSP-4 → SSP 4. Address of next instruction → (SSP) 5. "0" → S flag 6. (TBR+3E0H) → PC ■ Coprocessor Error Trap If an error occurs while a coprocessor is being used and then a coprocessor instruction that operates on the coprocessor is executed, a coprocessor error trap occurs. [Operation] 1. SSP-4 → SSP 2. PS → (SSP) 3. SSP-4 → SSP 4. Address of next instruction → (SSP) 5. "0" → S flag 6. (TBR+3DCH) → PC ■ Operation of RETI Instruction The RETI instruction specifies return from the EIT processing routine. [Operation] 1. (R15) → PC 2. R15+4 → R15 3. (R15) → PS 4. R15+4 → R15 The RETI instruction must be executed while the S flag is set to 0. 89 CHAPTER 3 CPU AND CONTROL UNITS 3.8 Operating Modes This section describes the operating modes of the FR family microcontrollers. ■ Overview of Operating Modes The two operating modes are bus mode and access mode. ■ Bus Mode Bus mode refers to a mode in which the operations of internal ROM and the external access function are controlled. A bus mode is specified using the mode setting pins (MD2, 1, and 0) and the ROMA bit in the mode data. ■ Access Mode An access mode, indicates the mode to control the external data bus width, is specified using the WTH1 and WTH0 bits in the mode register and the DBW1 and DBW0 bits in ACR0 to 7 (Area Configuration Register). 90 3.8.1 Bus Modes FR family microcontrollers have the three types of bus modes listed below. For details, see Section "3.1 Memory Space". ■ Bus Mode 0 (Single-chip Mode) In this mode, internal I/O, D-bus RAM, F-bus RAM, and F-bus ROM are valid. Access to other areas is invalid. External pins do not serve as bus pins, but serve as peripheral or general-purpose ports. ■ Bus Mode 1 (Internal-ROM/External-bus Mode) In this mode, internal I/O, D-bus RAM, and F-bus RAM, as well as F-bus ROM, are valid. Access to an area that enables external access is handled as access to an external space. Some external pins serve as bus pins. ■ Bus Mode 2 (External-ROM/External-bus Mode) In this mode, internal I/O and D-bus RAM are valid, but access to F-bus RAM and F-bus ROM are invalid. All accesses are handled as access to an external space. Some external pins serve as bus pins. 91 CHAPTER 3 CPU AND CONTROL UNITS 3.8.2 Mode Settings In the FR family microcontrollers, the mode pins (MD2, MD1, and MD0) and the mode register (MODR) are used to set the operating mode. ■ Mode Pins Use the three mode pins (MD2, MD1, and MD0) to specify mode vector fetch. Table 3.8-1 lists the specifications related to mode vector fetch. Table 3.8-1 Specifications Related to Mode Vector Fetch Mode pin Mode name Reset vector access area Remarks MD2 MD1 MD0 0 0 0 Internal ROM mode vector Internal - 0 0 1 External ROM mode vector External Set the bus width using the mode register. Settings not listed in the table above are not allowed. ■ Mode Register (MODR) Mode data is data written to the mode register by a mode vector fetch. For the mode vector fetch, see (Section "3.9.3 Reset Sequence"). After the data is set to the mode register (MODR), it operates in the operating mode according to this register setting. Mode data is always set in the mode register when any reset source arises. A user program cannot write data to the mode register. Reference: Nothing exists at the address (0000_07FFH) of the mode register in conventional FR family microcontrollers. Data can be rewritten to the mode register in emulator mode. Use an 8-bit long data transfer instruction to rewrite data. A 16-bit or 32-bit long data transfer instruction cannot be used to rewrite data to the mode register. Details of the mode register are given below: 92 [Detailed explanation of the register] MODR 000FFFF8H 7 6 5 4 3 0 0 0 0 0 2 1 0 Initial value XXXXXXXX ROMA WTH1 WTH0 B Operation mode setting bits [Bits 7 to 3] Reserved bits Be sure to set bits 7 to 3 to 00000. If any other value is set for these bits, operation is unpredictable. [Bit 2] ROMA (Internal ROM enable bit) This bit indicates whether to enable internal F-bus RAM and F-bus ROM areas. ROMA Function Remarks 0 External ROM mode The internal F-bus RAM is enabled, and the internal ROM area (80000H to 100000H) becomes the external ROM area. 1 Internal ROM mode The internal F-bus RAM and F-bus ROM are enabled. [Bits 1, 0] WTH1, WTH0 (Bus width specification bit) These bits indicate the bus width specification to be used in external bus mode. In external bus mode, this value is set in the BW1 and BW0 bits of AMD0 (CS0 area). WTH1 WTH0 Function Remarks 0 0 8-bit bus width External bus mode 0 1 16-bit bus width External bus mode 1 0 - Setting prohibited 1 1 Single-chip mode Single-chip mode 93 CHAPTER 3 CPU AND CONTROL UNITS 3.9 Reset (Device Initialization) This section describes a reset (that is, initialization) of the MB91350A. ■ Overview of Reset (Device Initialization) If a reset source occurs, the device stops all the programs and hardware operations and completely initializes the state. This state is called the reset state. When a reset source no longer exists, the device starts programs and hardware operations from their initial state. The series of operations from the reset state to the start of operations is called the reset sequence. 94 3.9.1 Reset Levels The reset operations of the MB91350A are classified into two levels, each of which has different causes and initialization operations. This section describes these reset levels. ■ Settings Initialization Reset (INIT) The highest-level reset, which initializes all settings, is called a settings initialization reset (INIT). A settings initialization reset (INIT) mainly performs the following initialization: [Items initialized in a settings initialization reset (INIT)] • Device operation mode (bus mode and external bus width settings) • All internal clock settings (clock source selection, PLL control, and divide ratio setting) • All settings on external bus CS0 area • All settings on pin statuses other than the above settings • All sections initialized by an operation initialization reset (RST) For more information, see the description of each for these functions. After power-on, be sure to apply a settings initialization reset (INIT) at the INIT pin. ■ Operation Initialization Reset (RST) A normal-level reset that initializes the operation of a program is called an operation initialization reset (RST). If a settings initialization reset (INIT) occurs, an operation initialization reset (RST) also occurs. An operation initialization reset (RST) mainly initializes the following items: [Items initialized by an operation initialization reset (RST)] • Program operation • CPU and internal buses • Register settings of peripheral circuits • I/O port settings • All CS0 area settings of external buses For more information, see the description of each for these functions. 95 CHAPTER 3 CPU AND CONTROL UNITS 3.9.2 Reset Sources This section describes the reset sources and the reset levels in the MB91350A. To determine reset sources that have occurred in the past, read the RSRR (reset source register). (For more information about registers and flags described in this section, see Section "3.10.5 Block Diagram of Clock Generation Controller" and "3.10.6 Register of Clock Generation Controller".) ■ INIT Pin Input (Settings Initialization Reset Pin) The INIT pin, which is an external pin, is used as the settings initialization reset pin. A settings initialization reset (INIT) request is generated while the "L" level is being input to this pin. Input the "H" level to this pin to clear a settings initialization reset (INIT) request. If a settings initialization reset (INIT) is generated in response to a request from this pin, Bit 15 (INIT bit) of the RSRR (reset source register) is set. Because a settings initialization reset (INIT) in response to a request from this pin has the highest interrupt level among all reset sources, it has precedence over any other input, operation, or state. Immediately after power-on, be sure to apply a settings initialization reset (INIT) at the INIT pin. To assure the oscillation stabilization wait time for the oscillation circuit immediately after power-on, input the "L" level to the INIT pin for the stabilization wait time required by the oscillation circuit. INIT at the INIT pin initializes the oscillation stabilization wait time to the minimum value. 96 • Reset source: "L" level input to the external INIT pin • Source of clearing: "H" level input to the external INIT pin • Reset level: Settings initialization reset (INIT) • Corresponding flag: Bit 15 (INIT) ■ Software Reset (STCR: SRST Bit Writing) If "0" is written to Bit 4 (SRST bit) of the standby control register (STCR), a software reset request occurs. A software reset request is an operation initialization reset (RST) request. When the request is accepted and a operation initialization reset (RST) is generated, the software reset request is cleared. If an operation initialization reset (RST) is generated due to a software reset request, a Bit 11 (SRST bit) in the RSRR (reset source register) is set. An operation initialization reset (RST) is generated due to a software reset request only after all bus access has stopped and if Bit 7 (SYNCR bit) of the timebase counter control register (TBCR) has been set (synchronization reset mode). Thus, depending on the bus usage status, a long time is required before an operation initialization reset (RST) occurs. • Reset source: Writing "0" to Bit 4 (SRST) of the standby control register (STCR) • Source of clearing: Generation of an operation initialization reset (RST) • Reset level: Operation initialization reset (RST) • Corresponding flag: Bit 11(SRST) ■ Watchdog Reset Writing to the watchdog timer control register (RSRR) starts the watchdog timer. Unless A5H/5AH is written to the watchdog reset postpone register (WPR) within the cycle specified in Bits 9 and 8 (WT1 and WT0 bits) in the RSRR, a watchdog reset request occurs. A watchdog reset request is a settings initialization reset (INIT) request. If, after the request is accepted, a settings initialization reset (INIT) occurs or an operation initialization reset (RST) occurs, the watchdog reset request is cleared. If a settings initialization reset (INIT) is generated due to a watchdog reset request, Bit 13 (WDOG bit) in the reset source register (RSRR) is set. Note that, if a settings initialization reset (INIT) is generated due to a watchdog reset request, the oscillation stabilization wait time is not initialized. • Reset source: Setting cycle of the watchdog timer elapses • Source of clearing: Generation of a settings initialization reset (INIT) or an operation initialization reset (RST) • Reset level: Settings initialization reset (INIT) • Corresponding flag: Bit 13 (WDOG) 97 CHAPTER 3 CPU AND CONTROL UNITS 3.9.3 Reset Sequence When a reset source no longer exists, the device starts to execute the reset sequence. A reset sequence has different operations depending on the reset level. This section describes the operations of the reset sequence for different reset levels. ■ Setting Initialization Reset (INIT) Clear Sequence If a settings initialization reset (INIT) request is cleared, the following operations are performed one step at a time for the device. 1. Clear the settings initialization reset (INIT) and enter the oscillation stabilization wait state. 2. For the oscillation stabilization wait time (set with Bits 3 and 2 [OS1 and OS0 bits] in the STCR), maintain the operation initialization reset (RST) state and stop the internal clock. 3. In the operation initialization reset (RST) state, start internal clock operation. 4. Clear the operation initialization reset (RST) and enter the normal operating state. 5. Read the mode vector from address 000FFFF8H. 6. Write the mode vector to the MODR (mode register) at address 000007FDH. 7. Read the reset vector from address 000FFFFCH. 8. Write the reset vector to the program counter (PC). 9. The program starts execution from the address loaded in the program counter (PC). ■ Operation Initialization Reset (RST) Clear Sequence If an operation initialization reset (RST) request is cleared, the following operations are performed one step at a time for the device. 1. Clear the operation initialization reset (RST) and enter the normal operating state. 2. Read the mode vector from address 000FFFF8H. 3. Write the mode vector to the mode register (MODR) at address 000007FDH. 4. Read the reset vector from address 000FFFFCH. 5. Write the reset vector to the program counter (PC). 6. The program starts execution from the address loaded in the program counter (PC). 98 3.9.4 Oscillation Stabilization Wait Time If a device returns from the state in which the original oscillation was or may have been stopped, the device automatically enters the oscillation stabilization wait state. This function prevents the use of oscillator output after starting before oscillation has stabilized. For the oscillation stabilization wait time, neither an internal nor an external clock is supplied; only the built-in timebase counter runs until the stabilization wait time set in the standby control register (STCR) has elapsed. This section describes the oscillation stabilization wait operation. ■ Sources of an Oscillation Stabilization Wait The following lists sources of an oscillation stabilization wait. ● Clearing of a settings initialization reset (INIT) The device enters the oscillation stabilization wait state if a settings initialization reset (INIT) is cleared for a variety of reasons. When the oscillation stabilization wait time has elapsed, the device enters the operation initialization reset (RST) state. For initialization that uses the INIT pin, since the oscillation stabilization wait time is set to the minimum value, there is no wait for oscillation stabilization. When power-on is executed or after oscillation has stopped, input an oscillation stabilization wait time INIT. ● Returning from stop mode The device enters the oscillation stabilization wait state immediately after stop mode is cleared. However, if it is cleared by a settings initialization reset (INIT) request, the device enters the settings initialization reset (INIT) state. Then, after the settings initialization reset (INIT) is cleared, the device enters the oscillation stabilization wait state. When the oscillation stabilization wait time has elapsed, the device enters the state corresponding to the source that cleared stop mode: • Return due to input of a valid external interrupt request (including NMI) and occurrence of a watch timer/main clock oscillation stabilization wait timer interrupt: The device enters the normal operating state. • Return due to a settings initialization reset (INIT) request: The device enters the operation initialization reset (RST) state. 99 CHAPTER 3 CPU AND CONTROL UNITS ● Returning from an abnormal state when PLL is selected If, while the device is operating with PLL as the source clock, an abnormal condition* occurs in PLL control, the device automatically enters an oscillation stabilization wait time to assure the PLL lock time. When the oscillation stabilization wait time has elapsed, the device enters the normal operating state. *: The multiply-by rate is changed while PLL is working, or an incorrect bit such as a bit equivalent to PLL operation enable bit is generated. ● Occurrence of a watchdog reset when main clock oscillation has been stopped by the subclock If, while the subclock is operating as the source clock, a watchdog reset occurs when main clock oscillation has been stopped due to bit 0 (OSCDS1 bit) of the OSCCR (oscillation control register), the device enters an oscillation stabilization wait immediately after the reset (INIT) is cleared. When the oscillation stabilization wait time elapses, the device enters the operation initialization reset (RST) state. There is no wait for oscillation stabilization when the OSCDS1 bit is "0" for the subclock or when the main clock is the source clock. ■ Selecting an Oscillation Stabilization Wait Time The oscillation stabilization wait time is measured with the built-in timebase counter. If a source for an oscillation stabilization wait occurs and the device enters the oscillation stabilization wait state, the built-in timebase counter is initialized and then it starts to measure the oscillation stabilization wait time. Using Bits 3 and 2 (OS1 and OS0 bits) of the standby control register (STCR), select and set one of the four types for oscillation stabilization wait time. Once selected, a setting is initialized only if a settings initialization reset (INIT) is generated due to the external INIT pin. The oscillation stabilization wait time that has been set before a reset is maintained if a settings initialization reset (INIT) is generated or an operation initialization reset (RST) is generated due to a watchdog reset condition. The four types of oscillation stabilization wait time settings are designed for the following four types of use: • OS1, OS0=00: No oscillation stabilization wait time (if neither PLL nor the oscillator should stop in stop mode) • OS1, OS0=01: PLL lock wait time (if an oscillator should not stop in stop mode) • OS1, OS0=10: Oscillation stabilization wait time (intermediate) (if an oscillator that stabilizes quickly, such as a ceramic vibrator, is used) • OS1, OS0=11: Oscillation stabilization wait time (long) (if an ordinary quartz oscillator will be used) 100 Immediately after power-on, be sure to apply the settings initialization reset (INIT) at the INIT pin. To assure the oscillation stabilization wait time of the oscillation circuit immediately after power-on, maintain "L" level input to the INIT pin for the stabilization wait time required by the oscillation circuit. (INIT generated due to the INIT pin initializes the oscillation stabilization wait time setting to the minimum value.) • INIT pin input immediately after power-on • INIT pin input while oscillation is stopped in STOP mode • INIT pin input when the subclock has been selected as the clock source and main clock oscillation has stopped Therefore, to ensure stabilization of both the main clock and subclock oscillation, input the "L" level to the INIT pin during an oscillation stabilization wait time that satisfies both the main clock and the subclock 101 CHAPTER 3 CPU AND CONTROL UNITS 3.9.5 Reset Operation Modes Two modes for an operation initialization reset (RST) are provided: normal (asynchronous) reset mode and synchronous reset mode. The operation initialization reset mode is selected with Bit 7 (SYNCR bit) of the timebase counter control register (TBCR). This mode setting is initialized only by a settings initialization reset (INIT). A settings initialization reset (INIT) always results in an asynchronous reset. This section describes the operation of these modes. ■ Normal Reset Operation Normal reset operation refers to a transition to the operation initialization rest (RST) state immediately after an operation initialization reset (RST) request. If a rest (RST) request is accepted in this mode, the device immediately enters the reset (RST) state regardless of the status for internal bus access. In this mode, the result of a bus access being performed prior to each state transition is unpredictable. However, these requests can certainly be accepted. If Bit 7 (SYNCR bit) of the timebase counter control register (TBCR) is set to "0", normal reset mode is selected. The initial value after a settings initialization reset (INIT) is normal reset mode. ■ Synchronous Reset Operation Synchronous reset operation refers to a transition to the operation initialization reset (RST) state after all bus access has stopped when an operation initialization reset (RST) request occurs. Even if a reset (RST) request is accepted in this mode, the device does not enter the reset (RST) state while internal bus access is in progress. If the above request is accepted, a sleep request is issued to the internal buses. If all the buses stop and enter the sleep state, the device enters the operation initialization reset (RST) state. In this mode, the result of all bus accesses is guaranteed because all bus access is stopped prior to each status transition. If bus access does not stop for some reason, no requests can be accepted while the bus access is in progress. (Even in this case, the settings initialization reset (INIT) is immediately valid.) Bus access may not stop in the following cases: 102 • A bus release request (BRQ) continues to be inputted to the external extended bus interface, bus release acknowledge (BGRNT) is valid, and a new bus access request arrives from an internal bus. • A ready request (RDY) continues to be inputted to the external extended bus interface and bus wait is valid. (In the following cases, the device eventually enters another state but only after a long time): • When the self-refresh of sleep time is available with activating the SDRAM interface (The state does not transit until the self-refresh mode is completed.): References: • The DMA controller, which stops transfer when a request is accepted, does not delay transition to another state. • If Bit 7 (SYNCR bit) of the timebase counter control register (TBCR) is set to "1", synchronous reset mode is selected. The initial value after a settings initialization reset (INIT) is normal reset mode. 103 CHAPTER 3 CPU AND CONTROL UNITS 3.10 Clock Generation Control This section describes clock generation control. ■ Generation of Internal Operating Clock The internal operating clock of the MB91350A model type is generated as follows: • Selection of a source clock: Select a clock supply source. • Generation of a base clock: • Generation of an internal clock: Divide the source clock by two or perform PLL oscillation to generate a base clock. Divide the base clock and generate four types of operating clocks, which are supplied to each section. The following describes generation and control of each clock. For a detailed explanation of the registers and flags used in the explanation, see Section "3.10.5 Block Diagram of Clock Generation Controller" and Section "3.10.6 Register of Clock Generation Controller". ■ Selection of Source Clock The following describes source clock selection. A resonator is connected to external oscillator pins X0/X1 and X0A/X1A, and the source oscillation generated by the built-in oscillator circuit is used as the source clock. The MB91350A model type is the source of all clocks, including the external bus clock. The external oscillator pins and built-in oscillator circuit can use the main clock or subclock, and these two clocks can be arbitrarily switched during operation. • Main clock: The main clock, generated from the X0/X1 pins, is intended for use as a high-speed clock. • Subclock: The subclock, generated from the X0A/X1A pins, is intended for use as a low-speed clock. The main clock and subclock are multiplied by the built-in main PLL and subclock, each of which can be independently controlled. Generate an internal base clock by selecting one of the following source clocks: • Main clock divided by 2 • Main clock multiplied in the main PLL • Subclock as is Select a source clock by setting the clock source control register (CLKR). 104 3.10.1 PLL Controls The settings for enabling and disabling operation (oscillation) and for the multiply-by rate can be controlled for the PLL oscillator circuits that correspond to the main clock. Each control is set in the clock source control register (CLKR). This section describes each control. ■ PLL Operation Enable To enable or disable the main PLL oscillator circuit operation, set bit 10 (PLL1EN bit) of the clock source control register (CLKR). To enable or disable the subclock oscillator circuit operation, set bit 11 (PLL2EN bit) of the clock source control register (CLKR). After a setting initialization reset (INIT), bits PLL1EN and PLL2EN are initialized to "0", causing the PLL oscillator circuit operation to stop. While it is stopped, PLL output cannot be selected as the source clock. When the program operation starts, set the multiply-by rate of the PLL to be used as the clock source, enable it, and switch the source clock after the PLL lock wait time elapses. For the PLL lock wait time, use of a timebase timer interrupt is recommended. While PLL output is selected as the source clock, the PLL cannot be stopped (writing to the register is disabled). To stop a PLL upon transition to stop mode, reselect as the source clock the main clock divided by two before stopping the PLL. If Bit 0 (OSCD1 bit) or Bit 1 (OSCD2 bit) of the standby control register (STCR) is set to stop oscillation in stop mode, the corresponding PLL automatically stops when the device enters stop mode. As a result, you do not need to set operation stop. When the device returns from stop mode later, the PLL automatically restarts the oscillation operation. If oscillation is not set to stop in stop mode, the PLL does not automatically stop. In this case, set operation stop before transition to stop mode as required. ■ PLL Multiply-by Rate Set the multiply-by rate of the main PLL in Bits 14 to 12 (PLL1S2, PLL1S1, and PLL1S0 bits) of the clock source control register (CLKR). After a setting initialization reset (INIT), all bits are initialized to "0". ● PLL multiply-by rate setting To change the PLL multiply-by rate setting from the initial value, do so before or as soon as the PLL is enabled after the program has started execution. After changing the multiply-by rate, switch the source clock after the lock wait time elapses. For the PLL lock wait time, use of a timebase timer interrupt is recommended. To change the PLL multiply-by rate setting during operation, switch the source clock to a clock other than the PLL in question before making the change. After changing the multiply-by rate, switch the source clock after the lock wait time has elapsed, as described above. You can also change the PLL multiply-by rate setting while using a PLL. In this case, however, the program stops running after the device automatically enters the oscillation stabilization wait state after the multiply-by rate setting is rewritten and does not resume execution until the specified oscillation stabilization wait time has elapsed. The program does not stop running if the clock source is switched to a clock other than a PLL. 105 CHAPTER 3 CPU AND CONTROL UNITS 3.10.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time If a clock selected as the source clock is not already stabilized, an oscillation stabilization wait time is required (See Section "3.9.4 Oscillation Stabilization Wait Time"). For a PLL, a lock wait time is required after operation starts until the output stabilizes to the specified frequency. This section describes the wait time used in various situations. ■ Wait Time after Power-On After power-on, an oscillation stabilization wait time for the main clock oscillation circuit is required. Since the oscillation stabilization wait time setting is initialized to the minimum value due to INIT pin input (settings initialization reset pin), assure the oscillation stabilization wait time by using the time during which the "L" level is sent to the INIT pin input. In this state, since no PLL is enabled, no lock wait time needs to be considered. ■ Wait Time after Setting Initialization If a settings initialization reset (INIT) is cleared, the device enters the oscillation stabilization wait state. In this case, the specified oscillation stabilization wait time is internally generated. In the first oscillation stabilization wait state after input from the INIT pin, the setting time is initialized to the minimum value, soon ending this state, and the device enters the operation initialization reset (RST) state. If, after a program starts running, a settings initialization reset (INIT) is generated for a reason other than INIT pin input and is then cleared, the oscillation stabilization wait time specified in the program is internally generated. In these states, since no PLL is enabled, no lock wait time needs to be considered. ■ Wait Time after Enabling a PLL If you enable a stopped PLL after a program starts execution, use the PLL output only after the lock wait time elapses. If the PLL is not selected as the source clock, the program can run even during the lock wait time. For the PLL lock wait time, use of a timebase timer interrupt is recommended. ■ Wait Time after Changing the PLL Multiply-by Rate If you change the multiply-by rate setting of a running PLL after a program starts execution, use the PLL output only after lock wait time elapses. If the PLL is not selected as the source clock, the program can run even during the lock wait time. For the PLL lock wait time, use of a timebase timer interrupt is recommended. 106 ■ Wait Time after Returning from Stop Mode If, after a program starts execution, the device enters stop mode and then stop mode is cleared, the oscillation stabilization wait time specified in the program is internally generated. If the clock oscillation circuit selected as the source clock is set to stop in stop mode, the oscillation stabilization wait time of the oscillation circuit or the lock wait time of the PLL in use, whichever is longer, is required. Set the oscillation stabilization wait time before entering stop mode. If the clock oscillation circuit selected as the source clock is not set to stop in stop mode, the PLL does not automatically stop. No oscillation stabilization wait time is required unless the PLL has stopped. Setting the oscillation stabilization wait time to the minimum value before stop mode is entered is recommended. ■ Wait Time after Switching From the Subclock to the Main Clock If the PLL is used after switching from the subclock to the main clock, the PLL output must not be used until the lock wait time has elapsed. This applies regardless of the value for bit 2 (PLL1EN) of the CLKR (clock source register). Even if there is a lock wait time, the program can be executed if the source clock has been selected to use a PLL. Fujitsu recommends using a timebase timer interrupt for the PLL lock wait time in this case. 107 CHAPTER 3 CPU AND CONTROL UNITS 3.10.3 Clock Distribution An operating clock for each function is generated based on the base clock generated from the source clock. A total of three internal operating clocks are provided. A divideby rate can be set independently for each of them. This section describes these internal operating clocks. ■ CPU Clock (CLKB) This clock is used for the CPU, internal memory, and internal buses. It is used by the following circuits: • CPU • Instruction cache • Built-in RAM and ROM • Bit search module • I-bus, D-bus, X-bus, and F-bus • DMA controller • DSU Since 50 MHz is the upper-limit frequency for operation, do not set a combination of multiply-by rate and divide-by rate that results in a frequency exceeding this limit. 108 ■ Peripheral Clock (CLKP) This clock is used for peripheral circuits and peripheral buses. It is used by the following circuits: • Peripheral bus • Clock controller (only for the bus interface) • Interrupt controller • Peripheral I/O ports • I/O port bus • External interrupt input • UART • 16-bit timer • A/D converter • ICU • Free-run timer • Reload timer • Up/down counter • Input capture • Output compare • I2C interface • PPG Since 25 MHz is the upper-limit frequency for operation, do not set a combination of multiply-by rate and divide-by rate that results in a frequency exceeding this limit. ■ External Bus Clock (CLKT) This clock is used for external extended bus interfaces. It is used by the following circuits: • External extended bus interface • External CLK output Since 25 MHz is the upper-limit frequency for operation, do not set a combination of multiply-by rate and divide-by rate that results in a frequency exceeding this limit. 109 CHAPTER 3 CPU AND CONTROL UNITS 3.10.4 Clock Division A divide-by rate from the base clock can be set independently for each of the internal operating clocks. With this function, an optimal operating frequency can be set for each circuit. ■ Setting the Divide-By Rate Set a divide-by rate in basic clock division setting register 0 (DIVR0) and basic clock division setting register 1 (DIVR1). Each of these registers has four setting bits and (Register setting value + 1) is the divide-by rate of the clock in relation to the base clock. Even if the divide-by rate setting is an odd number, the duty is always 50. If the setting value is changed, the new divide-by rate becomes valid at the leading edge of the next clock after the setting is made. ■ Initializing the Divide-By Rate The divide-by rate setting is not initialized if an operation initialization reset (RST) occurs and the setting made before the reset occurs is retained. The divide-by rate setting is initialized only if a settings initialization reset (INIT) occurs. In the initial state, all clocks other than the peripheral clock (CLKP) have a divide-by rate of 1. Thus, be sure to set the divide-by rate before changing the source clock to a faster clock. Note: An upper-limit frequency for the operation is set for each clock. If you set a combination of source clock, PLL multiply-by rate setting, and divide-by rate setting that results in a frequency exceeding this upper-limit frequency, operation is not guaranteed. Be extra careful of the order in which you change settings to select the source clock and to configure the associated setting items. 110 3.10.5 Block Diagram of Clock Generation Controller Figure 3.10-1 shows a block diagram of the clock generation controller. For a detailed explanation of the registers shown in the figure, see Section "3.10.6 Register of Clock Generation Controller". ■ Block Diagram of Clock Generation Controller Figure 3.10-1 Block Diagram of Clock Generation Controller Peripheral circuit operation stop control register [Clock generator] DIVR0,1 registers R-BUS CPU clock division Oscillation circuit X1 X0A X1A Oscillation circuit External bus clock division Selector Peripheral circuit operation stop control Selector Peripheral clock External bus clock CLKR register Main oscillation Sub oscillation PLL 1/2 Selector X0 Peripheral clock division Stop control Main clock oscillation stabilization wait timer (for subclock selection) CPU clock Selector Watch timer [Stop and sleep controller] Internal interrupt STCR register Stop status Status transition control circuit Internal reset Sleep status Reset occurrence F/F Internal reset (RST) Reset occurrence F/F Internal reset (INIT) [Reset source circuit] INIT pin RSRR register [Watchdog controller] WPR register Watchdog F/F Timebase counter CTBR register TBCR register Interrupt enable Counter clock Selector Overflow detection F/F Timebase timer interrupt request 111 CHAPTER 3 CPU AND CONTROL UNITS 3.10.6 Register of Clock Generation Controller This section describes the clock generation controller registers. ■ Reset Source Register/Watchdog Timer Control Register (RSRR) The configuration of the reset source and watchdog timer control registers is shown below: bit 15 Address: 00000480H INIT R Initial value (INIT pin) Initial value (INIT) Initial value (RST) 1 * X 14 13 12 11 10 9 8 R WDOG R R SRST R R WT1 R/W WT0 R/W 0 * X 0 * X 0 X * 0 X * 0 * X 0 0 0 0 0 0 * : Varies according to the source. X : Not initialized This register holds the source of the last reset that occurred as well as the interval setting and startup control for the watchdog timer. If the register is read, the reset source that has been held is cleared after it is read. If more than one reset is generated before this register is read, reset source flags are accumulated and the multiple flags are set. Writing to this register starts the watchdog timer. Thereafter, the watchdog timer continues running until a reset (RST) occurs. [Bit 15] INIT (INITialize reset occurred) This bit indicates whether a reset (INIT) occurred due to INIT pin input. Value Explanation 0 No INIT occurred due to INIT pin input. 1 INIT occurred due to INIT pin input. • This bit is initialized to "0" after it is read. • This bit is readable; writing to the bit has no effect on the bit value. [Bit 14] (Reserved bit) This bit is reserved. 112 [Bit 13] WDOG (WatchDOG reset occurred) This bit indicates whether a reset (INIT) occurred due to the watchdog timer. Value Explanation 0 No INIT occurred due to the watchdog timer. 1 INIT occurred due to watchdog timer. • This bit is initialized to "0" after a reset (INIT) due to INIT pin input or just after it is read. • This bit is readable; writing to the bit has no effect on the bit value. [Bit 12] (Reserved bit) This bit is reserved. [Bit 11] SRST (Software ReSeT occurred) This bit indicates whether a reset (RST) occurred due to writing to the SRST bit of the STCR register (a software reset). Value Explanation 0 No RST occurred due to a software reset. 1 RST occurred due to a software reset. • This bit is initialized to "0" after a reset (INIT) due to INIT pin input or just after it is read. • This bit is readable; writing to the bit has no effect on the bit value. [Bit 10] (Reserved bit) This bit is reserved. [Bits 9, 8] WT1, WT0 (Watchdog interval Time select) This bit sets the interval of the watchdog timer. The values written to these bits determine the interval of the watchdog timer, which can be selected from the four types shown in the following table. WT1 WT0 Minimum required interval for writing to the WPR to suppress a watchdog reset Time from writing the last 5AH to the WPR until a watchdog reset occurs 0 0 φ x 216 (initial value) φ x 216 to φ x 217 0 1 φ x 218 φ x 218 to φ x 219 1 0 φ x 220 φ x 220 to φ x 221 1 1 φ x 222 φ x 222 to φ x 223 φ: Frequency of the system base clock • These bits are initialized to "00" after a reset (RST). • These bits are readable, but are writable only once after a reset (RST). Any further writing is disabled. 113 CHAPTER 3 CPU AND CONTROL UNITS ■ Standby Control Register (STCR) The configuration of the standby control register is shown below: bit 7 6 5 4 3 2 Address: 00000481H STOP R/W SLEEP R/W HIZ R/W SRST R/W OS1 R/W OS0 R/W Initial value (INIT pin) Initial value (HST pin)* Initial value (INIT) Initial value (RST) 0 0 0 0 0 0 0 0 1 1 1 X 1 1 1 1 0 1 X X 0 1 X X 1 0 OSCD2 OSCD1 R/W R/W 1 1 1 X 1 1 1 X * : Occurs only at the same time as initialization due to the INIT pin. Otherwise, the same as INIT. The standby control register controls the operating mode of the device. This register controls the transition to the two standby modes of stop and sleep, pins when in stop mode, and the stopping of oscillation. It also sets the oscillation stabilization wait time and issues software resets. Note: To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR, or time - base counter control register) and be sure to use the following sequence: (LDI#value_of_standby,R0); value_of standby is write data to STCR. (LDI#_STCR,R12) ; _STCR is address (481H) of STCR. STB R0,@R12 ; Writing in standby control register (STCR) LDUB@R12,R0 ; STCR read for synchronous standby LDUB@R12,R0 ; Dummy re - read of STCR NOP ; NOP for timing adjustment: x5 NOP NOP NOP NOP In addition, set the I - flag, the ILM, and ICR registers to branch to an interrupt handler when the interrupt handler triggers the microcontroller to return from the standby mode. [Bit 7] STOP (STOP mode) This bit specifies entry into stop mode. If 1 is written to both Bit 6 (SLEEP bit) and this bit, this bit has precedence and the device enters stop mode Value 114 Explanation 0 Stop mode not entered (initial value) 1 Stop mode entered • This bit is initialized to "0" by a reset (RST) and by a stop return source. • This bit is readable and writable. [Bit 6] SLEEP (SLEEP mode) This bit specifies entry into sleep mode. If "1" is written to both Bit 7 (STOP bit) and this bit, this bit (STOP) has precedence and the device enters stop mode. Value Explanation 0 Sleep mode not entered (initial value) 1 Sleep mode entered • This bit is initialized to "0" by a reset (RST) and by a sleep return source. • This bit is readable and writable. [Bit 5] HIZ (HIZ mode) This bit controls the pin state in stop mode. Value Explanation 0 The pin state before stop mode entered is maintained. 1 Pin output is set to high-impedance state in stop mode (initial value). • This bit is initialized to "0" by a reset (INIT). • This bit is readable and writable. [Bit 4] SRST (Software ReSeT) This bit specifies issuing of a software reset (RST). Value Explanation 0 A software reset is issued. 1 A software reset is not issued (initial value). • This bit is initialized to "1" by a reset (RST). • This bit is readable and writable. The read value is always "1". 115 CHAPTER 3 CPU AND CONTROL UNITS [Bits 3, 2] OS1, OS0 (Oscillation Stabilization time select) These bits set the oscillation stabilization wait time used after a reset (INIT), return from stop mode, etc. The values written to these bits determine the oscillation stabilization wait time, which can be selected from the four types shown in the following table. OS1 OS0 Oscillation stabilization wait time If the source oscillation is 12.5 MHz If the subclock is 32 kHz 0 0 φ x 21 (initial value) 0.32 [µs] 120 [µs] 0 1 φ x 211 328 [µs] 123 [ms] 1 0 φ x 216 10.5 [ms] 3.9 [s] 1 1 φ x 222 671 [ms] 251 [s] φ: Frequency of the system base clock; in this case, twice the cycle of the source oscillation input • These bits are initialized to "00" by a reset (INIT) generated due to INIT pin input. If both resets (INIT) generated due to INIT and HST pin input are valid, these bits are initialized to "11". • These bits are readable and writable. [Bit 1] OSCD2 (OSCillation Disable mode for XIN2) This bit controls stopping of the sub-oscillation input (XIN2) in stop mode. Value Explanation 0 Not stopping the sub-oscillation in stop mode 1 Stopping the sub-oscillation in stop mode (initial value) • This bit is initialized to "1" by a reset (INIT). • This bit is readable and writable. [Bit 0] OSCD1 (OSCillation Disable mode for XIN1) This bit controls stopping of main oscillation input (XIN1) in stop mode. Value 116 Explanation 0 Main oscillation does not stop in stop mode. 1 Main oscillation stops in stop mode (initial value). • This bit is initialized to "1" by a reset (INIT). • This bit is readable and writable. ■ Timebase Counter Control Register (TBCR) The configuration of the timebase counter control register is shown below: bit Address: 00000482H 15 14 13 12 11 10 TBIF R/W TBIE R/W TBC2 R/W TBC1 R/W TBC0 R/W R/W 0 0 0 0 X X X X X X X X Initial value (INIT) Initial value (RST) 9 8 SYNCR SYNCS R/W R/W 0 X 0 X The timebase counter control register controls timebase timer interrupts, among other things. This register enables timebase timer interrupts, selects an interrupt interval time, and sets an optional function for the reset operation. [Bit 15] TBIF (TimeBasetimer Interrupt Flag) This bit is the timebase timer interrupt flag. It indicates that the interval time (TBC2-0 bits, which are Bits 13-11) specified by the timebase counter has elapsed. A timebase timer interrupt request is generated if this bit is set to "1" when interrupts are enabled by Bit 14 (TBIE bit, TBIE=1). Clear source An instruction writes "0". Set source The specified interval time elapses (the trailing edge of the timebase counter is detected). • This bit is initialized to "0" by a reset (RST). • This bit is readable and writable, although only "0" can be written to it. Writing "1" does not change the bit value. The value read by a read modify write instruction is always "1". [Bit 14] TBIE (TimeBasetimer Interrupt Enable) This bit is the timebase timer interrupt request output enable bit. It controls output of an interrupt request when the interval time of the timebase counter has elapsed. A time-base timer interrupt request is generated if bit 15 (TBIF bit) is set to "1" when this bit is set to "1". Value Explanation 0 timebase timer interrupt request output disabled (initial value) 1 timebase timer interrupt request output enabled • This bit is initialized to "0" by a reset (RST). • This bit is readable and writable. 117 CHAPTER 3 CPU AND CONTROL UNITS [Bits 13 to 11] TBC2, TBC1, TBC0 (TimeBasetimer Counting time select) These bits set the interval time of the timebase counter that is used for the timebase timer. The values written to these bits determine the interval time, which can be selected from the eight types listed in the table below: TBC2 TBC1 TBC0 Timer interval time If the source oscillation is 12.5 MHz and PLL is multiplied by 4 If the subclock is 32 kHz 0 0 0 φ x 211 41.0 [µs] 61.4 [ms] 0 0 1 φ x 212 81.9 [µs] 123 [ms] 0 1 0 φ x 213 164 [µs] 246 [ms] 0 1 1 φ x 222 83.9 [ms] 126 [s] 1 0 0 φ x 223 168 [ms] 256 [s] 1 0 1 φ x 224 336 [ms] 512 [s] 1 1 0 φ x 225 672 [ms] 1024 [s] 1 1 1 φ x 226 1342 [ms] 2048 [s] φ: Frequency of the system base clock • The initial value is undefined. Be sure to set a value before enabling an interrupt. • These bits are readable and writable. [Bit 10] (reserved bit) This bit is reserved. The read value is undefined. Writing to this bit has no effect on operation. [Bit 9] SYNCR (SYNChronous Reset enable) This bit is the synchronous reset enable bit. This bit specifies whether normal reset operation or synchronous reset operation is executed when an operation initialization reset (RST) request occurs. Normal reset operation performs a reset (RST) immediately. Synchronous reset operation performs an operation initialization reset (RST) after all bus access has stopped. Value 118 Explanation 0 Normal reset operation (initial value) 1 Synchronous reset operation • This bit is initialized to "0" by a reset (INIT). • This bit is readable and writable. [Bit 8] SYNCS (SYNChronous Standby enable) This bit is the synchronous standby enable bit. It is used to select one of the following operations, which is to be used if an standby request (either sleep or stop mode request) occurs: (1) Performing a normal standby operation only by writing to the control bit in the STCR register or (2) performing a synchronous standby operation by reading the STCR register after writing to the control bit in the STCR register. Value Explanation 0 Normal standby operation (initial value) 1 Synchronous standby operation • This bit is initialized to "0" by a reset (INIT). • This bit is readable and writable. ■ Timebase Counter Clear Register (CTBR) The configuration of the timebase counter clear register is shown below: bit Address: 00000483H Initial value (INIT) Initial value (RST) 7 6 5 4 3 2 1 0 D7 W D6 W D5 W D4 W D3 W D2 W D1 W D0 W X X X X X X X X X X X X X X X X The timebase counter clear register initializes the timebase counter. If {A5H} and {5AH} are written successively to this register, all the bits in the timebase counter are cleared to "0" as soon as {5AH} is written. There is no time limit between writing of {A5H} and {5AH}. However, if data other than {5AH} is written after {A5H} is written, {A5H} must be written again before {5AH} is written. Otherwise, a clear operation will not occur. The value read from this register is undefined. Note: If the timebase counter is cleared using this register, the oscillation stabilization wait interval, watchdog timer interval, and timebase timer interval temporarily vary. 119 CHAPTER 3 CPU AND CONTROL UNITS ■ Clock Source Control Register (CLKR) The configuration of the clock source control register is shown below: bit Address: 00000484H 15 14 13 12 11 10 9 8 PLL2S0 PLL1S2 PLL1S1 PLL1S0 PLL2EN PLL1EN CLKS1 CLKS0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value (INIT) Initial value (RST) 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X The clock source control register is used to select the clock source that will be used as the base clock of the system and control the PLL. Use this register to select one of three types for clock sources (the MB91350A model type supports only two types). This register also enables each of the main PLL and the sub-PLLs and selects the multiply-by rate for them. [Bit 15] PLL2S0 (PLL2 ratio Select 0) This bit is the multiply-by rate selection bit for the subclock. Select one of the two multiply-by rates for the subclock. For the MB91350A model type, always write "0" to this bit. Value Explanation 0 Multiply-by rate setting 1 (initial value) 1 Multiply-by rate setting 1 • This bit is initialized to "0" by a reset (INIT). • This bit is readable and writable. [Bits 14 to12] PLL1S2, PLL1S1, PLL1S0 (PLL1 ratio Select 2 to 0) These bits are the multiply-by rate selection bits for the main PLL. Select one of eight types for main PLL multiply-by-rates (*: the MB91350A model type supports only four types). Rewriting of this bit is disabled while the main PLL is selected as the clock source. The upper-limit frequency for operation is 50 MHz. Do not set a multiply-by rate that results in a frequency exceeding this limit. 120 PLL1S2 PLL1S1 PLL1S0 Main PLL multiply-by rate 0 0 0 × 1 (equal) 0 0 1 × 2 (multiplied by 2) For source oscillator 12.5 (MHz), φ = 40[ns] (25 (MHz)) 0 1 0 × 3 (multiplied by 3) For source oscillator 12.5 (MHz), φ = 26[ns] (37.5 (MHz)) 0 1 1 × 4 (multiplied by 4) For source oscillator 12.5 (MHz), φ = 20[ns] (50 (MHz)) 1 0 0 × 5 (multiplied by 5) Not supported by the MB91350A model type* 1 0 1 × 6 (multiplied by 6) Not supported by the MB91350A model type* 1 1 0 × 7 (multiplied by 7) Not supported by the MB91350A model type* 1 1 1 × 8 (multiplied by 8) Not supported by the MB91350A model type* For source oscillator 12.5 (MHz), φ = 80[ns] (12.5 (MHz)) φ: Frequency of the system base clock • These bits are initialized to "000" by a reset (INIT). • These bits are readable and writable. [Bit 11] PLL2EN (PLL2 ENable) This is the selection enable bit for the subclock. Rewriting of this bit is not allowed while the subclock is selected as the clock source. In addition, selecting the subclock as the clock source is not allowed while this bit is 0 (bits 9 and 8: Determined from the settings of the CLKS1 and CLKS0 bits). The subclock stops in stop mode even when this bit is set to "1" as long as STCR bit 1 (OSCD2) is set to "1". After the device returns from the stop mode, the subclock is enabled again. Value Explanation 0 Subclock stopped (initial value) 1 Subclock enabled • This bit is initialized to "0" by a reset (INIT). • This bit is readable and writable. 121 CHAPTER 3 CPU AND CONTROL UNITS [Bit 10] PLL1EN (PLL1 ENable) This bit is the enable bit of the main PLL. Rewriting of this bit is not allowed while the main PLL is selected as the clock source. In addition, selecting the main PLL as the clock source is not allowed while this bit is 0 (bits 9 and 8: Determined from the settings of the CLKS1 and CLKS0 bits). The main PLL stops in stop mode even when this bit is set to "1" as long as STCR bit 0 (OSCD1) is set to "1". After the device returns from the stop mode, the main PLL is enabled again. Value 122 Explanation 0 Main PLL stopped (initial value) 1 Main PLL enabled • This bit is initialized to "0" by a reset (INIT). • This bit is readable and writable. [Bits 9, 8] CLKS1, CLKS0 (CLocK source Select) These bits set the clock source that will be used by the FRex core. The values written to these bits determine the clock source, which can be selected from the three types listed in the table below: While bit 9 (CLKS1) is set to "1", the value of bit 8 (CLKS0) cannot be changed. Cannot be changed Can be changed "00" → "11" "00" → "01" or "10" "01" → "10" "01" → "11" or "00" "10" → "01" or "11" "10" → "00" "11" → "00" or "10" "11" → "01" To select the subclock in the post-INIT state, first write "01" and then write "11". Note: From subclock source X0A/X1A, the source oscillation input with the frequency divided by 2 cannot be selected. In addition, immediately after writing "01", insert at least one NOP instruction. CLKS1 CLKS0 Clock source setting 0 0 Source oscillation input from X0/X1 divided by 2 (initial value) 0 1 Source oscillation input from X0/X1 divided by 2 1 0 Main PLL 1 1 Subclock • These bits are initialized to "00" by a reset (INIT). • These bits are readable and writable. 123 CHAPTER 3 CPU AND CONTROL UNITS ■ Watchdog Reset Postpone Register (WPR) The configuration of the watchdog reset postpone register is shown below: bit Address: 00000485H Initial value (INIT) Initial value (RST) 7 6 5 4 3 2 1 0 D7 W D6 W D5 W D4 W D3 W D2 W D1 W D0 W X X X X X X X X X X X X X X X X The watchdog reset postpone register postpones a watchdog reset. If {A5H} and {5AH} are written successively to this register, the detection FF for the watchdog timer is cleared immediately after {5AH} is written and the watchdog reset is postponed. There is no time limit between writing of {A5H} and {5AH}. However, if data other than {5AH} is written after {A5H} is written, {A5H} must be written again before {5AH} is written. Otherwise, a clear operation will not occur. Table 3.10-1 "Time Intervals for Watchdog Reset Generation" shows the relationship between the time interval for the watchdog reset generation and RSRR register value. A watchdog reset is generated if writing for both of these data items is not completed within the indicated interval. The time until a watchdog reset is generated and the write interval required for suppressing generation depend on the states of WT1 (bit 9) and WT0 (bit 8) in the RSRR register. Table 3.10-1 Time Intervals for Watchdog Reset Generation WT1 WT0 Required minimum interval of writing to the WPR to suppress the generation of a watchdog reset of the RSRR Time elapsing between writing of the last 5AH to the WPR and the generation a watchdog reset 0 0 φ × 216 (initial value) φ × 216 to φ × 217 0 1 φ × 218 φ × 218 to φ × 219 1 0 φ × 220 φ × 220 to φ × 221 1 1 φ × 222 φ × 222 to φ × 223 Note: φ is the frequency of the system base clock. WT1 and WT0 are Bits 9 and 8 of the RSRR and are used to set the watchdog timer interval. Clearing occurs automatically while the CPU is not running, such as in the stop, sleep, or DMA transfer state. If one of these conditions occurs, a watchdog reset is automatically postponed. However, a watchdog reset is not postponed when an external bus hold request (BRQ) has been accepted. To hold the external bus for a long time, enter sleep mode and then input a hold request (BRQ). The value read from this register is undefined. 124 ■ Base Clock Division Setting Register 0 (DIVR0) The configuration of base clock division setting register 0 is shown below: bit Address: 00000486H Initial value (INIT) Initial value (RST) 15 14 13 12 11 10 9 8 B3 R/W B2 R/W B1 R/W B0 R/W P3 R/W P2 R/W P1 R/W P0 R/W 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X Base clock division setting register 0 (DIVR0) controls the divide-by rate of an internal clock in relation to the base clock. This register sets the divide-by rates of the CPU, the clocks of an internal bus (CLKB), a peripheral circuit, and the peripheral bus clock (CLKP). Note: An upper-limit frequency for the operation is prescribed for each clock. If the combination of source clock selected, PLL multiply-by rate setting, and divide-by rate setting results in a frequency exceeding this upper-limit frequency, operation is unpredictable. Be extremely careful of the order in which you change the settings when selecting the source clock. If the setting in this register is changed, the new frequency-divide-by rate takes effect for the clock rate following the one during which the setting was made. [Bits 15 to 12] B3, B2, B1, B0 (clkB divide select 3 to 0) These bits are the clock divide-by rate setting bits of the CPU clock (CLKB). Set the clock divide-by rate of the CPU, internal memory, and internal bus clock (CLKB) The values written to these bits determine the divide-by rate (clock frequency) for the base clock of the CPU and internal bus clocks. Select the divide-by rate from the 16 types listed in the table below. The upper-limit frequency for operation is 50 MHz. Do not set a divide-by rate that results in a frequency exceeding this limit. B3 B2 B1 B0 Clock divide-by rate Clock frequency: if the source oscillation is 12.5 [MHz] and the PLL is multiplied by 4 0 0 0 0 φ 50 [MHz] (initial value) 0 0 0 1 φ × 2 (divided by 2) 25 [MHz] 0 0 1 0 φ × 3 (divided by 3) 16.7 [MHz] 0 0 1 1 φ × 4 (divided by 4) 12.5 [MHz] 0 1 0 0 φ × 5 (divided by 5) 10 [MHz] 0 1 0 1 φ × 6 (divided by 6) 8.33 [MHz] 0 1 1 0 φ × 7 (divided by 7) 7.01 [MHz] 0 1 1 1 φ × 8 (divided by 8) 6.25 [MHz] ... ... ... ... ... ... 1 1 1 1 φ × 16 (divided by 16) 3.13 [MHz] φ: Frequency of the system base clock 125 CHAPTER 3 CPU AND CONTROL UNITS • These bits are initialized to "0000" by a reset (INIT). • These bits are readable and writable. [Bits 11 to 8] P3, P2, P1, P0 (clkP divide select 3 to 0) These bits are the clock divide-by rate setting bits of the peripheral clock (CLKP). Set the clock divide-by rate of the peripheral circuit and the peripheral bus clock (CLKP). The values written to these bits determine the divide-by rate (clock frequency) for the base clock of the peripheral circuit and peripheral bus clocks. Select the divide-by rate from the 16 types listed in the table below. The upper-limit frequency for operation is 25 MHz. Do not set a divide-by rate that results in a frequency exceeding this limit. P3 P2 P1 P0 Clock divide-by rate Clock frequency: if the source oscillation is 12.5[MHz] and the PLL is multiplied by 4 0 0 0 0 φ 50 [MHz] 0 0 0 1 φ x 2 (divided by 2) 25 [MHz] 0 0 1 0 φ x 3 (divided by 3) 16.7 [MHz] 0 0 1 1 φ x 4 (divided by 4) 12.5 [MHz] (initial value) 0 1 0 0 φ x 5 (divided by 5) 10 [MHz] 0 1 0 1 φ x 6 (divided by 6) 8.33 [MHz] 0 1 1 0 φ x 7 (divided by 7) 7.01 [MHz] 0 1 1 1 φ x 8 (divided by 8) 6.25 [MHz] ... ... ... ... ... ... 1 1 1 1 φ x 16 (divided by 16) 3.13 [MHz] φ: Frequency of the system base clock • These bits are initialized to "0011" by a reset (INIT). • These bits are readable and writable. ■ Base Clock Division Setting Register 1 (DIVR1) The configuration of base clock division setting register 1 is shown below: bit Address: 00000487H Initial value (INIT) Initial value (RST) 7 6 5 4 3 2 1 0 T3 R/W T2 R/W T1 R/W T0 R/W R/W R/W R/W R/W 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X Base clock division setting register 1 controls the divide-by rate of an internal clock in relation to the base clock. This register sets the divide-by rate for the external extended bus interface clock (CLKT). 126 Note: An upper-limit frequency for the operation is set for each clock. If the combination of source clock selected, PLL multiply-by rate setting, and divide-by rate setting results in a frequency exceeding this upper-limit frequency, operation is unpredictable. Be extremely careful of the order in which you change the settings when selecting the source clock. If the setting in this register is changed, the new divide-by rate takes effect for the clock rate following the one during which the setting was made. [Bits 7 to 4] T3, T2, T1, T0 (clkT divide select 3 to 0) These bits are the clock divide-by rate setting bits of the external bus clock (CLKT). Set the clock divide-by rate of the external extended bus interface clock (CLKT). The values written to these bits determine the divide-by rate (clock frequency) for the base clock of the external extended bus interface clock. Select the divide-by rate from the 16 types listed in the table below. The upper-limit frequency for operation is 25 MHz. Do not set a divide-by rate that results in a frequency exceeding this limit. T3 T2 T1 T0 Clock divide-by rate Clock frequency: if the source oscillation is 12.5[MHz] and the PLL is multiplied by 4 0 0 0 0 φ 50 [MHz] (initial value) 0 0 0 1 φ × 2 (divided by 2) 25 [MHz] 0 0 1 0 φ × 3 (divided by 3) 16.7 [MHz] 0 0 1 1 φ × 4 (divided by 4) 12.5 [MHz] 0 1 0 0 φ × 5 (divided by 5) 10 [MHz] 0 1 0 1 φ × 6 (divided by 6) 8.33 [MHz] 0 1 1 0 φ × 7 (divided by 7) 7.01 [MHz] 0 1 1 1 φ × 8 (divided by 8) 6.25 [MHz] ... ... ... ... ... ... 1 1 1 1 φ × 16 (divided by 16) 3.13 [MHz] φ: Frequency of the system base clock • These bits are initialized to "0000" by a reset (INIT). • These bits are readable and writable. [Bits 3 to 0] (reserved bits) These bits are reserved. 127 CHAPTER 3 CPU AND CONTROL UNITS ■ Oscillation Control Register (OSCCR) The configuration of the oscillation control register is shown below: bit Address: 0000048AH Initial value (INIT) Initial value (RST) 15 14 13 12 11 10 9 8 R/W R/W R/W R/W R/W R/W R/W OSCDS1 X X X X X X X X X X X X X X 0 X R/W The oscillation control register controls the main clock oscillation during operation of the subclock. [Bit 8] OSCDS1 (OSCillation Disable on Subclock for XIN1) This bit is the stop bit for main clock oscillation while the subclock is selected. Writing "1" to this bit stops main clock oscillation while the subclock is selected as the clock source. Writing "1" to this bit is disabled while the main clock is selected. Selection of the main clock is disabled while this bit is set to "1". Set this bit to "0", and wait for stabilization of the main clock oscillation. Then, switch to the main clock. Use the main oscillation stabilization wait timer to secure the oscillation stabilization wait time at this time. If INIT switches the clock source to the main clock when this bit stops main clock oscillation, the main oscillation stabilization wait time is also required. If the settings of bits 3 and 2 (OS1 and OS0) of the standby control register (STCR) do not satisfy the main oscillation stabilization wait time, the operation after return is unpredictable. In this case, set values that satisfy both the subclock oscillation stabilization wait time and the main clock oscillation stabilization wait time in the STCR (OS1 and OS0 bits). For INIT from the INIT pin, an "L" level signal must continue to be inputted to the INIT pin until main clock oscillation is stabilized. For details about the oscillation stabilization wait, see Section "3.10.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time". Value 128 Explanation 0 Main clock oscillation is not stopped during execution of subclock (default value). 1 Main clock oscillation is stopped during execution of subclock. • This bit is initialized to "0" by a reset (INIT). • This bit can be read and written. 3.10.7 Peripheral Circuits of Clock Controller This section describes the peripheral circuit functions of the clock controller. ■ Timebase Counter The clock controller has a 26-bit timebase counter that runs on the system base clock. The timebase counter is used to measure the oscillation stabilization wait time in addition to having the uses listed below (For more information about the oscillation stabilization wait time, see Section "3.9.4 Oscillation Stabilization Wait Time"). • Watchdog timer The watchdog timer, which is used to detect a system runaway, measures time using the bit output of the timebase counter. • Timebase timer The timebase timer generates an interval interrupt using output from the timebase counter. ● Watchdog timer The watchdog timer detects a runaway using output from the timebase counter. If a program runaway results in a watchdog reset no longer being postponed for a specified interval, a settings initialization reset (INIT) request is generated as a watchdog reset. [Startup and interval setting of the watchdog timer] The watchdog timer is started when the reset source register and the watchdog timer control register (RSRR) are written to for the first time after a reset (RST). At this time, the interval time of the watchdog timer is set in Bits 09 and 08 (WT1 and WT0 bits). Only the time defined in this first write is valid as the interval time setting. Any further writing is ignored. [Postponing a watchdog reset] Once the watchdog timer is started, the program must write {A5H} and {5AH} in this order to the watchdog reset postpone register (WPR) periodically. This operation initializes the watchdog reset generation flag. [Generation of a watchdog reset] The watchdog reset generation flag is set at the trailing edge of the timebase counter output of the specified interval. If the flag has already been set when a trailing edge is detected at a second time, a settings initialization reset (INIT) request is generated as a watchdog reset. [Stopping the watchdog timer] The watchdog timer, once started, cannot be stopped until an operation initialization reset (RST) occurs. In the following states, when an operation initialization reset (RST) occurs, the watchdog timer is stopped and remains inoperative until a program starts it. • Operation initialization reset (RST) state • Settings initialization reset (INIT) state • Oscillation stabilization wait reset (RST) state 129 CHAPTER 3 CPU AND CONTROL UNITS [Suspending the watchdog timer (automatic postponement)] If program operation stops on the CPU, the watchdog reset generation flag is initialized and generation of a watchdog reset is postponed. Stopping of program operation specifically refers to the following statuses: • Sleep state • Stop state • Oscillation stabilization wait RUN state • During a break taken when the emulator debugger or monitor debugger is being used • Period from execution of INTE instruction to execution of RETI instruction • Step trace trap (per - instruction break taken by setting the T flag in the PS register to "1") • Instruction cache control registers (ISIZE, ICHCR): Data to cache memory in RAM mode If the timebase counter is cleared, the watchdog reset generation flag is initialized at the same time, postponing generation of a watchdog reset. A watchdog reset may not be generated in the above situation caused by the system running out of control. In that case, please reset (INIT) by external INIT terminal. ● Timebase timer The timebase timer generates an interval interrupt using output from the timebase counter. This timer is appropriate for measurements that require a relatively long time (for example, a maximum interval of {base clock x 227} cycles such as for the PLL lock wait time or a subclock oscillation stabilization wait time. If the trailing edge of the timebase counter output for the specified interval is detected, a timebase timer interrupt request is generated. [Startup and interval settings of the timebase timer] For the timebase timer, the interval time is set in Bits 13-11 (TBC2, TBC1, and TBC0 bits) of the timebase counter control register (TBCR). The trailing edge of the timebase counter output for the specified interval is always detected. Thus, after setting the interval time, clear Bit 15 (TBIF bit) and then set Bit 14 (TBIE bit) to "1" to enable output of an interrupt request. Before changing the interval time, set Bit 14 (TBIE bit) to "0" to disable interrupt request output. Since the timebase counter always counts regardless of these settings, before enabling interrupts, clear the timebase counter to obtain an accurate interval interrupt time. Otherwise, an interrupt request may be generated immediately after an interrupt is enabled. [Clearing of the timebase counter due to a program] If {A5H} and {5AH} are written in this order to the timebase counter clear register (CTBR), all bits of the timebase counter are cleared to "0" immediately after {5AH} is written. There is no time limit between writing of {A5H} and {5AH}. However, if data other than {5AH} is written after {A5H} is written, {A5H} must be written again before {5AH} is written. Otherwise, no clear operation occurs. If the timebase counter is cleared, the watchdog reset generation flag is initialized at the same time, postponing generation of a watchdog reset. 130 [Clearing of the timebase counter due to the device state] All bits of the timebase counter are cleared to "0" at the same time if the device enters one of the following states: • Stop state • Settings initialization reset (INIT) state Especially in the stop state, an interval interrupt of the timebase timer may unintentionally be generated because the timebase counter is used to measure the oscillation stabilization wait time. Before setting stop mode, therefore, disable timebase timer interrupts to prevent the timebase timer from being used. In any other state, timebase timer interrupts are automatically disabled because an operation initialization reset (RST) occurs. ● Watch Timer The watch timer is a 15-bit free-run timer that performs incremental counting in synchronization with the 32 kHz subclock. The operation of this timer is not affected by the clock source selection or the clock division. The watch timer is used to measure the subclock stabilization wait time and perform processing at fixed intervals using the subclock. The watch timer performs incremental counting while the subclock is operating and is stopped when Bit 1 (OSCD2 bit) of the standby control register (STCR) is set to1 so that the watch timer enters stop mode. To prevent the watch timer from being stopped in stop mode, set the OSCD2 bit to "0" before the watch timer enters stop mode so that the subclock is not stopped. Follow the procedure below for switching the clock source from the main clock to subclock using the watch timer: 1. Set the watch timer for the oscillation stabilization wait time. If necessary, clear all bits of the watch timer to "0". 2. Use the watch timer to wait until the subclock is stabilized. At this time, use a watch interrupt to secure the oscillation stabilization wait time. 3. After the subclock has been stabilized, use Bits 9 and 8 (CLKS1 and CLKS0 bits) of the clock source register (CLKR) to switch the clock source from the main clock to subclock. Note: If the clock source is switched to the subclock before the subclock is stabilized, an unstable clock is supplied and subsequent operation is unpredictable. Be sure to switch to the subclock after the subclock has been stabilized. For more information on the watch timer, see Section "3.12 Watch Timer". 131 CHAPTER 3 CPU AND CONTROL UNITS ● Main Clock Oscillation Stabilization Wait Timer (When Subclock Selected) The main clock oscillation stabilization wait timer is a 26-bit timer that counts up in synchronization with the main clock. The operation of this timer is not affected by clock source selection or the clock division. The main clock oscillation stabilization wait timer is used to measure the main clock oscillation stabilization wait time during subclock is operating. Main clock oscillation can be controlled by Bit 0 (OSCDS1 bit) of the oscillation control register (OSCCR) while the device is operating on the subclock. This timer is used to measure the oscillation stabilization wait time when main clock oscillation is restarted after it has been stopped. Follow the procedure below for switching the clock source to the main clock when the device is operating on the subclock with the main clock stopped. 1. Clear the main clock oscillation stabilization wait timer. 2. Set Bit 0 (OSCDS1 bit) of the oscillation control register (OSCCR) to "0" to start main clock oscillation. 3. Use the main clock oscillation stabilization wait timer to wait until the main clock oscillation is stabilized. 4. After the main clock has been stabilized, use Bits 9 and 8 (CLKS1 and CLKS0 bits) of the clock source register (CLKR) to switch the clock source from the subclock to main clock. Note: If the clock source is switched to the main clock before the main clock is stabilized, an unstable clock is supplied and subsequent operation is unpredictable. Be sure to switch to the main clock after the main clock has been stabilized. For more information on the main clock oscillation stabilization wait timer, see Section "3.13 Main Clock Oscillation Stabilization Wait Timer". ● Peripheral Stop Control Peripheral stop control is used to control the clock supply to peripheral resources. Power saving can be implemented by stopping the clock supply to peripheral resources not being used. For details, see Section "3.14 Peripheral Stop Control". 132 3.11 Device State Control This section describes the states of the MB91350A and their control. ■ Overview of Device State Control The MB91350A model type has the following device states: • RUN state (normal operation) • Sleep state • Stop state • Oscillation stabilization wait RUN state • Oscillation wait reset (RST) state • Operation initialization reset (RST) state • Settings initialization reset (INIT) state The following sections provide details about the above device states and the two low-power consumption modes (sleep mode and stop mode). 133 CHAPTER 3 CPU AND CONTROL UNITS 3.11.1 Device States and State Transitions Figure 3.11-1 shows the state transitions of the device. ■ Device States Figure 3.11-1 Device States INTX pin = 0 (INIT) INIT pin = 1 (clearance of INIT state) End of oscillation stabilization wait time Release from reset (RST) state Software reset (RST) Entry to sleep state (writing of instruction) Entry to stop state (writing of instruction) Interrupt External interrupt not requiring a clock Switching from main clock to subclock (writing of instruction) 11 Switching from subclock to main clock (writing of instruction) 12 Watchdog timer reset (INIT) 13 Entry to subclock sleep state (writing of instruction) 1 2 3 4 5 6 7 8 9 10 Priority of state transition requests Settings initialization reset (INIT) request End of oscillation stabilization Highest wait time Operation initialization reset (RST) request Interrupt request Stop mode request Sleep mode request Lowest Power-on 1 Setting initialization reset (INIT) 2 Main clock mode 1 Main clock oscillation stabilization wait reset 3 Main clock stop 9 1 Oscillation stabilization wait RUN Program reset (RST) 3 7 1 6 Main clock sleep 5 1 4 12 Main clock RUN 8 1 1 10 Subclock mode 1 Subclock sleep 1 1 12 Subclock RUN 13 3 Oscillation stabilization wait RUN 7 5 1 4 Program reset (RST) 1 9 Subclock stop (watch state *2) 134 11 8 Subclock stop (watch state *2) *1 To switch the clock source between the main clock and subclock, change the status of Bits 1 and 0 (CLKS1 and CLKS0 bits) of the clock source register (CLKR) in the RUN state after oscillation of the switch-destination clock has been stabilized. *2 To stop (watch state) circuits other than the watch timer, set standby control register (STCR) bit 1 (OSCD2 bit) to 0 and bit 0 (OSCD1 bit) to 1 in the subclock operating state, then switch to stop mode (simultaneous write enabled). ■ Device Operating States The device operating states of the MB91350A model type are as follows: ● RUN state (Normal Operation) In the RUN state, a program is being executed. All internal clocks are supplied and all circuits are enabled. For the 16-bit peripheral bus, however, only the bus clock is stopped, when it is not being accessed. State transition request is accepted. If synchronous reset mode is selected, however, state transition operations different from normal reset mode are used for some requests. For more information, see "■ Synchronous Reset Operation" in Section "3.9.5 Reset Operation Modes". ● Sleep state In the sleep state, a program is stopped. Program operation causes a transition to this state. Only execution of the program on the CPU is stopped; peripheral circuits are enabled. The instruction cache is stopped and the built-in memory modules and the internal and external buses are stopped unless the DMA controller issues a request. If a valid interrupt request occurs, the state is cleared and the RUN state (normal operation) is entered. If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) state is entered. If an operation initialization reset (RST) request occurs, the operation initialization reset (RST) state is entered. ● Stop state In the stop state, the device is stopped. Program operation causes a transition to this state. All internal circuits are stopped. All internal clocks are stopped and the oscillation circuit and PLL can be stopped if set to do so. In addition, the external pins (except some) can be set to high impedance via settings. If a specific valid interrupt (no clock required) occurs or during oscillation, a watch timer/main clock oscillation stabilization wait timer interrupt request occurs, the oscillation stabilization wait RUN state is entered. If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) state is entered. If an operation initialization reset (RST) request occurs, the oscillation stabilization wait reset (RST) state is entered. 135 CHAPTER 3 CPU AND CONTROL UNITS ● Oscillation stabilization wait RUN state In the oscillation stabilization wait RUN state, the device is stopped. This state occurs after a return from the stop state. All internal circuits except the clock generation controller (timebase counter and device state controller) are stopped. All internal clocks are stopped, but the oscillation circuit and the PLL that has been enabled are running. High impedance control of external pins in the stop or other state is cleared. If the specified oscillation stabilization wait time elapses, the RUN state (normal operation) is entered. If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) state is entered. If an operation initialization reset (RST) request occurs, the oscillation stabilization wait reset (RST) state is entered. ● Oscillation stabilization wait reset (RST) status In the oscillation stabilization wait reset (RST) state, the device is stopped. This state occurs after a return from the stop state or the settings initialization reset (INIT) state. All internal circuits except the clock generation controller (timebase counter and device state controller) are stopped. All internal clocks are stopped, but the oscillation circuit and the PLL that has been enabled are running. High impedance control of external pins in the stop state, etc., is cleared. An operation initialization reset (RST) is outputted to the internal circuits. If the specified oscillation stabilization wait time elapses, the oscillation stabilization wait reset (RST) state is entered. If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) state is entered. ● Operation initialization reset (RST) state In the operation initialization reset (RST) state, a program is initialized. This state occurs if an operation initialization reset (RST) request is accepted or the oscillation stabilization wait reset (RST) state is ended. Execution of a program on the CPU is stopped and the program counter is initialized. Most peripheral circuits are initialized. All internal clocks, the oscillation circuit and the PLL that has been enabled are running. An operation initialization reset (RST) is outputted to the internal circuits. If an operation initialization reset (RST) request no longer exists, the RUN state (normal operation) is entered and the operation initialization reset sequence is executed. After a return from the settings initialization reset (INIT), the settings initialization reset sequence is executed. If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) state is entered. 136 ● Settings initialization reset (INIT) state In the settings initialization reset (INIT) state, all settings are initialized. This state occurs if a settings initialization reset (INIT) request is accepted or the hardware standby state is ended. Execution of a program on the CPU is stopped and the program counter is initialized. All peripheral circuits are initialized. The oscillation circuit runs, but the PLL stops running. All internal clocks are stopped while the "L" level is input to the external INIT pin; otherwise, they run. A settings initialization reset (INIT) and an operation initialization reset (RST) are outputted to the internal circuits. If a settings initialization reset (INIT) request no longer exists, the state is cleared and the oscillation stabilization wait reset (RST) state is entered. Then, the operation initialization reset (RST) state is entered and the settings initialization reset sequence is executed ● Priority of state transition requests In any state, state transition requests conform to the priority listed below. However, some requests that occur only in a specific state are valid only in that state. [Highest] Settings initialization reset (INIT) request End of oscillation stabilization wait time (occurs only in the oscillation stabilization wait reset state and the oscillation stabilization wait RUN state) Operation initialization reset (RST) request Valid interrupt request (occurs only in the RUN, sleep, and stop states) Stop mode request (writing to a register) (occurs only in the RUN state) [Lowest] Sleep mode request (writing to a register) (occurs only in the RUN state) 137 CHAPTER 3 CPU AND CONTROL UNITS 3.11.2 Low-power Consumption Modes This section describes the low-power consumption modes and their use in the states of the MB91350A model type. The low-power consumption modes of the MB91350A model type are as follows: • Sleep mode: The device enters the sleep state due to writing to a register. • Stop mode: The device enters the stop state due to writing to a register. These modes are described below. ■ Sleep Mode If "1" is set for Bit 6 (SLEEP bit) of the standby control register (STCR), sleep mode is initiated and the device enters the sleep state. The sleep state is maintained until a source for return from the sleep state is generated. If "1" is set for both Bit 7 (STOP bit) and Bit 6 of the standby control register (STCR), Bit 7 (STOP bit) has precedence and the device enters the stop state. For more information about the sleep state, see "❍Sleep State" in Section "3.11.1 Device States and State Transitions". [Transition to Sleep Mode] To enter the sleep mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR, or time - base counter control register) and be sure to use the following sequence: (LDI#value_of_sleep,R0) ; value_of _sleep is write data to STCR. (LDI#_STCR,R12) ; _STCR is address (481H) of STCR. STB R0,@R12 ; Writing in standby control register (STCR) LDUB@R12,R0 ; STCR read for synchronous standby LDUB@R12,R0 ; Dummy re - read of STCR NOP ; NOP for timing adjustment: x5 NOP NOP NOP NOP In addition, set the I - flag, the ILM, and ICR registers to branch to an interrupt handler when the interrupt handler triggers the microcontroller to return from the standby mode. 138 [Circuits that stop in the sleep state] • Program execution on the CPU • Data cache • Bit search module (enabled if DMA transfer occurs) • Various built-in memory (enabled if DMA transfer occurs) • Internal and external buses (enabled if DMA transfer occurs) [Circuits that do not stop in the sleep state] • Oscillation circuit • PLL that has been enabled • Clock generation controller • Interrupt controller • Peripheral circuit • DMA controller • DSU • Watch timer • Main clock oscillation stabilization wait timer [Sources of return from the sleep state] • Generation of a valid interrupt request If an interrupt request with an interrupt level other than interrupt disabled (1FH) occurs, sleep mode is cleared and the RUN state (normal operation state) is entered. To prevent sleep mode from being cleared even when an interrupt request occurs, set interrupt disabled (1FH) as the interrupt level in the corresponding ICR. • Generation of a settings initialization reset (INIT) request If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) state is unconditionally entered. • Generation of an operation initialization reset (RST) request If an operation initialization reset (RST) request occurs, the operation initialization reset (RST) state is unconditionally entered. Note: For information about the priority of sources, see "Priority of State Transition Requests" in Section "3.11.1 Device States and State Transitions". [synchronous standby operations] Synchronous standby operation is enabled with bit 8 (SYNCS bit) in the time - base counter control register (TBCR) set to "1". Transition to the sleep state does is not caused only by a write to the SLEEP bit. Transition to the sleep state occurs when the STCR register is read after that. To enter the sleep mode, be sure to use the sequence in (Transition to sleep mode). 139 CHAPTER 3 CPU AND CONTROL UNITS ■ Stop Mode If "1" is set for Bit 7 (STOP bit) of the standby control register (STCR), stop mode is initiated and the device enters the stop state. The stop state is maintained until a source for return from the stop state occurs. If "1" is set for both Bit 6 (SLEEP bit) and Bit 7 bit of the standby control register (STCR), Bit 7 (STOP bit) has precedence and the device enters the stop state. For more information about the stop state, see "❍Stop State" in Section "3.11.1 Device States and State Transitions". [Circuits that stop in the stop state] • Oscillation circuits set to stop If "1" is set for Bit 1 (OSCD2 bit) of the standby control register (STCR), the subclock oscillation circuit in the stop state is stopped. The watch timer is also stopped. If "1" is set for Bit 0 (OSCD1 bit) of the standby control register (STCR), the main clock oscillation circuit in the stop state is stopped. The main clock oscillation stabilization wait timer is also stopped at this time. • PLL connected to the oscillation circuit that is either disabled or set to stop If "1" is set for Bit 1 (OSCD2 bit) of the standby control register (STCR) and "1" is set for Bit 11 (PLL2EN bit) of the clock source control register (CLKR), the subclock PLL in the stop state is stopped. If "1" is set for Bit 0 (OSCD1 bit) of the standby control register (STCR) and "1" is set for Bit 10 (PLL1EN bit) of the clock source control register (CLKR), the main clock PLL in the stop state is stopped. • All internal circuits except those, described below, that do not stop in the stop state [Circuits that do not stop in the stop state] • Oscillation circuits that are set not to stop If "0" is set for Bit 1 (OSCD2 bit) of the standby control register (STCR), the subclock oscillation circuit in the stop state is not stopped. Also, the watch timer is not stopped. If "0" is set for Bit 0 (OSCD1 bit) of the standby control register (STCR), the main clock oscillation circuit in the stop state is not stopped. The main clock oscillation stabilization wait timer is also stopped. Also, the main clock oscillation stabilization wait timer is not stopped. • PLL connected to the oscillation circuit that is enabled and is not set to stop If "0" is set for Bit 1 (OSCD2 bit) of the standby control register (STCR) and "1" is set for Bit 11 (PLL2EN bit) of the clock source control register (CLKR), the subclock PLL in the stop state is not stopped. If "0" is set for Bit 0 (OSCD1 bit) of the standby control register (STCR) and "1" is set for Bit 10 (PLL1EN bit) of the clock source control register (CLKR), the main clock PLL in the stop state is not stopped. [High impedance control of a pin in the stop state] If "1" is set for Bit 5 (HIZ bit) of the standby control register (STCR), the output of a pin in the stop state is set to the high impedance state. See Appendix C "Pin States in Each CPU State" for the pins subject this type of control. If Bit 5 (HIZ bit) of the standby control register (STCR) is set to "0", the pin outputs in the stop state maintain the values set before transition to the stop state. For details, see Appendix C "Pin States in Each CPU State". 140 [Sources of return from the stop state] • Generation of a specific valid interrupt request (not requiring a clock) Only the external interrupt input pins (INTn pins), main clock oscillation stabilization wait timer interrupt during main clock oscillation, and watch interrupt during subclock oscillation are enabled. If an interrupt request with an interrupt level other than interrupt disabled (1FH) occurs, stop mode is cleared and the RUN state (normal operation state) is entered. To prevent stop mode from being cleared even when an interrupt request occurs, set interrupt disabled (1FH) as the interrupt level in the corresponding ICR. • Watch timer interrupt If a watch timer interrupt request occurs when standby control register (STCR) bit 1 (OSCD2 bit) is set to "0", stop mode is cleared and the RUN state (normal operation) is entered. To prevent stop mode from being cleared even when an interrupt request occurs, set the interrupt enable bit of the watch timer to interrupt disabled. • Main clock oscillation stabilization wait timer interrupt If a main clock oscillation stabilization wait timer interrupt request occurs when oscillation control register (OSCCR) bit 0 (OSCDS1 bit) is set to "0" during subclock selection or when standby control register (STCR) bit 0 (OSCD1 bit) is set to "0" during main clock selection, stop mode is cleared and the RUN state (normal operation) is entered. To prevent stop mode from being cleared even when an interrupt request occurs, stop the main clock oscillation stabilization wait timer or set the interrupt enable bit of the main clock oscillation stabilization wait timer to interrupt disabled. • Generation of a settings initialization reset (INIT) request If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) is unconditionally entered. • Generation of an operation initialization reset (RST) request If an operation initialization reset (RST) request occurs, the operation initialization reset (RST) is unconditionally entered. Note: For information about the priority of sources, see "❍Priority of state transition requests" in Section "3.11.1 Device States and State Transitions". [Selecting a clock source in stop mode] Select the main clock divided by 2 as the source clock before setting stop mode. For more information, see Section "3.10 Clock Generation Control" especially Section "3.10.1 PLL Controls". The same limitations as in the normal operation apply to the setting of a divide-by rate. 141 CHAPTER 3 CPU AND CONTROL UNITS ■ Normal and Synchronous Standby Operations If "1" is set for Bit 8 (SYNCS bit) of the timebase counter control register (TBCR), synchronous standby operation is enabled. In this case, simply writing to the STOP bit does not cause a transition to the stop state. Instead, writing to the STOP bit and then reading the STCR register causes a transition to the stop state. If "0" is set for the SYNCS bit, normal standby operation is selected. In this case, simply writing to the STOP bit causes a transition to the stop state. If, in normal standby operation, the value set for the divide-by rate of the peripheral clock (CLKP) is larger than the CPU clock (CLKB), many instructions are executed before writing to the STOP bit actually occurs. Thus, after the write instruction to the STOP bit, the same number of NOP instructions as {5 + (CPU clock divide-by rate/peripheral clock divide-by rate)} instructions or more must be inserted. Otherwise, subsequent instructions are executed before the transition to the stop state. In synchronous standby operation, the stop state occurs only after writing to the STOP bit actually occurs and the reading of STCR register are completed. This is because the CPU uses the bus until the value read from the STCR register is stored into the CPU. Thus, in any setting of relationship between divide-by rates of the CPU clock (CLKB) and the peripheral clock (CLKP), insert only two NOP instructions after the write instruction for the STOP bit and the read instruction for the STCR register to prevent any subsequent instructions from being executed before transition to the stop state. 142 3.12 Watch Timer The watch timer is a 15-bit free-run timer that performs incremental counting in synchronization with the subclock. The watch timer has an interval timer function to generate interrupts repeatedly at fixed time intervals. ■ Interval Time Table 3.12-1 lists the types of interval times. Select a time interval from one of the following four types. Table 3.12-1 Types of Interval Time Subclock cycle Interval time 1/FCL (about 30.5 µs) 210FCL (31.25 ms) 213FCL (0.25 s) 214FCL (0.50 s) 215FCL (1.00 s) Note: FCL indicates the subclock oscillation frequency. ■ Block Diagram of the Watch Timer Figure 3.12-1 shows the block diagram of the watch timer. Figure 3.12-1 Block Diagram of the Watch Timer Watch timer counter F CL 0 2 1 1 2 2 2 2 3 3 2 4 4 2 5 5 2 6 6 2 7 7 2 8 8 2 9 9 2 10 11 12 13 14 10 11 2 2 12 2 13 2 14 2 15 (31.25 ms) Interval timer selector (0.25 s) (0.5 s) (1.0 s) Reset (INIT) Counter clear circuit Watch interrupt Watch timer control register (WPCR) WIF WIE WS1 WS0 WCL F CL : Subclock source oscillation The numbers in the parentheses indicate the intervals when the subclock source oscillation is 32.768 kHz. 143 CHAPTER 3 CPU AND CONTROL UNITS ● Watch timer The watch timer is a 15-bit incremental counter that uses the subclock source oscillation as the count clock. ● Counter clear circuit The counter clear circuit clears the counter not only when the WCL bit of the WPCR register is set to "0" but also when a reset (INIT) request is generated. ● Interval timer selector The interval timer selector selects one of the four frequency-divide outputs of the watch timer counter for the interval timer. The trailing edge of the selected frequency-divide output becomes an interrupt source. ● Watch timer control register (WPCR) The watch timer control register is used to select the interval time, clear the counter, control interrupts, and check the counter status. ■ Watch Timer Control Register The configuration of the watch timer register is shown below: WPCR Initial value bit 0000048CH 15 14 13 12 11 10 9 8 at INIT WIF R/W WIE R/W - - - WS1 R/W WS0 R/W WCL W 00H at RST xxH Access R/W [Bit 15] WIF (watch timer interrupt flag) This bit is the watch interrupt request flag. This bit is set to "1" at the trailing edge of the selected frequency-divide output for the interval timer. If this bit and the watch interrupt request enable bit are "1", a watch timer interrupt request is outputted. Value 144 Explanation 0 Watch timer interrupt not requested (default value) 1 Watch timer interrupt requested • This bit is cleared to "0" by a reset (INIT) request. • Data can be written to and read from this bit. However, only "0" can be written. If an attempt is made to write "1" to this bit, its value is not changed. • If a read modify write instruction is issued, "1" is always read from this bit. [Bit 14] WIE (watch timer interrupt enable) This bit enables or disables the interrupt request output to the CPU. If this bit and the watch interrupt request flag bit are "1", a watch timer interrupt request is outputted. Value Explanation 0 Output of watch timer interrupt request disabled (default value) 1 Output of watch timer interrupt request disabled • This bit is cleared to "0" by a reset (INIT) request. • Data can be written to and read from this bit. [Bits 13 to 11] (reserved bits) These bits are reserved. When writing data to these bits, be sure to write "0". (Writing of "1" to these bits is prohibited.) Data read from these bits is undefined. [Bits 10, 9] WS1, WS0 (watch timer interval select 1, 0) These bits select the interval of the interval timer. Select the output bit of the watch timer counter from one of the four types listed in Table 3.12-2 . Table 3.12-2 Watch Timer Counter Output Bits Interval timer interval (at FCL = 32.768 kHz) WS1 WS0 0 0 210/FCL (31.25 ms) (default value) 0 1 213/FCL (0.25s) 1 0 214/FCL (0.50s) 1 1 215/FCL (1.00s) • These bits are cleared to "00" by a reset (INIT) request. • Data can be written to and read from these bits. [Bit 8] WCL (watch timer clear) Writing "0" to this bit clears the watch timer to "0". Only "0" can be written to this bit. Writing "1" to this bit does not affect timer operation. • The value read from this bit is always "1". 145 CHAPTER 3 CPU AND CONTROL UNITS ■ Watch Timer Interrupt If the set interval time elapses while the watch timer counter is counting with the subclock, the watch timer interrupt flag (WIF) is set to "1". Then, if the watch timer interrupt enable bit (WIE) has been set to "1" (interrupt output enabled), an interrupt request is outputted to the CPU. If subclock oscillation has stopped (see "■ Operation of Interval Timer Function" in Section "3.13 Main Clock Oscillation Stabilization Wait Timer"), a watch interrupt will not occur because counting has also stopped. To clear an interrupt request, write "0" to the WIF bit using the interrupt processing routine. Note that the WIF bit is set at the trailing edge of the selected frequency-divide output regardless of the value of the WIE bit. Notes: • The WIF and WCL bits must be cleared to "0" (WIF=WCL=0) at the same time if watch timer interrupt request output is to be enabled (WIE = 1) or the value of the WS1 and WS0 bits are to be changed after release from the reset state. • If the WIE bit is changed from "0" to "1" to enable interrupt output when the WIF bit is "1", an interrupt request is output immediately. • If a counter clear (WCL bit of WPCR is "1") and overflow of selected bits occur at the same time, the WIF bit is not set to "1". ■ Operation of Interval Timer Function The watch timer counter continues incremental counting while the subclock is running. When subclock oscillation stops, counting stops in the following cases: • Counting is stopped throughout stop mode if the MB91350A is put into stop mode by stopping subclock oscillation with Bit 1 [OSCD2 bit] of the standby control register [STCR] set to "1". • To make the watch timer operate in stop mode, set the OSCD2 bit to "0" before entry to the standby state, because the OSCD2 bit is initialized to "1" at reset by an INIT request. If the counter is cleared (WCL bit is cleared to "0"), the counter starts counting from 0000H. When the count reaches 7FFFH, the counter restarts counting from 0000H. When the trailing edge of the frequencydivide output selected for the interval timer is detected during incremental counting, the watch interrupt request (WIF) bit is set to "1". In other words, a watch timer interrupt request is generated at the selected intervals on the basis of the selected interval time. 146 ■ Operation of Clock Supply Function The MB91350A uses a timebase counter to secure the oscillation stabilization wait time after INIT or stop mode. On the other hand, the MB91350A uses the watch timer to secure the subclock oscillation stabilization wait time while the main clock is selected as the clock source. This is because the watch timer operates with the subclock regardless of clock source selection. Follow the procedure below to perform subclock oscillation stabilization wait operation while the MB91350A is operating on the main clock: 1. Set the interval time for the watch timer to "1" second (when FCL = 32.768 kHz), and clear the counter to "0" (by writing "11" to the WS1 and WS0 bits and "0" to the WCL bit). If it is necessary to perform processing after the end of the oscillation stabilization wait with an interrupt, initialize the interrupt flag (by writing "0" to the WIF bit and "1" to WIE bit). 2. Start subclock oscillation (by writing "1" to Bit 11 [PLL2EN bit] of CLKR). 3. In the program, wait until the WIF flag is set to "1". 4. Make sure that the WIF flag has been set to "1", then perform the processing to be done after the end of the oscillation stabilization wait. If interrupts are enabled, an interrupt is generated when the WIF bit is set to "1". Then, perform the processing to be done after the end of the oscillation stabilization wait by an interrupt routine. If it is necessary to switch the clock source from the main clock to subclock, switch the clock source after making sure that the WIF bit has been set to "1" as described above. (If the clock source is switched to the subclock before subclock oscillation is stabilized, unstable clock is supplied to the entire device and subsequent operation is unpredictable.) 147 CHAPTER 3 CPU AND CONTROL UNITS ■ Operation of the Watch Timer Figure 3.12-2 shows the counter states at start of watch timer, switching to the subclock, and transition to stop mode during operation with the subclock. Figure 3.12-2 Counter States at Transition to Subclock or Stop Mode FFF H Value of counter 4000 H Subclock oscillation stabilization wait time - Timer clearance (WS1 and WS0 bits=1) (other than 0) - Interval time selection (WS1 and WS0 bits = 11B) Interval time Cleared by interrupt routine WIF Clock source Clock mode Main clock Subclock RUN - Change of interval time (WS1 and WS0 bits = 10B) - Switching from main clock to subclock Stop * RUN Instruction to enter stop mode * : When the OSCD2 bit of STCR is set to 0 (oscillation is not stopped in stop mode) ■ Precautions for Using the Watch Timer Use the oscillation stabilization wait time as a reference value because the oscillation cycle is unstable immediately after oscillation is started. No watch interrupt is generated while subclock oscillation is stopped because the watch timer is stopped. Do not stop subclock oscillation if it is necessary to use the watch timer for processing. If a WIF flag setting request occurs at the same time as a zero-clearance request from the CPU, the WIF flag setting request has priority and the zero-clearance request is ignored. 148 3.13 Main Clock Oscillation Stabilization Wait Timer The main clock oscillation stabilization wait timer is a 23-bit counter that performs incremental counting in synchronization with the main clock. The main clock oscillation stabilization wait timer has an interval timer function to generate interrupts repeatedly at fixed time intervals. This timer is used to secure main clock oscillation stabilization wait time when main clock oscillation is restarted after it has been stopped by setting Bit 0 (OSCDS1) of the oscillation control register (OSCCR) during operation with the subclock. ■ Time Intervals for Main Clock Oscillation Stabilization Wait Timer Table 3.13-1 lists the types of time intervals. Select a time interval from one of the following three types for timer intervals. Table 3.13-1 Time Intervals for Main Clock Oscillation Stabilization Wait Timer Main clock interval Interval time 1/FCL (about 80 ns) 211/FCL (164 µs) 216/FCL (5.25 ms) 223/FCL (671 ms) Note: FCL indicates the main clock oscillation frequency. ■ Block Diagram of the Main Clock Oscillation Stabilization Wait Timer Figure 3.13-1 shows the block diagram of the main clock oscillation stabilization wait timer. Figure 3.13-1 Block Diagram of the Main Clock Oscillation Stabilization Wait Timer Main clock oscillation stabilization wait timer counter FC L 0 1 2 3 4 5 6 7 8 10 15 22 21 22 23 24 25 26 27 28 29 21 1 21 6 22 3 (164µs) Interval timer selector (5.25ms) (671ms) Reset (INIT) Main clock oscillation stabilization wait timer interrupt Counter clear circuit Main clock oscillation stabilization wait timer control register (OSCR) WIF WIE WEN WS1 WS0 WCL F CL : Main clock source oscillation The numbers in the parentheses indicate the intervals when the main clock source oscillation is 12.5 Hz. 149 CHAPTER 3 CPU AND CONTROL UNITS ● Main clock oscillation stabilization wait timer The main clock oscillation stabilization wait timer is a 32-bit incremental counter that uses the main clock source oscillation as the count clock. ● Counter clear circuit The counter clear circuit clears the counter not only when the WCL bit of the OSCR register is set to "0" but also when a reset (INIT) request is generated. ● Interval timer selector The interval timer selector selects one of the three frequency-divide outputs of the main clock oscillation stabilization wait timer counter for the interval timer. The trailing edge of the selected frequency-divide output becomes an interrupt source. ● Main clock oscillation stabilization wait timer control register (OSCR) The main clock oscillation stabilization wait timer control register is used to select the interval time, clear the counter, control interrupts, and check counter status. ■ Explanation of the Main Clock Oscillation Stabilization Wait Timer Register The configuration of the main clock oscillation stabilization wait timer register is shown below: OSCR Initial value bit 00000490H 15 14 13 12 11 10 9 8 WIF R/W WIE R/W WEN R/W - - WS1 R/W WS0 R/W WCL W at INIT 00H at RST xxH Access R/W [Bit 15] WIF (timer interrupt flag) This bit is the main clock oscillation stabilization wait interrupt request flag. This bit is set to "1" at the trailing edge of the selected divided output for the interval timer. If this bit and the interrupt request enable bit are "1", a main clock oscillation stabilization wait timer interrupt request is outputted. Value 150 Explanation 0 Main clock oscillation stabilization wait timer interrupt not requested (default value) 1 Main clock oscillation stabilization wait timer interrupt requested • This bit is cleared to "0" by a reset (INIT) request. • Data can be written to and read from this bit. However, only "0" can be written. If an attempt is made to write "1" to this bit, its value is not changed. • If a read modify write instruction is issued, "1" is always read from this bit. [Bit 14] WIE (timer interrupt enable) This bit enables or disables the interrupt request output to the CPU. If this bit and main clock oscillation stabilization interrupt request flag bit are "1", a main clock oscillation stabilization wait timer interrupt request is outputted. Value Explanation 0 Output of main clock oscillation stabilization wait timer interrupt request disabled (default value) 1 Output of main clock oscillation stabilization wait timer interrupt request enabled • This bit is cleared to "0" by a reset (INIT) request. • Data can be written to and read from this bit. [Bit 13] WEN (timer enable) This bit enables timer operation. When this bit is "1", the timer counts. Value Explanation 0 The timer is stopped (default value). 1 The timer operates. • This bit is cleared to "0" by a reset (INIT) request. • Data can be written to and read from this bit. [Bits 12, 11] (reserved bits) These bits are reserved. When writing data to these bits, be sure to write "0". (Writing "1" to these bits is not allowed). Data read from these bits is undefined. [Bits 10, 9] WS1, WS0 (timer interval select 1, 0) These bits select the interval of the interval timer. One of the following three intervals is selected according to the output bits of the main clock oscillation stabilization wait timer counter: Interval timer interval (at FCL = 12.5 MHz) WS1 WS0 0 0 Setting prohibited (default value) 0 1 211/FCL (164 µs) 1 0 216/FCL (5.25 ms) 1 1 223/FCL (671 ms) • These bits are cleared to "00" by a reset (INIT) request. • Data can be written to and read from these bits. • To use the main clock oscillation stabilization wait timer, write data to this register. 151 CHAPTER 3 CPU AND CONTROL UNITS [Bit 8] WCL (timer clear) Writing "0" to this bit clears the main clock oscillation stabilization wait timer to 0. Only "0" can be written to this bit. Writing "1" to this bit does not affect timer operation. • The value read from this bit is always "1". ■ Main Clock Oscillation Stabilization Wait Timer Interrupt If the set interval time elapses while the main clock oscillation stabilization wait timer counter is counting with the main clock, the main clock oscillation stabilization wait interrupt request flag (WIF) is set to "1". Then, if the interrupt request enable bit (WIE) is set to "1" (interrupt output is enabled), an interrupt request is output to the CPU. Note that main clock oscillation stabilization wait interrupt do not occur when main clock oscillation is stopped (see the next Item, "Operation of interval timer function") because counting is stopped when the main clock is stopped. To clear an interrupt request, write "0" to the WIF bit by the interrupt processing routine. Note that the WIF bit is set at the trailing edge of the selected frequency-divide output regardless of the value of the WIE bit. Notes: • The WIF and WCL bits must be cleared to "0" (WIF=WCL=0) at the same time if interrupt request output is to be enabled (WIE = 1) or the value of the WS1 and WS0 bits are to be changed after release from the reset state. • If the WIE bit is changed from "0" to "1" to enable interrupt output when the WIF bit is "1", an interrupt request is output immediately. • If a counter clear (WCL bit of WPCR is "1") and overflow of selected bits occur at the same time, the WIF bit is not set. ■ Operation of Interval Timer Function The main clock oscillation stabilization wait timer counter continues incremental counting while the main clock is oscillated. When main clock oscillation stops, counting stops in the following case: • When the WEN bit is "0" • Counting is stopped throughout stop mode if the MB91350A is put into stop mode by stopping main clock oscillation with Bit 0 [OSCD1 bit] of the standby control register [STCR] set to "1". To make the main clock oscillation stabilization wait timer operate in stop mode, set the OSCD2 bit to "0" before entry into the standby state because the OSCD1 bit is initialized to "1" at reset by an INIT request. • When oscillation control register (OSCCR) bit 0 (OSCDS1 bit) is set to "1" in subclock mode, main clock oscillation and timer counting are stopped. If the counter is cleared (WCL bit is cleared to "0"), the counter starts counting from 000000H. When the count reaches 7FFFFFH, the counter restarts counting from 000000H. If the trailing edge of the frequencydivide output selected for the interval timer is detected during incremental counting, the main clock oscillation stabilization wait interrupt request flag (WIF) bit is set to "1". In other words, a main clock oscillation stabilization wait timer interrupt request is generated at the selected intervals on the basis of the cleared time. 152 ■ Operation of Clock Supply Function The MB91350A uses a timebase counter to secure the oscillation stabilization wait time after INIT or stop mode. On the other hand, the MB91350A uses the main clock oscillation stabilization wait timer to secure the main clock oscillation stabilization wait time while the subclock is selected as the clock source. This is because the main clock oscillation stabilization wait timer operates on the main clock regardless of the clock source selection. Use the following procedure to execute main clock oscillation stabilization wait from main clock oscillation stop state during subclock operation: 1. Set the time required for main clock oscillation stabilization with the WT1 and WT0 bits, and clear the counter to "0" (by writing the oscillation stabilization wait time to the WS1 and WS0 bits and "0" to the WCL bit). If it is necessary to perform processing after the end of oscillation stabilization wait with an interrupt, initialize the interrupt flag (by writing "0" to the WIF and WIE bits). 2. Start main clock oscillation (by writing "1" to Bit 0 [OCSDS1 bit] of OSCR). 3. In the program, wait until the WIF flag is set to "1". 4. Make sure that the WIF flag has been set to "1", then perform the processing to be done after the end of oscillation stabilization wait. If interrupts are enabled, an interrupt is generated when the WIF bit is set to "1". Then, perform the processing to be done after the end of oscillation stabilization wait by an interrupt routine. If it is necessary to switch the clock source from the subclock to main clock, switch the clock source after making sure that the WIF bit has been set to "1" as described above. (If the clock source is switched to the main clock before main clock oscillation is stabilized, an unstable clock is supplied to the entire device and subsequent operation is unpredictable.) ■ Operation of the Main Clock Oscillation Stabilization Wait Timer Figure 3.13-2 shows the counter states at the start of the main clock oscillation stabilization wait timer and switching to the main clock. Figure 3.13-2 Counter States at the Start of the Main Clock Oscillation Stabilization Wait Timer and Switching to the Main Clock 7FFFFFH Value of counter Main clock oscillation stabilization wait time - Timer clearance (WCL bit = 1) (other than 0) - Timer interval selection (WS1 and WS0 bits = 11B) - Start of main clock oscillation (OSCDS1 bit of OSCR = 0) WIF (interrupt request) Cleared by interrupt routine WIE (interrupt mask) Clock mode Subclock Main clock - Switching from subclock to main clock 153 CHAPTER 3 CPU AND CONTROL UNITS ■ Precautions on Using the Main Clock Oscillation Stabilization Wait Timer Use the oscillation stabilization wait time as a reference value because the oscillation cycle is unstable immediately after oscillation is started. No main clock oscillation stabilization interrupt is generated while main clock oscillation is stopped. This is because the counter is stopped when main clock oscillation is stopped. Do not stop main clock oscillation if it is necessary to use the main clock oscillation stabilization interrupt for processing. If a WIF flag setting request occurs at the same time as a zero-clearance request from the CPU, the WIF setting request has priority and the zero-clearance request is ignored. 154 3.14 Peripheral Stop Control Peripheral stop control reduces the amount of power consumed by the device by stopping the supply of clocks to peripheral resources that are not being used. Because supplying or stopping a clock can be set for each channel of each peripheral resource, detailed settings appropriate for how resources are used can be made. ■ List of Peripheral Stop Control Registers The configuration of the peripheral stop control registers is shown below: RSTOP0 Initial value bit 00000494H 15 14 13 12 11 10 9 8 at INIT at RST Access ST07 ST06 ST05* ST04* ST03 ST02 ST01 ST00 00H xxH W 00H xxH W 00H xxH W 00H xxH W RSTOP1 bit 00000495H 7 6 5 4 3 2 1 0 ST17 ST16 ST15* ST14 ST13* ST12 ST11* ST10 RSTOP2 bit 00000496H 15 14 13 12 11 10 9 8 ST27* ST26* ST25 ST24 ST23 ST22 ST21 ST20 7 6 5 4 3 2 1 0 - - - - - ST32 ST31 ST30 RSTOP3 bit 00000497H *: For the MB91F353A/351A/352A/353A, the settings of bits ST05, ST04, ST15, ST13, ST11, ST27, and ST26 are disabled. ■ Block Diagram of Peripheral Stop Control Figure 3.14-1 shows a block diagram of peripheral stop control. Figure 3.14-1 Block Diagram of Peripheral Stop Control ST32 ST31 ST02 ST01 ST00 Each resource clock UART ch0 / U-TIMER ch0 UART ch1 / U-TIMER ch1 R-bus UART ch2 / U-TIMER ch2 A/D D/A CLKP 155 CHAPTER 3 CPU AND CONTROL UNITS ■ Detailed Explanation of the Peripheral Stop Control Registers The bits of each register are described below. When a bit of RSTOP0 to RSTOP3 (peripheral stop register) is "0", a clock is supplied to the corresponding peripheral resource. Writing "1" to the bit stops supply of the clock to that peripheral resource. A reset (INIT) clears all bits and sets all peripheral resources to receive a clock. ● Peripheral stop register 0 (RSTOP0) Peripheral stop register 0 controls the supply of clock signals to the UART and the synchronous serial interface. The configuration of peripheral stop register 0 is shown below: RSTOP0 Initial value bit 00000494H 15 14 13 12 11 10 9 8 at INIT ST07 ST06 ST05* ST04* ST03 ST02 ST01 ST00 00H at RST xxH W Bit Name 15 ST07 0: A clock signal is supplied to synchronous serial interface ch7 (initial value). 1: Supply of the clock signal is stopped. 14 ST06 0: A clock signal is supplied to synchronous serial interface ch6 (initial value). 1: Supply of the clock signal is stopped. 13 ST05* 0: A clock signal is supplied to synchronous serial interface ch5 (initial value). 1: Supply of the clock signal is stopped. 12 ST04* 0: A clock signal is supplied to UART ch4/U-TIMER ch4 (initial value). 1: Supply of the clock signal is stopped. 11 ST03 0: A clock signal is supplied to UART ch3/U-TIMER ch3 (initial value). 1: Supply of the clock signal is stopped. 10 ST02 0: A clock signal is supplied to UART ch2/U-TIMER ch2 (initial value). 1: Supply of the clock signal is stopped. 9 ST01 0: A clock signal is supplied to UART ch1/U-TIMER ch1 (initial value). 1: Supply of the clock signal is stopped. 8 ST00 0: A clock signal is supplied to UART ch0/U-TIMER ch0 (initial value). 1: Supply of the clock signal is stopped. * : For the MB91F353A/351A/352A/353A, the settings of the ST05 and ST04 bits are disabled. 156 Access ● Peripheral stop register 1 (RSTOP1) Peripheral stop register 1 controls the supply of clock signals to the reload timer and PPG. The configuration of peripheral stop register 1 is shown below: RSTOP1 Initial value bit 00000495H 7 ST17 6 ST16 5 ST15* 4 ST14 3 ST13* 2 ST12 1 ST11* 0 at INIT at RST Access ST10 00H xxH W Bit Name 7 ST17 0: A clock signal is supplied to reload timer ch3 (initial value). 1: Supply of the clock signal is stopped. 6 ST16 0: A clock signal is supplied to reload timer channels 0 to 2 (initial value). 1: Supply of the clock signal is stopped. 5 ST15* 0: A clock signal is supplied to PPG ch5 (initial value). 1: Supply of the clock signal is stopped. 4 ST14 0: A clock signal is supplied to PPG ch4 (initial value). 1: Supply of the clock signal is stopped. 3 ST13* 0: A clock signal is supplied to PPG ch3 (initial value). 1: Supply of the clock signal is stopped. 2 ST12 0: A clock signal is supplied to PPG ch2 (initial value). 1: Supply of the clock signal is stopped. 1 ST11* 0: A clock signal is supplied to PPG ch1 (initial value). 1: Supply of the clock signal is stopped. 0 ST10 0: A clock signal is supplied to PPG ch0 (initial value). 1: Supply of the clock signal is stopped. *: For the MB91F353A/351A/352A/353A, the settings of the ST15, ST13, and ST11 bits are disabled. 157 CHAPTER 3 CPU AND CONTROL UNITS ● Peripheral stop register 2 (RSTOP2) Peripheral stop register 2 controls the supply of clock signals to the up/down counter, free-running timer, input capture, and output compare. The configuration of peripheral stop register 2 is shown below: RSTOP2 Initial value bit 00000496H 15 14 13 12 11 10 9 8 at INIT ST27* ST26* ST25 ST24 ST23 ST22 ST21 ST20 00H Access W Bit Name 15 ST27* 0: A clock signal is supplied to output compare channels 6 and 7 (initial value). 1: Supply of the clock signal is stopped. 14 ST26* 0: A clock signal is supplied to output compare channels 4 and 5 (initial value). 1: Supply of the clock signal is stopped. 13 ST25 0: A clock signal is supplied to output compare channels 2 and 3 (initial value). 1: Supply of the clock signal is stopped. 12 ST24 0: A clock signal is supplied to output compare channels 0 and 1 (initial value). 1: Supply of the clock signal is stopped. 11 ST23 0: A clock signal is supplied to input capture channels 2 and 3 (initial value). 1: Supply of the clock signal is stopped. 10 ST22 0: A clock signal is supplied to input capture channels 0 and 1 (initial value). 1: Supply of the clock signal is stopped. 9 ST21 0: A clock signal is supplied to the free-running timer (initial value). 1: Supply of the clock signal is stopped. 8 ST20 0: A clock signal is supplied to up/down counter channels 0 and 1 (initial value). 1: Supply of the clock signal is stopped. *: For the MB91F353A/351A/352A/353A, the settings of the ST27 and ST26 bits are disabled. 158 at RST xxH ● Peripheral stop register 3 (RSTOP3) Peripheral stop register 3 controls the supply of clock signals to the I2C interface and the A/D and D/A converters. The configuration of peripheral stop register 3 is shown below: RSTOP3 Initial value bit 00000497H 7 6 5 4 3 2 1 0 - - - - - ST32 ST31 ST30 at INIT 00H at RST xxH Access W Bit Name 7 - (Reserved bit). Note: Writing "1" to this bit is not allowed. When this bit is read, "0" is always read. 6 - (Reserved bit). Note: Writing "1" to this bit is not allowed. When this bit is read, "0" is always read. 5 - (Reserved bit). Note: Writing "1" to this bit is not allowed. When this bit is read, "0" is always read. 4 - (Reserved bit). Note: Writing "1" to this bit is not allowed. When this bit is read, "0" is always read. 3 - (Reserved bit). Note: Writing "1" to this bit is not allowed. When this bit is read, "0" is always read. 2 ST32 0: A clock signal is supplied to the D/A converter (initial value). 1: Supply of the clock signal is stopped. 1 ST31 0: A clock signal is supplied to the A/D converter (initial value). 1: Supply of the clock signal is stopped. 0 ST30 0: A clock signal is supplied to the I2C interface (initial value). 1: Supply of the clock signal is stopped. Notes: • The following points regarding peripheral stop control that uses settings in these registers: • The register of a stopped resource cannot be read from or written to. Stop supply of the clock signal while the relevant resource is stopped. • Writing "1" stops the supply of the clock signal to the relevant resource. As a result, the resource cannot be activated. To use a resource that has been stopped, write "0" to the relevant bit to set clock signal supply state, then activate the resource. • Do not stop peripheral resources that are subject to DMA and are in the DMA enable state. Furthermore, do not enable DMA transfer for resources that have been stopped using these bits. 159 CHAPTER 3 CPU AND CONTROL UNITS • Do not stop resources that are operating or the resources in a DMA transfer. • The peripheral stop registers are not initialized at RST (software reset). (They are initialized at INIT.) To initialize a peripheral stop register after a software reset, use a program to reset the register. 160 CHAPTER 4 EXTERNAL BUS INTERFACE The external bus interface controller controls the interfaces with the internal bus for chips and with external memory and I/O devices. This chapter explains each function of the external bus interface. 4.1 Overview of the External Bus Interface 4.2 External Bus Interface Registers 4.3 Setting Example of the Chip Select Area 4.4 Byte Ordering (Endian) and Bus Access 4.5 Ordinary Bus Interface 4.6 Address/data Multiplex Interface 4.7 Prefetch Operation 4.8 DMA Access Operation 4.9 Bus Arbitration 4.10 Procedure for Setting a Register 161 CHAPTER 4 EXTERNAL BUS INTERFACE 4.1 Overview of the External Bus Interface This section describes the features of the external bus interface. ■ Features of the External Bus Interface • Addresses of up to 32 bits can be output. • Various kinds of external memory (8-bit/16-bit modules) can be directly connected and multiple access timings can be mixed and controlled. • Asynchronous SRAM and asynchronous ROM/FLASH memory (multiple write strobe method or byte enable method) • Page mode ROM/FLASH memory (Page sizes 2, 4, and 8 can be used) • Address/data multiplex bus (8-bit/16-bit width only) • Synchronous memory (such as ASIC built-in memory) Note: Synchronous SRAM cannot be directly connected. • • Four independent banks (chip select areas) can be set, and chip select corresponding to each bank can be output. • The size of each area can be set in multiples of 64K bytes (64K bytes to 2 GB for each chip select area). • An area can be set at any location in the logical address space (Boundaries may be limited depending on the size of the area.) In each chip select area, the following functions can be set independently: • Enabling and disabling of the chip select area (Disabled areas cannot be accessed) • Setting of the access timing type to support various kinds of memory • Detailed access timing setting (individual setting of the access type such as the wait cycle) • Setting of the data bus width (8-bit/16-bit) • Setting for the order of bytes (big or little endian) Note: Only big endian can be set for the CS0 area. • 162 • Setting of write disable (read-only area) • Enabling and disabling of fetches from the built-in cache • Enabling and disabling of the prefetch function • Maximum burst length setting (1, 2, 4, 8) A different detailed timing can be set for each access timing type. • For the same type of access timing, a different setting can be made in each chip select area. • Auto-wait can be set to up to 15 cycles (asynchronous SRAM, ROM, Flash, and I/O area). • The bus cycle can be extended by external RDY input (asynchronous SRAM, ROM, Flash, and I/O area). • The first access wait and page wait can be set (burst, page mode, and ROM/FLASH area). • Various kinds of idle/recovery cycles and setting delays can be inserted. • Fly-by transfer by DMA can be performed. • Transfer between memory and I/O can be performed in a single access operation. • The memory wait cycle can be synchronized with the I/O wait cycle in fly-by. • The hold time can be secured by only extending transfer source access. • Idle/recovery cycles specific to fly-by transfer can be set. • External bus arbitration using BRQ and BGRNT can be performed. • Pins that are not used by the external interface can be used as general-purpose I/O ports through settings. 163 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Block Diagram of the External Bus Interface Figure 4.1-1 shows the block diagram of the external bus interface. Figure 4.1-1 Block Diagram of the External Bus Interface Internal address bus 32 Internal data bus 32 External data bus MUX write buffer read buffer switch switch DATA BLOCK ADDRESS BLOCK +1 or +2 External address bus address buffer ASR CS0 to CS3 ASZ comparator External terminal controller All-block control resisters & control 164 RD WR0, WR1 AS BRQ BGRNT RDY ■ I/O Pins The I/O pins are external bus interface pins (Some pins have other uses). Ordinary bus interface A23-A00, D31-D16(AD15-AD00) CS0, CS1, CS2, CS3, AS, SYSCLK, MCLK RD WR0, WR1, RDY, BRQ, BGRNT Memory interface MCLK DMA interface IOWR, IORD, DACK0, DACK1, DACK2 DREQ0, DREQ1, DREQ2 DEOP0/DSTP0, DEOP1/DSTP1, DEOP2/DSTP2 165 CHAPTER 4 EXTERNAL BUS INTERFACE ■ List of External Bus Interface Registers The configuration of the external bus interface registers is shown below: Address 00000640H 00000644H 00000648H 0000064CH 00000650H 00000654H 00000658H 0000065CH 00000660H 00000664H 00000668H 0000066CH 00000670H 00000674H 00000678H 0000067CH 00000680H 00000684H 00000688H 0000068CH 000007F8H 000007FCH 31 24 23 16 15 8 7 ASR0 ASR1 ASR2 ASR3 ASR4 ASR5 ASR6 ASR7 AWR0 AWR2 AWR4 AWR6 Reserved Reserved IOWR0 Reserved CSER ACR0 ACR1 ACR2 ACR3 ACR4 ACR5 ACR6 ACR7 AWR1 AWR3 AWR5 AWR7 Reserved Reserved IOWR1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved (MODR) Reserved Reserved IOWR2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved indicates a reserved register. For a rewrite, be sure to set "0". MODR cannot be accessed from user programs. 166 0 Reserved Reserved Reserved Reserved TCR Reserved Reserved Reserved Reserved Reserved Reserved 4.2 External Bus Interface Registers This section describes the registers of the external bus interface. ■ Register Overview of External Bus Interface The following registers are used by the external bus interface: • Area Select Registers (ASR0 to ASR3) • Area Configuration Registers (ACR0 to ACR7) • Area Wait Registers (AWR0 to AWR3) • I/O Wait Registers for DMAC (IOWR0 to IOWR3) • Chip Select Enable Register (CSER) • Terminal and timing Control Register (TCR) 167 CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.1 ASR0 to ASR3 (Area Select Register) This section describes the area select registers in detail. ■ Configuration of ASR0 to ASR3 (Area Select Registers) The configuration of ASR0 to ASR3 is shown below: Initial value ASR0 00000640H 15 14 13 A31 A30 A29 ASR1 00000644H 15 14 13 A31 A30 A29 ASR2 00000648H 15 14 13 A31 A30 A29 ASR3 0000064CH 15 14 13 A31 A30 A29 ASR4 00000650H 15 14 13 A31 A30 A29 ASR5 00000654H 15 14 13 A31 A30 A29 15 14 13 A31 A30 A29 15 14 13 A31 A30 A29 ASR6 00000658H ASR7 0000065CH 12 ... ... ... 2 1 0 A18 A17 16 12 ... ... ... 2 1 0 A18 A17 16 12 ... ... ... 2 1 0 A18 A17 16 12 ... ... ... 2 1 0 A18 A17 16 12 ... ... ... 2 1 0 A18 A17 16 12 ... ... ... 2 1 0 A18 A17 16 12 ... ... ... 2 1 0 A18 A17 16 12 ... ... ... 2 1 0 A18 A17 16 at INIT 0000H at RST 0000H Access XXXXH XXXXH R/W XXXXH XXXXH R/W XXXXH XXXXH R/W XXXXH XXXXH R/W XXXXH XXXXH R/W XXXXH XXXXH R/W XXXXH XXXXH R/W R/W The area select registers (ASR0 to ASR7) specify the start address of each chip select area for CS0 to CS7. The start address can be specified in the 16 high-order bits from A31 to A16. Each chip select area starts with the address set in this register and covers the range set by the four bits ASZ3 to ASZ0 of registers ACR0 to ACR7. The boundary of each chip select area obeys the setting for the four bits ASZ3 to ASZ0 of registers ACR0 to ACR7. For example, if an area of 1M bytes is set by the four bits ASZ3 to ASZ0, the four low-order bits of registers ASR0 to ASR7 are ignored and only bits A31 to A20 are valid. The ASR0 register is initialized to 0000H by INIT and RST. ASR1 to 7 are not initialized by INIT and RST, and are therefore undefined. After starting chip operation, be sure to set the corresponding ASR register before enabling each chip select area with the CSER register. 168 4.2.2 ACR0 to ACR7 (Area Configuration Registers) This section describes the area configuration registers in detail. ■ Configuration of Area Configuration Registers 0 to 7 (ACR0 to ACR7) The configuration of ACR0 to ACR7 is shown below: Initial value ACR0H 00000642H 15 14 13 12 11 10 9 8 INIT RST ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 1111**00B 1111**00B ACR0L 00000643H SREN PFEN WREN TYP3 TYP2 TYP1 TYP0 00000000B 00000000B R/W ACR1H 00000646H 15 14 13 12 11 10 9 8 ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB R/W ACR1L 00000647H 7 6 5 4 3 2 1 0 SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB R/W ACR2H 0000064AH 15 14 13 12 11 10 9 8 ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB R/W ACR2L 0000064BH 7 6 5 4 3 2 1 0 SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB R/W ACR3H 0000064EH ACR3L 0000064FH ACR4H 00000652H ACR4L 00000653H ACR5H 00000656H ACR5L 00000657H 7 15 6 14 5 13 4 0 12 3 11 2 10 1 9 6 5 4 3 2 1 8 14 13 12 11 10 9 6 5 4 3 2 1 14 13 12 11 10 9 6 5 4 3 2 1 R/W 8 ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB 7 R/W 0 SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB 15 R/W 8 ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB 7 R/W 0 SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB 15 R/W 0 ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB 7 Access R/W 0 SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB R/W 169 CHAPTER 4 EXTERNAL BUS INTERFACE (Continued) Initial value ACR6H 0000065AH 15 14 13 12 11 10 9 8 INIT RST ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB ACR6L 0000065BH SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB ACR7H 0000065EH ACR7L 0000065FH 7 15 6 14 5 4 13 12 3 11 2 10 1 9 6 5 4 3 2 1 R/W 0 R/W 8 ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB 7 Access R/W 0 SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB R/W ACR0 to ACR7 (area configuration registers 0 to 7) are used to set the functions of each chip select area. [Bits 15 to 12] ASZ3:0 (Area Size Bits [3:0]) These bits set the size of each chip select area as indicated in Table 4.2-1 . Table 4.2-1 Size of Each Chip Select Area as Set with the Area Size Bits ASZ3 ASZ2 ASZ1 ASZ0 0 0 0 0 64K bytes (00010000H byte, ASR A[31:16] bits are valid) 0 0 0 1 128K bytes (00020000H byte, ASR A[31:17] bits are valid) 0 0 1 0 256K bytes (00040000H byte, ASR A[31:18] bits are valid) 0 0 1 1 512K bytes (00080000H byte, ASR A[31:19] bits are valid) 0 1 0 0 1M bytes (00100000H byte, ASR A[31:20] bits are valid) 0 1 0 1 2M bytes (00200000H byte, ASR A[31:21] bits are valid) 0 1 1 0 4M bytes (00400000H byte, ASR A[31:22] bits are valid) 0 1 1 1 8M bytes (00800000H byte, ASR A[31:23] bits are valid) 1 0 0 0 16M bytes (01000000H byte, ASR A[31:24] bits are valid) 1 0 0 1 32M bytes (02000000H byte, ASR A[31:25] bits are valid) 1 0 1 0 64M bytes (04000000H byte, ASR A[31:26] bits are valid) 1 0 1 1 128M bytes (08000000H byte, ASR A[31:27] bits are valid) 1 1 0 0 256M bytes (10000000H byte, ASR A[31:28] bits are valid) 1 1 0 1 512M bytes (20000000H byte, ASR A[31:29] bits are valid) 1 1 1 0 1024M bytes (40000000H byte, ASR A[31:30] bits are valid) 1 1 1 1 2048M bytes (80000000H byte, ASR A[31] bit is valid) 170 Size of each chip select area ASZ[3:0] are used to set the size of each area by modifying the number of bits for address comparison to a value different from ASR. Thus, an ASR contains bits that are not compared. Bits ASZ[3:0] of ACR0 are initialized to 1111B (0FH) by RST. Despite this setting, however, the CS0 area just after RST is executed is specially set from 00000000H to FFFFFFFFH (setting of entire area). The entire-area setting is reset after the first write to ACR0 and an appropriate size is set as indicated in Table 4.2-1 . [Bits 11 to 10] DBW[1:0] (Data Bus Width [1:0]) These bits set the data bus width of each chip select area as indicated in the following table: DBW1 DBW0 Data bus width 0 0 8 bits (byte access) 0 1 16 bits (halfword access) 1 0 Reserved Setting disabled 1 1 Reserved Setting disabled The same values as those of the WTH bits of the mode vector are written automatically to bits DBW[1:0] of ACR0 during the reset sequence. [Bits 9 to 8] BST[1:0] (Burst Size [1:0]) These bits set the data bus width of each chip select area as indicated in the following table: BST1 BST0 Maximum burst length 0 0 1 (single access) 0 1 2 bursts (address boundary: 1 bit) 1 0 4 bursts (address boundary: 2 bits) 1 1 8 bursts (address boundary: 3 bits) In areas for which a burst length other than the single access is set, continuous burst access is performed within the address boundary determined by the burst length only when prefetch access is performed or data having a size exceeding the bus width is read. The maximum burst length of the bus width 32-bit area must be set to four bursts or less. Setting of two bursts or less is recommended. Fujitsu recommends setting no more than two bursts for the maximum burst length of the bus width 16-bit area. RDY input is ignored in areas for which any burst length other than the single access is set. 171 CHAPTER 4 EXTERNAL BUS INTERFACE [Bit 7] SREN (ShaRed ENable) This bit enables or disables sharing of each chip select area by BRQ/BGRNT as indicated in the following table: SREN Sharing enable/disable 0 Disable sharing by BRQ/BGRNT (CS cannot be high impedance) 1 Enable sharing by BRQ/BGRNT (CS can be high impedance) In areas where sharing is enabled, chip select output (CSn) is set to high impedance while the bus is open (during BGRNT=Low output). In areas where sharing is disabled, chip select output (CSn) is not set to high impedance even though the bus is open (during BGRNT=Low output). Access strobe output (AS, RD, WR0, WR1) is set to high impedance only if sharing of all areas enabled by CSER is enabled. [Bit 6] PFEN (PreFetch ENable) This bit enables or disables prefetch of each chip select area as indicated in the following table: PFEN Prefetch enable/disable 0 Disable prefetch 1 Enable prefetch When reading from an area for which prefetching is enabled, the subsequent address is read in advance and stored in the built-in prefetch buffer. When the stored address is accessed from the internal bus, the lookahead data in the prefetch buffer is returned without performing external access. For more information, see Section "4.7 Prefetch Operation". [Bit 5] WREN (WRite ENable) This bit enables or disables writing to each chip select area. WREN Write enable/disable 0 Disable write 1 Enable write If an area for which write operations are disabled is accessed for a write operation from the internal bus, the access is ignored and no external access at all is performed. Set the WREN bit of areas for which write operations are required, such as data areas, to "1". [Bit 4] LEND (Little ENDian select) This bit sets the byte ordering of each chip select area. LEND Order of bytes 0 Big endian 1 Little endian Be sure to set the LEND bit of ACR0 to 0. CS0 area supports only the big endian method. 172 [Bits 3 to 0] TYP[3:0] (TYPe select) These bits set the access type of each chip select area as indicated in the following table: TYP3 TYP2 TYP1 TYP0 Access type 0 x x Normal access (asynchronous SRAM, I/O, and single/page) 1 x x Address data multiplex access (8/16-bit bus width only) x 0 Disable WAIT insertion by the RDY pin. x 1 Enable WAIT insertion by the RDY pin (disabled during bursts). 0 x Use the WR0 to WR3 pins as write strobes (WR is always H). 1 x Setting disabled 0 Setting disabled 1 Setting disabled 0 x 0 1 0 0 1 0 Setting disabled 0 1 1 Setting disabled 1 0 0 Setting disabled 1 0 1 Setting disabled 1 1 0 Setting disabled 1 1 1 Mask area setting (The access type is the same as that of the overlapping area) * Set the access type as the combination of all bits. * : CS area mask setting function If you want to set an area some of whose operation settings are changed for a certain CS area (referred to as the base setting area), you can set TYPE3 to "0" of ACR in another CS area to "1111" so that the area can function as a mask setting area. If you do not use the mask setting function, disable any overlapping area settings for multiple CS areas. Access operations to the mask setting area are as follows: • CSX corresponding to a mask setting area is not asserted. • CSX corresponding to a base setting area is not asserted. • For the following ACR settings, the settings on the mask setting area side are valid: • Bits [11:10]DBW[1:0]: Bus width setting • Bits [9:8]BST[1:0]: Burst length setting • Bit [7]SREN: Sharing-enable setting • Bit [6]PFEN: Prefetch-enable setting 173 CHAPTER 4 EXTERNAL BUS INTERFACE • • Bit [5]WREN: Write-enable setting (For this setting only, only a setting that is the same as that of the base setting area is allowed) • Bit [4]LEND: Little endian setting For the following ACR setting, the setting on the base setting area side is valid: • Bits [3:0]TYPE[3:0]: Access type setting • For the AWR settings, the settings on the mask setting area side are valid. • For the CHER settings, the settings on the mask setting area side are valid. A mask setting area can be set for only part of another CS area (base setting area). You cannot set a mask setting area for an area without a base setting area. In addition, the mask setting area must not be duplicated. Be careful when setting the ASR and ACR:ASZ[3:0] bits. Notes: The following restrictions apply to bits [3:0]TYP[3:0]: • A write-enable setting cannot be implemented by a mask. • Write-enable settings in the base CS area and the mask setting area must be identical. • If write operations to a mask setting area are disabled, the area is not masked and operates as a base CS area. • If write operations to the base CS area are disabled but are enabled to the mask setting area, the area has no base, resulting in malfunctions. • The MB91350A series does not have a CS4 to CS7 pin. As a result, only the ACR:TYPE[3:0] = 1111 mask area setting is valid for CS areas 4 to 7. • Set both ASR and ACR at the same time using word access. When accessing ASR and ACR using half word, please set ACR after setting ASR. 174 4.2.3 AWR0 to AWR3 (Area Wait Register) This section describes the area wait registers in detail. ■ Configuration of AWR0 to AWR3 (Area Wait Registers) The configuration of AWR0 to AWR3 is shown below: Initial value AWR0H 00000660H 31 30 29 28 27 26 25 W15 W14 W13 W12 W11 W10 W09 AWR0L 00000661H 23 22 21 20 19 18 17 W07 W06 W05 W04 W03 W02 W01 W00 11111111B 11111011B R/W AWR1H 00000662H 15 14 13 12 11 10 9 W15 W14 W13 W12 W11 W10 W09 8 W08 xxxxxxxxB xxxxxxxxB R/W AWR1L 00000663H 7 6 5 4 3 2 1 W07 W06 W05 W04 W03 W02 W01 0 W00 xxxxxxxxB xxxxxxxxB R/W AWR2H 00000664H 31 30 29 28 27 26 25 W15 W14 W13 W12 W11 W10 W09 24 W08 xxxxxxxxB xxxxxxxxB R/W AWR2L 00000665H 23 22 21 20 19 18 17 W07 W06 W05 W04 W03 W02 W01 16 W00 xxxxxxxxB xxxxxxxxB R/W 15 14 13 12 11 10 9 W15 W14 W13 W12 W11 W10 W09 7 6 5 4 3 2 1 W07 W06 W05 W04 W03 W02 W01 31 30 29 28 27 26 25 W15 W14 W13 W12 W11 W10 W09 23 22 21 20 19 18 17 W07 W06 W05 W04 W03 W02 W01 15 14 13 12 11 10 9 W15 W14 W13 W12 W11 W10 W09 7 6 5 4 3 2 1 W07 W06 W05 W04 W03 W02 W01 AWR3H 00000666H AWR3L 00000667H AWR4H 00000668H AWR4L 00000669H AWR5H 0000066AH AWR5L 0000066BH 24 at INIT at RST W08 01111111B 01111111B Access R/W 16 8 W08 xxxxxxxxB xxxxxxxxB R/W 0 W00 xxxxxxxxB xxxxxxxxB R/W 24 W08 xxxxxxxxB xxxxxxxxB R/W 16 W00 xxxxxxxxB xxxxxxxxB R/W 8 W08 xxxxxxxxB xxxxxxxxB R/W 0 W00 xxxxxxxxB xxxxxxxxB R/W 175 CHAPTER 4 EXTERNAL BUS INTERFACE (Continued) Initial value AWR6H 0000066CH 31 30 29 28 27 26 25 W15 W14 W13 W12 W11 W10 W09 AWR6L 0000066DH 23 22 21 20 19 18 17 W07 W06 W05 W04 W03 W02 W01 15 14 13 12 11 10 9 W15 W14 W13 W12 W11 W10 W09 7 6 5 4 3 2 1 W07 W06 W05 W04 W03 W02 W01 AWR7H 0000066EH AWR7L 0000066FH 24 at INIT at RST W08 xxxxxxxxB xxxxxxxxB Access R/W 16 W00 xxxxxxxxB xxxxxxxxB R/W 8 W08 xxxxxxxxB xxxxxxxxB R/W 0 W00 xxxxxxxxB xxxxxxxxB R/W Registers AWR0 to AWR7 specify various kinds of waits for each chip select area. The function of each bit depends on the setting of the access type (bits TYP3 to TYP0) for registers ACR0 to ACR7. ■ Normal Access and Address/Data Multiplex Access A chip select area specified using the following settings for the access type (bits TYP3 to TYP0) of registers ACR0 to ACR3 operates as an area for normal access or address/data multiplex access. TYP3 TYP2 TYP1 TYP0 Access type 0 0 x x Normal access (asynchronous SRAM, I/O, and single/page) 0 1 x x Address data multiplex access (8/16-bit bus width only) The following lists the functions of each AWR0 to 3 bit for a normal access or address/data multiplex access area. Since the initial values of registers other than AWR0 are undefined, set them to their initial values before enabling each area with the CSER register. [Bits 15 to 12] W15 to 12 (First Access Wait Cycle) These bits set the number of auto-wait cycles to be inserted into the first access cycle of each cycle. Except for the burst access cycles, only this wait setting is used. The initial value of the CS0 area is set to 7 (wait). The initial values of the other areas are undefined. W15 W14 W13 W12 0 0 0 0 Auto-wait cycle 0 0 0 0 1 Auto-wait cycle 1 ... 1 176 1 First access wait cycle ... 1 1 Auto-wait cycle 15 [Bits 11 to 8] W11 to 08 (Inpage Access Wait Cycle) These bits set the number of auto-wait cycles to be inserted into the inpage access cycle during burst access. They are valid only for burst cycles. W11 W10 W09 W08 0 0 0 0 Auto-wait cycle 0 0 0 0 1 Auto-wait cycle 1 ... 1 1 Inpage access wait cycle ... 1 1 Auto-wait cycle 15 If the same value is set for the first access wait cycle and inpage access wait cycle, the access time for the address in each access cycle is not the same. (This is because the inpage access cycle contains an address output delay.) [Bits 7,6] W07, 06 (Read → Write Idle Cycle) The read → write idle cycle is set to prevent collision of read data and write data on the data bus when a write cycle follows a read cycle. During an idle cycle, all chip select signals are negated and the data terminals maintain the high impedance state. If a write cycle follows a read cycle or an access operation to another chip select area occurs after a read cycle, the specified idle cycle is inserted. Read → write idle cycles W07 W06 0 0 0 cycle 0 1 1 cycle 1 0 2 cycles 1 1 3 cycles [Bits 5 and 4] W05, 04 (Write Recovery Cycle) The write recovery cycle is set if a device that limits the access period after write access is to be controlled. During a write recovery cycle, all chip select signals are negated and the data pins maintain the high impedance state. If the write recovery cycle is set to "1" or more, a write recovery cycle is always inserted after write access. W05 W04 Write recovery cycles 0 0 0 cycle 0 1 1 cycle 1 0 2 cycles 1 1 3 cycles 177 CHAPTER 4 EXTERNAL BUS INTERFACE [Bit 3] W03 (WR0 to WR1 Output Timing Selection) The WR0 to WR1 output timing setting selects whether to use write strobe output as an asynchronous strobe or synchronous write enable. The asynchronous strobe setting corresponds to normal memory/IO. The synchronous enable setting corresponds to clock-synchronized memory/IO (such as the memory in an ASIC). W03 WR0 to WR1 output timing selection 0 MCLK synchronous write enable output (valid from AS=L) 1 Asynchronous write strobe output (normal operation) If synchronous write enable (W03 bit of AWR is "0") is used, operations are as follows: • The timing of synchronous write enable output assumes that the output is captured by the rising edge of MCLK output of an external memory access clock. This timing is different from the asynchronous strobe output timing. • The WR0 to WR1 terminal output asserts synchronous write enable output at the timing at which AS pin output is asserted. For a write to an external bus, the synchronous write enable output is L. For a read from an external bus, the synchronous write enable output is "H". • Write data is output from the external data output pin at the clock cycle at which synchronous write enable output is asserted. • Read strobe output (RD) functions as an asynchronous read strobe regardless of the setting of the WR0 to WR1 output timing. Use it as is for controlling the data I/O direction. If synchronous write enable output is used, the following restrictions apply: Do not make the following additional wait settings: • CS → RD/WR setup (Always set "0" for the W01 bit of AWR) • • Do not make the following access type settings (TYPE3-0 bits in the ACR register (bits 3 to "0")) • • Address/data multiplex bus setting (Always set "0" for the TYPE2 bit in the ACR register) Setting to use WR0 to WR1 as a write strobe (Always set "0" for the TYPE1 bit of ACR) • • First access wait cycle setting (Always set 0000B for the W15 to W12 bits of AWR) RDY input enable setting (Always set "0" for the TYPE0 bit of ACR) For synchronous write enable output, always set "1" (00B for bits BST1 to 0 bits of ACR) as the burst length. [Bit 2] W02 (Address → CS Delay) The address → CS delay setting is made when a certain type of setup is required for the address when CS falls or CS edges are needed for successive accesses to the same chip select area. Set the address and set the delay from AS output to CS0 to CS3 output. Address → CS delay W02 178 0 Delay 1 No delay If no delay is selected by setting "0", assertion of CS0 to 3 starts at the same timing that AS is asserted. If, at this point, successive accesses are made to the same chip select area, assertion of CS0 to CS3 without change between two access operations may continue. If delay is specified by selecting "1", assertion of CS0 to CS3 starts when the external memory clock MCLK output rises. If, at this point, successive accesses are made to the same chip select area, CS0 to CS3 are negated at a timing between two access operations. If CS delay is selected, one setup cycle is inserted before asserting the read/write strobe after assertion of the delayed CS (operation is the same as the CS → RD/WR setup setting of W01). The address → CS delay setting works for DACK signal (basic mode) output to the same area in the same way. DACK output in basic mode has the same waveforms as those of CS output to the same area. [Bit 1] W01 (CS → RD/WR Setup Extension Cycle: CS → RD/WR setup) The CS → RD/WR setup extension cycle is set to extend the period before the read/write strobe is asserted after CS is asserted. At least one setup extension cycle is inserted before the read/write strobe is asserted after CS is asserted. CS → RD/WR setup delay cycle W01 0 0 cycle 1 1 cycle If 0 cycle is selected by setting "0", RD/WR0 to WR1/WR are output at the earliest when external memory clock MCLK output rises just after CS is asserted. WR0 to WR1 may be delayed one cycle or more depending on the internal bus state. If 1 cycle is selected by setting "1", RD/WR0 to WR1 are always output 1 cycle or more later. When successive accesses are made within the same chip select area without negating CS, a setup extension cycle is not inserted. If a setup extension cycle for determining the address is required, set the W02 bit and insert the address → CS delay. Since CS is negated for each access operation, the setup extension cycle is enabled. If the CS delay set by W02 is inserted, this setup cycle is always enabled regardless of the setting of the W01 bit. [Bit 0] W00 (RD/WR → CS Hold Extension Cycle: RD/WR → CS Hold Cycle) The RD/WR → CS hold extension cycle is set to extend the period before negating CS after the read/ write strobe is negated. One hold extension cycle is inserted before CS is negated after the read/write strobe is negated. RD/WR → CS hold extension cycle W00 0 0 cycle 1 1 cycle If 0 cycle is selected by setting "0", CS0 to CS3 are negated after the hold delay after it starts on the rising edge of external memory clock MCLK output after RD/WR0 to WR1 are negated. If 1 cycle is selected by setting "1", CS0 to CS3 are negated one cycle later. When making successive accesses within the same chip select area without negating CS, the hold extension 179 CHAPTER 4 EXTERNAL BUS INTERFACE cycle is not inserted. If a hold extension cycle for determining the address is required, set the W02 bit and insert the address → CS delay. Since CS is negated for each access operation, this hold extension cycle is enabled. 180 4.2.4 IOWR0 to IOWR3 (I/O Wait Registers for DMAC) This section describes the I/O wait registers for DMAC in detail. ■ Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR3) The configuration of IOWR0 to IOWR3 is shown below: IOWR0 Initial value Access 00000678H 31 30 29 28 27 26 25 24 at INIT at RST RYE0 HLD0 WR01 WR00 IW03 IW02 IW01 IW00 xxxxxxxxB xxxxxxxxB IOWR1 00000679H RYE1 HLD1 WR11 WR10 IW13 IW12 IW11 IW10 xxxxxxxxB xxxxxxxxB R/W IOWR2 0000067AH 15 14 13 12 11 10 9 8 RYE2 HLD2 WR21 WR20 IW23 IW22 IW21 IW20 xxxxxxxxB xxxxxxxxB R/W IOWR3 0000067BH 15 14 13 12 11 10 9 8 RYE3 HLD3 WR31 WR30 IW33 IW32 IW31 IW30 xxxxxxxxB xxxxxxxxB R/W 23 22 21 20 19 18 17 R/W 16 Note : The MB91F355A/355A/354A/F356B/F357B series have IOWR3 only. These registers are used to set various waits for DMA fly-by access. [Bits 31, 23, 15] RYE0,1,2 (RDY function setting: ReadY Enable 0,1,2,3) These bits set the wait control using RDY for channels 0 to 2 at DMA fly-by access. RYEn RDY function setting 0 Disable RDY input for I/O access. 1 Enable RDY input for I/O access. When "1" is set, wait insertion by the RDY pin can be performed during fly-by transfer on the relevant channel. IOWR and IORD are extended until the RDY pin is enabled. Also, RD/WR0-WR3/WR on the memory side are extended synchronously. If the chip select area of the fly-by transfer destination is set to RDY-enabled in the ACR register, wait insertion by the RDY pin can be performed regardless of the RYEn bit of IOWR side. When the chip select area of the fly-by transfer destination is set to RDY-disabled in the ACR register, wait insertion by the RDY pin can only be performed during fly-by access if the area is set to RDY-enabled by the RYEn bit on the IOWR side. 181 CHAPTER 4 EXTERNAL BUS INTERFACE [Bits 30, 22, 14] HLD0,1,2 (Hold Wait Setting: HoLD wait control) These bits control the hold cycle of the read strobe signal on the transfer source access side during DMA fly-by access. HLDn Hold wait setting 0 Do not insert a hold extension cycle. 1 Insert a hold extension cycle to extend the read cycle by one cycle. If "0" is set, the read strobe signal (RD for memory → I/O and IORD for I/O → memory) and the write strobe signal (IOWR for memory → I/O and WR0 to WR3 and WR for I/O → memory) on the transfer source access side are outputted at the same timing. If "1" is set, the read strobe signal is outputted one cycle longer than the write strobe signal to secure a hold time for data at the transfer source access side when sending it to the transfer destination. [Bits 29 to 28, 21 to 20, 13 to 12] WR0,1,2 (I/O Idle Cycle setting: I/O Idle Wait) These bits set the idle cycle for continuous I/O access during DMA fly-by access. WRn1 WRn0 Setting of the I/O idle cycle 0 0 0 cycle 0 1 1 cycle 1 0 2 cycles 1 1 3 cycles If one or more cycles is set as the number of idle cycles, cycles equal to the number specified are inserted after I/O access during DMA fly-by access. During the idle cycles, all CS and strobe output is negated and the data pin is set to the high impedance state. [Bits 27 to 24, 19 to 16, 11 to 8] IW03 to 00, IW13 to 10, IW23 to 20 (I/O Wait Cycle: I/O access Wait) These bits set the auto-wait cycle for I/O access during DMA fly-by access. IWn3 IWn2 IWn1 IWn0 0 0 0 0 0 cycle 0 0 0 1 1 cycle ... 1 1 I/O wait cycle ... 1 1 15 cycles Because data is synchronized between the transfer source and transfer destination, the I/O side setting of the IWnn bits and the wait setting for the fly-by transfer destination (such as memory), whichever is larger, is used as the number of wait cycles to be inserted. Consequently, more wait cycles than specified by the IWnn bits may be inserted. 182 4.2.5 Chip Select Enable Register (CSER) This section describes the chip select enable register in detail. ■ Configuration of the Chip Select Enable Register (CSER) The configuration of CSER is shown below: Initial value 00000680H 31 30 29 28 27 26 25 24 at INIT at RST CSE7 CSE6 CSE5 CSE4 CSE3 CSE2 CSE1 CSE0 00000001B 00000001B Access R/W This register enables or disables each chip select area. [Bits 31 to 24] CSE[7:0] (Chip Select Area Enable: Chip select enable 0-7) These bits are the chip select area enable bits for CS0 to CS7. The initial value is 00000001B, which enables only the CS0 area. When "1" is written, a chip select area operates according to the settings of ASR0 to 7, ACR0 to 7, and AWR0 to 7. Before setting this register, be sure to make all settings required for the corresponding chip select areas. CSE[7:0] Area control 0 Disable 1 Enable Table 4.2-2 lists the CSE bits and corresponding CSKs. Table 4.2-2 CSE Bits and Corresponding CSKs CSE bit Corresponding CSn Bit [24]:CSE0 CS0 Bit [25]:CSE1 CS1 Bit [26]:CSE2 CS2 Bit [27]:CSE3 CS3 Bit [28]:CSE4 CS4 Bit [29]:CSE5 CS5 Bit [30]:CSE6 CS6 Bit [31]:CSE7 CS7 183 CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.6 TCR (Terminal and Timing Control Register) This section describes the terminal and timing control register in detail. ■ Configuration of the Terminal and Timing Control Register (TCR) The configuration of the TCR is shown below: Initial value 7 00000683H 6 5 BREN PSUS PCLR 4 3 2 Reserved Reserved Reserved 1 0 at INIT at RST RDW1 RDW0 00000000B 0000xxxxB Access R/W This register controls all functions related to the external bus interface controller, such as setting of shared pin functions and timing control. [Bit 7] BREN (BRQ input enable: BRQ enable) This bit enables BRQ pin input and external bus sharing. BREN BRQ input enable setting 0 No bus sharing by BRQ/BGRNT. BRQ input is disabled. 1 Bus sharing by BRQ/BGRNT. BRQ input is enabled. In the initial state (0), BRQ input is ignored. When "1" is set, the bus is made open (control with high impedance) and BGRNT is activated ("L" level is output) when the bus is ready to be made open after the BRQ input becomes "H" level. [Bit 6] PSUS (Prefetch suspend: Prefetch SUSpend) This bit controls temporary stopping of prefetch to all areas. PSUS Prefetch control 0 Enable prefetch 1 Suspend prefetch. If "1" is set, no new prefetch operation is performed before "0" is written. Since during this time the contents of the prefetch buffer are not deleted unless the error to a prefetch buffer occurs, clear the prefetch buffer using the PCLR bit function (bit 5) before restarting prefetch. 184 [Bit 5] PCLR (Prefetch buffer all clear: Prefetch buffer CleaR) This bit completely clears the prefetch buffer. PCLR Prefetch buffer control 0 Normal state 1 Clear the prefetch buffer. If "1" is written, the prefetch buffer is cleared completely. When clearing is completed, the bit value automatically returns to "0". Interrupt (set to "1") the prefetch by the PSUS bit and then clear the buffer (It is also possible to write 11B to both the PSUS and PCLR bits). [Bits 4 to 2] Reserved (Reserved bit) This bits are reserved. Be sure to set it to "0". [Bits 1 to 0] RDW[1:0] (Wait cycle reduction: ReDuce Wait cycle) These bits instruct all chip select areas and fly-by I/O channels to reduce only the number of auto-wait cycles in the auto-access cycle wait settings uniformly while the AWR register settings are retained unchanged. The settings for idle cycles, recovery cycles, setup cycles, and hold cycles are not affected. These bits are not functional for the SDRAM control area. RDW1 RDW0 Wait cycle reduction 0 0 Normal wait (AWR0-7 settings) 0 1 1/2 (1-bit shift to the right) of the AWR0 to 3 settings 1 0 1/4 (2-bit shift to the right) of the AWR0 to 3 settings 1 1 1/8 (3-bit shift to the right) of the AWR0 to 3 settings The purpose of this function is to prevent an excessive access cycle wait during operation on a low-speed clock (for example, when the base clock is switched to low speed or the frequency division ratio setting of the external bus clock is large). To reset the wait cycle in these cases, each of the AWRs must usually be rewritten one at a time. However, when the RDW1/0 bit function is used, the access cycle wait is reduced for all of the AWRs in a single operation while all of the other high-speed clock settings in each register are retained. Before returning the clock to high speed, be sure to reset the RDW1/0 bits to 00B. 185 CHAPTER 4 EXTERNAL BUS INTERFACE 4.3 Setting Example of the Chip Select Area In the external bus interface, a total of four chip select areas can be set. The address space of each area can be placed, in units of a minimum of 64K bytes, anywhere in the 4 GB space using ASR0 to 3 (Area Select Registers) and ACR0 to 3 (Area Configuration Registers). When bus access is made to an area specified by these registers, the corresponding chip select signals (CS0 to CS3) are activated (L output) during the access cycle. ■ Example of Setting ASRs and ASZ[3:0] 1. ASR1=0003H ACR1 → ASZ[3:0]=0000B: Chip select area 1 is assigned to 00030000H to 0003FFFFH. 2. ASR2=0FFCH ACR2 → ASZ[3:0]=0010B: Chip select area 2 is assigned to 0FFC0000H to 10000000H. 3. ASR3=0011H ACR3 → ASZ[3:0]=0100B: Chip select area 3 is assigned to 00100000H to 00200000H. Since at this point 1M bytes is set for bits ASZ[3:0] of the ACR, the unit for boundaries 1M bytes and [19:16] of ASR3 are ignored. Before there is any writing to ACR0 after a reset, 00000000H to FFFFFFFFH is assigned to chip select area 0. Note: Set the chip select areas so that there is no overlap. Figure 4.3-1 shows the chip select area. 186 Figure 4.3-1 Chip Select Area (Initial value) 00000000H (Example) 00000000H 00030000H Area 1 64 KB Area 3 1 MB Area 2 256 KB 00040000H Area 0 00100000H 00200000H 0FFC0000H 0FFFFFFFH FFFFFFFFH FFFFFFFFH 187 CHAPTER 4 EXTERNAL BUS INTERFACE 4.4 Byte Ordering (Endian) and Bus Access This section describes byte ordering and bus access. ■ Overview of Byte Ordering Except for specific areas, FR family devices enable switching between the big endian and little endian methods for each chip select. 188 4.4.1 Relationship Between Data Bus Widths and Control Signals There is a one-to-one correspondence between the WR[3:0] control signals and the location of the bytes on the data bus regardless of the data bus width. This section summarizes the location of the bytes on the data bus used for the specified data bus width and the corresponding control signal for each bus mode. ■ Control Signals on the Ordinary Bus Interface Figure 4.4-1 shows the 16-bit bus width and 8-bit bus width control signals on the ordinary bus interface. Figure 4.4-1 Control Signals on the Ordinary Bus Interface a) 16-bit bus width b) 8-bit bus width Data bus Data bus Control signal Control signal WR0 WR0 WR1 (D23 to D16 are not used.) ■ Control Signals on the Time Division I/O Interface Figure 4.4-2 shows the 16-bit bus width and 8-bit bus width control signals on the time division I/O interface. Figure 4.4-2 Control Signals on the Time Division I/O Interface b) 8-bit bus width a) 16-bit bus width Data bus Output address Control signal Data bus Output address Control signal D31 A15 to 8 WR0 A7 to 0 WR1 A7 to 0 WR0 - - - D16 - - - - - - - - - - (D23 to 16 are not used) 189 CHAPTER 4 EXTERNAL BUS INTERFACE 4.4.2 Big Endian Bus Access Except for the CS0 area, the FR family can switch between the big endian method and little endian method for each chip select area. When the LEND bit of the ACR register is set to "0", the chip select area is treated as big endian. Normally, the FR family executes external bus access using big endian. ■ Big Endian Data Format Figure 4.4-3 shows the relationship between the internal register and external data bus based on the data format of word access (when the LD and ST instructions are executed). Figure 4.4-3 Word Access (When LD and ST Instructions Executed) Internal register External bus D31 AA D31 AA D23 D23 BB BB CC CC DD DD D15 D15 D7 D7 D0 D0 Figure 4.4-4 shows the relationship between the internal register and external data bus based on the data format of halfword access (when the LDUH and STH instructions are executed). Figure 4.4-4 Halfword Access (When LDUH and STH Instructions Executed) a) Output address low-order digits "00" Internal register External bus D31 D31 D31 D31 D23 D23 D23 D15 D15 D15 AA D23 b) Output address low-order digits "10" Internal register External bus BB D15 AA D7 D7 BB D0 190 D0 AA AA BB BB D7 D0 D7 D0 Figure 4.4-5 shows the relationship between the internal register and external data bus based on the data format of byte access (when the LDUB and STB instructions are executed). Figure 4.4-5 Byte Access (When LDUB and STB Instructions Executed) a) Output address low-order digits "00" Internal register b) Output address low-order digits "01" External bus Internal register External bus D31 D31 D31 c) Output address low-order digits "10" Internal register External bus d) Output address low-order digits "11" Internal register External bus D31 D31 D31 D31 D31 D23 D23 D23 D23 D23 D15 D15 D15 AA D23 D23 D23 AA D15 D15 D15 D15 D15 AA D7 D7 D7 AA D0 D7 D7 AA D0 D0 D7 D7 AA D0 D0 D7 AA D0 D0 AA D0 191 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Bus Width of Big Endian Data Figure 4.4-6 shows the data bus width for a bus width of 16 bits. Figure 4.4-6 Data Bus Width for 16-bit Bus Width Internal register External bus Output address low-order digits "00" "10" AA CC BB DD D31 D31 AA D23 D15 BB read/write D23 CC D07 DD Figure 4.4-7 shows the data bus width for a bus width of 8 bits. Figure 4.4-7 Data Bus Width for 8-bit Bus Width Internal register External bus Output address low-order digits "00" "01" "10" read/write D31 AA BB CC AA D23 BB D15 CC D07 DD 192 "11" DD D31 ■ External Bus Access For big endian ordering for external bus access, the following items are arranged as illustrated later for bus widths of 16 and 8 bits and for word, halfword, and byte access: • Access byte location • Program address and output address • Bus access count : PA1/ PA0 Output A1/A0 : : : 1 4 : Two low-order bits of the address specified by the program Two low-order bits of the output address Location of initial byte of the output address Data byte location to be accessed Bus access count The FR family does not detect misalignment errors. Therefore, for word access, the lower two bits of the output address are always "00" regardless of whether "00", "01", "10", or "11" is specified as the lower two bits by the program. For halfword access, the lower two bits of the output address are "00" if the lower two bits specified by the program are "00" or "01", and are "10" if "10" or "11". 193 CHAPTER 4 EXTERNAL BUS INTERFACE ● 16-bit bus width Figure 4.4-8 shows the access operations for a bus width of 16 bits. Figure 4.4-8 16-bit Bus Width Access (A) Word access (a) PA1/PA0="00" (b) PA1/PA0="01" (c) PA1/PA0="10" (1) Output A1/A0="00" (1) Output A1/A0="00" (1) Output A1/A0="00" (2) Output A1/A0="10" (2) Output A1/A0="10" (2) Output A1/A0="10" (d) PA1/PA0="11" (1) Output A1/A0="00" (2) Output A1/A0="10" LSB MSB (1) 00 01 (1) 00 01 (1) 00 01 (1) 00 01 (2) 10 11 (2) 10 11 (2) 10 11 (2) 10 11 16-bit (B) Halfword access (a) PA1/PA0="00" (b) PA1/PA0="01" (c) PA1/PA0="10" (1) Output A1/A0="00" (1) Output A1/A0="00" (1) Output A1/A0="10" (1) 00 01 10 11 (1) 00 01 10 11 (1) 00 01 10 11 (d) PA1/PA0="11" (1) Output A1/A0="10" (1) 00 01 10 11 (C) Byte access (a) PA1/PA0="00" (b) PA1/PA0="01" (c) PA1/PA0="10" (1) Output A1/A0="00" (1) Output A1/A0="01" (1) Output A1/A0="10" (1) 194 00 01 10 11 (1) 00 01 10 11 (1) 00 01 10 11 (d) PA1/PA0="11" (1) Output A1/A0="11" (1) 00 01 10 11 ● 8-bit bus width Figure 4.4-9 shows the access operations for bus width of 8 bits. Figure 4.4-9 8-bit Bus Width Access (A) Word access (a) PA1/PA0="00" (1) Output A1/A0="00" (2) Output A1/A0="01" (3) Output A1/A0="10" (4) Output A1/A0="11" (b) PA1/PA0="01" (1) Output A1/A0="00" (2) Output A1/A0="01" (3) Output A1/A0="10" (4) Output A1/A0="11" (c) PA1/PA0="10" (1) Output A1/A0="00" (2) Output A1/A0="01" (3) Output A1/A0="10" (4) Output A1/A0="11" (d) PA1/PA0="11" (1) Output A1/A0="00" (2) Output A1/A0="01" (3) Output A1/A0="10" (4) Output A1/A0="11" MSB LSB (1) 00 (1) 00 (1) 00 (1) 00 (2) 01 (2) 01 (2) 01 (2) 01 (3) 10 (3) 10 (3) 10 (3) 10 (4) 11 (4) 11 (4) 11 (4) 11 8bit (B) Halfword access (a) PA1/PA0="00" (1) Output A1/A0="00" (2) Output A1/A0="01" (b) PA1/PA0="01" (1) Output A1/A0="00" (2) Output A1/A0="01" (c) PA1/PA0="10" (1) Output A1/A0="10" (2) Output A1/A0="11" (d) PA1/PA0="11" (1) Output A1/A0="10" (2) Output A1/A0="11" (1) 00 (1) 00 00 00 (2) 01 (2) 01 01 01 10 10 (1) 10 (1) 10 11 11 (2) 11 (2) 11 (C) Byte access (a) PA1/PA0="00" (1) Output A1/A0="00" (1) (b) PA1/PA0="01" (1) Output A1/A0="01" 00 01 (1) (c) PA1/PA0="10" (1) Output A1/A0="10" (d) PA1/PA0="11" (1) Output A1/A0="11" 00 00 00 01 01 01 10 10 10 10 11 11 (1) 11 (1) 11 195 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Example of Connection with External Devices Figure 4.4-10 shows an example of connection between the MB91350A device and external devices. Figure 4.4-10 Connection With External Devices This LSI D31 D23 to WR0 to WR1 D24 D16 Note : For 16/8-bit devices, use the data bus on 0 1 D15 D08 D07 D00 0 D07 D00 8-bit device 16-bit device (low-order 1 bit of the address 0/1) 196 4.4.3 Little Endian Bus Access Except for the CS0 area, the FR family can switch between the big endian method and little endian method for each chip select area. When the LEND bit of the ACR register is set to "1", the chip select area is treated as little endian. ■ Overview of Little Endian Method Little endian bus access of the FR family is implemented by using the bus access operation used for the big endian method. Basically, the order of output addresses and control signal output are the same as those for the big endian method and the locations of the bytes on the data bus are swapped in accordance with the bus width. Note that, when a connection is made, the big endian area and the little endian area must be kept physically separate. • The order of addresses that are output is the same for little endian and big endian. • Word access The byte data on the MSB side for big endian address A1-0=00 becomes byte data on the LSB side when the little endian method is used. For a word access, the locations of all four bytes in the word are reversed. • Halfword access The byte data on the MSB side for the big endian address A0 becomes byte data on the LSB side when the little endian method is used. For halfword access, the byte locations of 2 bytes in the halfword are reversed. • Byte access There is no difference between little endian and big endian. • There is no difference between the little and big endian methods regarding the data bus and control signals used for bus widths of 16 and 8 bits. [Restrictions on the Little Endian Area] • If prefetch is enabled for a little endian area, always use word access to access the area. If data read to the prefetch buffer is accessed with any length other than word length, the correct endian conversion is not performed and the wrong data will be read. The reason is hardware restrictions related to the endian conversion mechanism. • Do not place any instruction code in a little endian area. 197 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Little Endian Data Format Figure 4.4-11 shows the relationship between the internal register and external data bus based on the data format of word access (when the LD and ST instructions are executed). Figure 4.4-11 Word Access (When LD and ST Instructions Executed) Internal register External bus D31 AA DD BB CC CC BB DD AA D31 D23 D23 D15 D15 D7 D7 D0 D0 Figure 4.4-12 shows the relationship between the internal register and external data bus based on the data format of halfword access (when the LDUH and STH instructions are executed). Figure 4.4-12 Halfword Access (When LD and ST Instructions Executed) a) Output address low-order digits 00 Internal register D31 b) Output address low-order digits 10 Internal register External bus BB D23 External bus D31 D31 D31 D23 D23 D23 D15 D15 AA D15 AA D7 BB BB AA D7 D7 D7 BB D0 D15 AA D0 D0 D0 Figure 4.4-13 shows the relationship between the internal register and external data bus based on the data format of byte access (when the LDUB and STB instructions are executed). Figure 4.4-13 Byte Access (When LDUB and STB Instructions Executed) a) Output address low-order digits 00 Internal External register bus D31 b) Output address low-order digits 01 Internal External register bus D31 D31 D23 D23 c) Output address low-order digits 10 Internal External register bus d) Output address low-order digits 11 Internal External register bus D31 D31 D31 D31 D31 D23 D23 D23 D23 D23 D15 D15 D15 D15 D15 D7 D7 AA D23 AA D15 D15 D15 AA D7 D7 D7 AA D0 198 D7 D7 AA D0 D0 AA D0 D0 D7 AA D0 D0 AA D0 ■ Bus Width of Little Endian Data Figure 4.4-14 shows the data bus width for a bus width of 16 bits. Figure 4.4-14 Data Bus Width for 16-bit Bus Width Internal register Output address low-order digits External bus "00" "10" D31 AA read/write D23 BB D15 CC D07 DD DD BB CC AA D31 D23 Figure 4.4-15 shows the data bus width for a bus width of 8 bits. Figure 4.4-15 Data Bus Width for 8-bit Bus Width Internal register Output address low-order digits External bus "00" "01" D31 D23 AA read/write DD CC "10" "11" BB AA D31 BB D15 CC D07 DD 199 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Connection Between the MB91350A Device and the Endian Areas Figure 4.4-16 shows connection between the MB91350A device and endian. Figure 4.4-16 Connection Between MB91350A Device and Endian 16-bit bus width This LSI D31 to D24 WR0 D23 to D16 WR1 0 1 D15 D08 D07 D00 big endian area 1 0 D15 D08 D07 D00 little endian area 8-bit bus width This LSI D31 to D24 WR0 D07 D00 big endian area 200 D07 D00 little endian area 4.4.4 External Access This section describes the relationship between the internal register and external data bus based on the byte ordering (endian method) and the bus width. ■ Word Access External access using word access is shown below: Big endian mode 16-bit bus width Internal External Reg terminal address: "0" "2" D31 D31 AA AA CC BB BB DD Little endian mode Control terminal WR0 Internal External Reg terminal address: "0" "2" D31 WR1 WR0 CC AA WR1 CC DD DD D00 (1) (1) Control terminal AA BB CC DD (2) Internal External Reg terminal address: "0" "1" "2" "3" D31 D31 AA D00 (2) Internal External Reg terminal address: "0" "1" "2" "3" WR0 D31 AA DD CC BB AA Control terminal WR0 D24 D24 BB BB CC CC DD DD D00 DD BB D16 D16 CC D31 D31 BB D16 8-bit bus width AA Control terminal (1) (2) (3) (4) D00 (1) (2) (3) (4) 201 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Halfword Access External access using halfword access is shown below: Big endian mode 16-bit bus width Internal External Reg terminal address: "0" D31 D31 Little endian mode Control terminal Internal External Reg terminal address: "0" D31 AA WR0 BB WR1 D31 WR0 AA WR1 AA AA BB BB D00 D00 (1) (1) Internal External Reg terminal address: "2" D31 D31 Control terminal CC WR0 DD WR1 Internal External Reg terminal address: "2" D31 D31 D16 DD WR0 CC WR1 DD D00 (1) (1) Internal External Reg terminal address: "0" "1" D31 D31 AA BB D24 Control terminal WR0 Internal External Reg terminal address: "0" "1" D31 D31 BB AA D24 AA Control terminal WR0 AA BB BB D00 (1) D00 (2) Internal External Reg terminal address: "2" "3" D31 D31 CC DD D24 D00 (1) Control terminal WR0 (2) Internal External Reg terminal address: "2" "3" D31 D31 CC DD D24 CC CC DD D00 DD CC D00 D00 Control terminal D16 CC DD D00 D00 (1) 202 BB D16 D16 8-bit bus width Control terminal (2) D00 (1) (2) Control terminal WR0 ■ Byte Access External access using byte access is shown below: Big endian mode 16-bit bus width Internal External Reg terminal address: "0" D31 D31 AA Little endian mode Control terminal WR0 Internal External Reg terminal address: "0" D31 D31 AA Control terminal WR0 D16 D16 AA AA D00 D00 (1) (1) Internal External Reg terminal address: "1" D31 D31 BB Control terminal Internal External Reg terminal address: "1" D31 D31 BB WR1 Control terminal WR1 D16 D16 BB BB D00 D00 (1) (1) Internal External Reg terminal address: "2" D31 D31 CC Control terminal WR0 Internal External Reg terminal address: "2" D31 D31 CC Control terminal WR0 D16 D16 CC CC D00 D00 (1) (1) Internal External Reg terminal address: "3" D31 D31 DD Control terminal Internal External Reg terminal address: "3" D31 D31 DD WR1 D16 Control terminal WR1 D16 DD DD D00 D00 (1) (1) 203 CHAPTER 4 EXTERNAL BUS INTERFACE Big endian mode 8-bit bus width Internal External Reg terminal address: "0" D31 D31 AA Little endian mode Control terminal WR0 Internal External Reg terminal address: "0" D31 D31 AA D24 WR0 D24 AA AA D00 D00 (1) Internal External Reg terminal address: "1" D31 D31 BB (1) Control terminal WR0 Internal External Reg terminal address: "1" D31 D31 BB D24 Control terminal WR0 D24 BB BB D00 D00 (1) Internal External Reg terminal address: "2" D31 D31 CC (1) Control terminal WR0 Internal External Reg terminal address: "2" D31 D31 CC D24 Control terminal WR0 D24 CC CC D00 D00 (1) Internal External Reg terminal address: "3" D31 D31 DD (1) Control terminal WR0 Internal External Reg terminal address: "3" D31 D31 DD D24 D24 DD DD D00 D00 (1) 204 Control terminal (1) Control terminal WR0 4.5 Ordinary Bus Interface For an ordinary bus interface, the two clock cycles required for both read access and write access become the basic bus cycle. ■ Basic Timing (For Successive Accesses) (TYP[3:0]=0000B,AWR=0008H) Figure 4.5-1 shows the basic timing for successive accesses. Figure 4.5-1 Basic Timing For Successive Accesses MCLK A[23:0] #2 #1 AS CSn RD READ D[31:16] #1 #2 WRn WRITE D[31:16] #1 #2 • AS is asserted for one cycle in the bus access start cycle. • A[23:0] continues to output the address of the location of the start byte in word/halfword/byte access from the bus access start cycle to the bus access end cycle. • If the W02 bit of the AWR[0:3] registers is "0", CS0 to CS3 are asserted at the same timing as AS. For successive accesses, CS0 to CS3 are not negated. If the W00 bit of the AWR register is "0", CS0 to CS3 are negated after the bus cycle ends. If the W00 bit is "1", CS0 to CS3 are negated one cycle after bus access ends. • RD and WR0 to WR1 are asserted from the 2nd cycle of the bus access. Negation occurs after the wait cycle of bits W15 of W12 for the AWR register is inserted. The timing of asserting RD and WR0 to WR1 can be delayed by one cycle by setting the W01 bit of the AWR register to "1". • For read access, D[31:0] is read when MCLK rises in the cycle in which the wait cycle ended after RD was asserted. • For write access, data output to D[31:0] starts at the timing at which WR0 to WR1 are asserted. 205 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Read → Write Timing (TYP[3:0]=0000B,AWR=0048H) Figure 4.5-2 shows the read → write timing. Figure 4.5-2 Read → Write Timing Read Idle Write MCLK A[23:0] AS CSn RD WRn D[31:16] 206 • Setting of the W07/W06 bits of the AWR register enables [0:3] idle cycles to be inserted. • Settings in the CS area on the read side are enabled. • This idle cycle is inserted if the next access after a read access is write access or access to another area. ■ Write → Write Timing (TYP[3:0]=0000B,AWR=0018H) Figure 4.5-3 shows the write → write timing. Figure 4.5-3 Write → Write Timing Read Write recovery Write MCLK A[23:0] AS CSn WRn D[31:16] • Setting of the W05/W04 bits of the AWR register enables 0-3 write recovery cycles to be inserted. • After all of the write cycles, recovery cycles are generated. • Write recovery cycles are also generated if write access is divided into phases for access with a bus width wider than that specified. 207 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Auto-Wait Timing (TYP[3:0]=0000B,AWR=2008H) Figure 4.5-4 shows the auto-wait timing. Figure 4.5-4 Auto-Wait Timing Basic cycle Wait cycle MCLK A[23:0] AS CSn RD D[31:16] WRn D[31:16] Setting of the W15-12 bits (first wait cycles) of the AWR register enables 0-15 auto-wait cycles to be set. In Figure 4.5-4 , two auto-wait cycles are inserted, making a total of four cycles for access. If auto-wait is set, the minimum number of bus cycles is 2 cycles + (first wait cycles). For a write operation, the minimum number of bus cycles may be still longer depending on the internal state. 208 ■ External Wait Timing (TYP[3:0]=0001B,AWR=2008H) Figure 4.5-5 shows the external wait timing. Figure 4.5-5 External Wait Timing Basic cycle 2 auto-wait cycles Wait cycle by RDY MCLK A[23:0] AS CSn RD D[31:16] WRn D[31:16] Release RDY Wait • Setting "1" for the TYP0 bit of the ACR register and enabling the external RDY input pin enables external wait cycles to be inserted. In the figure above, because waiting using the auto-wait cycle is enabled, the section of the RDY pin indicated by hatching is disabled. The value of the RDY input pin is decided following the last cycle of the auto-wait cycle. Also, after a wait cycle is completed, the value of the RDY input pin is disabled until the next access cycle starts. 209 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Synchronous Write Enable Output Timing (TYP[3:0]=0000B,AWR=0000H) Figure 4.5-6 shows the synchronous write enable output timing. Figure 4.5-6 Synchronous Write Enable Output Timing MCLK A[23:0] #1 #2 AS CSn RD Read D[31:16] #1 #2 WRn Write D[31:16] #1 #2 • If synchronous write enable output is enabled (If the W03 bit of the AWR is "1"), operation is as follows. • WR0 to WR1 pin output asserts synchronous write enable output at the timing at which AS pin output is asserted. For a write to an external bus, the synchronous write enable output is L. For a read from an external bus, the synchronous write enable output is "H". • Write data is outputted from the external data output pin at the clock cycle at which synchronous write enable output is asserted. • Read strobe output (RD) functions as an asynchronous read strobe regardless of the setting of WR0 to WR3 and WR output timing. Use it as it is for controlling the data I/O. If synchronous write enable output is used, the following restrictions apply: Do not set the following additional wait because the timing for synchronous write enable output becomes meaningless: - CS → RD/WR setup (Always write "0" to the W01 bit of AWR) - First wait cycle setting (Always write "0000" to bits W15 of W12 of AWR) Do not set the following access types (TYPE3 to TYPE0 bits (Bit 3 to Bit 0) in the ACR register) because the timing for synchronous write enable output becomes meaningless: - Multiplex bus setting (Always write "0" to the TYPE2 bit of ACR) - RDY input enable setting (Always write "0" to the TYPE0 bit of ACR) For synchronous write enable output, always set the burst length to "1" (set bits BST1 and BST0 to "0"). 210 ■ CS Delay Setting (TYP[3:0]=0000B, AWR=000CH) Figure 4.5-7 shows setting of a CS delay. Figure 4.5-7 Setting of CS Delay MCLK A[23:0] AS CSn RD READ D[31:16] WRn WRITE D[31:16] • If the W02 bit is "1", assertion starts in the cycle following the cycle in which AS is asserted. For successive accesses, a negation period is inserted. 211 CHAPTER 4 EXTERNAL BUS INTERFACE ■ Setting of CS → RD/WR Setup and of RD/WR → CS Hold (TYP[3:0]=0000B,AWR=000BH) Figure 4.5-8 shows setting of the CS → RD/WR setup and setting of RD/WR → CS hold. Figure 4.5-8 Setting of CS → RD/WR Setup and RD/WR → CS Hold MCLK A[23:0] AS CSn CS->RD/WR Delay RD/WR->CS Delay RD READ D[31:16] WRn WRITE D[31:16] 212 • Setting "1" for the W01 bit of the AWR register enables the CS → RD/WR setup delay to be set. Set this bit to extend the period between chip select assertion and read/write strobe. • Setting "1" for the W00 bit of the AWR register enables the RD/WR → CS hold delay to be set. Set this bit to extend the period between read/write strobe negation and chip select negation. • The CS → RD/WR setup delay (W01 bit) and RD/WR → CS hold delay (W00 bit) can be set independently. • When making successive accesses within the same chip select area without negating the chip select, neither a CS → RD/WR setup delay nor an RD/WR → CS hold delay is inserted. • If a setup cycle for determining the address or a hold cycle for determining the address is needed, set "1" for the address → CS delay setting (W02 bit of the AWR register). ■ DMA Fly-by Transfer (I/O → Memory) (TYP[3:0] = 0000B, AWR = 0008H, and IOWR = 51H) Figure 4.5-9 shows DMA fly-by transfer (I/O → memory). • No wait setting in memory side Figure 4.5-9 DMA Fly-by Transfer (I/O → Memory) Basic cycle I/O wait I/O wait I/O idle cycle cycle cycle Basic cycle I/O wait I/O hold cycle wait MCLK A[23:0] AS CSn WRn D[31:16] IORD • Setting "1" for the HLD bit of the IOWR0 to 3 registers enables the I/O read cycle to be extended by one cycle. • Setting bits IW[3:0], IW[13:10], and IW[23:20] of the IOWR0 to 3 registers enables 0 to 15 wait cycles to be inserted. • If wait is also set on the memory side (AWR[15:12] is not "0"), the larger value is used as the wait cycle after comparison with the I/O wait (IW[3:0], IW[13:10], and IW[23:20] bits). 213 CHAPTER 4 EXTERNAL BUS INTERFACE ■ DMA Fly-by Transfer (Memory → I/O) (TYP[3:0] = 0000B, AWR = 0008H, and IOWR = 51H) Figure 4.5-10 shows DMA fly-by transfer (memory → I/O). • No wait setting in memory side Figure 4.5-10 DMA Fly-by Transfer (Memory → I/O) Basic cycle I/O wait I/O hold I/O idle cycle wait cycle Basic cycle I/O wait I/O hold cycle wait MCLK A[23:0] AS CSn RD D[31:16] IORD 214 • Setting "1" for the HLD bit of the IOWR0 to 3 registers enables the I/O read cycle to be extended by one cycle. • Setting the WR[1:0] bits of the IOWR0 to 3 registers enables 0 to 3 write recovery cycles to be inserted. • If the write recovery cycle is set to "1" or more, a write recovery cycle is always inserted after write access. • Setting bits IW[3:0], IW[13:10], and IW[23:20] of the IOWR0 to 3 registers enables 0 to 15 wait cycles to be inserted. • If wait is also set on the memory side (AWR[15:12] is not "0"), the larger value is used as the wait cycle after comparison with the I/O wait (IW[3:0], IW[13:10], and IW[23:20] bits). 4.6 Address/data Multiplex Interface This section describes setting of the address/data multiplex interface. ■ Without External Wait (TYP[3:0] = 0100B and AWR = 0008H) Figure 4.6-1 shows setting of the address/data multiplex interface when there is no external wait. Figure 4.6-1 Setting of Address/Data Multiplex Interface Without an External Wait MCLK A[23:0] address[23:0] AS CSn RD READ D[31:16] address[15:0] data[15:0] WR WRITE D[31:16] address[15:0] data[15:0] • Making a setting such as TYP[3:0]=01xxB in the ACR register enables the address/data multiplex interface to be set. • If the address/data multiplex interface is set, set 8 bits or 16 bits for the data bus width (DBW[1:0] bits). The 32-bit bus width is not supported. • In the address/data multiplex interface, the total of 3 cycles of 2 address output cycles + 1 data cycle becomes the basic number of access cycles. • In the address output cycle, AS is asserted as the output address latch enable signal. However, when CS → RD/WR setup delay (AWR[1]) is set to "0", the multiplex address output cycle consists of only one cycle as shown in the figure above. Since the address cannot be directly latched at the rising edge of AS, fetch the address at the rising edge for MCLK of the cycle in which AS is asserted (Low). • As with a normal interface, the address indicating the start of access is outputted to A[23:0] during the time division bus cycle. Use this address if you want to use an address more than 8/16 bits in the address/data multiplex interface. 215 CHAPTER 4 EXTERNAL BUS INTERFACE • As with the normal interface, auto-wait (AWR[15:12]), read → write idle cycle (AWR[7:6]), write recovery (AWR[5:4]), address → CS delay (AWR[2]), CS → RD/WR setup delay (AWR[1]), and RD/ WR → CS hold delay (AWR[0]) can be set. • In areas for which the address/data multiplex interface is set, set "1" (DBW[1:0]=00B) as the burst length. ■ With External Wait (TYP[3:0]=0101B, AWR=1008H) Figure 4.6-2 shows setting of the address/data multiplex interface with an external wait. Figure 4.6-2 Setting of Address/Data Multiplex Interface With an External Wait MCLK address[23:0] A[23:0] AS CSn RD READ D[31:16] data[15:0] address[15:0] WR WRITE D[31:16] address[15:0] data[15:0] Release RDY External wait • 216 Making a setting such as TYP[3:0]=01x1B in the ACR register enables RDY input in the address/data multiplex interface. ■ CS → RD/WR Setup (TYP[3:0] =0101B, AWR=100BH) Figure 4.6-3 shows setting of the CS → RD/WR setup. Figure 4.6-3 Setting of CS → RD/WR Setup MCLK A[23:0] address[23:0] AS CSn RD READ D[31:16] address[15:0] data[15:0] WR WRITE D[31:16] • address[15:0] data[15:0] Setting "1" for the CS → RD/WR setup delay (AWR1) enables the multiplex address output cycle to be extended by one cycle as shown in Figure 4.6-3 , allowing the address to be latched directly to the rising edge of AS. Use this setting if you want to use AS as an ALE (Address Latch Enable) strobe without using MCLK. 217 CHAPTER 4 EXTERNAL BUS INTERFACE 4.7 Prefetch Operation The external bus interface controller contains a prefetch buffer consisting of 16 × 8 bits. If the PSUS bit of the TCR register is "0" and read access to an area to which the PFEN bit of the ACR register is set to "1" occurs, the subsequent address is prefetched and then stored in the prefetch buffer. If the stored address is accessed from the internal bus, the look-ahead data in the prefetch buffer is returned without external access being performed. This can reduce the wait time for successive accesses to the external bus areas. ■ Basic Conditions for Starting External Access Using Prefetch External bus access using prefetch occurs when the following conditions are met: • The PSUS bit of the TCR register is "0". • Neither sleep mode nor stop mode is set. • Read access by the external bus to a chip select area for which prefetch is enabled has been performed. DMA access and read access by a read modified write system instruction, however, are excluded. • No external bus access request (external bus area access to an area for which prefetch is not enabled or DMA transfer with an external bus area) other than the prefetch access has occurred. • The part of the prefetch buffer for the next operation of capturing the prefetch access is completely empty. • While the above conditions are met, the prefetch access will continue. If external bus area access to an area for which prefetch is not enabled occurs after prefetch access, prefetch access to the area for which prefetch is enabled will continue as long as the prefetch buffer clear conditions are not met. For an access that mixes multiple prefetch-enabled areas and multiple prefetch-disabled areas, the prefetch buffer always holds data of the prefetch-enabled area accessed last. Since, in this case, access to prefetchdisabled areas does not affect the prefetch buffer state at all, data in the prefetch buffer is not wasted even if prefetch-disabled data access and prefetch-enabled instruction fetch are mixed. 218 ■ Optional Clear and Temporary Stopping of a Prefetch Access Setting "1" for the PSUS bit of the TCR register temporarily stops a prefetch. The prefetch can be restarted by setting the PSUS bit to "0". At this point, the contents of the buffer are retained if no error occurs or a buffer clear such as occurs when the PCLR bit is set does not occur. Setting "1" for the PCLR bit of the TCR register completely clears the prefetch buffer. Clear the buffer by setting the PSUS bit when prefetch is interrupted. Prefetch is temporarily stopped for the minimum unit (64K bytes) of the boundary=chip select area where the high-order 16 bits of an address change. If the boundary is crossed, first a buffer read error occurs and then prefetch starts in a new area. ■ Unit for One Prefetch Access Operation The unit for one prefetch access operation is determined by the DBW bits (bus width) and BST bits (burst length) of the ACR register. Prefetch access always occurs with the full size of the bus width specified by the DBW bits and access for the count of the burst length set by the BST bits in one access operation is performed. That is, if any value other than 00B is set for the BST bits, the prefetch access always occurs in page mode/burst mode. Keep in mind whether ROM/RAM is conformable and enough access time is applicable. (Set an appropriate value bits W15-08 bits of the AWR register). During burst access, successive accesses occur only within the address boundary that is determined by the burst length. Thus, if the boundary is crossed, for example, 4 bytes of free space are available in the buffer, these 4 bytes cannot be accessed in one operation (If the prefetch buffer starts at xxxxxx0EH, 4 bytes of free space are available in the buffer, and two bursts are set even though the bus width is 16 bits, only 2 bytes, xxxxxx0EH and xxxxxx0FH, can be captured in the next prefetch access). Examples: • Area whose bus width is set to 16 bits and whose burst length is set to "2" The amount of data read into the buffer in one prefetch operation is 4 bytes. In this case, prefetch access is delayed until 4 bytes of free space are available in the prefetch buffer. • Area whose bus width is set to 8 bits and whose burst length is set to "8" The amount of data read into the buffer in one prefetch operation is 8 bytes. In this case, prefetch access is delayed until 8 bytes of free space are available in the prefetch buffer. ■ Burst Length Setting and Prefetch Efficiency If requests for external bus access, other than prefetch access, to or errors in the prefetch buffer occur during one operation of prefetch access as explained in the previous bullet, "Unit for One Prefetch Access Operation," these access requests must wait until access to the prefetch buffer that is being executed is completed. Thus, if the burst length is too long, the efficiency and reaction of bus access other than prefetch may be degraded. If, on the other hand, the burst length is set to "1", many read cycles may be wasted even if burst/ page access memory is connected because single access is always performed. If settings are made so that the amount of data read in one prefetch access operation is large, prefetch access can be started only after free space in the prefetch buffer for this amount is available. Thus, access to the prefetch buffer is infrequent, and the external bus tends to be idle. For example, if the bus width is set to 16 bits and the burst length is set to "8", the amount of data read into the buffer in one prefetch operation is 16 bytes. Thus, a new prefetch access can be started only after the prefetch buffer is completely empty. Adjust the optimum burst length to suit use and the environment after taking the above into consideration. 219 CHAPTER 4 EXTERNAL BUS INTERFACE Generally, when connecting asynchronous memory to which burst/page access cannot be applied, it is best to set the burst length to "1" (single access). Conversely, when memory whose burst/page access cycle is short is connected, it is better to set the burst length to any value other than "1" (single access). In this case, it is best to make the setting so that 8 bytes (half of the buffer) are read in one read operation according to the bus width. However, the optimum condition varies with the frequency of external access and varies with the frequency divide-by rate setting of the external access clock. ■ Reading from the Prefetch Buffer Data stored in the prefetch buffer is read in response to access from the internal bus if an address matches, and no external access is performed. In reading from the buffer, addresses can be hit (up to 16 bits) if they are in the forward direction but not continuous, so that a second read from the external bus is avoided, if possible, even for a short forward branch. If the address currently being accessed for prefetch matches during access from the internal bus, a wait signal is returned internally before data is captured after prefetch access is completed. In this case, no buffer error occurs. If an address in the prefetch buffer matches when a read is performed for DMA transfer, data in the prefetch buffer is not used, and instead, external data is read by the external bus. In this case, a buffer error occurs. The prefetch is not continued and no prefetch access is performed until a new external access operation to a prefetch-enabled area occurs. ■ Clearing/Updating the Prefetch Buffer If either of the following conditions is met, the prefetch buffer is completely cleared: • If "1" is written to the PCLR bit of the TCR register • If a buffer read error occurs. • If a buffer write hit occurs. Only part of the prefetch buffer is cleared when the following condition is met: • If a buffer read hit occurs In this case, only the part of the buffer before the hit address is cleared. A buffer read error is if any of the following events occurs: • When no address is found in the buffer that matches in an to read from a prefetch-enabled area. In this case, the external bus is accessed again. Data read in this case is not stored in the buffer, but the prefetch access is started from the subsequent address to store addresses in the buffer. • In an access to read from a prefetch-enabled area with a read modified system instruction. In this case, the external bus is accessed again. Data read in this case is not stored in the buffer. Also, no prefetch access is performed (This is because data is written to the next address). • In an access to read from a prefetch-enabled area for DMA transfer. In this case, the external bus is accessed again. Data read in this case is not stored in the buffer. Also, no prefetch access is performed. A buffer write hit is as follows: • 220 When the address of just one byte that matches is found in the buffer in an access to write to a prefetchenabled area. In this case, the external bus is accessed again, but no prefetch access is performed before a new read access occurs. ■ Restrictions on Prefetch-enabled Areas If prefetch to a little endian area is enabled, be sure to access the area using word access. If data read into the prefetch buffer is accessed with any length other than word length, the correct endian conversion is not performed and thus the wrong data will be read. This is due to hardware restrictions related to the endian conversion mechanism. 221 CHAPTER 4 EXTERNAL BUS INTERFACE 4.8 DMA Access Operation This section explains DMA access operation. ■ DMA Fly-by Transfer (I/O → Memory) (TYP[3:0] = 0000B, AWR = 0008H, and IOWR = 41H) Figure 4.8-1 shows setting of DMA fly-by transfer (I/O → memory). Figure 4.8-1 Setting of DMA Fly-by Transfer (I/O → Memory) When a wait has not been set on the memory side Basic cycle I/O wait cycle I/O hold wait MCLK A[23:0] memory address AS CSn WRn D[31:16] FR30 compatible mode Basic mode DACKn EOPn DACKn EOPn IORD DREQn 222 Sense timing in demand mode • Setting "1" for the W01 bit of the AWR register enables the CS → RD/WR setup delay to be set. Set this bit to extend the period between assertion of chip select and the read/write strobe. • Setting "1" for the W00 bit of the AWR register enables the RD/WR → CS hold delay to be set. Set this bit to extend the period between negation of the read/write strobe and negation of chip select. • The CS → RD/WR setup delay (W01 bit) and RD/WR → CS hold delay (W00 bit) can be set independently. • When successive accesses are made within the same chip select area without negating the chip select, neither CS → RD/WR setup delay nor RD/WR → CS hold delay is inserted. • If a setup cycle for determining the address or a hold cycle for determining the address is needed, set "1" for the address → CS delay setting (W02 bit of the AWR register). For I/O on the data output side, a read strobe of three bus cycles extended by the I/O wait cycle and I/O hold wait cycle is generated. For memory on the receiving side, a write strobe of two bus cycles extended by the I/O wait cycle is generated. The I/O hold wait cycle does not affect the write strobe. However, the address and CS signal are retained until the fly-by bus access cycles end. ■ DMA Fly-By Transfer (Memory → I/O) (TYP[3:0]=0000B, AWR=0008H, and IOWR=41H) Figure 4.8-2 shows setting of DMA fly-by transfer (memory → I/O). When a wait has not been set on the memory side Figure 4.8-2 Setting of DMA Fly-by Transfer (Memory → I/O) Basic cycle I/O wait cycle I/O hold wait MCLK A[23:0] memory address AS CSn RD D[31:16] FR30 compatible mode DACKn EOPn Basic mode DACKn EOPn IOWR DREQn Sense timing in demand mode 223 CHAPTER 4 EXTERNAL BUS INTERFACE • Setting "1" for the HLD bit of the IOWR0 to 3 registers extends the I/O read cycle by one cycle. • Setting bits WR[1:0] bits of the IOWR0 to 3 registers enables 0-3 write recovery cycles to be inserted. • If the write recovery cycle is set to "1" or more, a write recovery cycle is always inserted after write access. • Setting bits IW[3:0], IW[13:10], and IW[23:20] of the IOWR0 to 3 registers enables 0 to 15 wait cycles to be inserted. • If wait is also set on the memory side (AWR[15:12] is not "0"), the larger value is used as the wait cycle after comparison with the I/O wait (IW[3:0], IW[13:10], and IW[23:20] bits). Reference: For memory on the data output side, a read strobe of three bus cycles extended by the I/O wait cycle and I/O hold wait cycle is generated. For I/O on the receiving side, a write strobe of two bus cycles extended by the I/O wait cycle is generated. The I/O hold wait cycle does not affect the write strobe. However, the address and CS signal are retained until the fly-by bus access cycles end. Always execute fly-by transfer between the same data bus widths. 224 ■ 2-Cycle Transfer (The Timing is the Same for Internal RAM → External I/O and RAM and for External I/O and RAM → Internal RAM.) (TYP[3:0] = 0000B, AWR = 0008H, and IOWR = 00H) Figure 4.8-3 shows setting of 2-cycle transfer. When a wait has not been set on the I/O side Figure 4.8-3 Setting of 2-Cycle Transfer MCLK A[23:0] I/O address AS CSn (I/O side) WRn D[31:16] FR30 compatible mode Basic mode DACKn EOPn DACKn EOPn DREQn Sense timing in demand mode • The bus is accessed in the same way as an interface when DMAC transfer is not performed. • DACKn/EOPn is not outputted in the internal RAM access cycles. 225 CHAPTER 4 EXTERNAL BUS INTERFACE ■ 2-Cycle Transfer (External → I/O) (TYP[3:0] = 0000B, AWR = 0008H, and IOWR = 00H) Figure 4.8-4 shows setting of 2-cycle transfer (external → I/O). When a wait has not been set on the memory and the I/O side Figure 4.8-4 Setting of 2-Cycle Transfer (External → I/O) MCLK A[23:0] memory address idle I/O address AS CSn RD CSn WRn D[31:16] FR30 compatible mode DACKn EOPn DACKn Basic mode EOPn DREQn 226 • The bus is accessed in the same way as an interface when the DMAC transfer is not performed. • In basic mode, DACKn/EOPn is outputted in both transfer source bus access and transfer destination bus access. ■ 2-Cycle Transfer (I/O → External) (TYP[3:0] = 0000B, AWR = 0008H, and IOWR = 00H) Figure 4.8-5 shows setting of 2-cycle transfer (I/O → external). When a wait has not been set on the memory and the I/O side Figure 4.8-5 Setting of 2-Cycle Transfer (I/O → External) MCLK A[23:0] I/O address Idle Memory address AS CSn WRn CSn RD D[31:16] FR30 compatible mode DACKn EOPn DACKn Basic mode EOPn DREQn • The bus is accessed in the same way as an interface when the DMAC transfer is not performed. • In basic mode, DACKn/EOPn is outputted both in the transfer source bus access and transfer destination bus access. 227 CHAPTER 4 EXTERNAL BUS INTERFACE 4.9 Bus Arbitration This section describes the settings for executing bus arbitration. ■ Releasing the Bus Right Figure 4.9-1 shows setting of releasing for the bus right. Figure 4.9-1 Setting of Releasing the Bus Right MCLK A23 to A0 AS CSn RD Read D31 to D16 BRQ BGRNT 1 cycle 228 ■ Acquiring the Bus Right Figure 4.9-2 shows setting of acquiring the bus right. Figure 4.9-2 Setting of Acquiring the Bus Right MCLK A23 to A0 AS CSn WR D31 to D16 BRQ BGRNT 1 cycle • Setting "1" for the BREN bit of the TRC register enables bus arbitration by BRQ/BGRNT to be performed. • When the bus right is released, the pin is set to high impedance and then BGRNT is asserted one cycle later. • When the bus right is acquired, BGRNT is negated and then each pin is activated one cycle later. • CSn is set to high impedance only if the SREN bit in the ACR0 to 7 registers is set. • If all areas enabled by the CSER register are shared (the SREN bit of the ACR register is "1"), AS, BAA, RD, WR, and WR0 to WR3 are set to high impedance. 229 CHAPTER 4 EXTERNAL BUS INTERFACE 4.10 Procedure for Setting a Register Observe the following rules when setting the external bus interface: ■ Procedure for Setting the External Bus Interface 1. Before rewriting the contents of a register, be sure to set the CSER register so that the corresponding area is not used (0). If you change the settings while "1" is set, access before and after the change cannot be guaranteed. 2. Use the following procedure to change a register: 1) Set "0" for the CSER bit corresponding to the applicable area. 2) Set both ASR and ACR at the same time using word access. When accessing ASR and ACR using half word, please set ACR after setting ASR. 3) Set AWR. 4) Set the CSER bit corresponding to the applicable area. 3. The CS0 area is enabled after a reset is released. If the area is used as a program area, the register contents need to be rewritten while the CSER bit is "1". In this case, make the settings described in 2) to 3) above in the initial state with a low-speed internal clock. Then, switch the clock to a high-speed clock. 4. Use the following procedure to change the register value in an area for which prefetch is enabled: 1) Set "0" for the bit of CSER corresponding to the applicable area. 2) Set "1" for both the PSUS bit and PCLR bit of the TCR register. 3) Set both ASR and ACR at the same time using word access. 4) Set AWR. 5) Set "0" for both the PSUS bit and PCLR bit of the TCR register. 6) Set "1" for the bit of CSER corresponding to the applicable area. 230 CHAPTER 5 I/O PORT This chapter describes the I/O ports and the configuration and functions of registers. 5.1 Overview of the I/O Port 5.2 I/O Port Registers 231 CHAPTER 5 I/O PORT 5.1 Overview of the I/O Port This section provides an overview of the I/O port. ■ Basic Block Diagram of the I/O Port The pins of the MB91350A device can be used as I/O ports. To do so, set so that the corresponding pins are not used for I/O with the external bus interface or peripherals. Figure 5.1-1 shows the basic configuration of the port. Figure 5.1-1 Basic Block Diagram of the Port Port Bus Peripheral input 0 Peripheral PDR read 1 output PDR 1 Pull-up resistor (about 50 kΩ) Pin 0 PFR DDR PCR PCR = 0: Without a pull-up resistor PCR = 1: With a pull-up resistor DDR: Data Direction Register PDR: Port Data Register PFR: Port Function Register PCR: Pull-up resistor control register ■ I/O Ports With Pull-up Resistors The I/O ports with pull-up resistors are configured as follows: • PDR: Port data register • DDR: Data direction register • PFR: Port function register • PCR: Pull-up resistor control register ● Port input mode (PFR=0 & DDR=0) PDR read: Reads the level of the corresponding external pin. PDR write: Writes a setting value to the PDR. ● Port output mode (PFR= 0 & DDR=1) PDR read: Reads the value of the PDR. PDR write: Outputs the value of the PDR to the corresponding external pin. ● Peripheral output mode (PFR=1 & DDR=×) PDR read: Reads the value of the corresponding peripheral output. PDR write: Writes a setting value to the PDR. 232 Notes: • Use byte access to access the ports. When ports 0 to A (excluding bit 3 of port 9) are being used as external bus pins, the external bus functions have priority. Therefore, when the ports operate as external bus pins, I/O switching will not occur even though the DDR register is rewritten. The value of the DDR register is valid when the PFR register is switched and the pins are used as general-purpose pins. • In stop mode (HIZ = 0), the setting of the pull-up resistor control register has priority. • In stop mode (HIZ = 1), the setting of the pull-up resistor control register is disabled. • When a pin is being used as an external bus pin, use of a pull-up resistor is not allowed. Set so that "1" is not written to the relevant bit of the pull-up control register (PCR). • When the registers are used in single-chip mode, the external bus functions of PFR6, 8, 9, A, B1, B2, and C cannot be used. Do not rewrite these registers. In addition, in single-chip mode, external bus function output is disabled for the functions (A23 to A16, WR1, SYSCLK, and CS3 to CS0) that result from the initial values set to "1" in PFR6, 8, 9, and A. (Use these registers as general-purpose ports.) 233 CHAPTER 5 I/O PORT 5.2 I/O Port Registers This section describes the configuration and functions of the I/O port registers. ■ Port Data Registers (PDR) The configuration of the port data registers (PDR) is shown below: 7 6 PDR2 Address : 00000002H P27 P26 7 6 PDR3 Address : 00000003H P37 P36 7 6 PDR4 Address : 00000004H P47 P46 7 6 PDR5 Address : 00000005H P57 P56 7 6 PDR6 Address : 00000006H *P67 *P66 7 6 PDR8 Address : 00000008H 7 6 PDR9 Address : 00000009H 7 6 PDRA Address : 0000000AH 7 6 * PDRB Address : 0000000BH *PB7 *PB6 7 6 * PDRC Address : 0000000CH 7 6 * PDRG Address : 00000010H 7 6 PDRH Address : 00000011H 7 6 PDRI Address : 00000012H 7 6 * PDRJ Address : 00000013H *PJ7 *PJ6 7 6 PDRK Address : 00000014H PK7 PK6 7 6 PDRL Address : 00000015H 7 6 PDRM Address : 00000016H 7 6 PDRN Address : 00000017H PDR0 7 6 Address : 00000018H *P07 *P06 7 6 * PDRP Address : 00000019H 5 P25 5 P35 5 P45 5 P55 5 *P65 5 P85 5 4 P24 4 P34 4 P44 4 P54 4 P64 4 P84 4 P94 4 3 2 P23 P22 3 2 P33 P32 3 2 P43 P42 3 2 P53 P52 3 2 P63 P62 3 2 P83 P82 3 2 P93 *P92 3 2 PA3 PA2 4 3 2 *PB4 *PB3 *PB2 4 3 2 *PC2 4 3 2 *PG4 *PG3 *PG2 4 3 2 PH4 PH3 PH2 4 3 2 PI4 PI3 PI2 4 3 2 *PJ4 *PJ3 *PJ2 4 3 2 PK4 PK3 PK2 4 3 2 1 P21 1 P31 1 P41 1 P51 1 P61 1 P81 1 P91 5 1 PA1 5 1 *PB5 *PB1 5 1 *PC1 5 1 *PG5 *PG1 5 1 PH5 PH1 5 1 PI5 PI1 5 1 *PJ5 *PJ1 5 1 PK5 PK1 5 1 PL1 5 4 3 2 1 PM5 PM4 PM3 PM2 PM1 5 4 3 2 1 *PN5 PN4 *PN3 PN2 *PN1 5 4 3 2 1 *P05 *P04 *P03 P02 *P01 5 4 3 2 1 *PP3 *PP2 *PP1 0 P20 0 P30 0 P40 0 P50 0 P60 0 P80 0 P90 0 PA0 0 *PB0 0 *PC0 0 *PG0 0 PH0 0 PI0 0 *PJ0 0 PK0 0 PL0 0 PM0 0 PN0 0 P00 0 *PP0 Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value - - XXXXXXB Initial value - - - XXXXXB Initial value - - - - XXXXB Initial value XXXXXXXXB Initial value - - - - - XXXB Initial value - - XXXXXXB Initial value - - XXXXXXB Initial value - - XXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value - - - - - - XXB Initial value - - XXXXXXB Initial value - - XXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W PDR0 to PDRP are I/O data registers for the I/O ports. I/O is controlled by the corresponding DDR2 to DDRP and PFR6 to PFRP. There is no port function register (PFR) for P20 to P27, P30 to P37, P40 to P47, P50 to P57, P91, PJ0 to PJ7, PK0 to PK7, PG0, PG3, PH0, PH3, PI0, PI3, PM1, or PM3. *: The MB91F353A/351A/352A/353A do not have PDRs that are PDRB, PDRC, PDRG, PDRJ, and PDRP. Also, the bit values of P65, P66, P67, P92, PN1, PN3, PN5, P01, P03, P04, P05, P06, and P07 are invalid. 234 ■ Data Direction Registers (DDR) The configuration of the data direction registers (DDR) is shown below: DDR2 Address : 00000602H DDR3 Address : 00000603H DDR4 Address : 00000604H DDR5 Address : 00000605H DDR6 Address : 00000606H DDR8 Address : 00000608H DDR9 Address : 00000609H DDRA Address : 0000060AH * DDRB Address : 0000060BH * DDRC Address : 0000060CH * DDRG Address : 00000400H DDRH Address : 00000401H DDRI Address : 00000402H * DDRJ Address : 00000403H DDRK Address : 00000404H DDRL Address : 00000405H DDRM Address : 00000406H DDRN Address : 00000407H DDR0 Address : 00000408H * DDRP Address : 00000409H 7 P27 7 P37 7 P47 7 P57 7 *P67 7 6 P26 6 P36 6 P46 6 P56 6 *P66 6 5 P25 5 P35 5 P45 5 P55 5 *P65 5 P85 5 4 P24 4 P34 4 P44 4 P54 4 P64 4 P84 4 P94 4 3 2 P23 P22 3 2 P33 P32 3 2 P43 P42 3 2 P53 P52 3 2 P63 P62 3 2 P83 P82 3 2 P93 *P92 3 2 PA3 PA2 4 3 2 *PB4 *PB3 *PB2 4 3 2 *PC2 4 3 2 *PG4 *PG3 *PG2 4 3 2 PH4 PH3 PH2 4 3 2 PI4 PI3 PI2 4 3 2 *PJ4 *PJ3 *PJ2 4 3 2 PK4 PK3 PK2 4 3 2 1 P21 1 P31 1 P41 1 P51 1 P61 1 P81 7 6 1 P91 7 6 5 1 PA1 7 6 5 1 *PB7 *PB6 *PB5 *PB1 7 6 5 1 *PC1 7 6 5 1 *PG5 *PG1 7 6 5 1 PH5 PH1 7 6 5 1 PI5 PI1 7 6 5 1 *PJ7 *PJ6 *PJ5 *PJ1 7 6 5 1 PK7 PK6 PK5 PK1 7 6 5 1 PL1 7 6 5 4 3 2 1 PM5 PM4 PM3 PM2 PM1 7 6 5 4 3 2 1 *PN5 PN4 *PN3 PN2 *PN1 7 6 5 4 3 2 1 *P07 *P06 *P05 *P04 *P03 P02 *P01 7 6 5 4 3 2 1 *PP3 *PP2 *PP1 0 P20 0 P30 0 P40 0 P50 0 P60 0 P80 0 P90 0 PA0 0 *PB0 0 *PC0 0 *PG0 0 PH0 0 PI0 0 *PJ0 0 PK0 0 PL0 0 PM0 0 PN0 0 P00 0 *PP0 Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value - - 000000B Initial value - - - 00000B Initial value - - - - 0000B Initial value 00000000B Initial value - - - - - 000B Initial value - - 000000B Initial value - - 000000B Initial value - - 000000B Initial value 00000000B Initial value 00000000B Initial value - - - - - - 00B Initial value - - 000000B Initial value - - 000000B Initial value 00000000B Initial value 00000000B Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W DDR0 to DDRP control the input/output direction of the corresponding I/O port at the bit level. • • If PFR=0 • DDR=0: Port input • DDR=1: Port output If PFR=1 • DDR=0: Peripheral input • DDR=1: Peripheral output *: The MB91F353A/351A/352A/353A do not have DDRs that are DDRB, DDRC, DDRG, DDRJ, and DDRP. Also, the bit values of P65, P66, P67, P92, PN1, PN3, PN5, P01, P03, P04, P05, P06, and P07 are invalid. 235 CHAPTER 5 I/O PORT ■ Pull-up Control Registers (PCR) The configuration of the pull-up control registers (PCR) is shown below: PCR2 Address: 00000622 H 7 P27 6 P26 5 P25 4 P24 3 P23 2 P22 1 P21 0 P20 Initial value 00000000 B Access R/W PCR3 Address: 00000623 H 7 P37 6 P36 5 P35 4 P34 3 P33 2 P32 1 P31 0 P30 Initial value 00000000 B Access R/W PCR4 Address: 00000624 H 7 P47 6 P46 5 P45 4 P44 3 P43 2 P42 1 P41 0 P40 Initial value 00000000 B Access R/W PCR5 Address: 00000625 H 7 P57 6 P56 5 P55 4 P54 3 P53 2 P52 1 P51 0 P50 Initial value 00000000 B Access R/W PCR6 Address: 00000626 H 7 *P67 6 *P66 5 *P65 4 P64 3 P63 2 P62 1 P61 0 P60 Initial value 00000000 B Access R/W PCR8 Address: 00000628 H 7 - 6 - 5 P85 4 P84 3 P83 2 P82 1 P81 0 P80 Initial value --000000B Access R/W PCR9 Address: 00000629 H 7 - 6 - 5 - 4 P94 3 P93 2 *P92 1 P91 0 P90 Initial value ---00000B Access R/W PCRA Address: 0000062AH 7 - 6 - 4 - 3 PA3 2 PA2 1 PA1 0 PA0 Initial value ----0000 B Access R/W * PCRB Address: 0000062BH 7 *PB7 6 *PB6 4 *PB4 3 *PB3 2 *PB2 1 *PB1 0 *PB0 Initial value 00000000 B Access R/W * PCRC Address: 0000062CH 7 - 6 - * PCRG Address: 00000420H 7 - 6 - PCRH Address: 00000421H 7 - PCRI Address: 00000422 H 5 5 *PB5 5 3 - - 2 *PC2 1 *PC1 0 *PC0 Initial value -----000 B Access R/W 5 *PG5 4 *PG4 3 *PG3 2 *PG2 1 *PG1 0 *PG0 Initial value ---00000B Access R/W 6 - 5 PH5 4 PH4 3 PH3 2 PH2 1 PH1 0 PH0 Initial value ---00000B Access R/W 7 - 6 - 5 PI5 4 PI4 3 PI3 2 PI2 1 PI1 0 PI0 Initial value --000000B Access R/W PCRM Address: 00000426 H 7 - 6 - 5 PM5 4 PM4 3 PM3 2 PM2 1 PM1 0 PM0 Initial value --000000B Access R/W PCRN Address: 00000427H 7 - 6 - 5 *PN5 4 PN4 3 *PN3 2 PN2 1 *PN1 0 PN0 Initial value --000000 B Access R/W PCR0 Address: 00000428 H 7 *P07 6 *P06 5 *P05 4 *P04 3 *P03 2 P02 1 *P01 0 P00 Initial value 00000000 B Access R/W * PCRP Address: 00000429 H 7 - 6 - 4 3 *PP3 2 *PP2 1 *PP1 0 *PP0 Initial value 00000000 B Access R/W - 4 5 - - PCR2 to PCRP execute pull-up resistor control for the corresponding I/O port. • PCR = 0: Without pull-up resistor • PCR = 1: With pull-up resistor PJ0 to PJ7, PK0 to PK7, and PL0 and PL1 do not have a pull-up resistor. *: The MB91F353A/351A/352A/353A do not have PCRs that are PCRB, PCRC, PCRG, and PCRP. Also, the bit values of P65, P66, P67, P92, PN1, PN3, PN5, P01, P03, P04, P05, P06, and P07 are invalid. 236 ■ Port Function Registers (PFR) The configuration of the port function registers (PFR) is shown below: 7 6 5 4 3 2 1 0 PFR6 Initial value Address : 00000616H *A23E *A22E *A21E A20E A19E A18E A17E A16E 11111111B 7 6 5 4 3 2 1 0 PFR8 Initial value --1--0--B WR1XE BRQE Address : 00000618H Access R/W Access R/W 7 6 5 4 3 PFR9 ASXE *1 Address : 00000619H 7 6 5 4 3 PFRA CS3XE Address : 0000061AH 7 6 5 4 3 * PFRB1 Address : 0000061BH *DES1 *AK12 *AK11 *AK10 *DES0 7 6 5 4 3 * PFRB2 Address : 0000061CH *DRDE *DWRE 7 6 5 4 3 * PFRC *AKH2 *DES2 Address : 0000061DH 7 6 5 4 3 * PFRG *SCE5 *SOE5 Address : 00000410H 7 6 5 4 3 PFRH SCE3 SOE3 Address : 00000411H 7 6 5 4 3 PFRI SCE1 SOE1 Address : 00000412H Access R/W PFRL Address : 00000415H PFRM Address : 00000416H PFRN Address : 00000417H PFRO Address : 00000418H * PFRP 00000419H 7 1 0 Initial value TEST I2CE ------00B 7 6 5 4 3 2 1 0 Initial value SCE7 SOE7 SCE6 SOE6 --00-00-B 7 6 5 4 3 2 1 0 Initial value *PGE5 *PGE4 *PGE3 *PGE2 *PGE1 *PGE0 --000000B 7 6 5 4 3 2 1 0 Initial value *OTE7 *OTE6 *OTE5 *OTE4 *OTE3 OTE2 *OTE1 OTE0 00000000B 7 6 6 5 5 4 4 3 2 1 0 Initial value ---010-1B *MCKE SYSE 2 1 0 Initial value ----1111B CS2XE CS1XE CS0XE 2 1 0 Initial value *AK02 *AK01 *AK00 00000000B 2 1 0 Initial value 00----00B *AKH1 *AKH0 2 1 0 Initial value *AK22 *AK21 *AK20 ---00000B 2 1 0 Initial value --00-00-B *SCE4 *SOE4 2 1 0 Initial value SCE2 SOE2 --00-00-B 2 1 0 Initial value SCE0 SOE0 --00-00-B 2 3 2 1 0 Initial value *TOE3 *TOE2 *TOE1 *TOE0 ----0000B Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W PFR6 to PFR0 control output of the corresponding external bus interface and peripherals at the bit level. Always set empty PFR bits to "0" except for the bits with *. For these bits, always write "1". When the registers are used in single-chip mode, the external bus functions of PFR6, 8, 9, A, B1, B2, and C cannot be used. Do not rewrite these registers. In addition, in single-chip mode, external bus function output is disabled for the functions (A23-A16, WR1, SYSCLK, and CS3-CS0) that result from the initial values set to "1" in PFR6, 8, 9, and A. (Use these registers as general-purpose ports.) *: The MB91F353A/351A/352A/353A do not have PFRs that are PFRB1, PFRB2, PFRC, PFRG, and PFRP. Also, the bit values of A23E, A22E, A21E, MCKE, PGE1, PGE3, PGE5, OTE1, OTE3, OTE4, OTE5, OTE6, and OTE7 are invalid. 237 CHAPTER 5 I/O PORT ■ Initial Values and Functions of the Port Function Registers (PFRs) Table 5.2-1 lists the initial values and functions of the port function registers (PFRs). When the registers are used in single-chip mode, the external bus functions of PFR6, 8, 9, A, B1, B2, and C cannot be used. Do not rewrite these registers. In addition, in single-chip mode, external bus function output is disabled for the functions (A23-A16, WR1, SYSCLK, and CS3 -CS0) that result from the initial values set to "1" in PFR6, 8, 9, and A. (Use these registers as general-purpose ports.) Table 5.2-1 Initial Values and Functions of the Port Function Registers (PFRs) (1 / 7) Register name Bit name PFR6(A16E to A23E) [P60/A16 to P67/A23] A16E P65/A21E,P66/A22E,P67/ A23E* A17E Bit Function 0 General-purpose port * 1 Address output (initial value) 0 General-purpose port * 1 Address output (initial value) 0 General-purpose port * 1 Address output (initial value) 0 General-purpose port * 1 Address output (initial value) 0 General-purpose port * 1 Address output (initial value) 0 General-purpose port * 1 Address output (initial value) 0 General-purpose port * 1 Address output (initial value) * 0 General-purpose port * 1 Address output (initial value) * 0 General-purpose port (initial value) * 1 BRQ, BGRNT 0 General-purpose port 1 WR1/ULB output (initial value) 0 General-purpose port 1 Set "1" when using SYSCLK output (initial value). 0 General-purpose port (initial value) * 1 Set "1" when using memory clock output. * A18E A19E A20E A21E* A22E* A23E* PFR8(BRQE) [P81/IN1/BGRNT,P82/IN2/ BRQ] BRQE PFR8(WR1XE) [P85/IN3/WR1] WR1XE PFR9(SYSE) [P90/SYSCLK] SYSE PFR9(MCKE) [P92/MCLK] * MCKE* 238 Table 5.2-1 Initial Values and Functions of the Port Function Registers (PFRs) (2 / 7) Register name Bit name PFR9(ASXE) [P94/AS] ASXE PFRA(CS0XE to CS3XE) [PA0/CS0 to PA3/CS3] CS0XE CS1XE CS2XE CS3XE PFRB1(AK02,AK01,AK00) [PB1/DACK0]* PFRB1(DES0),DDRB(PB2) [PB2/DSTP0/DEOP0]* AK02,AK01,AK00* DES0,PB2 * Bit Function 0 General-purpose port (initial value) 1 Set when using address strobe output. 0 General-purpose port 1 CS0 output (initial value) 0 General-purpose port 1 CS1 output (initial value) 0 General-purpose port 1 CS2 output (initial value) 0 General-purpose port 1 CS3 output (initial value) 0,0,0 General-purpose port (initial value) 0,0,1 DACK0, DEOP0 output (FR30 compatible for fly-by transfer) 0,1,0 DACK0, DEOP0 output (FR30 compatible for 2cycle transfer RD timing) 0,1,1 DACK0, DEOP0 output (FR30 compatible for 2cycle transfer WRn timing) 1,0,0 DACK0, DEOP0 output (FR30 compatible for 2cycle transfer WE timing) 1,0,1 DACK0, DEOP0 output (FR30 compatible for 2cycle transfer WRn, RD timing) 1,1,0 DACK0, DEOP0 output (FR30 compatible for 2cycle transfer WE, RD timing) 1,1,1 DACK0, DEOP0 output (chip select timing) 0,0 General-purpose port input (initial value) 0,1 General-purpose port output 1,0 DMAC: DSTP0 input 1,1 DMAC: DEOP0 output 239 CHAPTER 5 I/O PORT Table 5.2-1 Initial Values and Functions of the Port Function Registers (PFRs) (3 / 7) Register name Bit name Bit PFRB1(AK12,AK11,AK10) [PB4/DACK1]* AK12,AK11,AK10* 0,0,0 General-purpose port (initial value) 0,0,1 DACK1, DEOP1 output (FR30 compatible for fly-by transfer) 0,1,0 DACK1, DEOP1 output (FR30 compatible for 2cycle transfer RD timing) 0,1,1 DACK1, DEOP1 output (FR30 compatible for 2cycle transfer WRn timing) 1,0,0 DACK1, DEOP1 output (FR30 compatible for 2cycle transfer WE timing) 1,0,1 DACK1, DEOP1 output (FR30 compatible for 2cycle transfer WRn, RD timing) 1,1,0 DACK1, DEOP1 output (FR30 compatible for 2cycle transfer WE, RD timing) 1,1,1 DACK1, DEOP1 output (chip select timing) PFRB1(DES1),DDRB(PB5) [PB5/DSTP1/DEOP1]* DES1,PB5* PFRB2(DWRE) [PB6/IOWR]* DWRE* PFRB2(DRDE) [PB7/IORD]* DRDE* PFRB2(AKH0) [PB1/DACK0]* AKH0* PFRB2(AKH1) [PB4/DACK1]* AKH1* 240 Function 0,0 General-purpose port input (initial value) 0,1 General-purpose port output 1,0 DMAC: DSTP1 input 1,1 DMAC: DEOP1 output 0 General-purpose port (initial value) 1 IOWR output 0 General-purpose port (initial value) 1 IORD output 0 DACK0 output is active low (initial value). 1 DACK0 output is active high. 0 DACK1 output is active low (initial value). 1 DACK1 output is active high. Table 5.2-1 Initial Values and Functions of the Port Function Registers (PFRs) (4 / 7) Register name PFRC(AK22,AK21,AK20) [PC1/DACK2]* PFRC(DES2),DDRC(PC2) [PC2/DEOP2]* Bit name Bit AK22,AK21,AK20* 0,0,0 General-purpose port (initial value) 0,0,1 DACK2, DEOP2 output (FR30 compatible for fly-by transfer) 0,1,0 DACK2, DEOP2 output (FR30 compatible for 2cycle transfer RD timing) 0,1,1 DACK2, DEOP2 output (FR30 compatible for 2cycle transfer WRn timing) 1,0,0 DACK2, DEOP2 output (FR30 compatible for 2cycle transfer WE timing) 1,0,1 DACK2, DEOP2 output (FR30 compatible for 2cycle transfer WRn, RD timing) 1,1,0 DACK2, DEOP2 output (FR30 compatible for 2cycle transfer WE, RD timing) 1,1,1 DACK2, DEOP2 output (chip select timing) DES2,PC2* PFRC(AKH2) [PC1/DACK2]* AKH2* PFRG(SOE4) [PG1/SO4]* SOE4* PFRG(SCE4) [PG2/SCK4]* SCE4* PFRG(SOE5) [PG4/SO5]* SOE5* PFRG(SCE5) [PG5/SCK5]* SCE5* PFRH(SOE2) [PH1/SO2] SOE2 PFRH(SCE2) [PH2/SCK2] SCE2 Function 0,0 General-purpose port input (initial value) 0,1 General-purpose port output 1,0 DMAC: DSTP2 input 1,1 DMAC: DEOP2 output 0 DACK2 output is active low (initial value). 1 DACK2 output is active high. 0 General-purpose port (initial value) 1 S04 output 0 General-purpose port (initial value) 1 SCK4 output 0 General-purpose port (initial value) 1 S05 output 0 General-purpose port (initial value) 1 SCK5 output 0 General-purpose port (initial value) 1 S02 output 0 General-purpose port (initial value) 1 SCK2 output 241 CHAPTER 5 I/O PORT Table 5.2-1 Initial Values and Functions of the Port Function Registers (PFRs) (5 / 7) Register name Bit name PFRH(SOE3) [PH4/SO3] SOE3 PFRH(SCE3) [PH5/SCK3] SCE3 PFRI(SOE0) [PI1/SO0] SOE0 PFRI(SCE0) [PI2/SCK0] SCE0 PFRI(SOE1) [PI4/SO1] SOE1 PFRI(SCE1) [PI5/SCK1] SCE1 PFRL(I2CE) [PL1/SDL,PL0/SDA] I2CE PFRL(TEST) TEST PFRM(SOE6) [PM1/SO6/BIN0/TRG1] SOE6 PFRM(SCE6) [PM2/SCK6/ZIN0/TRG2] SCE6 PFRM(SOE7) [PM4/SO7/BIN1/TRG4] SOE7 PFRM(SCE7) [PM5/SCK7/ZIN1/TRG5] SCE7 242 Bit Function 0 General-purpose port (initial value) 1 S03 output 0 General-purpose port (initial value) 1 SCK3 output 0 General-purpose port (initial value) 1 SO0 output 0 General-purpose port (initial value) 1 SCK0 output 0 General-purpose port (initial value) 1 SO1 output 0 General-purpose port (initial value) 1 SCK1 output 0 General-purpose port (initial value) 1 SDA, SDL I/O 0 Always set to 0 (initial value). 1 Test function. Setting is not allowed. 0 General-purpose port (initial value) 1 SO6 output 0 General-purpose port (initial value) 1 SCK6 output 0 General-purpose port (initial value) 1 SO7 output 0 General-purpose port (initial value) 1 SCK7 output Table 5.2-1 Initial Values and Functions of the Port Function Registers (PFRs) (6 / 7) Register name PFRN(PGE0 to 7) [PN0/PPG0 to PN7/PPG7]* Bit name PGE0 PGE1* PGE2 PGE3* PGE4 PGE5* PFRO(OTE0 to 7) [PO0/OC0 to PO7/OC7]* OTE0 OTE1* OTE2 OTE3* OTE4* OTE5* OTE6* OTE7* Bit Function 0 General-purpose port (initial value) 1 PPG0 output 0 General-purpose port (initial value) * 1 PPG1 output * 0 General-purpose port (initial value) 1 PPG2 output 0 General-purpose port (initial value) * 1 PPG3 output * 0 General-purpose port (initial value) 1 PPG4 output 0 General-purpose port (initial value) * 1 PPG5 output * 0 General-purpose port (initial value) 1 OC0 output 0 General-purpose port (initial value) * 1 OC1 output * 0 General-purpose port (initial value) 1 OC2 output 0 General-purpose port (initial value) * 1 OC3 output * 0 General-purpose port (initial value) * 1 OC4 output * 0 General-purpose port (initial value) * 1 OC5 output * 0 General-purpose port (initial value) * 1 OC6 output * 0 General-purpose port (initial value) * 1 OC7 output * 243 CHAPTER 5 I/O PORT Table 5.2-1 Initial Values and Functions of the Port Function Registers (PFRs) (7 / 7) Register name PFRP(TOE0 to TOE3) [PP0/TOT0 to PP3/TOT3]* Bit name TOE0* TOE1* TOE2* TOE3* Bit 0 General-purpose port (initial value) * 1 TOT0 output * 0 General-purpose port (initial value) * 1 TOT1 output * 0 General-purpose port (initial value) * 1 TOT2 output * 0 General-purpose port (initial value) * 1 TOT3 output * *: This setting is invalid for the MB91F353A/351A/352A/353A. 244 Function CHAPTER 6 8/16-bit Up/Down Counters/ Timer and U-Timers This chapter describes the overview of the 8/16-bit up/ down counters/timers and the U-TIMER, the configuration and functions of registers, and 8/16-bit up/ down counter/timer and U-TIMER operation. 6.1 8/16-bit Up/Down Counters/Timers 6.2 U-TIMER 245 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers 6.1 8/16-bit Up/Down Counters/Timers This section describes the overview of the 8/16-bit up/down counters/timers, the configuration and functions of registers, and counter/timer operation. ■ Overview of the 8/16-bit Up/Down Counters/Timers The 8/16-bit up/down counters/timers consist of six event input pins, two 8-bit up/down counters, two 8-bit reload/compare registers, and control circuits. The MB91F355A/355A/354A/F356B/F357B provides two channels for the 8-bit up/down counters/timers. The MB91F353A/351A/352A/353A provide one channel for the 8-bit up/down counters/timers. The 8/16-bit up/down counters/timers cannot be used in 16-bit mode. 246 6.1.1 Overview of 8/16-bit Up/Down Counters/Timers The 8/16-bit up/down counters/timers consist of six event input pins, two 8-bit up/down counters, two 8-bit reload/compare registers, and their control circuits. ■ Characteristics of the 8/16-bit Up/Down Counters/Timers • With the 8-bit count register, counting can be performed in a range between 0 and 255 (decimal numbers). In 16-bit × 1 operation mode, counting can be performed in a range between 0 and 65535 (decimal numbers). • The following four count modes can be selected for the count clock: Count mode Timer mode Up/down counter mode Phase difference count mode (multiply-by-2) Phase difference count mode (multiply-by-4) • In timer mode, the count clock can be selected from two internal clocks and input from an internal circuit. Count clocks available for selection (for operation at 25 MHz): 80 ns (12.5 MHz: divide-by-2) 320 ns (3.125 MHz: divide-by-8) • The detection edge of the external pin input signal can be selected in up and in down counting mode. Detection of trailing edges: Detection of leading edges Detection of both trailing and leading edges Edge detection disabled • The phase difference counting mode is suitable for counting for an encoder, such as for a motor. Using one of A phase output, B phase output, and Z phase output as input allows to count rotation angle and number of rotations easily and with high precision. • Two different functions can be selected for the ZIN pin (this applies for all modes). ZIN pin: Counter clear function Gate function • The compare function and reload function are available. These functions can be used separately or combined. By combining these functions, counting up or down can be performed with an arbitrary width. Compare and reload functions: Compare function (compare interrupt request output) Compare function (compare interrupt request output and counter clearing) Reload function (underflow interrupt request output and reloading) 247 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers Compare and reload function (compare interrupt request output, counter clearing, underflow interrupt request output, and reloading) Compare and reload disabled • With the count direction flag, the counting direction immediately before the current count can be identified. • The generation of interrupts when a compare match occurs, at reload (underflow), at overflow, or when the counting direction changes, can be controlled individually. ■ List of Registers of the 8/16-bit Up/Down Counters/Timers The registers for the 8/16-bit up/down counters/timers are shown below. 31 24 23 RCR1* CCRH0 CCRH1* 16 15 RCR0 CCRL0 CCRL1* 8 UDCR1* - 7 0 UDCR0 CSR0 CSR1* *: On the MB91F353A/351A/352A/353A, access to the RCR1, UDCR1, CCRH1, CCRL1, and CSR1 registers is not allowed. ● Up/down count register (UDCR) The bit configuration of the up/down count register (UDCR) is shown below. bit Address : 0000B3H bit Address : 0000B2H 7 D07 6 D06 5 D05 4 D04 3 D03 2 D02 1 D01 0 D00 Up/down count register (channel 0) (UDCR0) 15 D15 14 D14 13 D13 12 D12 11 D11 10 D10 9 D09 8 D08 Up/down count register (channel 1) (UDCR1) ● Reload/compare register (RCR) The bit configuration of the reload/compare register (RCR) is shown below. bit Address : 0000B1H 7 D07 6 D06 5 D05 4 D04 3 D03 2 D02 1 D01 0 D00 Reload/compare register (channel 0) (RCR0) bit 15 D15 14 D14 13 D13 12 D12 11 D11 10 D10 9 D09 8 D08 Reload/compare register (channel 1) (RCR1) Address : 0000B0H 248 ● Counter status register (CSR) The bit configuration of the counter status register (CSR) is shown below. bit 7 Address : 0000B7H CSTR 0000BBH 6 CITE 5 UDIE 4 3 CMPF OVFF 2 UDFF 1 UDF1 0 Counter status register (channel 0, 1) UDF0 (CSR0, CSR1) ● Counter control register (CCRL) The bit configuration of the counter control register (CCRL) is shown below. bit Address : 0000B5H 0000B9H 7 Reserved 6 5 4 3 2 1 CTUT UCRE RLDE UDCC CGSC CGE1 0 Counter control register (channel 0, 1) CGE0 (CCRL0, CCRL1) ● Counter control register (CCRH) The bit configuration of the counter control register (CCRH) is shown below. bit 15 14 Address : 0000B4H M16E CDCF 13 CFIE bit Address : 0000B8H 15 14 13 Reserved CDCF CFIE 12 11 10 CLKS CMS1 CMS0 12 11 10 CLKS CMS1 CMS0 9 CES1 9 CES1 8 Counter control register (channel 0) CES0 (CCRH0) 8 Counter control register (channel 1) CES0 (CCRH1) 249 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers ■ Block Diagram of the 8/16-bit Up/Down Counters/Timers (ch0) Figure 6.1-1 shows a block diagram of the 8/16-bit up/down counters/timers (for Channel 0). Figure 6.1-1 Block Diagram of the 8/16-bit Up/Down Counters/Timers (ch0) CGE1 ZIN0 CGE0 CGSC Detects edge or level UDCC CES1 Data bus 8 bits RCR0 (Reload/ compare register 0) CTUT Control reload UCRE RLDE To channel 1 M16E Carry Clear counter 8 bits UDCR0 (Up/down count register 0) CES0 CMPF CMS1 CMS0 UDFF AIN0 BIN0 Select up or down count clock Count clock CSTR UDF1 UDF0 UDIE CDCF Prescaler CITE CLKS CFIE Output interrupt 250 OVFF ■ Block Diagram of the 8/16-bit Up/Down Counters/Timers (ch1) Figure 6.1-2 shows a block diagram of the 8/16-bit up/down counters/timers (for Channel 1). Figure 6.1-2 Block Diagram of the 8/16-bit Up/Down Counters/Timers (ch1) CGE1 ZIN1 CGE0 CGSC Detects edge or level UDCC CES1 CES0 Data bus 8 bits RCR1 (Reload/ compare register 1) CTUT Control reload UCRE RLDE Clear counter 8bit UDCR1 (Up/down count register 1) CMS1 CMS0 CMPF Carry M16E AIN1 BIN1 Select up or down count clock UDFF OVFF Count clock CSTR UDF1 UDF0 UDIE CDCF Prescaler CITE CLKS CFIE Output interrupt Note: The MB91F353A/351A/352A/353A do not have ch1. 251 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers 6.1.2 8/16-bit Up/Down Counters/Timer Registers This section describes the configuration and functions of the registers used by the 8/ 16-bit up/down counters/timers. ■ Counter Control Register High/Low ch0 (CCR H/L ch0) The bit configuration of the counter control register high/low (ch0) (CCRH/L ch0) is shown below. bit 15 14 Address : 0000B4H M16E CDCF 0000B5H R/W R/W 7 Reserved R/W 6 13 CFIE R/W 5 12 11 10 CLKS CMS1 CMS0 R/W R/W R/W 4 3 9 CES1 R/W 2 1 CTUT UCRE RLDE UDCC CGSC CGE1 R/W R/W R/W R/W R/W R/W 8 CES0 R/W Initial value 00000000B 0 Initial value CGE0 R/W 00001000B [Bit 15] M16E: 16-bit mode permission setting bit 8 bits × 2 channels/16 bits × 1 channel operation mode selection (switching) bit M16E 16-bit mode permission setting 0 8 bits × 2 channels operation mode (initial value) 1 16 bits × 1 channel operation mode [Bit 14] CDCF: Count direction change flag This flag is set when the count direction is changed. When the count direction is changed from up to down or down to up during counting, this flag is set to "1". 0: Writing "0" clears the setting. 1: Writing "1" is ignored. The value of this bit is not changed. CDCF Direction change detection 0 Direction has not been changed (initial value). 1 Direction has been changed once or more. Note: The count direction is set to down when the counter is reset. Therefore, CDCF is set to "1" when up counting is performed immediately after a reset. If a read modify write instruction is issued, "1" is read from the CDCF bit. 252 [Bit 13] CFIE: Count direction change interrupt enable bit This bit controls the interrupt output for the CPU when CDCF is set. An interrupt occurs if the count direction is changed at least once during counting. CFIE Direction change interrupt output 0 Disables direction change interrupt output (initial value). 1 Enables direction change interrupt output. [Bit 12] CLKS: Internal prescaler selection bit When timer mode is selected, this bit selects the frequency of the internal prescaler. This bit is effective only in timer mode and only for down counting. CLKS Selected internal clock 0 2 machine cycles (initial value) 1 8 machine cycles [Bits 11 and 10] CMS1 and CMS0: Counting mode selection bit These bits select counting mode. CMS1 CMS0 Counting mode 0 0 Timer mode [down count] (initial value) 0 1 Up or down counting mode 1 0 Phase difference counting mode, 2 multiplication 1 1 Phase difference counting mode, 4 multiplication [Bits 9 and 8] CES1 and CES0: Count clock edge selection bit In up/down counting mode, these bits select the input of internal circuit and detection edge of external pins AIN and BIN. This setting is invalid in modes other than up or down counting mode. CES1 CES0 Selection edge 0 0 Disables edge detection (initial value). 0 1 Detects falling edge. 1 0 Detects rising edge. 1 1 Detects rising and falling edges. [Bit 7] (reserved) This bit is reserved. This bit must always be set to "0". 253 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers [Bit 6] CTUT: Counter write bit This bit transfers data from RCR to UDCR. When this bit is set to "1", data is transferred from RCR to UDCR. Writing "0" to this bit has no effect. The read value is always "0". Do not set this bit to "1" during counting (when the CSTR bit of the CSR is "1"). [Bit 5] UCRE: UDCR clear enable bit This bit controls the compare operation that clears UDCR. UDCR clear functions other than clearing due to comparing (such as due to the ZIN pin) are not affected. UCRE Counter clear by compare 0 Disables counter clear (initial value). 1 Enables counter clear. [Bit 4] RLDE: Reload enable bit This bit controls the start of the reload function. When the reload function is started, if UDCR leads the underflow, this bit transfers the value of RCR to UDCR. RLDE Reload function 0 Disables the reload function (initial value). 1 Enables the reload function. [Bit 3] UDCC: UDCR clear bit This bit clears the UDCR. When this bit is set to "0", the UDCR is cleared to 0000H. Writing "1" to this bit has no effect. The read value is always "1". [Bit 2] CGSC: Counter clear/gate selection bit This bit selects the function of the external pin ZIN. CGSC 254 ZIN function 0 Counter clear function (initial value) 1 Gate function [Bits 1 and 0] CGE1 and CGE0: Counter clear/gate edge selection bit This bit selects the detection edge/level of the external pin ZIN. When counter clear function is selected When gate function is selected CGE1 CGE0 0 0 Disables edge detection (initial value). Disables level detection (count disable) 0 1 Falling edge "L" level 1 0 Rising edge "H" level 1 1 Setting not allowed Setting not allowed 255 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers ■ Counter Control Register High/Low ch1 (CCR H/L ch1) The bit configuration of the counter control register high/low (ch1) (CCRH/L ch1) is shown below. bit 15 14 Address : 0000B8H Reserved CDCF 0000B9H R/W R/W 7 Reserved R/W 13 CFIE R/W 12 11 10 CLKS CMS1 CMS0 R/W R/W R/W 9 CES1 R/W 8 CES0 R/W Initial value 00000000B 6 5 4 3 2 1 CTUT UCRE RLDE UDCC CGSC CGE1 R/W R/W R/W R/W R/W R/W 0 CGE0 R/W Initial value 00001000B [Bit 15] (reserved) This bit is reserved. This bit must always be set to "0". [Bits 14 to 0] For details of these bits, see the explanation for CCRH/L ch0. ■ Counter Status Register 0/1 (CSR0/1) The bit configuration of the counter status register 0/1 (CSR0/1) is shown below. bit 7 Address : 0000B7H CSTR 0000BBH R/W 6 CITE R/W 5 UDIE R/W 4 3 CMPF OVFF R/W R/W 2 UDFF R/W 1 UDF1 R 0 UDF0 R Initial value 00000000B [Bit 7] CSTR: Count start bit This bit controls the start and stop of UDCR counting. CSTR Operation 0 Stops the counting operation (initial value) 1 Starts the counting operation [Bit 6] CITE: Compare interrupt output control bit This bit controls whether to enable or disable interrupt output to the CPU when a compare detection flag (CMPF) is set (during a compare operation). CITE 256 Compare interrupt output 0 Disables compare interrupt output (initial value). 1 Enables compare interrupt output. [Bit 5] UDIE: Overflow/underflow interrupt output control bit This bit controls whether to enable or disable interrupt output to the CPU when OVFF/UDFF is set (when overflow or underflow occurs). UDIE Overflow/underflow interrupt output 0 Disables overflow/underflow output (initial value). 1 Enables overflow/underflow output. [Bit 4] CMPF: Compare detection flag This flag indicates that the comparison result of the UDCR value and RCR value is that the values are equal. In write operations, the flag can only be set to "0", not to "1". If a read modify write instruction is issued, "1" is read from the CMPF bit. CMPF Meaning of flag 0 Comparison result does not match (initial value). 1 Comparison result matches. [Bit 3] OVFF: Overflow detection flag This flag indicates the occurrence of an overflow. During write operations, this flag can only be set to "0", not to "1". If a read modify write instruction is issued, "1" is read from the OVFF bit. OVFF Meaning of flag 0 No overflow (initial value) 1 Overflow [Bit 2] UDFF: Underflow detection flag This flag indicates that an underflow occurs. During write operations, this flag can only be set to "0", not to "1". If a read modify write instruction is issued, "1" is read from the UDFF bit. UDFF Meaning of flag 0 No underflow (initial value) 1 Underflow 257 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers [Bits 1 and 0] UDF1 and UDF0: Up/down flag These bits indicate the type of a counting operation (up or down) immediately preceding the current operation. Only reading is allowed. No writing is allowed. UDF1 UDF0 Detection edge 0 0 No input (initial value) 0 1 Down count 1 0 Up count 1 1 Both up and down counting was performed simultaneously. ■ Up/Down Count Register 0/1 (UDCR 0/1) The bit configuration of the up/down count register 0/1 (UDCR0/1) is shown below. bit Address : 0000B2H 0000B3H 15 D15 R 14 D14 R 13 D13 R 12 D12 R 11 D11 R 10 D10 R 9 D09 R 8 D08 R Initial value 00000000B 7 D07 R 6 D06 R 5 D05 R 4 D04 R 3 D03 R 2 D02 R 1 D01 R 0 D00 R Initial value 00000000B This register is an 8-bit count register. Up/down counting is performed with an input from internal circuit, an internal prescaler or an input through the AIN pin or BIN pin. In 16-bit counting mode, this bit operates as a 16-bit count register. Values cannot be written to this register directly. To write a value to this register, the RCR must be used. First write the value to write to this register to the RCR, then set the CTUT bit of the CCRL register to "1". The value will then be transferred from the RCR to this register (in a reload-operation by software). In 16-bit mode, perform a 16-bit read operation for this register once. ■ Reload/Compare Register 0/1 (RCR 0/1) The bit configuration of the reload/compare register 0/1 (RCR0/1) is shown below. bit Address : 0000B0H 0000B1H 15 D15 W 14 D14 W 13 D13 W 12 D12 W 11 D11 W 10 D10 W 9 D09 W 8 D08 W Initial value 00000000B 7 D07 W 6 D06 W 5 D05 W 4 D04 W 3 D03 W 2 D02 W 1 D01 W 0 D00 W Initial value 00000000B This register is an 8-bit reload/compare register. This register sets the reload value and compare value. The reload value and compare value are the same. Starting the reload function and compare function enables counting up or down between 00H and the value of this register (In 16-bit operation mode: counting up and down between 0000H and the value of this register). Only writing is allowed for this register. This register cannot be read. By setting the CTUT bit of the CCR0/1 register to "1" while counting is stopped, the value of this register can be transferred to the UDCR (reloaded by software). In 16-bit mode (when M16E = 1), write a 16-bit value to this register once. 258 6.1.3 Operation of the 8/16-bit Up/Down Counters/Timers This section describes the 8/16-bit up/down counter/timer operation ■ Selecting Counting Mode The 8/16-bit up/down counters/timers have four counting modes. The CMS1 and CMS0 bits of the CCR register are used to select the counting modes. Table 6.1-1 lists the values of the CMS1 and CMS0 bits and corresponding counting modes. Table 6.1-1 Selecting Timer Counting Mode CMS1, CMS0 Counting mode 00B Timer mode [down count] 01B Up/down counting mode 10B Phase difference counting mode, 2 multiplication 11B Phase difference counting mode, 4 multiplication (a) Timer mode [down count] In timer mode, the output of the internal prescaler is used for counting down. For the internal prescaler, either two machine cycles or eight machine cycles can be selected with the CLKS bit of the CCRH register. (b) Up/down counting mode In up/down counting mode, counting up/down is performed by counting the input through external pin AIN and BIN. The input through the AIN pin controls counting up and the input through the BIN pin controls counting down. The inputs through the AIN pin and BIN pin are subject to edge-detected. The edge detection can be selected by the CES1 and CES0 bits of the CCRH register. Table 6.1-2 lists the values of the CES1 and CES0 bits and the corresponding detection edges. Table 6.1-2 Selecting the Detection Edge CES1, CES0 Detection edge 00B Disables the edge detection. 01B Detects rising edge. 10B Detects falling edge. 11B Detects both falling and rising edges. (c) Phase difference counting mode (two multiplication/four multiplication) In phase difference counting mode, to count the phase difference between phase A and phase B of the encoder output signal, detect the input level of the BIN pin at input edge detection of the AIN pin and detect the input level of the AIN pin at input edge detection of the BIN pin. 259 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers For the phase difference between AIN pin input and BIN pin input in two multiplication or four multiplication mode, count up if the AIN is faster, and count down if the BIN is faster. In two multiplication mode, counting is performed by detecting the value of the AIN pin in the period between the rising and falling edges of the BIN pin. In this case, counting is performed as follows: • When the value of the AIN pin detected at the rising edge of the BIN pin is "H", count up. • When the value of the AIN pin detected at the rising edge of the BIN pin is "L", count down. • When the value of the AIN pin detected at the falling edge of the BIN pin is "H", count down. • When the value of the AIN pin detected at the falling edge of the BIN pin is "L", count up. Figure 6.1-3 provides an overview of operation in phase difference counting mode (multiply-by-2). Figure 6.1-3 Overview of the Phase Difference Counting Mode (Two Multiplication) Operation AIN pin BIN pin Count value 0 +1 +1 +1 +1 +1 -1 +1 -1 -1 -1 -1 -1 1 2 3 4 5 4 5 4 3 2 1 0 In four-multiplication mode, counting is performed by detecting the value of the AIN pin at the rising and falling edges of the BIN pin, and detecting the value of the BIN pin at the rising and falling edges of the AIN pin. In this case, counting is performed as follows: • When the value of the AIN pin detected at the rising edge of the BIN pin is "H", count up. • When the value of the AIN pin detected at the rising edge of the BIN pin is "L", count down. • When the value of the AIN pin detected at the falling edge of the BIN pin is "H", count down. • When the value of the AIN pin detected at the falling edge of the BIN pin is "L", count up. • When the value of the BIN pin detected at the rising edge of the AIN pin is "H", count down. • When the value of the BIN pin detected at the rising edge of the AIN pin is "L", count up. • When the value of the BIN pin detected at the falling edge of the AIN pin is "H", count up. • When the value of the BIN pin detected at the falling edge of the AIN pin is "L", count down. Figure 6.1-4 shows an overview of operation in phase difference counting mode (multiply-by-4). Figure 6.1-4 Overview of the Phase Difference Counting Mode (Four Multiplication) Operation AIN pin BIN pin Count value 0 +1 +1 +1 +1 +1 1 2 3 4 5 +1 +1 6 7 +1 +1 +1 -1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 8 9 10 9 10 9 8 7 6 5 4 3 2 1 For counting the encoder output, by inputting the A phase to the AIN pin, the B phase to the BIN pin, and the Z phase to the ZIN pin, a highly precise count of the rotation angle and number of rotations can be obtained and the rotation direction can be detected as well. When this counting mode is selected, the detection edge selection with the CES1 and CES0 bits is invalid. 260 ■ Reload and Compare Functions The 8/16-bit up/down counters/timers have reload and compare clear functions, which can be combined for processing. Table 6.1-3 presents examples of selecting the reload and compare clear functions. Table 6.1-3 Selecting the Reload and Compare Clear Functions RLDE, UCRE Reload/compare function 00B Disables clear by reload/compare (initial value). 01B Enables clear by compare. 10B Enables reload. 11B Enables clear by reload/compare. ● When the Reload Function is Enabled When the reload function is started, the value of the RCR is transferred to the UDCR with the timing of the down count clock after an underflow. In this case, when UDFF is set, an interrupt request is generated. In a mode in which down counting is not performed, starting this function is invalid. Figure 6.1-5 shows an overview of reload function operation. Figure 6.1-5 Overview of the Operation of the Reload Function (0FFFFH) 0FFH Reload, interrupt occur. Reload, interrupt occur. RCR 00H Underflow Underflow 261 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers ● When the compare clear function is enabled The compare clear function can be used in all modes other than timer mode. When the compare function is started, if the value of RCR and the value of UDCR match, CMPF is set and an interrupt request is generated. When the compare clear function is started, the UDCR is cleared with the timing of the next up count clock. (The UDCR is not cleared when counting down is performed.) In a mode in which up counting is not performed, starting this function is invalid. Figure 6.1-6 shows an overview of compare function operation. Figure 6.1-6 Overview of the Compare Function Operation (0FFFFH) 0FFH Compare match Compare match RCR 00H Counter is cleared, interrupt is generated. Counter is cleared, interrupt is generated. ■ Up/Down Counting with an Arbitrary Width when the Reload and Compare Functions are Started When the reload/compare function is started, counting up or down can be performed with an arbitrary width. The reload function is started at an underflow and transfers the value of the RCR to the UDCR. When the values of RCR and UDCR match, the compare function clears the UDCR. By using these functions, counting up or down is performed for values between 0000H and the value of the RCR. Figure 6.1-7 shows an overview of operation when the reload and compare functions are started simultaneously. 262 Figure 6.1-7 Overview of the Operation when the Reload and Compare Functions are Started at the Same Time 0FFH Compare match Compare match Reload Reload Reload Compare match Underflow Underflow Counter clear RCR 00H Counter clear Counter clear Underflow An interrupt to the CPU can be generated at a compare match or at reload (underflow). These interrupt outputs can be enabled separately. The timing for clearing the UDCR is different during counting and when counting is stopped. Reloading (writing "1" to the CTUT bit) by software is not allowed during counting. • During counting, if an event for clearing occurs, all the events are synchronized with the count clock. Figure 6.1-8 shows the timing of UDCR clearing during counting. Figure 6.1-8 Timing of UDCR Clearing During Counting UDCR 0065H Clear event 0066H 0000H 0001H Synchronizes with this clock. Count clock Note: During counting, reloading due to an underflow is performed in synchronization with the count clock. • When clearing occurs during counting, if counting is stopped in counter clock synchronization wait state (state of waiting for the count input for synchronization), the clear operations is performed when counting is stopped. Figure 6.1-9 shows the timing of UDCR clearing when counting is stopped. 263 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers Figure 6.1-9 Timing of UDCR Clearing when Counting is Stopped 0065H UDCR 0066H 0000H Clear event Count clock Count enable Enable (counting permitted) • Disable (counting prohibited) If reloading or clearing occurs while the counter is stopped, reload and clear are performed when the event occurs (the figure shows the state when 080H is reloaded). Figure 6.1-10 shows the timing of UDCR reloading and clearing when counting is stopped. Figure 6.1-10 Timing of UDCR Reloading and Clearing when Counting is Stopped UDCR 065H 080H Reload/clear event Clear by compare is performed when the values of the UDCR and the RCR match and while counting up. Even when the values of RCR and UDCR match, clearing is not performed if down counting occurs or counting is stopped after a match or if up counting occurs after the value of RCR is rewritten. As for the timing of clearing and reloading, the clear operation follows the above timing for all events other than reset input, and reloading also uses the above timing for all events. When the events for clearing and reloading occur at the same time, the clear event takes priority. ■ Writing Data to the Up/Down Count Register (UDCR) Data cannot be written to the UDCR directly from the data bus. To write arbitrary data to the UDCR, follow the procedure below. 1. Write the data that is to be written to the UDCR first to the RCR (Note that this means that the original data in the RCR will be lost). 2. By setting the CTUT of the CCR to "1", data is transferred from the RCR to the UDCR. Perform the above operation while counting is stopped (when the CSTR bit of the CSR is "0"). If "1" is written to the CTUT bit by mistake during counting, the value of the RCR is transferred to the UDCR at the timing for a write. Besides the above procedure, the following procedure can also be applied to clear the counter. • Clearing by reset input (initialization). • Clearing by edge input through the ZIN pin. • Clearing by writing "0" to UDCC of the CCR. • Clearing by compare. The above can be performed regardless of the status of the counter (regardless of whether counting is performed or stopped). 264 ● Count clear/gate function The ZIN pin can be used after selecting the count clear function or gate function based on the CGSC bit of the CCR register. When the count clear function is started, the ZIN pin clears the counter. The CGE1 and CGE0 bits of the CCRL register can control which edge input of the ZIN pin to use for clearing the counter. When the gate function is started, the ZIN pin enables or disables counting. The CGE1 and CGE0 bits of the CCR register can control which level input of the ZIN pin enables counting. This function is effective for all modes. Table 6.1-4 summarizes how the ZIN pin functions are selected. Table 6.1-4 Selecting the ZIN Pin Function CGSC ZIN pin function 0 Counter clear function 1 Gate function CGE1, CGE0 When counter clear function is used When gate function is used 00B Disables detection. Disables detection. 01B Rising edge "L" level 10B Falling edge "H" level ● Count direction flag The count direction flag (UDF1 and UDF0) indicates at the time of up/down counting whether the counting operation preceding the current operation was counting up or down. Based on the count clock signal from the input of the AIN and BIN pins, this value of this flag changes for each count. By checking this flag, the current rotation direction can be determined by such as motor. Table 6.1-5 summarizes how the count direction flag works. Table 6.1-5 Count Direction Flag UDF1, UDF0 Count direction 01B Down count 10B Up count 11B Up/down occurs simultaneously (no counting operation is performed). ● Count direction change flag The CDCF is set when the counting direction changes between up and down. Simultaneously to setting this flag, an interrupt request to the CPU can be generated. By referring the interrupt and count direction flag, 265 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers the direction to which counting is changed can be determined. However, note that when the period of direction change is short and multiple direction changes are performed in succession, the direction that the flag indicates after the direction change may return to the original direction so that it appears as if the counting direction has not changed at all in between. Table 6.1-6 summarizes how the count direction change flag works. Table 6.1-6 Count Direction Change Flag CDCF Count direction change detection 0 No direction change 1 Counting direction has changed (at least once). ● Compare detection flag The CMPF is set when the values of UDCR and RCR match during counting. This flag is set for a match during counting up/down, match by occurrence of a reloading event, as well as when the values already match when counting started. ● Operations for 8 bits × 2 channels and 16 bits × 1 channel This module can be used as an 8-bit up/down counter for 2 channels or a 16-bit up/down counter for 1 channel. Setting the M16E bit of the CCRH0 register to 0 sets 8-bit mode for 2 channels. Setting the bit to 1 sets 16-bit mode for one channel. For operation in 16-bit mode for 1 channel, the registers CSR0, CCRL0, CCRH0 are valid and the CSR1, CCRL1, and CCRH1 registers are invalid. In addition, the AIN0, BIN0, ZIN0 pins are enabled as input pins, while the AIN1, BIN1, and ZIN1 pins are disabled. 266 ■ Interrupt Generation Timing Table 6.1-7 shows the timing at which interrupts are generated. Table 6.1-7 Interrupt Generation Timing Interrupt flag Flag setting interrupt Reloading Clearing Count direction change flag (CDCF) An interrupt is generated simultaneously with setting of the flag when counting starts immediately after the counting direction is changed. Compare detection flag (CMPF) An interrupt is generated simultaneously with setting of the flag when the values of RCR and UDCR match when up or down counting, reloading, or counting is initiated. UDCR is cleared at the timing of the first up count after RCR and UDCR match. (UDCR is not cleared for down counting). Overflow detection flag (OVFF) An interrupt is generated simultaneously with setting of the flag at the timing of the first up count after the count reaches FFFFH. UDCR is cleared at the timing of the first count after the count reaches FFFFH. Underflow detection flag (UDFF) An interrupt is generated simultaneously with setting of the flag at the timing of the first down count after the count reaches 0000H. The value of RCR is transferred to UDCR at the timing of the first count after the count reaches 0000H. Because the value of RCR is used for both the reload and compare values, the compare detection flag is set always when reloading is performed. If the clear function enabled, clearing occurs when up counting is performed after the values of RCR and UDCR match during down counting. If a read modify write instruction is issued, "1" is read. Even when the values of RCR and UDCR match, clearing is not performed if down counting occurs or counting is stopped after a match or if up counting occurs after the value of RCR is rewritten. Note: The count direction is set to down when the count is reset. Therefore, at the first up count after resetting, CDCF is set to "1" to indicate that the counting direction has been changed. After the up/down count register (UDCR) reaches the maximum count that the register can hold, counting continues without a carry-over. It therefore appears that counting is continuing with the updown count register cleared. The minimum pulse width at the AIN, BIN, and ZIN pins is 2.T (T stands for the peripheral clock machine cycle). 267 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers 6.2 U-TIMER This section describes the overview of the U-TIMER, the configuration and functions of registers, and U-TIMER operation. ■ Overview of the U-TIMER The U-TIMER is a 16-bit timer that is used to generate the baud rate for the UART. A baud rate can be specified by a combination of a chip operating frequency and U-TIMER reload value. 268 6.2.1 Overview of the U-TIMER The MB91F355A/355A/354A/F356B/F357B have five built-in U-TIMER channels. The MB91F353A/351A/352A/353A have four built-in U-TIMER channels. ■ U-TIMER Registers The U-TIMER registers are shown below. 15 8 7 UTIM UTIMR 0 (R) (W) (R/W) UTIMC ■ Block Diagram of the U-TIMER Figure 6.2-1 shows the block diagram of the U-TIMER. Figure 6.2-1 Block Diagram of the U-TIMER 0 15 UTIMR (reload register) load 15 0 UTIM (timer) clock (Peripheral Clock) underflow control f.f. to UART 269 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers 6.2.2 U-TIMER Registers This section describes the configuration and functions of the registers used by the UTIMER. ■ U-TIMER Registers (UTIM) The bit configuration of the U-TIMER register (UTIM) is shown below. Note: The MB91F353A/351A/352A/353A do not have ch4. UTIM ch0 Address : ch1 Address : ch2 Address : ch3 Address : ch4 Address : 00000064H 0000006CH 00000074H 000000C4H 000000CCH 15 14 b15 b14 ................................... 2 1 0 b2 b1 b0 R Access 0 Initial value UTIM is a register that indicates the timer value. Use a 16-bit transfer instruction to access this register. 270 ■ Reload Register (UTIMR) The bit configuration of the reload register (UTIMR) is shown below. Note: The MB91F353A/351A/352A/353A do not have ch4. UTIMR ch0 Address : ch1 Address : ch2 Address : ch3 Address : ch4 Address : 00000064H 0000006CH 00000074H 000000C4H 000000CCH 15 14 b15 b14 ................................... 2 1 0 b2 b1 b0 W Access 0 Initial value UTIMR is a register that stores the value to be reloaded into UTIM if UTIM underflows. Be sure to use a 16-bit transfer instruction to access this register. Note: Please do not set UTIMR (reload register) to "0" when you use U-TIMER by Mode 2 (CLK synchronous mode) of UART as baud rate. 271 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers ■ U-TIMER Control Register (UTIMC) The bit configuration of the U-TIMER control register (UTIMC) is shown below. Note: The MB91F353A/351A/352A/353A do not have ch4. UTIMC ch0 Address : ch1 Address : ch2 Address : ch3 Address : ch4 Address : 00000067H 0000006FH 00000077H 000000C7H 000000CFH 7 UCC1 R/W 6 - 5 - 4 UTIE R/W 3 UNDR R/W 2 CLKS R/W 1 UTST R/W 0 - - 0 0 0 0 0 UTCR R/W Access 1 Initial value UTIMC controls the operation of the U-TIMER. Be sure to use a byte transfer instruction to access this register. [Bit 7] UCC1 (U-timer Count Control 1) This bit controls the U-TIMER counting method. UCC1 Operation 0 Normal operation α=2n+2 (initial value) 1 +1 mode α=2n+3 n is the setting value of UTIMR. α is the cycle of the output clock for UART. The U-TIMER can set a normal cycle, 2(n+1) as well as an odd-numbered division for the UART. Set UCC1 to "1" to generate a cycle of 2n+3. Examples: 1. UTIMR=5, UCC1=0 → Generation cycle =2n+2= 12 cycles 2. UTIMR=25, UCC1=1 → Generation cycle =2n+3= 53 cycles 3. UTIMR=60, UCC1=0 → Generation cycle =2n+2=122 cycles Set UCC1 to 0 to use the U-TIMER as the interval timer. [Bits 6, 5] (reserved) These bits are reserved. [Bit 4] UTIE (U-TIMER Interrupt Enable) Note: Always write "0" to this bit because the MB91350A has no U-Timer interrupt. 272 This bit is the interrupt enable bit for a U-TIMER underflow. UTIE Operation 0 Interrupt disabled (initial value) 1 Interrupt enabled [Bit 3] UNDR (UNDeR flow flag) This bit is a flag indicating that an underflow has occurred. The UNDR bit is cleared at reset and when "0" is written to it. For a read by a read modify write instruction, "1" is always read. Writing "1" to the UNDR has no effect. [Bit 2] CLKS (CLOCK Select) Note: In the MB91350A, always write "0" to this bit. [Bit 1] UTST (U-TIMER STart) This bit is the U-TIMER operation enable bit. UTST Operation 0 Stopped. Writing "0" during operation stops running of the U-TIMER. (initial value) 1 Operation. Writing "1" during operation does not stop the U-TIMER. 273 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers [Bit 0] UTCR (U-TIMER CleaR) Writing "0" to UTCR clears the U-TIMER to 0000H (also clears the f.f. to "0"). The read value is always "1". Notes: • In the stop state, assert the start bit UTST (started) to automatically reload data. • In the stop state, assert both the clear bit UTCR and the start bit UTST at the same time to clear the counter to "0" and generate an underflow in the count-down immediately after the counter is cleared. • During operation, the clear bit UTCR is asserted to clear the counter to "0". As a result, a short, whisker-like pulse may be outputted in the output waveform, possibly causing the UART to malfunction. While the output clock is being used, do not clear it using the clear bit. • In the timer stop state, assert both bit 1 (U-TIMER start bit: UTST) and bit 0 (U-TIMER clear bit: UTCR) of the U-TIMER control register at the same time to set bit 3 (underflow flag: UNDR) of this register when the counter is loaded after it has been cleared. At this timing, the internal baud rate clock is set to "H" level. • If the device attempts to set and clear the underflow flag at the same time, the flag is set and the clear operation becomes ineffective. • Always write "0" to bit 4 (UTIE) and bit 2 (CLKS) of the U-TIMER control register (UTIMC). • If the device attempts to write to and reload the data into the U-TIMER reload register at the same time, old data is loaded into the counter. New data is loaded into the counter only in the next reload timing. • If the device attempts to clear and count/reload U-TIMER at the same time, the timer clear operation takes precedence. 274 6.2.3 Operation of the U-TIMER This section describes the U-TIMER operation. ■ Calculation of Baud Rate The UART uses the underflow flip-flop (f.f. in the block diagram shown in Figure 6.2-1 ) of the corresponding U-TIMER (from U-TIMER0 to UART0, from U-TIMER1 to UART1, from U-TIMER2 to UART2, from U-TIMER3 to UART3, or from U-TIMER4 to UART4) as the clock source for baud rates. ● Asynchronous (start-stop synchronization) mode The UART uses the U-TIMER output divided by 8. bps = (2n+2) 8 bps = (2n+3) 8 UCC 1=0 n : UTIMR (reload value) : Peripheral machine clock frequency (Varies depending on the gear) UCC 1=1 Maximum bps peripheral machine clock (CLKP): 25MHz, 1562500bps ● CLK synchronous mode bps = UCC 1=0 (2n+2) bps = n: UTIMR (reload value) : Peripheral machine clock frequency (Varies depending on the gear) UCC 1=1 (2n+3) Maximum bps peripheral machine clock (CLKP): 25MHz, 12500000bps Note: Please do not set UTIMR (reload register) to "0" when you use U-TIMER by Mode 2 (CLK synchronous mode) of UART as baud rate. 275 CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers 276 CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER This chapter describes the overview of the 16-bit freerunning and 16-bit reload timers, the configuration and functions of registers, and timer operation. 7.1 16-bit Free-Running Timer 7.2 16-bit Reload Timer 277 CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER 7.1 16-bit Free-Running Timer This section describes the overview of the 16-bit free-running timer, the configuration and functions of registers, and timer operation. ■ Overview of the 16-bit Free-running Timer The count value of the 16-bit free-running timer is used as the base time (of the base timer) for the output compare and input capture operations. 278 7.1.1 Structure of the 16-bit Free-Running Timer The 16-bit free-running timer consists of a 16-bit up counter and a control status register. • One of four count clocks can be selected. • An interrupt can be generated for a counter overflow. • The counter can be initialized on a match of the value for output compare register 0 when the mode setting allows the initialization. ■ 16-bit Free-running Timer Registers The 16-bit free-running timer registers are shown below. 15 14 13 12 11 10 9 8 T15 T14 T13 T12 T11 T10 T09 T08 7 6 5 4 3 2 1 0 T07 T06 T05 T04 T03 T02 T01 T00 7 ECLK 6 IVF 5 IVFE 4 STOP 3 MODE 2 CLR 1 CLK1 Timer data register (high-order bits) Timer data register (low-order bits) (TCDT) 0 Timer control status register CLK0 (low-order bits) (TCCS) ■ Block Diagram of the 16-bit Free-running Timer Figure 7.1-1 shows a block diagram of the 16-bit free-running timer. Figure 7.1-1 Block Diagram of the 16-bit Free-running Timer Interrupt ECLK IVF IVFE STOP MODE CLR CLK1 CLK0 Freq. divider FRC K R-bus Clock selector 16-bit free-running timer (TCDT) Clock To internal circuit (T15 to T00) Comparator 0 279 CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER 7.1.2 16-bit Free-Running Timer Registers This section describes the configuration and functions of the registers used by the 16bit free-running timer. ■ Timer Data Register (TCDT) The timer data register is used to read the count value of the 16-bit free-running timer. The bit configuration of the timer data register (TCDT) is shown below. TCDT Address: 0000D4H 15 14 13 12 11 10 9 8 Initial value T15 T14 T13 T12 T11 T10 T09 T08 0000H R/W R/W R/W R/W R/W R/W R/W R/W 7 T07 R/W 6 T06 R/W 5 T05 R/W 4 T04 R/W 3 T03 R/W 2 T02 R/W 1 T01 R/W 0 T00 R/W The counter value is cleared to "0000" when the counter is reset. A timer value can be set by writing a value to the timer data register. Always write a value to this register in stop mode (STOP = 1). This register must be accessed in word units. The 16-bit free-running timer is initialized when one of the following events occurs: 280 • Reset • Clearing (CLR) of the control status register • Match for the value of the compare clear register (compare register for ch0) and the value of the timer counter (A mode setting is required.) ■ Timer Control Status Register (TCCS) The bit configuration of the timer control status register (TCCS) is shown below. TCCS bit 7 Address: 0000D7H ECLK R/W Initial value (0) 6 5 4 3 2 1 0 IVF R/W (0) IVFE R/W (0) STOP R/W (0) MODE R/W (0) CLR R/W (0) CLK1 R/W (0) CLK0 R/W (0) [Bit 7] ECLK This bit is used to switch the count clock source for the 16-bit free-running timer between internal and external sources. Because the clock source is changed immediately after a value is written to the ECLK bit, the value of this bit must be changed while the output compare and input capture operations are stopped. ECLK Clock selection 0 Internal clock source (initial value) 1 Input clock from external pin (FRCK) Notes: • If the internal clock is selected, set the count clock using bits 1 and 0 (CLK1 and CLK0). The count clock becomes the base clock. To input an external clock from the FRCK pin, set the corresponding DDR bit to "0". • The minimum pulse width required for the external clock is 2.T (T stands for the peripheral clock machine cycle). If the external clock is specified and the output compare function is used, compare match output and an interrupt occur at the next clock cycle. Therefore, to generate the compare match output and interrupt, at least one clock pulse must be input after matching of values occurs. [Bit 6] IVF This bit is the interrupt request flag for the 16-bit free-running timer. This bit is set to "1" when the 16-bit free-running timer overflows or the counter is cleared because the values of the counter and compare register 0 compare match depending on the mode setting. An interrupt is generated if the interrupt request enable bit (bit 5 [IVFE]) is set. The IVF bit is cleared by writing "0". Writing "1" to the IVF bit is ignored. If a read modify write instruction is issued, "1" is always read from the IVF bit. IVF Interrupt request flag 0 Interrupt not requested (initial value) 1 Interrupt requested 281 CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER [Bit 5] IVFE This bit is the interrupt enable bit for the 16-bit free-running timer. An interrupt is generated when the IVFE bit is "1" and the interrupt flag (bit 6 [IVF]) is set to "1". IVFE Interrupt enable 0 Interrupts disabled (initial value) 1 Interrupts enabled [Bit 4] STOP This bit is used to stop the counting operation of the 16-bit free-running timer. Writing "1" to the STOP bit stops the counting operation of the 16-bit free-running timer. Writing "0" to the STOP bit starts the counting operation of the 16-bit free-running timer. STOP Counting operation 0 Counting enabled (started; initial value) 1 Counting disabled (stopped) Note: When the 16-bit free-running timer is stopped, the output compare operation is also stopped. [Bit 3] MODE This bit is used to set the initialization condition for the 16-bit free-running timer. When the MODE bit is "0", the counter value can be initialized by a reset or the clear bit (bit 2 [CLR]). When the MODE bit is "1", the counter value can be initialized by a reset, the clear bit (bit 2 [CLR]), or matching of the values of the counter and output compare register 0. MODE Counter initialization 0 Initialization by reset or clear bit (initial value) 1 Initialization by reset, clear bit, or compare register 0 Note: The counter value is initialized at the exact point at which the count value changes. 282 [Bit 2] CLR This bit is used to initialize the value of the 16-bit free-running timer to 0000H during timer operation. Writing "1" to the CLR bit initializes the counter to 0000H. Writing "0" to the CLR bit is ignored. The value read from the CLR bit is always 0. CLR Flag meaning 0 Invalid (initial value) 1 Initialization of counter value to 0000H Note: The counter value is initialized at the exact point at which the count value changes. To initialize the counter while the 16-bit free-running timer is stopped, write 0000H to the data register. [Bits 1 and 0] CLK1 and CLK0 These bits are used to select the count clock for the 16-bit free-running timer. Because the count clock is changed immediately after a value is written to the CLK1 and CLK0 bits, the value of these bits must be changed while the output compare and input capture operations are stopped. CLK1 CLK0 Count clock Φ=25MHz Φ=12.5MHz Φ=6.25MHz Φ=3.125MHz 0 0 Φ/4 160ns 320ns 640ns 1.28µs 0 1 Φ/16 640ns 1.28µs 2.56µs 5.12µs 1 0 Φ/32 1.28µs 2.56µs 5.12µs 10.24µs 1 1 Φ/64 2.56µs 5.12µs 10.24µs 20.48µs Φ: Machine clock 283 CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER 7.1.3 Operation of the 16-bit Free-Running Timer The 16-bit free-running timer starts counting from counter value 0000 after a reset. This counter value is used as the reference time for 16-bit output compare and 16-bit input capture operation. ■ Clearing of the Counter for the 16-bit Free-running Timer The counter is cleared when any of the following conditions occurs: • An overflow occurs. • The value of the counter compare matches the value of the compare clear register (the compare register for output compare ch0). (A mode setting is required). • A 1 is written to the CLR bit of the TCCS register during timer operation. • 0000H is written to the TCDT register while the timer is stopped. • A reset is performed. An interrupt can be generated when an overflow occurs or when the values of the counter correspond to the compare clear register 0. (A mode setting is required for the compare match interrupt.) Figure 7.1-2 shows how the counter is cleared for an overflow. Figure 7.1-3 shows how the counter is cleared on a compare match of the values for the counter and the compare clear register. Figure 7.1-2 Clearing of Counter for Overflow Counter value Time Reset Interrupt Figure 7.1-3 Clearing of Counter on Compare Match with Value of the Compare Clear Register Counter value FFFFH Match BFFFH Match 7FFFH 3FFFH Time 0000H Reset Compare register Interrupt 284 BFFFH ■ Timing of Clearing of the 16-bit Free-running Timer The counter is cleared by a reset or by software or on a match with the compare clear register. Clearing of the counter by a reset or by software is performed at the same time that the clearing occurs. However, for clearing on a match with the compare clear register 0, the counter is cleared synchronized with the count timing. Figure 7.1-4 shows the timing of clearing the 16-bit free-running timer. Figure 7.1-4 Timing of Clearing of the 16-bit Free-running Timer φ N Value of compare clear register Counter clearing Counter value N ■ Timing of 16-bit Free-running Timer Counting The 16-bit free-running timer counts up according to the input clock (internal or external clock). If an external clock is selected, the falling edge (indicated by a down arrow) of the external clock is synchronized with the system clock, then the 16-bit free-running timer counts up at the falling edge of the internal count clock. Figure 7.1-5 shows the timing of counting by the 16-bit free-running timer. Figure 7.1-5 Timing of 16-bit Free-running Timer Counting φ External clock input Internal count clock Counter value N N+1 Notes: • If setting of the interrupt request flag and counter clearing occur at the same time, setting of the interrupt request flag has priority over clearing of the counter and the clearing operation is ignored. • If "1" is written to bit 2 (counter initialization bit [CLR]) of the control status register, the written value is retained until the timing that clears the internal counter. The CLR bit is also cleared by the same timing. If writing "1" to the CLR bit occurs at the same time as the timing that clears the counter, writing "1" to the CLR bit has priority over clearing of the counter and the CLR bit remains "1" until the next timing for clearing the counter. • The counter clearing operation is valid only while the internal counter is operating (and the internal prescaler is also operating). To clear the counter while the counter is stopped, write 0000H to the timer count data register. 285 CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER 7.2 16-bit Reload Timer This section describes the overview of the 16-bit reload timer, the configuration and functions of registers, and timer operation. ■ Overview of the 16-bit Reload Timer The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, an internal count, a prescaler for clock generation, and a control register. 286 7.2.1 Structure of the 16-bit Reload Timer The clock source can be selected from three internal clocks (machine clocks divided by 2, 8, and 32. However, only ch3 can be selected up to machine clocks divided by 64 and 128.) and external event. • DMA transfer can be triggered by an interrupt. • Four channels for the 16-bit reload timer are built-in. • The MB91F353A/351A/352A/353A do not have timer output (TOT0 to TOT3). ■ 16-bit Reload Timer Registers The 16-bit reload timer registers are shown below. 15 14 13 12 11 10 9 8 - - Reserved CSL2 CSL1 CSL0 Reserved Reserved Control status register(TMCSR) (ch3 only) 7 6 5 4 3 2 1 0 Reserved - OUTL RELD INTE UF CNTE TRG 15 0 16-bit timer register (TMR) 15 0 16-bit reload register (TMRLR) 287 CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER ■ Block Diagram of the 16-bit Reload Timer Figure 7.2-1 is a block diagram of the 16-bit reload timer. Figure 7.2-1 Block Diagram of the 16-bit Reload Timer 16-bit reload register (TMRLR) 16 7 Reload 16 16-bit down counter (TMR) UF RELD OUTL OUT CTL. Count enable INTE Re-trigger UF R-bus CSL2 Clock selector 3 CSL1 CNTE CSL0 TRG EXCK External timer output (TOT0 to TOT3) IN CTL. T0E0 to T0E3 φ φ − − φ φ φ − − − Prescaler clearing (Channel 3 only) Peripheral machine clock input Note: The MB91F353A/351A/352A/353A do not have external timer output (TOT0 to TOT3). 288 IRQ Bits in PFRK 7.2.2 16-bit Reload Timer Register This section describes the configuration and functions of the registers used by the 16bit reload timer. ■ Control Status Register (TMCSR) The bit configuration of the control status register (TMCSR) is shown below. TMCSR Address : 00004EH 000056H 00005EH 0000AEH 15 14 13 - - (Reserved) - - 7 12 11 10 9 8 Initial value (CSL2) CSL1 CSL0 Reserved Reserved ----0000 00000000B (R/W) (R/W) R/W R/W R/W R/W 2 1 0 6 5 4 3 Reserved - OUTL RELD INTE UF CNTE TRG R/W R R/W R/W R/W R/W R/W R/W This register controls the 16-bit timer operation modes and interrupts. Rewrite bits other than UF, CNTE, and TRG only when CNTE = 0. Concurrent write to this register is allowed. [Bit 13] Reserved This bit is reserved. Be sure to set this bit to "0". This bit is available only for ch3 except channels 0, 1, and 2. [Bits 12, 11, and 10] CSL2, CSL1, CSL0 (Count source Select) These bits are the count source select bits. Count sources can be selected from internal clocks and external events. Table 7.2-1 shows the count sources that can be selected. The count effective edges are set using the MOD1 and MOD0 bits when external events are specified for count sources. The CSL2 register is not available for the reload timer (ch0 to ch2). The CSL2 register is only available for ch3, and up to divide-by 64 or 128 clock can be selected. Table 7.2-1 Count Sources Set Using the CSL Bits CSL2 CSL1 CSL0 Count source (φ: machine clock) 0 0 0 Internal clock φ/21 (ch0 to ch3) 0 0 1 Internal clock φ/23 (ch0 to ch3) 0 1 0 Internal clock φ/25 (ch0 to ch3) 0 1 1 Setting prohibited (ch0 to ch3) 1 0 1 Internal clock φ/26 (ch3 only) 1 1 0 Internal clock φ/27 (ch3 only) Settings not listed in the table above are prohibited. The CSL2 bit is not available for channels 0 to 2. 289 CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER [Bits 9, 8, 7] Reserved These bits are reserved. Be sure to set these bits to "0". [Bit 6] (Reserved) This bit is unused. The read value is always "0". [Bit 5] OUTL This bit sets the output level of the external timer. The output level is reversed depending on whether this bit is "1" or "0". Table 7.2-2 shows the settings of TOEx, OUTL, and RELD. Table 7.2-2 Settings of TOEx, OUTL, and RELD TOEx OUTL RELD Output waveform 0 × × Output prohibited 1 0 0 "H" level square wave while counting is in progress 1 1 0 "L" level square wave while counting is in progress 1 0 1 "L" level toggle output while the counting is started 1 1 1 "H" level toggle output while the counting is started × in the table indicates an arbitrary value. TOEx indicates TOE0 to TOE3 in PFR (Port Function Register). [Bit 4] RELD This bit is the reload enable bit. If it is set to "1", reload mode is entered. As soon as the counter value underflows from 0000H to FFFFH, the contents of the reload register are loaded into the counter and the count operation is continued. If this bit is set to "0", one-shot mode is entered and the count operation is stopped when the counter value underflows from 0000H to FFFFH. [Bit 3] INTE This bit is the interrupt request enable bit. If the INTE bit is set to "1", an interrupt request is generated when the UF bit is set to "1". If it is set to "0", no interrupt request is generated. [Bit 2] UF This bit is the timer interrupt request flag. This bit is set to "1" when the counter value underflows from 0000H to FFFFH. Write "0" to this bit to clear it. Writing "1" to this bit is meaningless. When this bit is read by a read modify write instruction, "1" is always read. [Bit 1] CNTE This bit is the count enable bit of the timer. Write "1" to this bit to enter the start trigger wait state. Write "0" to this bit to stop the count operation. [Bit 0] TRG This bit is the software trigger bit. Write "1" to this bit to generate a software trigger, load the contents of the reload register into the counter, and start the count operation. Writing "0" to this bit is meaningless. The read value is always "0". The trigger input to this register is valid only if CNTE=1. No operation occurs if CNTE=0. 290 ■ 16-bit Timer Register (TMR) The bit configuration of the 16-bit timer register (TMR) is shown below. TMR 15 Address : 00004AH 000052H 00005AH 0000AAH 0 Initial value XXXXH R R R R R R R R The 16-bit timer register is used to read the count value of the 16-bit timer. The initial value of this register is undefined. Be sure to use a 16-bit data transfer instruction to read this register. ■ 16-bit Reload Register (TMRLR) The bit configuration of the 16-bit reload register (TMRLR) is shown below. TMRLR 15 Address : 000048H 000050H 000058H 0000A8H 0 Initial value XXXXH W W W W W W W W The 16-bit reload register is used to retain the initial value of the count. The initial value of this register is undefined. Be sure to use a 16-bit data transfer instruction to write a value to this register. 291 CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER 7.2.3 Operation of the 16-bit Reload Register This section describes operation of the 16-bit reload register. ■ Clock Operation If the timer operates with a divide-by clock of the clock, one of the clocks generated by dividing the machine clock by 2, 8, or 32 can be selected as the count source. (In addition, in the case of ch3 only, up to divide-by 64 or 128 clock can be selected.) To start the count operation as soon as counting is enabled, write "1" to the CNTE and TRG bits of the control status register. Trigger input occurring due to the TRG bit is always valid regardless of the operating mode while the timer is running (CNTE=1). Figure 7.2-2 shows the startup and operations of the counter. After the counter start trigger is inputted, Time T (T: peripheral clock machine cycle) is required until the data of the reload register is loaded into the counter. Figure 7.2-2 Startup and Operations of the Counter Count clock Reload data Counter Data load CNTE (register) TRG (register) T 292 -1 -1 -1 ■ Underflow Operation An underflow is an event in which the counter value changes from 0000H to FFFFH. Thus, an underflow occurs at the count of [Reload register setting value + 1]. If the RELD bit of the control register is set to "1" when an underflow occurs, the contents of the reload register are loaded into the counter and the count operation is continued. If the RELD bit is set to "0", the counter stops at FFFFH. An underflow sets the UF bit of the control register and, if the INTE bit is set to "1", generates an interrupt request. Figure 7.2-3 shows the timing chart for the underflow operation. Figure 7.2-3 Timing Chart for the Underflow Operation Count clock Counter 0000H Reload data -1 -1 -1 Data load Underflow set [RELD=1] Count clock Counter 0000H FFFFH Underflow set [RELD=0] 293 CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER ■ Output Pin Function The TOT (0-3) output pin provides a toggle output that is inverted by an underflow in reload mode and a pulse output that indicates that counting is in progress in one-shot mode. The output polarity can be set using the OUTL bit of the register. If OUTL=0, toggle output is "0" for the initial value and the one-shot pulse output is "1" while the count operation is in progress. If OUTL=1, the output waveform is reversed. Note: The MB91F353A/351A/352A/353A do not have the TOT (0-3) output function. Figure 7.2-4 and Figure 7.2-5 show the timing charts for output pin function. Figure 7.2-4 Timing Chart for Output Pin Function (1) Count started Underflow Reversed if OUTL=1 TOT (0-3) General-purpose port CNTE Startup trigger [RELD=1, OUTL=0] Figure 7.2-5 Timing Chart for Output Pin Function (2) Count started Underflow TOT (0-3) Reversed if OUTL=1 General-purpose port CNTE Startup trigger Startup trigger wait status [RELD=0, OUTL=0] 294 ■ Operating States of the Counter The counter state is determined by the CNTE bit of the control register and the internal signal WAIT. The counter states that can be set include the stop state (STOP state; when CNTE = 0 and WAIT = 1), the startup trigger wait state (WAIT state; when CNTE = 1 and WAIT = 1), and the operation state (RUN state; when CNTE = 1 and WAIT = 0). Figure 7.2-6 shows the state transitions. Figure 7.2-6 Status Transitions of Counter State transition due to hardware Reset STOP CNTE=0, WAIT=1 State transition due to register access Counter: Holds the value when it stops; undefined just after reset CNTE='1' TRG='0' WAIT CNTE='1' TRG='1' CNTE=1, WAIT=1 Counter: Holds the value when it stops; undefined just after reset and until data is reloaded RUN RELD.UF TRG='1' CNTE=1, WAIT=0 Counter: Running TRG='1' LOAD CNTE=1, WAIT=0 Loads contents of reload register into counter. RELD.UF Load completed ■ Additional Information Because the TOT2 output of reload timer ch2 is connected to the A/D converter in the LSI chip, A/D conversion can be started in the cycle set in the reload register. Notes: • The internal prescaler is enabled if a trigger is applied when bit 1 (timer enable: CNTE) of the control status register is set to "1". • If the device attempts to set and clear the interrupt request flag at the same time, the flag is set and the clear operation becomes ineffective. • If the device attempts to write to the 16-bit reload timer register and reload the data into the 16-bit reload timer register at the same time, old data is loaded into the counter. New data is loaded into the counter at the next reload timing. • If the device attempts to load and count the 16-bit timer register at the same time, the load (reload) operation takes precedence. 295 CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER 296 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER This chapter gives an outline of the PPG (Programmable Pulse Generator) timer and explains the register configuration and functions and the timer operations. 8.1 Overview of the PPG Timer 8.2 PPG Timer Registers 8.3 Operation of the PPG Timer 297 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER 8.1 Overview of the PPG Timer The programmable pulse generator (PPG) efficiently outputs highly accurate PWM waveforms. The MB91F355A/355A/354A/F356B/F357B have six built-in PPG timer channels. The MB91F353A/351A/352A/353A have three built-in PPG timer channels. ■ Characteristics of PPG Timer • Each channel consists of a 16-bit down counter, 16-bit data register with a cycle setting buffer, 16-bit compare register with a duty setting buffer, and pin control block. • One of the four count clocks can be selected for the 16-bit down counter: • Peripheral system clock ∞ φ • φ/4 • φ/16 • φ/64 • A reset or counter borrow can initialize the counter value to "FFFFH". • Each channel has PPG output (PPG0 to PPG5). Note: The MB91F353A/351A/352A/353A have three channels for PPG output (PPG0, PPG2, and PPG4); it does not have PPG1, PPG3, and PPG5. • • • • Overview of registers • Cycle setting register: Data register for reload with buffer Data is transferred from the buffer when an activation trigger signal is detected and a counter borrow occurs. The PPG output is inverted when a counter borrow occurs. • Duty setting register: Compare register with buffer PPG output is inverted when the value of this register and the counter value match. Outline of pin control • Set to "1" when the duty matches (priority) • Reset to "0" when a counter borrow occurs. • Output-value fixed mode is available to facilitate output of all-"L" (or "H"). • The polarity can be specified. An interrupt request can be generated as one of the following combinations: • Activation of PPG timer (software trigger or trigger input) • Generation of counter borrow (cycle match) • Generation of duty match • Generation of counter borrow (cycle match) or duty match Multiple channels can be activated at one time by using software or other interval timers. Restart during operation can also be set. 298 ■ Registers of the PPG Timer Figure 8.1-1 shows the registers of the PPG timer. Figure 8.1-1 Registers of the PPG Timer Address 00000118H GCN10 0 Access R/W General Control Register 10 0000011BH GCN20 R/W General Control Register 20 00000120H PTMR0 R ch0 timer register 00000122H PCSR0 W ch0 cycle setting register 00000124H PDUT0 W ch0 duty setting register 00000126H 15 PCNH0 PCNL0 R/W ch0 control/status register 00000128H PTMR1 R ch1 timer register 0000012AH PCSR1 W ch1 cycle setting register 0000012CH PDUT1 W ch1 duty setting register 0000012EH PCNH1 PCNL1 R/W ch1 control/status register 00000130H PTMR2 R ch2 timer register 00000132H PCSR2 W ch2 cycle setting register 00000134H PDUT2 W ch2 duty setting register 00000136H PCNH2 PCNL2 R/W ch2 control/status register 00000138H PTMR3 R ch3 timer register 0000013AH PCSR3 W ch3 cycle setting register 0000013CH PDUT3 W ch3 duty setting register 0000013EH PCNH3 PCNL3 R/W ch3 control/status register 00000140H PTMR4 R ch4 timer register 00000142H PCSR4 W ch4 cycle setting register 00000144H PDUT4 W ch4 duty setting register 00000146H PCNH4 PCNL4 R/W ch4 control/status register 00000148H PTMR5 R ch5 timer register 0000014AH PCSR5 W ch5 cycle setting register 0000014CH PDUT5 W ch5 duty setting register 0000014EH PCNH5 PCNL5 R/W ch5 control/status register 299 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER ■ Block Diagram of the PPG Timer (Overall Configuration and One Channel) Figure 8.1-2 shows the overall block diagram of the PPG timer. Figure 8.1-2 Block Diagram of the PPG Timer (Overall Configuration) 16-bit reload timer channel 0 TRG input PPG timer channel 0 PPG0 TRG input PPG timer channel 1 PPG1 TRG input PPG timer channel 2 PPG2 TRG input PPG timer channel 3 PPG3 External TRG4 TRG input PPG timer channel 4 PPG4 External TRG5 TRG input PPG timer ch5 PPG5 16-bit reload timer channel 1 General control register 10 General control register 20 External TRG0 to TRG3 (source selection) 4 Note: The MB91F353A/351A/352A/353A do not have PPG1, PPG3, PPG5, and external TRG5. 300 Figure 8.1-3 shows a block diagram of one PPG timer channel. Figure 8.1-3 Block Diagram of the PPG Timer (One Channel) PCRS PDUT Prescaler 1/1 cmp CK Load 16-bit down counter 1/4 1/16 Start 1/64 Borrow PPG mask PPG output S Q Peripheral clock R Reverse bit Enable TRG input Edge detection Interrupt select IRQ Software trigger 301 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER 8.2 PPG Timer Registers This section describes the configuration and functions of the registers used by the PPG timer. ■ PPG Timer Registers The PPG timer uses the following six types of registers: 302 • Control status register • PPG cycle setting register (PCSR) • PPG duty setting register (PDUT) • PPG timer register (PTMR) • General control register 10 • General control register 20 8.2.1 Control Status Register On the MB91F353A/351A/352A/353A, setting of data in the control status registers for ch1, ch3, and ch5 is invalid. ■ Configurations of Control Status Registers The configurations of the control status registers are shown below. PCNH bit 15 Address : ch0 000126H CNTE ch1 00012EH R/W ch2 000136H 0 ch3 00013EH ch4 000146H ch5 00014EH 14 STGR R/W 13 MDSE R/W 12 RTRG R/W 11 CKS1 R/W 10 CKS0 R/W 9 PGMS R/W 8 - 0 0 X 0 X 0 X 0 X 0 - 6 EGS0 R/W 5 IREN R/W 4 IRQF R/W 3 IRS1 R/W 2 IRS0 R/W 1 - 0 X 0 0 0 X 0 X X - <- Attribute <- Initial value <- Rewrite during operation PCNL bit 7 Address : ch0 000127H EGS1 ch1 00012FH R/W ch2 000137H 0 ch3 00013EH X ch4 000147H ch5 00014FH 0 OSEL R/W <- Attribute 0 X <- Initial value <- Rewrite during operation [Bit 15] CNTE (Timer Enable) This bit enables operation of the 16-bit down counter. Value Meaning 0 Disabled (initial value) 1 Enabled [Bit 14] STGR (Software Trigger) Writing "1" into this bit applies software trigger. The read value is always "0". 303 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER [Bit 13] MDSE (Mode Select) This bit is used to select either the PWM mode in which continuous pulses are output or the one-shot mode in which a single pulse is output. Value Meaning 0 PWM mode (initial value) 1 One-shot mode [Bit 12] RTRG (Restart enable) This bit enables a restart resulting from a software trigger or trigger input. Value Meaning 0 Restart disabled (initial value) 1 Restart enabled [Bits 11 and 10] CKS1 and CKS0 (Counter Clock Select) These bits are used to select the count clock of the 16-bit down counter. CKS1 CKS0 Cycle 0 0 φ (initial value) 0 1 φ/4 1 0 φ/16 1 1 φ/64 φ: Peripheral machine clock [Bit 9] PGMS (PPG Output Mask Select) Writing "0" into this bit allows PPG output to be masked to "0" or "1", regardless of mode, cycle, and duty settings. Table 8.2-1 lists the PPG output states when "1" has been written to the PGMS bit. Table 8.2-1 PPG Output States when PGMS Bit is 1 Polarity PPG output Ordinary polarity "L" output Reverse polarity "H" output For all-"H" output in ordinary polarity mode or all-"L" output in reverse polarity mode, specify the same value in the cycle setting register and duty setting register in order to output the above mask value with the polarity reversed. 304 [Bit 8] (Unused bit) [Bits 7 and 6] EGS1 and EGS0 (Trigger Input Edge Select Bit) These bits are used to select an effective edge for the activation cause selected in general control register 1. Regardless of the mode that is selected, writing "1" to the bit of a software trigger enables the software trigger. EGS1 EGS0 Edge selection 0 0 Not effective (initial value) 0 1 Rising edge 1 0 Falling edge 1 1 Both edges [Bit 5] IREN (PPG Interrupt Request Enable) Value Meaning 0 Disabled (initial value) 1 Enabled [Bit 4] IRQF (PPG Interrupt Request Flag) If bit 5, IREN, is enabled and an interrupt source selected in bits 3 and 2, the IRS1 and IRS0, occurs then this bit is set and an interrupt request is generated and issued to the CPU. This bit is cleared if "0" is written to it. This bit remains unchanged if "1" is written to it. The read value by a read-modify-write instruction is always "1", regardless of the bit value. [Bits 3 and 2] IRS1, IRS0 (Interrupt Source Select) These bits are used to select a source that sets bit 4, the IRQF. IRS1 IRS0 Interrupt source 0 0 Software trigger or trigger input (initial value) 0 1 Occurrence of a counter borrow (cycle match) 1 0 Occurrence of a duty match 1 1 Occurrence of a counter borrow (cycle match) or duty match [Bit 1] (reserved) This bit is unused. 305 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER [Bit 0] OSEL: PPG Output Polarity Specification Bit This bit sets the polarity of the PPG output. The table below lists the polarity settings that can be specified by combinations of the OSEL bit and bit 9 (PGMS bit). PGMS OSEL 0 0 Ordinary polarity (initial value) 0 1 Reverse polarity 1 0 Output fixed to "L" 1 1 Output fixed to "H" Polarity Ordinary polarity Reverse polarity 306 PPG output After reset "L" output "H" output Duty match Counter borrow 8.2.2 PPG Cycle Setting Register (PCSR) The PPG cycle setting register (PCSR) is a register with a buffer for setting a cycle. On the MB91F353A/351A/352A/353A, setting of data in the PPG cycle setting registers for ch1, ch3, and ch5 is invalid. ■ Configuration of PPG Cycle Setting Register (PCSR) The configuration of the PPG cycle setting register (PCSR) is shown below. PCSR bit Address : ch0 000122H ch1 00012AH ch2 000132H ch3 00013AH ch4 000142H ch5 00014AH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Attribute→ Write only Initial value→ Undefined Data transfer from the buffer is performed as a counter borrow operation. Notes: • When initializing or rewriting the cycle setting register, be sure to write to the duty setting register after the writing of the cycle setting register. • This register must be accessed using 16-bit data. 307 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER 8.2.3 PPG Duty Setting Register (PDUT) The PPG duty setting register (PDUT) is a register that has a buffer for setting the duty. On the MB91F353A/351A/352A/353A, setting of data in the PPG duty setting registers for ch1, ch3, and ch5 is invalid. ■ Configuration of PPG Duty Setting Register (PDUT) The configuration of the PPG duty setting register (PDUT) is shown below. PDUT bit Address : ch0 000124H ch1 00012CH ch2 000134H ch3 00013CH ch4 000144H ch5 00014CH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Attribute→ Write only Initial value→ Undefined Data transfer from the buffer is performed as a counter borrow operation. When the same value is set in the cycle setting register and the duty setting register, all-"H" is outputted in ordinary polarity mode and all-"L" is outputted in reverse polarity mode. Notes: • Do not specify a smaller value in PCSR than that in PDUT. Otherwise, PPG output becomes undefined. • This register must be accessed using 16-bit data. 308 8.2.4 PPG Timer Register (PTMR) The PPG timer register (PTMR) is a register used to read the value of the 16-bit down counter. On the MB91F353A/351A/352A/353A, setting of data in the PPG timer registers for ch1, ch3, and ch5 is invalid. ■ Configuration of PPG Timer Register (PTMR) The configuration of the PPG timer register (PTMR) is shown below. PTMR bit Address : ch0 000120H ch1 000128H ch2 000130H ch3 000138H ch4 000140H ch5 000148H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Attribute→ Read only Initial value→ FFFFH Note: This register must be accessed using 16-bit data. 309 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER 8.2.5 General Control Register 10 General control register 10 is used to select the source of trigger input for the PPG timer. ■ Configuration of General Control Register 10 The configuration of general control register 10 is shown below. GCN10 Bit 15 Address: 000118H 14 13 12 11 10 TSEL33:30 9 8 TSEL23:20 Attribute Initial value R/W R/W R/W R/W R/W R/W R/W R/W 0 0 1 1 0 0 1 0 Bit 7 6 5 4 TSEL13:10 3 2 1 0 TSEL03:00 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 1 0 0 0 0 Attribute Initial value General control register 10 does not have functions corresponding to PPG timer channels 4 and 5. [Bits 15 to 12] TSEL33 to TSEL30: ch3 trigger input selection bits Note: On the MB91F353A/351A/352A/353A, specification of the ch3 trigger input selection bits is invalid. TSEL33 to 30 310 ch3 trigger input 0 0 0 0 EN0 bit of GCN2 0 0 0 1 EN1 bit of GCN2 0 0 1 0 EN2 bit of GCN2 0 0 1 1 EN3 bit of GCN2 (initial value) 0 1 0 0 16-bit reload timer ch0 0 1 0 1 16-bit reload timer ch1 0 1 1 × Setting not allowed 1 0 0 0 External TRG0 1 0 0 1 External TRG1 1 0 1 0 External TRG2 1 0 1 1 External TRG3 1 1 × × Setting not allowed [Bits 11 to 8] TSEL23 to TSEL20: ch2 trigger input selection bits TSEL23 to 20 ch2 trigger input 0 0 0 0 EN0 bit of GCN2 0 0 0 1 EN1 bit of GCN2 0 0 1 0 EN2 bit of GCN2 (initial value) 0 0 1 1 EN3 bit of GCN2 0 1 0 0 16-bit reload timer ch0 0 1 0 1 16-bit reload timer ch1 0 1 1 × Setting not allowed 1 0 0 0 External TRG0 1 0 0 1 External TRG1 1 0 1 0 External TRG2 1 0 1 1 External TRG3 1 1 × × Setting not allowed [Bits 7 to 4] TSEL13 to TSEL10: ch1 trigger input selection bits Note: On the MB91F353A/351A/352A/353A, specification of the ch1 trigger input selection bits is invalid. TSEL13 to 10 ch1 trigger input 0 0 0 0 EN0 bit of GCN2 0 0 0 1 EN1 bit of GCN2 (initial value) 0 0 1 0 EN2 bit of GCN2 0 0 1 1 EN3 bit of GCN2 0 1 0 0 16-bit reload timer ch0 0 1 0 1 16-bit reload timer ch1 0 1 1 × Setting not allowed 1 0 0 0 External TRG0 1 0 0 1 External TRG1 1 0 1 0 External TRG2 1 0 1 1 External TRG3 1 1 × × Setting not allowed 311 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER [Bits 3 to 0] TSEL03 to TSEL00: ch0 trigger input selection bits TSEL03 to 00 312 ch0 trigger input 0 0 0 0 EN0 bit of GCN2 (initial value) 0 0 0 1 EN1 bit of GCN2 0 0 1 0 EN2 bit of GCN2 0 0 1 1 EN3 bit of GCN2 0 1 0 0 16-bit reload timer ch0 0 1 0 1 16-bit reload timer ch1 0 1 1 × Setting not allowed 1 0 0 0 External TRG0 1 0 0 1 External TRG1 1 0 1 0 External TRG2 1 0 1 1 External TRG3 1 1 × × Setting not allowed 8.2.6 General Control Register 20 General control register 20 is used to generate a start trigger by the software. ■ Configuration of General Control Register 20 The configuration of general control register 20 is shown below. GCN20 bit Address : 00011BH 7 6 5 4 3 2 1 0 - - - - EN3 EN2 EN1 EN0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 <-- Attribute <-- Initial value General control register 20 does not have functions corresponding to PPG timer channels 4 and 5. If an EN bit of general control register 20 is selected by the GCN1 register, the value of general control register 20 is transferred to the PPG timer trigger input. To start multiple PPG timer channels at the same time, generate the edges selected by the ESG1 and ESG0 bits of the control status register by software. Note: Always write "0" to the bits 7 to 4 of general control register 20. 313 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER 8.3 Operation of the PPG Timer This section describes the PPG timer operation. ■ Precautions If the device attempts to set and clear the interrupt request flag at the same time, the flag is set and the clear operation becomes ineffective. The settings of bits 11 and 10 (count clock select bits CKS1 and CKS0) of the PPG control register are reflected immediately after data is written to the bits. Change the settings of the bits when counting stops. If the device attempts to load and count the PPG down counter (PPGC: 16-bit down counter) at the same time, the load operation takes precedence. 314 8.3.1 Timing Charts for PWM Operation This section describes the timing charts for PWM operation. ■ When Reactivation is Disabled Figure 8.3-1 shows the timing chart for PWM operation when reactivation is disabled. Figure 8.3-1 Timing Chart for PWM Operation with Reactivation Disabled Rising edge detection Trigger ignored Start Trigger m n 0 PPG (1) (2) (1) = T (n+1) ms (2) = T (m+1) ms T : Count clock cycle m : PCSR value n : PDUT value 315 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER ■ When Reactivation is Enabled Figure 8.3-2 shows the timing chart for PWM operation when reactivation is enabled. Figure 8.3-2 Timing Chart for PWM Operation with Reactivation Enabled Rising edge detection Trigger restarted Start Trigger m n 0 PPG (1) (2) (1) = T (n+1) ms (2) = T (m+1) ms T : Count clock cycle m : PCSR value n : PDUT value [PWM Mode] In PWM mode, the PPG timer can output pulses continuously after an activation trigger signal is detected. The output pulse cycle can be controlled by changing the PCSR value, and the duty ratio can be controlled by changing the PDUT value. Note: After data is written to PCSR, be sure to write data to PDUT. 316 8.3.2 Timing Charts for One-Shot Operation This section describes the timing charts for one-shot operation. ■ When Reactivation is Disabled Figure 8.3-3 shows the timing chart for one-shot operation when reactivation is disabled. Figure 8.3-3 Timing Chart for One-shot Operation with Reactivation Disabled Rising edge detection Trigger ignored Start Trigger m n 0 PPG (1) (1) = T (n+1) ms (2) = T (m+1) ms T : Count clock cycle m : PCSR value n : PDUT value (2) ■ When Reactivation is Enabled Figure 8.3-4 shows the timing chart for one-shot operation when reactivation is enabled. Figure 8.3-4 Timing Chart for One-shot Operation with Reactivation Enabled Rising edge detection Trigger restarted Start Trigger m n 0 PPG (1) (2) (1) = T (n+1) ms (2) = T (m+1) ms T : Count clock cycle m : PCSR value n : PDUT value [One-shot Mode] In one-shot mode, the PPG timer can output a single pulse of an arbitrary width when triggered. When reactivation is enabled, the PPG timer reloads the counter value after an edge is detected during operation. 317 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER 8.3.3 Interrupt Sources and Timing Chart (with PPG output set for ordinary polarity) This section shows the interrupt sources and timing chart. ■ Interrupt Sources and Timing Chart Figure 8.3-5 shows the interrupt sources and a timing chart. Figure 8.3-5 Interrupt Sources and Timing Chart Start Trigger 2.5T maximum Load Clock Count value 0003 0002 0001 0000 0003 PPG Interrupt Effective edge Duty match Counter borrow Note: It takes at most 2.5T (T stands for the count clock cycle) to load a count value after an activation trigger is input. 318 8.3.4 Examples of Methods of All-L and All-H PPG Output This section describes the methods used to perform all-L and all-H PPG output. ■ Examples of Methods Used to Perform All-L and All-H PPG Output Figure 8.3-6 shows examples of the methods used to perform all-L and all-H PPG output. Figure 8.3-6 Examples of Methods Used to Perform All-L and All-H PPG Output PPG Reduce the duty value. Using an interrupt by borrow, set the PGMS (mask bit) to "1". If the PGMS (mask bit) is set to "0" during use of an interrupt by borrow, the PWM waveform can be outputted without generating glitches. PPG Increase the duty value. Using an interrupt by compare match, write to the duty setting register the same values as that in the cycle setting register. 319 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER 8.3.5 Activation of Multiple Channels Using the General Control Register If multiple activation triggers are specified using the GCN1 register, multiple channels of PPG timer can be activated at the same time. This section provides an example of multiple-channel activation by software using the GCN2 register. ■ Activation Setting Procedure 1. Set a cycle in the PCSR register. 2. Set a duty in the PDUT register. • Be sure to perform setting in order given above. 3. Specify the sources of trigger input for the channels to be activated using the GCN1 register. • In this case, use the GCN2 register with the initial settings. • (ch0 → EN0, ch1 → EN1, ch2 → EN2, and ch3 → EN3) 4. Set required values in the control status registers for the channels to be activated as follows: • CNTE: 1 → Timer operation enabled • STGR: 0 → No activation (because the channel is activated according to GCN2) • MDSE: 0 → PWM operation • RTRG: 0 → Reactivation disabled • CSK1 and CSK0: 00 → Count clock = Φ • PGMS: 0 → Output not masked • (Bit 8: 0 → Any setting allowed, since this is an unused bit) • EGS1 and EGS0: 01 → Activation at rising edge • IREN: 1 → Interrupt request enabled • IRQF: 0 → Clearing of interrupt source • IRS1 and IRS0: 01 → Generation of interrupt request when counter borrow occurs • OSEL: 0 → Ordinary polarity 5. Write data to the GCN2 register to generate activation triggers. To activate channels 0 and 1 at the same time with the above settings, write "1" to the EN0 and EN1 bits of the GCN2 register. A rising edge is generated, and pulse signals are outputted from PPG0 and PPG1. To use the 16-bit reload timer for activation: Specify the 16-bit reload timer as a trigger input source in the GCN1 register in step 3), and activate the 16-bit reload timer in place of the GCN2 register in step 5). 320 The PPG timer can be reactivated at certain intervals when the output of the 16-bit reload timer is set for toggle output and the following settings are made in the control status register: RTRG: 1 → Reactivation enabled EGS1 and EGS0: 11 → Activation at both rising and falling edges 321 CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER 322 CHAPTER 9 INTERRUPT CONTROLLER This chapter describes the overview of the interrupt controller, the configuration and functions of registers, and interrupt controller operation. 9.1 Overview of the Interrupt Controller 9.2 Interrupt Controller Registers 9.3 Operation of the Interrupt Controller 323 CHAPTER 9 INTERRUPT CONTROLLER 9.1 Overview of the Interrupt Controller The interrupt controller controls interrupt acceptance and arbitration processing. ■ Hardware Configuration of the Interrupt Controller The interrupt controller module consists of the following components: • ICR register • Interrupt priority decision circuit • Interrupt level and interrupt number (vector) generator • HOLD request cancellation request generator ■ Major Functions of the Interrupt Controller The interrupt controller has the following major functions: 324 • Detecting NMI requests and interrupt requests • Deciding priority (using a level or number) • Passing to the CPU an interrupt level based on the decision result to provide information about the interrupt source • Passing to the CPU an interrupt number based on the decision result to provide information about the interrupt source • Instruction for return from stop mode due to the occurrence of an interrupt with an NMI/interrupt level other than 11111 (to CPU) • Generating a HOLD request cancellation request for the bus master ■ Interrupt Controller Registers Figure 9.1-1 shows the registers used by the interrupt controller. Figure 9.1-1 Interrupt Controller Registers bit 7 6 5 4 3 2 1 0 Address : 00000440H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR00 Address : 00000441H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR01 Address : 00000442H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR02 Address : 00000443H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR03 Address : 00000444H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR04 Address : 00000445H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR05 Address : 00000446H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR06 Address : 00000447H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR07 Address : 00000448H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR08 Address : 00000449H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR09 Address : 0000044AH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR10 Address : 0000044BH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR11 Address : 0000044CH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR12 Address : 0000044DH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR13 Address : 0000044EH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR14 Address : 0000044FH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR15 Address : 00000450H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR16 Address : 00000451H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR17 Address : 00000452H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR18 Address : 00000453H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR19 Address : 00000454H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR10 Address : 00000455H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR21 Address : 00000456H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR22 Address : 00000457H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR23 Address : 00000458H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR24 Address : 00000459H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR25 Address : 0000045AH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR26 Address : 0000045BH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR27 Address : 0000045CH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR28 Address : 0000045DH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR29 Address : 0000045EH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR30 Address : 0000045FH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR31 Address : 00000460H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR32 Address : 00000461H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR33 Address : 00000462H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR34 Address : 00000463H - - - ICR4 R ICR3 R/W ICR2 R/W ICR1 R/W ICR0 R/W ICR35 325 CHAPTER 9 INTERRUPT CONTROLLER (Continued) bit 326 7 6 5 4 3 2 1 0 Address : 00000464H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR36 Address : 00000465H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR37 Address : 00000466H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR38 Address : 00000467H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR39 Address : 00000468H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR40 Address : 00000469H - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR41 Address : 0000046AH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR42 Address : 0000046BH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR43 Address : 0000046CH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR44 Address : 0000046DH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR45 Address : 0000046EH - - - ICR4 ICR3 ICR2 ICR1 ICR0 ICR46 Address : 0000046FH - - - ICR4 R ICR3 R/W ICR2 R/W ICR1 R/W ICR0 R/W ICR47 Address : 00000045H MHALTI R/W - - LVL4 R LVL3 R/W LVL2 R/W LVL1 R/W LVL0 R/W HRCL ■ Block Diagram of the Interrupt Controller Figure 9.1-2 shows the block diagram of the interrupt controller. Figure 9.1-2 Block Diagram of the Interrupt Controller UNMI WAKEUP (LEVEL 11111: '1') Priority decision 5 LEVEL4 to 0 NMI processing LEVEL and VECTOR generation LEVEL decision RI00 ICR00 RI47 (DLYIRQ) ICR47 . . . . . . VECTOR decision 6 HLDREQ cancellation request MHALTI VCT5 to 0 R-bus 327 CHAPTER 9 INTERRUPT CONTROLLER 9.2 Interrupt Controller Registers This section describes the configuration and functions of the registers used by the interrupt controller. ■ Details of the Interrupt Controller Registers The interrupt controller uses the following two types of registers: 328 • Interrupt control register (ICR) • Hold request cancellation request register (HRCL) 9.2.1 Interrupt Control Register (ICR) An interrupt control register (ICR) is provided for each of the interrupt input and sets the interrupt level of the corresponding interrupt request. ■ Bit Configuration of the Interrupt Control Register (ICR) The bit configuration of the interrupt control register (ICR) is shown below. bit 7 6 5 4 3 2 1 0 Initial value - - - ICR4 R ICR3 R/W ICR2 R/W ICR1 R/W ICR0 R/W ---11111 [Bits 4 to 0] ICR4 to 0 These bits, which are the interrupt level setting bits, specify the interrupt level of the corresponding interrupt request. If an interrupt request has an interrupt level defined in this register that exceeds the level mask value defined in the ILM register of the CPU, it is masked by the CPU. These bits are initialized to 11111B by a reset. Table 9.2-1 shows the correspondence between possible interrupt level setting bits and interrupt levels. 329 CHAPTER 9 INTERRUPT CONTROLLER Table 9.2-1 Correspondence Between Possible Interrupt Level Setting Bits and Interrupt Levels ICR4 * ICR3 ICR2 ICR1 ICR0 Interrupt level 0 0 0 0 0 0 0 1 1 1 0 14 0 1 1 1 1 15 NMI 1 0 0 0 0 16 Maximum level that can be set 1 0 0 0 1 17 1 0 0 1 0 18 1 0 0 1 1 19 1 0 1 0 0 20 1 0 1 0 1 21 1 0 1 1 0 22 1 0 1 1 1 23 1 1 0 0 0 24 1 1 0 0 1 25 1 1 0 1 0 26 1 1 0 1 1 27 1 1 1 0 0 28 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31 Reserved for system *: ICR4 is always 1; 0 cannot be written to this bit. 330 (High) (Low) Interrupt disabled 9.2.2 Hold request cancellation request register (HRCL) The hold request cancellation request register (HRCL) is used to set an interrupt level for generating a hold request cancellation request. ■ Bit Configuration of the Hold Request Cancellation Request Register (HRCL) The bit configuration of the hold request cancellation request register (HRCL) is shown below. bit Address :00000045H 7 6 5 4 3 2 1 0 MHALTI - - LVL4 LVL3 LVL2 LVL1 LVL0 R R/W R/W R/W R/W R/W HRCL 0--11111 (Initial value) [Bit 7] MHALTI This bit is the DMA transfer disable bit controlled by an NMI request. An NMI request sets this bit to "1". Write "0" to this bit to clear it. At the end of an NMI routine, clear this bit the same way it would be cleared in a normal interrupt routine. [Bits 4 to 0] LVL4 to 0 These bits set the interrupt level used to issue a hold request cancellation request to the bus master. If an interrupt request with a higher level than the level defined in the HRCL register occurs, a hold request cancellation request is issued to the bus master. The LVL4 bit is always "1"; "0" cannot be written to this bit. 331 CHAPTER 9 INTERRUPT CONTROLLER 9.3 Operation of the Interrupt Controller This section describes interrupt controller operation. ■ Priority Decision When multiple interrupt sources exist at the same time, the interrupt controller module selects the interrupt source that has the highest priority and outputs the interrupt level and interrupt number of the selected interrupt source to the CPU. The following shows the priority decision criteria for interrupt sources: 1. NMI 2. Source that meets the following conditions: • Source with a value other than 31 as the interrupt level (31 means interrupts disabled) • Source with the smallest value for the interrupt level • Source with the smallest interrupt number that satisfies the both conditions above If no interrupt source is selected according to the above decision criteria, 31 (11111B) is outputted as the interrupt level. The interrupt number at this time is undefined. Table 9.3-1 shows the relationship among interrupt sources, interrupt numbers, and interrupt levels. Table 9.3-1 Relationship Among Interrupt Sources, Interrupt Numbers, and Interrupt Levels (1 / 4) Interrupt number Interrupt source Interrupt level Offset Default address of TBR RN Decimal Hexadecimal Reset 0 00 − 3FCH 000FFFFCH − Mode vector 1 01 − 3F8H 000FFFF8H − Reserved for system 2 02 − 3F4H 000FFFF4H − Reserved for system 3 03 − 3F0H 000FFFF0H − Reserved for system 4 04 − 3ECH 000FFFECH − Reserved for system 5 05 − 3E8H 000FFFE8H − Reserved for system 6 06 − 3E4H 000FFFE4H − No-coprocessor trap 7 07 − 3E0H 000FFFE0H − Coprocessor error trap 8 08 − 3DCH 000FFFDCH − INTE instruction 9 09 − 3D8H 000FFFD8H − Instruction break exception 10 0A − 3D4H 000FFFD4H − Operand break trap 11 0B − 3D0H 000FFFD0H − Step trace trap 12 0C − 3CCH 000FFFCCH − 332 Table 9.3-1 Relationship Among Interrupt Sources, Interrupt Numbers, and Interrupt Levels (2 / 4) Interrupt number Interrupt source Interrupt level Offset Default address of TBR RN Decimal Hexadecimal NMI request (tool) 13 0D − 3C8H 000FFFC8H − Undefined instruction exception 14 0E − 3C4H 000FFFC4H − NMI request 15 0F Always 15 (FH) 3C0H 000FFFC0H − External Interrupt 0 16 10 ICR00 3BCH 000FFFBCH 6 External Interrupt 1 17 11 ICR01 3B8H 000FFFB8H 7 External Interrupt 2 18 12 ICR02 3B4H 000FFFB4H 11 External Interrupt 3 19 13 ICR03 3B0H 000FFFB0H − External interrupt 4 20 14 ICR04 3ACH 000FFFACH − External interrupt 5 21 15 ICR05 3A8H 000FFFA8H − External interrupt 6 22 16 ICR06 3A4H 000FFFA4H − External interrupt 7 23 17 ICR07 3A0H 000FFFA0H − Reload timer 0 24 18 ICR08 39CH 000FFF9CH 8 Reload timer 1 25 19 ICR09 398H 000FFF98H 9 Reload timer 2 26 1A ICR10 394H 000FFF94H 10 UART0 (reception completed) 27 1B ICR11 390H 000FFF90H 0 UART1 (reception completed) 28 1C ICR12 38CH 000FFF8CH 1 UART2 (reception completed) 29 1D ICR13 388H 000FFF88H 2 UART0 (transmission completed) 30 1E ICR14 384H 000FFF84H 3 UART1 (transmission completed) 31 1F ICR15 380H 000FFF80H 4 UART2 (transmission completed) 32 20 ICR16 37CH 000FFF7CH 5 DMAC0 (end, error) 33 21 ICR17 378H 000FFF78H − DMAC1 (end, error) 34 22 ICR18 374H 000FFF74H − DMAC2 (end, error) 35 23 ICR19 370H 000FFF70H − DMAC3 (end, error) 36 24 ICR20 36CH 000FFF6CH − DMAC4 (end, error) 37 25 ICR21 368H 000FFF68H − A/D 38 26 ICR22 364H 000FFF64H 15 333 CHAPTER 9 INTERRUPT CONTROLLER Table 9.3-1 Relationship Among Interrupt Sources, Interrupt Numbers, and Interrupt Levels (3 / 4) Interrupt number Interrupt source Interrupt level Offset Default address of TBR RN Decimal Hexadecimal I2C 39 27 ICR23 360H 000FFF60H − UART4*1 (reception completed) 40 28 ICR24 35CH 000FFF5CH − SIO 5*1 41 29 ICR25 358H 000FFF58H 12 SIO 6 42 2A ICR26 354H 000FFF54H 13 SIO 7 43 2B ICR27 350H 000FFF50H 14 UART3 (reception completed) 44 2C ICR28 34CH 000FFF4CH − UART3 (transmission completed) 45 2D ICR29 348H 000FFF48H − Reload timer 3 or main oscillation stabilization wait timer 46 2E ICR30 344H 000FFF44H − Timebase timer overflow 47 2F ICR31 340H 000FFF40H − External interrupt 8-15 *2 48 30 ICR32 33CH 000FFF3CH − Watch counter 49 31 ICR33 338H 000FFF38H − U/D counter 0 50 32 ICR34 334H 000FFF34H − U/D counter 1 *2 51 33 ICR35 330H 000FFF30H − PPG 0/1 52 34 ICR36 32CH 000FFF2CH − PPG 2/3 53 35 ICR37 328H 000FFF28H − PPG 4/5 54 36 ICR38 324H 000FFF24H − 16-bit free-running timer 55 37 ICR39 320H 000FFF20H − ICU 0 (fetching) 56 38 ICR40 31CH 000FFF1CH − ICU 1 (fetching) or UART4*2 (transmission completed) 57 39 ICR41 318H 000FFF18H − ICU 2/3 (fetching) 58 3A ICR42 314H 000FFF14H − OCU0/1 (matching) 59 3B ICR43 310H 000FFF10H − OCU2/3 (matching) 60 3C ICR44 30CH 000FFF0CH − OCU4/5*2 (matching) 61 3D ICR45 308H 000FFF08H − OCU6/7*2 (matching) 62 3E ICR46 304H 000FFF04H − Delayed interrupt source bit 63 3F ICR47 300H 000FFF00H − 334 Table 9.3-1 Relationship Among Interrupt Sources, Interrupt Numbers, and Interrupt Levels (4 / 4) Interrupt number Interrupt source Interrupt level Offset Default address of TBR RN Decimal Hexadecimal Reserved for system (used in REALOS) 64 40 − 2FCH 000FFEFCH − Reserved for system (used in REALOS) 65 41 − 2F8H 000FFEF8H − Reserved for system 66 42 − 2F4H 000FFEF4H − Reserved for system 67 43 − 2F0H 000FFEF0H − Reserved for system 68 44 − 2ECH 000FFEECH − Reserved for system 69 45 − 2E8H 000FFEE8H − Reserved for system 70 46 − 2E4H 000FFEE4H − Reserved for system 71 47 − 2E0H 000FFEE0H − Reserved for system 72 48 − 2DCH 000FFEDCH − Reserved for system 73 49 − 2D8H 000FFED8H − Reserved for system 74 4A − 2D4H 000FFED4H − Reserved for system 75 4B − 2D0H 000FFED0H − Reserved for system 76 4C − 2CCH 000FFECCH − Reserved for system 77 4D − 2C8H 000FFEC8H − Reserved for system 78 4E − 2C4H 000FFEC4H − Reserved for system 79 4F − 2C0H 000FFEC0H − Used in INT instruction 80 to 255 50 to FF − 2BCH to 000H 000FFEBCH to 000FFC00H − * 1: The MB91F353A/351A/352A/353A do not have the UART4 and SI05 interrupt sources. The MB91F353A/351A/352A/353A do not have the interrupt sources that are external interrupts 8-15, U/D counter 1, UART4, OCU4/5, and OCU6/7 *2: 335 CHAPTER 9 INTERRUPT CONTROLLER ■ NMI (Non Maskable Interrupt) An NMI (Non Maskable Interrupt) has the highest priority among the interrupt sources handled by this module. Thus, an NMI is always selected if it occurs at the same time as other interrupt sources. ● Occurrence of NMI If an NMI occurs, the following information is reported to the CPU: Interrupt level: 15 (01111B) Interrupt number: 15 (0001111B) ● Detecting an NMI The external interrupt and NMI module set and detect an NMI. This module only generates an interrupt level, interrupt number, and MHALTI in response to an NMI request. ● Preventing a DMA transfer occurring due to an NMI If an NMI request occurs, the MHALTI bit of the HRCL register is set to "1" to prevent DMA transfer. To clear the state preventing DMA transfer, clear the MHALTI bit to "0" at the end of the NMI routine. 336 ■ Hold Request Cancellation Request (HRLC: Hold Request Cancel Request) For an interrupt with a higher priority to be processed during CPU hold, the device that has generated the hold request must cancel the request. Set in the HRCL register the interrupt level to be used as the criterion of generating a cancellation request. ● Generation criteria If an interrupt source with a higher interrupt level than the level defined in the HRCL register occurs, a hold request cancellation request is generated. If the interrupt level of the HRCL register is greater than the interrupt level after a priority decision, a cancellation request occurs. If the interrupt level of the HRCL register is equal to or less than the interrupt level after a priority decision, no cancellation request occurs. Because the cancellation request remains valid, no DMA transfer occurs unless the interrupt source that has caused the cancellation request is cleared. Be sure to clear the corresponding interrupt source. If an NMI is used, the cancellation request is valid because the MHALTI bit of the HRCL register is set to "1". ● Possible levels Values that can be set in the HRCL register range from 10000B to 11111B, which is the same range as for the ICR. If this register is set to 11111B, an interrupt request is issued for all the interrupt levels. If this register is set to 10000B, an interrupt request is issued only for an NMI. Table 9.3-2 shows the settings of interrupt levels at which a hold request cancellation request occurs. Table 9.3-2 Settings of Interrupt Levels at which Hold Request Cancellation Request Occurs HRCL register Interrupt levels at which a cancellation request occurs 16 NMI only 17 NMI and Interrupt level 16 18 NMI and Interrupt levels 16 to 17 to to 31 NMI and Interrupt levels 16 to 30 [initial value] After a reset, since DMA transfer is not allowed at any interrupt level, no DMA transfer is performed if an interrupt has occurred. Be sure to set the HRCL register to the necessary value. 337 CHAPTER 9 INTERRUPT CONTROLLER ■ Return from Standby Mode (Sleep/Stop) This module implements a function that causes a return from stop mode if an interrupt request occurs. If at least one interrupt request that includes NMI occurs (with an interrupt level other than 11111) from the peripheral, a return request from stop mode is generated for the clock controller. Since the priority decision unit restarts operation when a clock is supplied after returning from stop, the CPU executes instructions until the result of the priority decision unit is obtained. The same operation occurs after a return from the sleep state. Registers in this module can be accessed even in the sleep state. Notes: • The device returns from stop mode if an NMI request is issued. However, set an NMI so that valid input can be detected in the stop state. • Provide an interrupt level of 11111 in the corresponding peripheral control register for an interrupt source that you do not want to cause return from stop or sleep. (5) Clearing an interrupt source. ■ Example of Using the Hold Request Cancellation Request Function (HRCR) To allow the CPU to perform high-priority processing during DMA transfer, cancel a hold request for DMA and clear the hold state. In this example, an interrupt is used to cancel a hold request to the DMA, allowing the CPU to perform priority operations. ● Control registers 1. Hold request cancellation level setting register (HRCL): This module If an interrupt with a higher interrupt level than the level defined in this register occurs, a hold request cancellation request is issued to DMA. This register sets the level to be used as the criterion for this purpose. 2. ICR: This module This register sets a higher level than the level in the HRCL register for the ICR corresponding to the interrupt source that will be used. ● Hardware configuration Figure 9.3-1 shows the flow of the signals that are related to the hold request. Figure 9.3-1 Flow of Signals Related to Hold Request This module IRQ Bus access request MHALTI I-UNIT DHREQ DMA B-UNIT CPU (ICR) (HRCL) 338 DHACK DHREQ: D bus hold request DHACK: D bus hold acknowledge IRQ: Interrupt request MHALTI: Hold request cancellation request ● Sequence Figure 9.3-2 shows an INTC-2 interrupt level that is higher than the one set in the HRCL register. Figure 9.3-2 Interrupt Level (HRCL < ICR) [LEVEL] RUN Bus hold Bus hold (DMA transfer) Interrupt processing DHREQ Example of interrupt routine (1) Interrupt source clear DHACK (2) RETI CPU Bus access request (1) (2) to IRQ LEVEL MHALTI If an interrupt request occurs, the interrupt level changes. If the interrupt level is higher than the level defined in the HRCL register, MHALTI becomes active for DMA. This causes DMA to cancel an access request and the CPU to return from the hold state to perform the interrupt processing. Figure 9.3-3 shows the INTC-2 interrupt levels when there are multiple interrupts. Figure 9.3-3 INT-C3 Interrupt Levels (HRCL < ICR [interrupt I] < ICR [interrupt II]) RUN Bus hold Interrupt processing II Interrupt I CPU (3) (4) Interrupt processing I (1) Bus hold (DMA transfer) (2) Bus access request DHREQ DHACK IRQ1 IRQ2 LEVEL MHALTI [Example of interrupt routine] (1), (3) Interrupt source clear to (2), (4) RETI In the above example, while interrupt routine I is being executed, an interrupt with a higher priority occurs. While the interrupt with a higher level than the level in the HRCL register occurs, DHREQ is low. Note: Be especially careful about the relationship between interrupt levels defined in the HRCL register and ICR. 339 CHAPTER 9 INTERRUPT CONTROLLER 340 CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER This chapter describes the overview of the external interrupt and NMI controller, the configuration and functions of registers, and operation of the external interrupt and NMI controller. 10.1 Overview of the External Interrupt and NMI Controller 10.2 External Interrupt and NMI Controller Registers 10.3 Operation of the External Interrupt and NMI Controller 341 CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER 10.1 Overview of the External Interrupt and NMI Controller The external interrupt controller is a block that controls external interrupt requests input to NMI and INT0 to INT15. "H" level, "L" level, rising edge, or falling edge can be selected as the level of a request to be detected (except for NMI). Note: INT8 to INT15 is not supported for MB91F353A/351A/352A/353A. ■ External Interrupt and NMI Controller Registers The registers for the external interrupt and NMI controller are shown below. bit bit bit bit 7 EN7 6 EN6 5 EN5 4 EN4 3 EN3 2 EN2 1 EN1 0 EN0 15 ER7 14 ER6 13 ER5 12 ER4 11 ER3 10 ER2 9 ER1 8 ER0 15 LB7 14 LA7 13 LB6 12 LA6 11 LB5 10 LA5 9 LB4 8 LA4 7 LB3 6 LA3 5 LB2 4 LA2 3 LB1 2 LA1 1 LB0 0 LA0 Enable interrupt register (ENIR) External interrupt request register (EIRR) External level register (ELVR) The above registers (for eight channels) are provided in two sets for a total of 16 channels. 342 ■ Block Diagram of the External Interrupt and NMI Controller Figure 10.1-1 is a block diagram of the external interrupt and NMI controller. Figure 10.1-1 Block Diagram of the External Interrupt and NMI Controller R-bus 8 Interrupt request 17 8 Enable interrupt register Gate Source F/F Edge detection circuit 17 INT0 to INT15 NMI External interrupt request register 16 External level register 343 CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER 10.2 External Interrupt and NMI Controller Registers This section describes the configuration and functions of the registers used by the external interrupt and NMI controller. ■ Details of the Registers for the External Interrupt and NMI Controller The external interrupt and NMI controller uses the following three types of registers: 344 • Enable interrupt request register (ENIRn) • External interrupt request register (EIRRn) • External level register (ELVRn) 10.2.1 Enable Interrupt Request Register (ENIRn) Enable interrupt request register (ENIRn) controls masking of external interrupt request output. ■ Bit Configuration of Enable Interrupt Request Register (ENIRn) The bit configuration of enable interrupt request register is shown below. bit ENIR0 address :000041H 7 6 5 4 3 2 1 0 Initial value EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 00000000B [R/W] bit 7 ENIR1 address :0000D1H EN15 6 5 4 3 2 1 0 Initial value EN14 EN13 EN12 EN11 EN10 EN9 EN8 00000000B [R/W] Output for an interrupt request is enabled based on the bit in this register to which "1" has been written (INT0 enable is controlled by EN0), after which the interrupt request is output to the interrupt controller. The pin corresponding to the bit to which "0" is written holds the interrupt source but does not generate a request to the interrupt controller. No mask bit exists for NMI. 345 CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER 10.2.2 External Interrupt Request Register (EIRRn) The external interrupt request register (EIRRn) indicates the presence or absence of a corresponding external interrupt request when reading from this register and the contents of the flip-flop (NMI flag) that indicates this interrupt request are cleared when writing to this register. ■ Bit Configuration of External Interrupt Request Register (EIRRn) The bit configuration of the external interrupt request register is shown below. bit EIRR0 address :000040H 15 14 13 12 11 10 9 8 Initial value ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 00000000B [R/W] bit 15 EIRR1 address :0000D0H ER15 14 13 12 11 10 9 8 Initial value ER14 ER13 ER12 ER11 ER10 ER9 ER8 00000000B [R/W] When the EIRR register is read, operation depends on the value that is read. If the value read from a bit is "1", there is an external interrupt request at the pin corresponding to the bit. Write "0" to this register to clear the request flip-flop of the corresponding bit. Writing "1" to this has no effect. For a read by a read modify write instruction, "1" is read. The NMI flag cannot be read or written to by a user. Note: For details on the NMI flag, see Figure 10.3-4 in Section "10.3 Operation of the External Interrupt and NMI Controller". 346 10.2.3 External Level Register (ELVRn) The external level register (ELVRn) specifies how a request is detected. ■ Bit Configuration of External Level Register (ELVRn) The bit configuration of the external level register is shown below. bit ELVR0 address :000042H bit 000043H 15 14 13 12 11 10 9 8 Initial value LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 00000000B 7 6 5 4 3 2 1 0 Initial value LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 00000000B [R/W] bit 15 ELVR1 address :0000D2H LB15 bit 7 000043H LB11 14 13 12 11 10 9 8 Initial value LA15 LB14 LA14 LB13 LA13 LB12 LA12 00000000B 6 5 4 3 2 1 0 Initial value LA11 LB10 LA10 LB9 LA9 LB8 LA8 00000000B [R/W] 2 bits of the ELVRn register are assigned to each of INT0 to INT15, and level settings are as shown below. Even though the bits of the EIRR are cleared while the request input is level-base operation, the pertinent bits are set again as long as the input is at the level that is active. Table 10.2-1 lists the assignment of ELVR. Table 10.2-1 Assignment of ELVR LBx LAx Operation 0 0 "L" level indicates the existence of a request. 0 1 "H" level indicates the existence of a request. 1 0 A rising edge indicates the existence of a request. 1 1 A falling edge indicates the existence of a request. A falling edge is always detected at NMI (except in the stop state). In the stop state, the "L" level is detected. 347 CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER 10.3 Operation of the External Interrupt and NMI Controller This section describes operation of the external interrupt and NMI controller. ■ Operation of an External Interrupt If, after the required data is set in the ENIR and ELVR registers, a request defined in the ELVR register is input to the corresponding pin, this module generates an interrupt request signal to the interrupt controller. For simultaneous interrupt requests from resources, the interrupt controller determines the interrupt request with the highest priority and generates an interrupt for it. Figure 10.3-1 shows external interrupt operation. Figure 10.3-1 External Interrupt Operation External interrupt ELVR Resource request Interrupt controller ENIR IL ICR y y EIRR CPU CMP ICR x x CMP ILM Source ■ Return from Standby To use an external interrupt to return from the standby state in the clock stop mode, use an "H" level or "L" level request as the input request. If you use an edge request, the device does not return from the stop state in clock stop mode. ■ Operating Procedure for an External Interrupt Set up a register located inside the external interrupt controller as follows: 1. Terminal and general-purpose I/O port used as external interrupt input are set to input port. 2. Disable the target bit in the enable register. 3. Set the target bit in the request level setting register. 4. Clear the target bit in the interrupt source register. 5. Enable the target bit in the enable register. Simultaneous writing of 16-bit data is supported for steps 4 and 5. Before setting a register in this module, you must disable the enable register. In addition, before enabling the enable register, you must clear the interrupt source register. This procedure is required to prevent an interrupt source from occurring by mistake while a register is being set or an interrupt is enabled. 348 ■ External Interrupt Request Level If the request level is an edge request, a pulse width of at least three machine cycles (peripheral clock machine cycles) is required to detect an edge. If the request level is a level setting, and request input arrives from outside and is then cancelled, the request to the interrupt controller remains active because a source holding circuit exists internally. The interrupt source register must be cleared to cancel a request to the interrupt controller. Figure 10.3-2 shows the operation that clears the source holding circuit when a level is set. Figure 10.3-2 Clearing the Source Holding Circuit when a Level is Set Interrupt input Source F/F (Source holding circuit) Level detection Enable gate Interrupt controller Holds a source while it is not cleared Figure 10.3-3 shows the timing of an interrupt source and interrupt request to the interrupt controller when interrupts are enabled. Figure 10.3-3 Interrupt Source and Interrupt Request to Interrupt Controller when Interrupts are Enabled "H" level Interrupt input Interrupt request to interrupt controller Becomes inactive when source F/F is cleared ■ NMI • An NMI has priority over all other user interrupts, and cannot be masked. However, if an NMI is activated before it is set in ILM, the CPU does not accept the NMI but only detects the NMI source. The NMI source is then held until ILM is set to the level that allows the NMI to be accepted. For this reason, before using an NMI, be sure to set ILM to 16 or more after a reset. • • An NMI is accepted under the following conditions: • Normal: Falling edge • STOP mode: "L" level An NMI can be used to clear stop mode. Inputting the "L" level in the stop state clears the stop state and causes the oscillation stabilization wait time to start. The NMI request detector has an NMI flag that is set for an NMI request and is cleared only if an interrupt for the NMI itself is accepted or a reset occurs. Note that this bit is not readable or writable. Figure 10.3-4 shows the NMI request detection. 349 CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER Figure 10.3-4 NMI Request Detection (NMI flag) NMI request (Stop clearing) Q SX R 0 Falling edge detection 1 STOP φ clear (RST, interrupt acknowledge) 350 NMI CHAPTER 11 REALOS-RELATED HARDWARE This chapter describes the hardware related to REALOS. The REALOS-related hardware is used by the real-time operating system (OS). Accordingly, when REALOS is used, the REALOS-related hardware cannot be used by a user program. 11.1 Delayed Interrupt Module 11.2 Bit Search Module 351 CHAPTER 11 REALOS-RELATED HARDWARE 11.1 Delayed Interrupt Module This section describes the overview of the delayed interrupt module, the configuration and functions of registers, and module operation. ■ Overview of the Delayed Interrupt Module The delayed interrupt module generates an interrupt for switching tasks. Use this module to enable a software program to generate an interrupt request to the CPU and to clear the request. 352 11.1.1 Overview of the Delayed Interrupt Module This section describes the delayed interrupt module, the configuration and functions of its register, and module operation. ■ Register for the Delayed Interrupt Module The register for the delayed interrupt module is shown below. bit 7 6 5 4 3 2 1 Address : 00000044H - - - - - - - 0 DLYI DICR [R/W] ■ Block Diagram of the Delayed Interrupt Module Figure 11.1-1 is a block diagram of the delayed interrupt module. Figure 11.1-1 Block Diagram of the Delayed Interrupt Module R-bus Interrupt request DLYI 353 CHAPTER 11 REALOS-RELATED HARDWARE 11.1.2 Delayed Interrupt Module Registers This section describes the configuration and functions of the registers used by the delayed interrupt module. ■ Delayed Interrupt Module Register (DICR: Delayed Interrupt Module Register) The delayed interrupt module register (DICR) controls delayed interrupts. The bit configuration of the delayed interrupt module register (DICR) is shown below. Bi t 7 6 5 4 3 2 1 0 - - - - - - - DLYI [R/W] -------0B(initial value) [Bit 0] DLYI DLYI Description 0 A delayed interrupt source is cleared or no request exists. [initial value] 1 A delayed interrupt source is generated. This bit controls generation and clearing of the relevant interrupt source. 354 11.1.3 Operation of the Delayed Interrupt Module A delayed interrupt refers to an interrupt generated for switching tasks. Use this function to allow a software program to generate an interrupt request for the CPU or to clear an interrupt request. ■ Interrupt Number A delayed interrupt is assigned to the interrupt source corresponding to the largest interrupt number. On the MB91350A, a delayed interrupt is assigned to interrupt number 63 (3FH). ■ DLYI Bit of DICR Write "1" to this bit to generate a delayed interrupt source. Write "0" to it to clear a delayed interrupt source. This bit is the same as the interrupt source flag for a normal interrupt. Therefore, clear this bit and switch tasks in the interrupt routine. 355 CHAPTER 11 REALOS-RELATED HARDWARE 11.2 Bit Search Module This section describes the overview of the bit search module, the configuration and functions of registers, and module operation. ■ Overview of the Bit Search Module The bit search module searches the data written to an input register for bit values "0" or "1" or points at which the bit value changes and returns the locations where these are detected. 356 11.2.1 Overview of the Bit Search Module This section explains the configuration and functions of the registers used by the bit search module. ■ Bit Search Module Registers The registers for the bit search module are shown below. 31 0 Address : 000003F0H BSD0 0 detection data register Address : 000003F4H BSD1 1 detection data register Address : 000003F8H BSDC Change point detection data register Address : 000003FCH BSRR Detection result register ■ Block Diagram of the Bit Search Module Figure 11.2-1 is a block diagram of the bit search module. Figure 11.2-1 Block Diagram of the Bit Search Module D-bus Input latch Address decoder Detection mode 1 detection data coding Bit search circuit Detection result 357 CHAPTER 11 REALOS-RELATED HARDWARE 11.2.2 Bit Search Module Registers This section describes the configuration and functions of the registers used by the bit search module. ■ 0 Detection Data Register (BSD0) 0 detection is performed for the written data. The configuration of the 0 detection data register (BSD0) is shown below. 31 0 000003F0H Read/write Initial value →W → Undefined The initial value after a reset is undefined. The read value is undefined. Use a 32-bit length data transfer instruction for data transfer. (Do not use 8-bit or 16-bit length data transfer instructions.) ■ 1 Detection Data Register (BSD1) The configuration of the 1 detection data register (BSD1) is shown below. 31 0 000003F4H Read/write Initial value → R/W → Undefined Use a 32-bit length data transfer instruction for data transfer. (Do not use 8-bit or 16-bit length data transfer instructions.) • Writing 1 detection is performed for the written data. • Reading Save data of the internal state for the bit search module is read. This register is used to save and restore the original state when the bit search module is used by, for example, an interrupt handler. Even though data is written to the 0 detection or change point detection data register, data can be saved and restored only by using the 1 detection data register. The initial value after a reset is undefined. 358 ■ Change Point Detection Data Register (BSDC) Change point detection is performed for the written data. The configuration of the change point detection data register (BSDC) is shown below. 31 0 000003F8H Read/write Initial value →W → Undefined The initial value after a reset is undefined. The read value is undefined. Use a 32-bit length data transfer instruction for data transfer. (Do not use 8-bit or 16-bit length data transfer instructions.) ■ Detection Result Register (BSRR) 0,1,or a change point is detected. What is detected depends on the data register that wrote date last. The configuration of the detection result register (BSRR) is shown below. 31 0 000003FCH Read/write Initial value →R → Undefined 359 CHAPTER 11 REALOS-RELATED HARDWARE 11.2.3 Operation of the Bit Search Module This section describes operation of the bit search module. ■ 0 Detection The bit search module scans data written to the 0 detection data register from the MSB to LSB and returns the location where the first 0 is detected. The detection result can be obtained by reading the detection result register. The relationship between the detected location and the return value is given in Table 11.2-1 . If a 0 is not found (that is, the value is FFFFFFFFH), 32 is returned as the search result. [Execution example] Write data 11111111111111111111000000000000B 11111000010010011110000010101010B 10000000000000101010101010101010B 11111111111111111111111111111111B Read value (decimal) (FFFFF000H) (F849E0AAH) (8002AAAAH) (FFFFFFFFH → 20 →5 →1 → 32 ■ 1 Detection The bit search module scans data written to the 1 detection data register from the MSB to LSB and returns the location where the first 1 is detected. The detection result can be obtained by reading the detection result register. The relationship between the detected location and the return value is given in Table 11.2-1 . If a 1 is not found (that is, the value is 00000000H), 32 is returned as the search result. [Execution example] Write data 00100000000000000000000000000000B 00000001001000110100010101100111B 00000000000000111111111111111111B 00000000000000000000000000000001B 00000000000000000000000000000000B 360 Read value (decimal) (20000000H) (01234567H) (0003FFFFH) (00000001H) (00000000H) →2 →7 → 14 → 31 → 32 ■ Change Point Detection The bit search module scans data written to the change point detection data register from bit 30 to the LSB for comparison with the MSB value. The first location where a value that is different from that of the MSB is detected is returned. The detection result can be obtained by reading the detection result register. The relationship between the detected location and the return value is given in Table 11.2-1 . If a change point is not detected, 32 is returned. In change point detection, 0 is never returned as a result. [Execution example] Write data Read value (decimal) →2 →7 → 14 → 31 → 32 → 20 →5 →1 → 32 (20000000H) (01234567H) (0003FFFFH) (00000001H) (00000000H) (FFFFF000H) (F849E0AAH) (8002AAAAH) (FFFFFFFFH) 00100000000000000000000000000000B 00000001001000110100010101100111B 00000000000000111111111111111111B 00000000000000000000000000000001B 00000000000000000000000000000000B 11111111111111111111000000000000B 11111000010010011110000010101010B 10000000000000101010101010101010B 11111111111111111111111111111111B Table 11.2-1 lists bit locations and the corresponding return values (decimal). Table 11.2-1 Bit Locations and Return Values (decimal) Detected bit location Return value Detected bit location Return value Detected bit location Return value Detected bit location Return value 31 0 23 8 15 16 7 24 30 1 22 9 14 17 6 25 29 2 21 10 13 18 5 26 28 3 20 11 12 19 4 27 27 4 19 12 11 20 3 28 26 5 18 13 10 21 2 29 25 6 17 14 9 22 1 30 24 7 16 15 8 23 0 31 Not found 32 361 CHAPTER 11 REALOS-RELATED HARDWARE ■ Save/Restore Processing If it is necessary to save and restore the internal state of the bit search module, such as when the bit search module is used in an interrupt handler, use the following procedure: 1. Read the 1 detection data register and save its contents (save). 2. Use the bit search module. 3. Write the data saved in 1) to the 1 detection data register (restore). With the above operation, the value obtained when the detection result register is read the next time corresponds to the value written to the bit search module before 1). If the data register written to last is the 0 detection or change point detection register, the value is restored correctly with the above procedure. 362 CHAPTER 12 A/D CONVERTER This chapter describes the overview of the A/D converter, the configuration and functions of registers, and converter operation. 12.1 Overview of the A/D Converter 12.2 A/D Converter Registers 12.3 Operation of the A/D Converter 363 CHAPTER 12 A/D CONVERTER 12.1 Overview of the A/D Converter The A/D converter converts an analog input voltage into digital value. This section describes the A/D converter. ■ Features of the A/D Converter The A/D converter has the following features: • Conversion time: Minimum of 1.48 µs per channel • Serial/parallel conversion system with a sample & hold circuit • Resolution of 10 bits (switchable between 8 bits and 10 bits) • Selection of analog input from 12 channels by a program Note: The MB91F353A/351A/352A/353A have only eight input channels. • Conversion modes Single conversion mode: Converts the input on a selected channel. Scan conversion mode: Scan the input on up to 4 channels, and converts the input. • Storage of converted data in a data buffer (A total of four data buffers are provided.) • Possible generation of an interrupt request to the CPU to indicate the end of A/D conversion (DMA transfer can be started by this interrupt request.) • Selection of the conversion activation source from a program, external trigger (falling edge), and reload timer channel 2 (rising edge) ■ Overview of the A/D Converter Registers The A/D converter registers are shown below. Bit Address: 000078H 15 8 7 ADCS2 Address: 00007AH 364 0 ADCS1 Control status register Conversion time setting register ADCT Address: 00007CH ADTH0 ADTL0 Converted-data register 0 Address: 00007EH ADTH1 ADTL1 Converted-data register 1 Address: 000080H ADTH2 ADTL2 Converted-data register 2 Address: 000082H ADTH3 ADTL3 Converted-data register 3 ■ Block Diagram of the A/D Converter Figure 12.1-1 shows a block diagram of the A/D converter. Note: The MB91F353A/351A/352A/353A do not have analog inputs AN8 to AN11. Figure 12.1-1 Block Diagram of the A/D Converter Analog input AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 M P X S/H 10-bit A/D converter Control logic circuit M P X ADT0 ADT1 ADT2 ADT3 R-bus AVCC, AVRH, AVCC, AVRL Interrupt Reload timer channel 2 External input 365 CHAPTER 12 A/D CONVERTER 12.2 A/D Converter Registers This section describes the configuration and functions of the registers used by the A/D converter. ■ A/D Converter Registers The A/D converter uses the following four types of registers: 366 • Control status register (ADCS1) • Control status register (ADCS2) • Conversion time setting register (ADCT) • Data registers (ADTHx and ADTLx) 12.2.1 Control Status Register (ADCS1) The control status register (ADCS1) controls the A/D converter and indicates its status. ■ Bit Configuration of the Control Status Register (ADCS1) The bit configuration of the control status register (ADCS1) is shown below. bit Address : 000079H 7 BUSY 0 6 INT 0 5 INTE 0 4 - 3 STS1 0 2 STS0 0 1 STAR 0 Reserved 0 ADCS1 0 R/W R/W R/W - R/W R/W R/W R/W <− Initial value <− Bit attribute [Bit 7] BUSY (busy) Read values Value Meaning 0 A/D converter stopped 1 A/D converter operating Written values Value Meaning 0 Forcible stopping of A/D converter 1 Invalid Do not start the A/D converter by software and forcibly stop it at the same time (by writing "1" to the STAR bit and "0" to the BUSY bit). If a read modify write instruction is issued, "1" is always read from the BUSY bit. The BUSY bit is cleared to "0" by a reset. 367 CHAPTER 12 A/D CONVERTER [Bit 6] INT (interrupt) This INT bit is set when conversion ends. (It is set when conversion of the input on a channel ends in single conversion mode or when conversion of all input on all the specified channels ends in scan conversion mode.) Value Meaning 0 Interrupt request not found 1 Interrupt request found The INT bit is cleared by writing "0" to it or by clearing of a DMA transfer interrupt, or at the start of conversion or by a reset. Writing "1" to the INT bit is invalid. If a read modify write instruction is issued, "1" is always read from the INT bit. [Bit 5] INTE (interrupt enable) The INTE bit specifies whether to enable or disable the interrupt that indicates the end of conversion. Value Meaning 0 Interrupt disabled 1 Interrupt enabled Set the INTE bit to "1" for automatic transfer by DMA. The INTE bit is initialized to "0" by a reset. [Bit 4] (unused) This bit is not used. [Bits 3 and 2] STS1 and STS0 (start select) The STS1 and STS0 bits specify the A/D converter activation source. STS1 STS0 Function 0 0 Start by software 0 1 Start by external pin trigger or software 1 0 Start by reload timer or software 1 1 Start by external pin trigger, reload timer, or software In the mode in which multiple types of activation sources are allowed, the A/D converter is started by the source that occurs first. All of the activation sources that occur while the A/D converter is operating (BUSY = 1) are ignored. (This means the A/D converter cannot be restarted during operation.) To restart the A/D converter, stop the A/D conversion by writing "0" to the BUSY bit, then restart it. When an external trigger is used for starting, the falling edge is detected. When the reload timer is used for starting, the rising edge is detected. The STS1 and STS0 bits are cleared to "00" by a reset. 368 [Bit 1] STAR (start) Writing "1" to the STAR bit starts the A/D converter. Writing "1" to the STAR bit while the A/D converter is operating (BUSY = 1) is ignored. The value read from the STAR bit is always "0". Do not start the A/D converter by software and forcibly stop it at the same time (by writing "1" to the STAR bit and "0" to the BUSY bit). [Bit 0] (reserved) Always write "0" to this bit. 369 CHAPTER 12 A/D CONVERTER 12.2.2 Control Status Register (ADCS2) The control status register (ADCS2) controls the A/D converter and indicates its status. ■ Bit Configuration of the Control Status Register (ADCS2) The bit configuration of the control status register (ADCS2) is shown below. bit Address : 000078H 15 ACS3 0 14 ACS2 0 13 ACS1 0 12 ACS0 0 11 - 10 - R/W R/W R/W R/W - - 9 8 CREG SCAN ADCS2 0 0 <− Initial value <− Bit attribute R/W R/W [Bits 15 to 12] ACS3 to ACS0 (analog channel set) The ACS3 to ACS0 bits specify the channels that are to be targets of A/D conversion. • In single conversion mode, these bits specify one channel as the target of conversion. • In scan conversion mode, these bits specify the channel on which scanning is to start (see Section "12.3 Operation of the A/D Converter"). - If a channel from AN0 to AN3 is specified, the channels from the specified channel to AN3 are scanned and converted. - If a channel from AN4 to AN7 is specified, the channels from the specified channel to AN7 are scanned and converted. - If a channel from AN8 to AN11 is specified, the channels from the specified channel to AN11 are scanned and converted. • The register in which converted data is stored depends on the channel that is converted. Note that the same data registers are used to store the data converted from three groups of channels (AN0 to AN3, AN4 to AN7, and AN8 to AN11). If, for example, channel AN4 or AN8 is converted after the AN0 channel has been converted, the data converted from AN4 or AN8 is written over the stored data converted from AN0, corrupting the data converted from AN0. • The ACS3 to ACS0 bits must not be set to a value from 1100B to 1111B. If any of these values is written to these bits, the data set in data registers ADTH0 to ADTH3 is corrupted. 370 ACS3 ACS2 ACS1 ACS0 Channel Corresponding data register Remarks 0 0 0 0 AN0 ADTH0, ADTL0 0 0 0 1 AN1 ADAH1, ADTL1 0 0 1 0 AN2 ADTH2, ADTL2 0 0 1 1 AN3 ADTH3, ADTL3 0 1 0 0 AN4 ADTH0, ADTL0 0 1 0 1 AN5 ADAH1, ADTL1 0 1 1 0 AN6 ADTH2, ADTL2 0 1 1 1 AN7 ADTH3, ADTL3 1 0 0 0 AN8 ADTH0, ADTL0 1 0 0 1 AN9 ADAH1, ADTL1 1 0 1 0 AN10 ADTH2, ADTL2 1 0 1 1 AN11 ADTH3, ADTL3 1 1 0 0 - - Setting not allowed 1 1 0 1 - - Setting not allowed 1 1 1 0 - - Setting not allowed 1 1 1 1 - - Setting not allowed Note: Because the MB91F353A/351A/352A/353A do not have channels AN8, AN9, AN10, and AN11, the corresponding channel settings are not allowed on the MB91F353A/351A/352A/353A. [Bits 11 and 10] (unused) These bits are not used. [Bit 9] CREG The CREG bit specifies the number of bits of the data to be stored as the result of A/D conversion. [0: 10-bit mode] The high-order two bits of the converted data are stored in the ADTHx register, and the low-order eight bits are stored in the ADTLx register. [1: 8-bit mode] The high-order eight bits of the converted data are stored in the ADTLx register. The CREG bit is cleared to "0" by a reset. 371 CHAPTER 12 A/D CONVERTER [Bit 8] SCAN The SCAN bit specifies the conversion mode. The SCAN bit is cleared to "0" by a reset. Value 372 Function 0 Single conversion mode 1 Scan conversion mode 12.2.3 Conversion Time Setting Register (ADCT) The conversion time setting register (ADCT) specifies the lengths of sampling period and conversion periods a to c (see Figure 12.2-1 ). The width of each period is calculated from "(value set in register × 2 + 1) × 0.04 µs" for a peripheral clock of 25 MHz. The ADCT register must be accessed in 16-bit or 32-bit units. Since the value of this register is undefined when it is reset, be sure to set data in the ADCT register before starting the A/D converter. ■ Bit Configuration of the Conversion Time Setting Register (ADCT) The bit configuration of the conversion time setting register (ADCT) is shown below. bit Address : 00007AH bit 7 CV13 X 6 CV12 X 5 CV11 X 4 CV10 X 3 CV23 X 2 CV22 X 1 CV21 X R/W R/W R/W R/W R/W R/W R/W 15 SMP3 X 14 SMP2 X 13 SMP1 X 12 SMP0 X 11 CV03 X 10 CV02 X 9 CV01 X R/W R/W R/W R/W R/W R/W R/W 0 CV20 X <− Initial value <− Bit attribute R/W 8 CV00 X <− Initial value R/W <− Bit attribute Figure 12.2-1 shows the conversion time. Figure 12.2-1 Conversion Time Sampling period Conversion Conversion period b period a Start of A/D conversion Conversion period c End of conversion (generation of interrupt) [Bits 15 to 12] SMP3 to SMP0 (sampling time) The SMP3 to SMP0 bits specify the length of the sampling period. [Bits 11 to 8] CV03 to CV00 (convert time a) The CV03 to CV00 bits specify the length of the conversion period a. [Bits 7 to 4] CV13 to CV10 (convert time b) The CV13 to CV10 bits specify the length of the conversion period b. [Bits 3 to 0] CV23 to CV20 (convert time c) The CV23 to CV20 bits specify the length of the conversion period c. 373 CHAPTER 12 A/D CONVERTER Note: The A/D conversion time per channel from the start of conversion to the end of conversion is "sampling time + conversion time a + conversion time b + conversion time c + 3 machine cycles". ■ Recommended ADCT Register Value If the peripheral system clock is 25 MHz, the value shown below is recommended as the value to be set in the ADCT register. (Set each of the sampling time, conversion time a, conversion time b, and conversion time c to be 245 ns or more.) ADCT 0101 0011 B 0011 0100 B Sampling time + Conversion time a + Conversion time b + Conversion time c + 3 = 37 cycles(1.48µs) (5×2+1) (4×2+1) (3×2+1) (3×2+1) 374 12.2.4 Data Registers (ADTHx and ADTLx) The data registers (ADTHx and ADTLx) store the digital value that is the result of conversion. ■ Overview of the Data Registers (ADTHx and ADTLx) The format of data storage in the data registers depends on the value of the CREG bit of the ADCS2 register. (The format can be switched regardless of whether A/D conversion is in progress.) The data stored in the data registers is updated at the end of every conversion operation. The data registers normally store the data that was converted most recently. When the data registers are reset, their contents are undefined. ● When the GREG bit is "0": When the GREG bit is "0", the bit configurations of the data registers are as shown below. bit Address : 00007DH 00007FH 000081H 000083H 7 D7 X 6 D6 X 5 D5 X 4 D4 X 3 D3 X 2 D2 X 1 D1 X 0 D0 X R R R R R R R R bit Address : 00007CH 00007EH 000080H 000082H 15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 D9 X 8 D8 X - - - - - - R R ATDLx <− Initial value <− Bit attribute ATDHx <− Initial value <− Bit attribute The ADTHx register corresponds to the high-order two bits of the converted data, and the ADTLx register corresponds to the low-order eight bits of the converted data. Th l df bit 15 t 10 f th ADTL i t "0" ● When the GREG bit is "1": When the GREG bit is 1, the bit configurations of the data registers are as shown below. bit Address : 00007DH 00007FH 000081H 000083H 7 D7 X 6 D6 X 5 D5 X 4 D4 X 3 D3 X 2 D2 X 1 D1 X 0 D0 X R R R R R R R R bit Address : 00007CH 00007EH 000080H 000082H 15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 - - - - - - - - ATDLx <− Initial value <− Bit attribute ATDHx <− Initial value <− Bit attribute The ADTLx register corresponds to the high-order eight bits of the converted data. The value read from the ADTHx register is 00H. 375 CHAPTER 12 A/D CONVERTER 12.3 Operation of the A/D Converter The A/D converter uses a 10-bit serial/parallel conversion system and can convert data in a period as short as 1.48 µs. The A/D converter provides two conversion modes (single conversion and scan conversion modes), which can be selected. ■ Single Conversion Mode The A/D converter enters the single conversion mode when the SCAN bit of the control status register is set to "0". In single conversion mode, the A/D converter converts the analog input specified by the ACS2 to ACS0 bits of the control status register, then ends conversion. Figure 12.3-1 shows the conversion operation in single conversion mode. Example: Value of ACS bits = 010B (specifying channel AN2) Figure 12.3-1 Single Conversion Mode Example: Value of ACS bits = 010B (specifies channel AN2) STAR INT Start of A/D conversion End of A/D conversion A/D conversion period The A/D converter converts the analog input on channel AN2 and sets the INT bit when conversion ends. The interrupt request flag is set at the end of every conversion operation. 376 ■ Scan Conversion Mode The A/D converter enters the scan conversion mode when the SCAN bit of the control status register is set to "1". In scan conversion mode, the A/D converter starts scanning and conversion with the analog input channel specified by the ACS2 to ACS0 bits of the control status register. The analog input channel to end scanning and conversion depends on the setting in the ACS2 to ACS0 bits. Up to 4 channels can be scanned and converted at a time. Table 12.3-1 lists the channel settings available in scan conversion mode. Table 12.3-1 Channel Settings in Scan Conversion Mode ACS3 ACS2 ACS1 ACS0 Start channel End channel Remarks 0 0 0 0 AN0 AN3 Scan conversion of 4 channels 0 0 0 1 AN1 AN3 Scan conversion of 3 channels 0 0 1 0 AN2 AN3 Scan conversion of 2 channels 0 0 1 1 AN3 AN3 Single conversion of 1 channel 0 1 0 0 AN4 AN7 Scan conversion of 4 channels 0 1 0 1 AN5 AN7 Scan conversion of 3 channels 0 1 1 0 AN6 AN7 Scan conversion of 2 channels 0 1 1 1 AN7 AN7 Single conversion of 1 channel 1 0 0 0 AN8 AN11 Scan conversion of 4 channels 1 0 0 1 AN9 AN11 Scan conversion of 3 channels 1 0 1 0 AN10 AN11 Scan conversion of 2 channels 1 0 1 1 AN11 AN11 Single conversion of 1 channel 1 1 0 0 - - Setting not allowed 1 1 0 1 - - Setting not allowed 1 1 1 0 - - Setting not allowed 1 1 1 1 - - Setting not allowed *: Because the MB91F353A/351A/352A/353A do not have channels AN8, AN9, AN10, and AN11, the corresponding channel settings are not allowed on the MB91F353A/351A/352A/353A. 377 CHAPTER 12 A/D CONVERTER Figure 12.3-2 shows the conversion operation in scan conversion mode. Figure 12.3-2 Scan Conversion Mode Example: Value of ACS bits = 010B (specifies scan conversion of channels AN0 to AN3) STAR INT Start of A/D conversion Conversion of channel AN0 End of A/D conversion Conversion of channel AN1 Conversion Conversion of channel of channel AN2 AN3 Sequential conversion The A/D converter converts the analog input on channels AN0 to AN3 sequentially, and sets the INT bit when conversion of all channels ends. The interrupt request flag is set at the end of every conversion operation. 378 CHAPTER 13 8-BIT D/A CONVERTER This chapter describes the overview of the 8-bit D/A converter, the configuration and functions of registers, and converter operation. 13.1 Overview of the 8-bit D/A Converter 13.2 8-bit D/A Converter Register 13.3 8-bit D/A Converter Operation 379 CHAPTER 13 8-BIT D/A CONVERTER 13.1 Overview of the 8-bit D/A Converter The MB91350A has 3 channels of D/A converters with 8-bit resolution. The output of each channel can be controlled separately using the D/A control registers. Note: The MB91F353A/351A/352A/353A have 2 channels of D/A converters. ■ Features of the 8-bit D/A Converter The 8-bit D/A converter has the following features: • Power-down function • 3.3 V interface ■ 8-bit D/A Converter Registers The 8-bit D/A converter registers are shown below. Note: The MB91F353A/351A/352A/353A do not have DADR2 and DACR2. 380 7 6 5 4 3 2 1 0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 7 6 5 4 3 2 1 0 - - - - - - - DAE D/A data registers 0 to 2 (DADR0 to DADR2) D/A control registers 0 to 2 (DACR0 to DACR2) ■ Block Diagram of the 8-bit D/A Converter Figure 13.1-1 shows a block diagram of the 8-bit D/A converter. Note: The MB91F353A/351A/352A/353A do not have D/A converter ch2. Figure 13.1-1 Block Diagram of the 8-bit D/A Converter R-bus D/A control register D/A data register 0 D/A data register 1 DAE1 DAE0 PD DAE2 PD STOP STOP D/A data register 2 D/A converter channel 0 D/A output 0 D/A converter channel 1 D/A output 1 PL STOP D/A converter channel 2 D/A output 2 381 CHAPTER 13 8-BIT D/A CONVERTER 13.2 8-bit D/A Converter Register This section describes the configuration and functions of the registers used by the 8-bit D/A converter. ■ DADR0 (D/A Data Register 0) The bit configuration of the D/A data register 0 (DADR0) is shown below. bit Address : 00008BH 7 DA7 R/W 6 DA6 R/W 5 DA5 R/W 4 DA4 R/W 3 DA3 R/W 2 DA2 R/W 1 DA1 R/W • D/A data register 0 specifies the output voltage of D/A converter ch0. • This register is not initialized by a reset. 0 DA0 R/W Initial value XXH ■ DADR1 (D/A Data Register 1) The bit configuration of the D/A data register 1 (DADR1) is shown below. bit Address : 00008AH 7 DA7 R/W 6 DA6 R/W 5 DA5 R/W 4 DA4 R/W 3 DA3 R/W 2 DA2 R/W 1 DA1 R/W 0 DA0 R/W • The D/A data register 1 specifies the output voltage of D/A converter ch1. • This register is not initialized by a reset. Initial value XXH ■ DADR2 (D/A Data Register 2) The bit configuration of D/A data register 2 (DADR2) is shown below. Note: The MB91F353A/351A/352A/353A do not have DADR2. bit Address : 000089H 382 7 DA7 R/W 6 DA6 R/W 5 DA5 R/W 4 DA4 R/W 3 DA3 R/W 2 DA2 R/W 1 DA1 R/W • D/A data register 2 specifies the output voltage of D/A converter ch2. • This register is not initialized by a reset. 0 DA0 R/W Initial value XXH ■ DACR0 (D/A Control Register 0) The bit configuration of D/A control register 0 (DACR0) is shown below. bit Address : 000087H 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DAE R/W Initial value 00B D/A control register 0 specifies whether to enable or disable output from D/A converter ch0. Value Meaning 0 D/A output disabled (0.0 V output) 1 D/A output enabled ■ DACR1 (D/A Control Register 1) The bit configuration of the D/A control register 1 (DACR1) is shown below. bit Address : 000086H 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DAE R/W Initial value 00B D/A control register 1 specifies whether to enable or disable output from D/A converter ch1. Value Meaning 0 D/A output disabled (0.0 V output) 1 D/A output enabled ■ DACR2 (D/A Control Register 2) The bit configuration of the D/A control register 2 (DACR2) is shown below. Note: The MB91F353A/351A/352A/353A do not have DACR2. bit Address : 000085H 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DAE R/W Initial value 00B D/A control register 2 specifies whether to enable or disable output from D/A converter ch2. Value Meaning 0 D/A output disabled (0.0 V output) 1 D/A output enabled 383 CHAPTER 13 8-BIT D/A CONVERTER 13.3 8-bit D/A Converter Operation The 8-bit D/A converter outputs the D/A output value set in the D/A data register when 1 is set in the D/A control register. If D/A output from an 8-bit D/A converter channel is disabled, that channel outputs 0.0 V. Such an output also applies to the operation in stop mode. In output-enabled status, the D/A converter output voltage ranges from 0 V to 255/256 × DAVC V. The range of output voltage can be changed by external adjustment of the DAVC pin. ■ Logical Expressions for D/A Converter Output Voltage Table 13.3-1 lists the logical expressions used to calculate the D/A converter output voltage. Table 13.3-1 Logical Expressions for D/A Converter Output Voltage Values specified in DADR0 DADR1 DADR2 D/A converter output 00H 0/256 × DAVC (=0V) 01H 1/256 x DAVC 02H 2/256 x DAVC to to FDH 253/256 x DAVC FEH 254/256 x DAVC FFH 255/256 x DAVC Note: The D/A converter output contains no buffer amplifier. 384 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE MODULE This chapter describes the overview of the UART, serial I/O interface (SIO), input capture module, and output compare module, the configuration and functions of registers, and the operation of each. 14.1 UART 14.2 Serial I/O Interface (SIO) 14.3 Input Capture Module 14.4 Output Compare 385 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE 14.1 UART This section describes the overview of the UART, the configuration and functions of registers, and UART operation. ■ Overview of the UART The UART is a serial I/O port that is used to perform asynchronous (start-stop synchronization) or CLK synchronous communication. The UART has the features described below. The MB91F355A/355A/354A/ F356B/F357B have a 5 channel UART. The MB91F353A/351A/352A/353A have a 4 channel UART. 386 14.1.1 Features of the UART This section describes the features and registers of the UART, and also provides a block diagram of the UART. ■ Features The UART has the following features: • Full-duplex double buffer • Either asynchronous (start-stop synchronization) or CLK synchronous communication can be selected. • Multiprocessor mode is supported. • Fully programmable baud rate • An arbitrary baud rate can be set using a built-in timer. (See the item about the U-TIMER.) • An external clock can be used to set a baud rate. • Error detection functions (parity, framing, overrun) • The transfer signal is an NRZ code. • UARTs ch0 to ch2 can use an interrupt to start DMA transfer (UARTs ch3 and ch4 cannot start DMA transfer). • The DMAC interrupt source is cleared if the DRCL register is written to. 387 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ■ UART Registers The UART registers are shown below. 15 388 8 7 0 SCR SSR SMR SIDR(R)/SODR(W) DRCL 8bit 8bit (R/W) (R/W) (W) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 15 14 13 12 11 10 9 8 PE ORE FRE RDRF TDRE BDS RIE TIE 7 6 5 4 3 2 1 0 MD1 MD0 - - CS0 - - - 15 14 13 12 11 10 9 8 PEN P SBL CL A/D REC RXE TXE 7 6 5 4 3 2 1 0 - - - - - - - - Serial input register Serial output register (SIDR /SODR) Serial status register (SSR) Serial mode register (SMR) Serial control register (SCR) (DRCL) ■ Block Diagram of the UART Figure 14.1-1 is a block diagram of the UART. Figure 14.1-1 Block Diagram of the UART Control signal Receive interrupt (to CPU) From U-TIMER External clock SCK SCK (clock) Send clock Clock selection circuit Receive clock SI (receive data) Send interrupt (to CPU) Receive control circuit Send control circuit Start bit detection circuit Send start circuit Receive bit counter Send bit counter Receive parity counter Send parity counter SO (send data) Receive status decision circuit Receive shifter Receiving completed SIDR Send shifter Sending starts SODR DMA receive error occurrence signal (To DMAC) R-bus MD1 MD0 SMR register CS0 SCR register PEN P SBL CL A/D REC RXE TXE SSR register PE ORE FRE RDRF TDRE BDS RIE TIE Control signal 389 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE 14.1.2 UART Registers This section describes the configuration and functions of the registers used by the UART. ■ Serial Mode Register (SMR) The bit configuration of the serial mode register (SMR) is shown below. Note: The MB91F353A/351A/352A/353A do not have SMR ch4. SMR Address : ch0 000063H 7 ch1 00006BH MD1 ch2 000073H R/W ch3 0000C3H ch3 0000CBH 6 5 4 3 2 1 0 MD0 R/W - - CS0 W - - - Initial value 00--0--B The SMR specifies the UART operating mode. Set the operating mode while operation is stopped. Do not write to this register during operation. [Bits 7, 6] MD1, MD0 (MoDe select) These bits are used to select a UART operating mode. Table 14.1-1 lists the UART operating modes that can be selected. Table 14.1-1 Selecting UART Operating Modes Mode MD1 MD0 Operating mode 0 0 0 Asynchronous (start-stop synchronization) normal mode [initial value] 1 0 1 Asynchronous (start-stop synchronization) multiprocessor mode 2 1 0 CLK synchronous mode − 1 1 Setting disabled Note: In Mode 1, which is CLK asynchronous mode (multiprocessor), more than one slave CPU can be connected to one host CPU. Since this resource cannot identify the data format of received data, however, only the master in multiprocessor mode is supported. Because the parity check function cannot be used, set PEN of the SCR register to "0". [Bits 5, 4] (reserved) Always write "1" to these bits. 390 [Bit 3] CS0 (Clock Select) This bit selects the UART operating clock. Value Meaning 0 Built-in timer (U-TIMER) [initial value] 1 External clock [Bit 2, 1] (reserved) Always write "0" to these bits. [Bit 0] (reserved) This bit is unused. ■ Serial Control Register (SCR) The bit configuration of the serial control register (SCR) is shown below. Note: The MB91F353A/351A/352A/353A do not have SCR ch4. SCR Address : ch0 000062H ch1 00006AH ch2 000072H ch3 0000C2H ch3 0000CAH 7 6 5 4 3 2 1 0 PEN R/W P R/W SBL R/W CL R/W A/D R/W REC W RXE R/W TXE R/W Initial value 00000100B The SCR controls the transfer protocol that is used for serial communication. [Bit 7] PEN (Parity Enable) This bit specifies whether to add parity in serial communication when data communication is performed. Value Meaning 0 No parity 1 Parity [initial value] Note: Parity can be added only in normal mode (Mode 0) of asynchronous (start-stop synchronization) communication mode. No parity can be added in multiprocessor mode (Mode 1) and CLK synchronous communication mode (Mode 2). 391 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE [Bit 6] P (Parity) This bit specifies that even or odd parity be added to perform data communication. Value Meaning 0 Even parity 1 Odd parity [initial value] [Bit 5] SBL (Stop Bit Length) This bit specifies the number of stop bits, which marks the end of a frame in asynchronous (start-stop synchronization) communication. Value Meaning 0 1 stop bit 1 2 stop bits [initial value] [Bit 4] CL (Character Length) This bit specifies the data length of one frame that is sent or received. Value Meaning 0 7 bits [initial value] 1 8 bits Note: 7-bit data can be handled only in normal mode (Mode 0) of asynchronous (start-stop synchronization) communication mode. Use 8-bit data in multiprocessor mode (Mode 1) and CLK synchronous communication mode (Mode 2). [Bit 3] A/D (Address/Data) This bit specifies the data format of a frame that is sent or received in multiprocessor mode (Mode 1) of asynchronous (start-stop synchronization) communication mode. Value Meaning 0 Data frame [initial value] 1 Address frame [Bit 2] REC (Receiver Error Clear) Write "0" to this bit to clear the error flags (PE, ORE, and FRE) in the SSR register. Writing "1" to this bit has no effect. "1" is always read from this bit. 392 [Bit 1] RXE (Receiver Enable) This bit controls the UART receive operation. Value Meaning 0 Disables receive operation. 1 Enables receive operation. [initial value] Note: If a receive operation is disabled while it is in progress (while data is being inputted to the receive shift register), reception of the frame is completed. The receive operation is stopped when the received data is stored in the receive data buffer register (SIDR). [Bit 0] TXE (Transmitter Enable) This bit controls the UART send operation. Value Meaning 0 Disables send operation. 1 Enables send operation. [initial value] Note: If a send operation is disabled while it is in progress (while data is being outputted from the transmission register), sending is stopped when no more send data is stored in the send data buffer register (SODR). 393 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ■ Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) The bit configurations of the serial input data register (SIDR) and serial output data register (SODR) are shown below. Note: The MB91F353A/351A/352A/353A do not have SIDR ch4 and SODR ch4. SIDR Address : ch0 000061H ch1 000069H ch2 000071H ch3 0000C1H ch4 0000C9H 7 D7 R 6 D6 R 5 D5 R 4 D4 R 3 D3 R 2 D2 R 1 D1 R 0 D0 R 7 D7 W 6 D6 W 5 D5 W 4 D4 W 3 D3 W 2 D2 W 1 D1 W 0 D0 W Initial value Undefined SODR Address : Same as above Undefined These registers are data buffer registers for sending and receiving. If the data length is seven bits, bit 7 (D7) of SIDR and SODR contains invalid data. Accessing SIDR and SODR when BDS = 1 switches the high-order and low-order data on the bus. As a result, it appears that bit 0 (D0) is ignored. Write to the SODR register only while the TDRE bit of the SSR register is "1". Note: Writing to the register with this address means writing to the SODR register. Reading from the register with this address means reading from the SIDR register. 394 ■ Serial Status Register (SSR) The bit configuration of the serial status register (SSR) is shown below. Note: The MB91F353A/351A/352A/353A do not have SSR ch4. SSR Address : ch0 000060H ch1 000068H ch2 000070H ch3 0000C0H ch4 0000C8H 7 6 5 4 3 2 1 0 PE R ORE R FRE R RDRF R TDRE R BDS R/W RIE R/W TIE R/W Initial value 00001000B The SSR is configured from flags that indicate the operating status of the UART. [Bit 7] PE (Parity Error) This bit, which is an interrupt request flag, is set when a parity error occurs during reception. To clear the flag when it has been set, write "0" to the REC bit (Bit 10) of the SCR register. If the PE bit is set, the SIDR data becomes invalid. Value Meaning 0 No parity error has occurred. 1 A parity error has occurred. [initial value] [Bit 6] ORE (Over Run Error) This bit, which is an interrupt request flag, is set when an overrun error occurs during reception. To clear the flag when it has been set, write "0" to the REC bit of the SCR register. If the ORE bit is set, the SIDR data becomes invalid. Value Meaning 0 No overrun error has occurred. 1 An overrun error has occurred. [initial value] 395 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE [Bit 5] FRE (FRaming Error) This bit, which is an interrupt request flag, is set when a framing error occurs during reception. To clear the flag when it has been set, write "0" to the REC bit of the SCR register. If the FRE bit is set, the SIDR data becomes invalid. Value Meaning 0 No framing error has occurred. 1 A framing error has occurred. [initial value] Notes: • Switch the internal and external baud rate clocks using Bit 3 of the serial mode register only while the UART is stopped, since the switching takes effect immediately after writing. • Bit 3 of the serial mode register is write-only. [Bit 4] RDRF (Receiver Data Register Full) This bit, which is an interrupt request flag, indicates that the SIDR register has receive data. This bit is set when receive data is loaded into the SIDR register. It is automatically cleared when the data is read from the SIDR register. Value Meaning 0 No receive data exists. 1 Receive data exists. [initial value] [Bit 3] TDRE (Transmitter Data Register Empty) This bit, which is an interrupt request flag, indicates whether send data can be written to SODR. This bit is cleared when send data is written to the SODR register. It is set again when the written data is loaded into the send shifter and begins to be transferred, indicating that the next send data can be written. Value 396 Meaning 0 Disables writing of send data. 1 Enables writing of send data. [initial value] [Bit 2] BDS (Bit Direction Select) This bit selects the transfer direction. Value Meaning 0 Sends starting from the least significant bit (LSB). [initial value] 1 Sends starting from the most significant bit (MSB). Note: Because the high-order and low-order data are switched when the serial data register is written to or read, the data will become invalid if the bit is rewritten after data is written to the SDR register. If the SODR register and BDS are rewritten at the same time using halfwords (16 bits), data will be written to the SODR register based on the BDS value before rewriting. [Bit 1] RIE (Receiver Interrupt Enable) This bit controls a reception interrupt. Value Meaning 0 Disables receive interrupt. 1 Enables receive interrupt. [initial value] Note: Receive interrupt sources include errors due to PE, ORE, and FRE as well as normal receive due to RDRF. [Bit 0] TIE (Transmitter Interrupt Enable) This bit controls send interrupt. Value Meaning 0 Disables send interrupt. 1 Enables send interrupt. [initial value] Note: Send interrupt sources include send requests due to TDRE. 397 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ■ DRCL The bit configuration of the DRCL register is shown below. DRCL Address : ch0 000066H ch1 00006EH ch2 000076H 15 14 13 12 11 10 9 8 W W W W W W W W Initial value --------B The DRCL register clears a DMAC interrupt source. Write an arbitrary value to the DRCL register to clear a DMAC interrupt source. Always use byte access to access the DRCL register. When an interrupt occurs, DMAC transfer terminates and the DMAC retains the DMAC source until the DMAC interrupt source is cleared. Even if the various interrupt request flags are cleared by interrupt processing when the DMAC is not activated, the DMAC interrupt source is retained as it is. If the DMAC interrupt source remains as it is and DMAC activation is enabled with a UART specified for the DMAC activation source, the DMAC will be activated and unintended operation executed even if the interrupt request flags are not set. Therefore, when the DMAC is activated for the first time and when the UART has already been used using interrupts that do not activate the DMAC, use this register to clear the DMAC interrupt source. (This register is write-only.) 398 14.1.3 Operation of the UART This section describes the UART operation. ■ Operating Modes of the UART The UART has the operating modes shown in Table 14.1-2 . Set a value in the SMR and SCR registers to switch mode. Table 14.1-2 lists the UART operating modes. Table 14.1-2 UART Operating Modes Mode Parity Data length Operating mode Yes/No 7 Yes/No 8 Asynchronous (start-stop synchronization) normal mode 1 No 8+1 Asynchronous (start-stop synchronization) multiprocessor mode 2 No 8 CLK synchronous mode 0 Stop bit length 1 bit or 2 bits No The stop bit length in asynchronous (start-stop synchronization) mode can be specified only for a send operation. The stop bit length is always one bit for a receive operation. Since operation is possible only in the above modes, do not make any other setting. ■ Selecting a Clock for the UART a) Internal timer If you select the U-TIMER by setting CS0 to "0", the baud rate is determined according to the reload value set for the U-TIMER. At this time, you can calculate the baud rate as follows: Asynchronous (start-stop synchronization): Φ/(8 x β) CLK synchronous: Φ/β Φ: Peripheral machine clock frequency β: Cycle defined for the U-TIMER (2n+2 or 2n+3; n is the reload value.) In asynchronous (start-stop synchronization) mode, data can be transferred in the range from +1% of the specified baud rate. -1% to b) External clock If you select an external clock by setting CS0 to "1", the baud rate is as follows (the frequency of the external clock is assumed to be f): Asynchronous (start-stop synchronization): f/8 CLK synchronous: f However, that the maximum value for f is 3.125 MHz. 399 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ■ Asynchronous (Start-stop Synchronization) Mode ● Transfer data format UART handles only data in the NRZ (Non Return to Zero) format. Figure 14.1-2 shows the data format. Figure 14.1-2 Transfer Data Format (Modes 0 and 1) SI,SO 0 1 Start LSB 1 1 0 0 1 0 1 1 MSB Stop A/D Stop (Mode 0) (Mode 1) Data that has been transferred is 01001101B. As shown in Figure 14.1-2 , the transfer of data always starts with the start bit ("L" level data), continues as long as the data bit length specified in LSB First, and ends with a stop bit ("H" level data). If an external clock is selected, you always must input a clock. The data length can be set to 7 or 8 bits in normal mode (Mode 0), but must be set to 8 bits in multiprocessor mode (Mode 1). In multiprocessor mode, no parity can be added; instead, the A/D bit is always added. ● Receive operation If the RXE bit (Bit 1) of the SCR register is set to "1", a receive operation is always in progress. If a start bit appears on the receive line, one-frame data is received according to the data format specified in the SCR register. If an error occurs after reception of one frame is completed, the error flag is set and then the RDRF flag (Bit 4 of the SSR register) is set. If, at this time, the RIE bit (Bit 1) of the same SSR register is set to "1", a receive interrupt is generated for the CPU. Check the flags of the SSR register and read the SIDR register if normal reception has occurred or perform the necessary processing if an error has occurred. The RDRF flag is cleared when the SIDR register is read. ● Send operation If the TDRE flag (Bit 3) of the SSR register is set to "1", send data is written to the SODR register. If, at this time, the TXE bit (bit 0) of the SCR register is set to "1", transmission occurs. The TDRE flag is set again when the data set in the SODR register is loaded into the send shift register and begins to be transferred, indicating that the next send data can be set. If, at this time, the TIE bit (bit 0) of the same SSR register is set to "1", a send interrupt requesting that the send data be set in the SODR register is generated for the CPU. The TDRE flag is cleared if data is set in the SODR register. 400 ■ CLK Synchronous Mode ● Transfer data format The UART handles only data in the NRZ (Non Return to Zero) format. Figure 14.1-3 relationship between send and receive clocks and data. shows the Figure 14.1-3 Transfer Data Format (Mode 2) Writing to SODR Mark SCK RXE, TXE SI, SO 1 0 LSB 1 1 0 0 1 0 MSB (Mode 2) Data that has been transferred is 01001101B. When the internal clock (U-TIMER) has been selected, a data receive synchronous clock is automatically generated as soon as data is received. While an external clock has been selected, you must check that data exists in the send data buffer SODR register of the send side UART (TDRE flag is "0") and then supply an accurate clock for one byte. Before sending starts and after it ends, be sure to set the mark level. The data length is 8 bits only, and no parity can be added. Only overrun errors are detected because there is no start or stop bit. ● Initialization The following shows the setting values of the control registers required to use CLK synchronous mode. • • SMR register • MD1, MD0: 10 • CS: Specifies the clock input. PFR (port function) register • SCE: Set to "1" for an internal timer and to "0" for an external clock. • SOE: Set to "1" for send and to "0" for receive only. 401 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE • • SCR register • PEN: 0 • P,SBL,A/D: These bits are meaningless. • CL: 1 • REC: 0 (to initialize the register) • RXE, TXE: At least one of the bits must be set to "1". SSR register • RIE: Set to "1" to enable interrupts and to "0" to disables interrupts. • TIE: 0 ● Start of communication Write to the SODR register to start communication. If only reception is performed, dummy send data must be written to the SODR register. ● End of communication Check for the end of communication by making sure that the RDRF flag of the SSR register has changed to "1". Use the ORE bit of the SSR register to check that communication has been performed correctly. ■ Occurrence of Interrupts and Timing for Setting Flags The UART has five flags and two interrupt sources. The five flags are PE, ORE, FRE, RDRF, and TDRE. PE means parity error, ORE means overrun error, and FRE means framing error. These flags are set when an error occurs during reception and are then cleared when "0" is written to REC of the SCR register. RDRF is set when receive data is loaded into the SIDR register and then cleared when data is read from the SIDR register. Mode 1 does not provide a parity detection function. Mode 2 does not provide a parity detection function or a framing error function. TDRE is set when the SODR register is empty, and writing to it is enabled and then cleared when data is written to the SODR register. There are two interrupt sources, one for receiving and the other for sending. During receiving, an interrupt is requested due to PE, ORE, FRE, or RDRF. During sending, an interrupt is requested due to TDRE. The following shows the timing for setting the interrupt flags in each of these modes. 402 ● Receive operation in Mode 0 The PE, ORE, FRE, and RDRF flags are set when the last stop bit is detected after a receive transfer is completed, causing an interrupt request to be generated for the CPU. The SIDR data is invalid while PE, ORE, and FRE are active. Figure 14.1-4 shows the timing for setting ORE, FRE, and RDRF in Mode 0. Figure 14.1-4 Timing for Setting ORE, FRE, and RDRF (Mode 0) Data D6 D7 Stop PE, ORE,FRE RDRF Receive interrupt ● Receive operation in Mode 1 The ORE, FRE, and RDRF flags are set when the last stop bit is detected after a receive transfer is completed, causing an interrupt request to be generated for the CPU. The data indicating an address or the data in Bit 9 is invalid because the length of data that can be received is 8 bits. The SIDR data is invalid while ORE and FRE are active. Figure 14.1-5 shows the timing for setting ORE, FRE, and RDRF in Mode 1. Figure 14.1-5 Timing for Setting ORE, FRE, and RDRF (Mode 1) Data D6 Address/Data Stop ORE,FRE RDRF Receive interrupt 403 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ● Reception operation in Mode 2 The ORE and RDRF flags are set when the last data (D7) is detected after the reception transfer is completed, generating an interrupt request to the CPU. The SIDR data is invalid while ORE is active. Figure 14.1-6 shows the timing of setting ORE and RDRF in Mode 2. Figure 14.1-6 Timing of Setting ORE and RDRF (Mode 2) Data ORE RDRF Receive interrupt 404 D5 D6 D7 ● Send operation in modes 0, 1, and 2 TDRE is cleared when data is written to the SODR register. This bit is set when data is transferred to the internal shift register and the next data can be written, causing an interrupt request to be generated for the CPU. If "0" is written to TXE of the SCR register (as well as RXE in mode 2) during a send operation, TDRE of the SSR register is set to "1", disabling the UART send operation after the transmission shifter stops. The device sends data written to the SODR register before transmission stops after "0" is written to the TXE of the SCR register (as well as RXE in mode 2) during the send operation. Figure 14.1-7 shows the timing for setting the TDRE bit in mode 0 or 1. Figure 14.1-7 Timing for Setting TDRE (Modes 0 and 1) Writing to SODR TDRE Interrupt request to CPU SO interrupt SO output ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3 A/D ST: Start bit, D0 to D7: Data bits SP: Stop bit, A/D: Address/data multiplexer Figure 14.1-8 shows the timing for setting the TDRE bit in mode 2. Figure 14.1-8 Timing for Setting TDRE (Mode 2) Writing to SODR TDRE Interrupt request to CPU SO interrupt SO output D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 405 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE Notes: • Writing to the SODR register starts communication. Even for receive only, dummy send data must be written to the SODR register. • Set the communication mode while operation is stopped. Data send and received while the operating mode is being set is unpredictable. • Write to the DRCL register before starting DMA transfer due to an interrupt for the first time. 406 14.1.4 Example of using the UART UART mode 1 is used in a system in which multiple slave CPUs are connected to a host CPU. ■ Example of System Construction (Using Mode 1) Figure 14.1-9 shows an example of constructing a system using mode 1. This resource supports only a communications interface on the host. Figure 14.1-9 Example of Constructing a System Using Mode 1 SO SI Host CPU SO SI Slave CPU #0 SO SI Slave CPU #1 Communication starts when the host CPU transfers address data. Address data is data used when A/D of the SCR register is set to "1". This data is used to select a destination slave CPU, enabling communication with the host CPU. Normal data is data used when A/D of the SCR register is set to "0". Figure 14.1-10 shows the flowchart. In this mode, set the PEN bit of the SCR register to "0", since the parity check function cannot be used. 407 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE Figure 14.1-10 Communication Flowchart in Mode 1 (Host CPU) START Set transfer mode to "1". Set data used to select slave CPUs in D0 to D7, set "1" in A/D, and transfer 1 byte. Set "0" in A/D. Enable receive operation. Communicate with a slave CPU. Communication completed? No Yes Communicate with other slave CPUs? No Yes Disable the receive operation. END 408 ■ Example of Setting Baud Rates and U-TIMER Reload Values Table 14.1-3 gives examples of setting values for baud rates and U-TIMER reload values in asynchronous (start-stop synchronization) mode. Table 14.1-4 gives examples of setting values for baud rates and UTIMER reload values in CLK synchronous mode. A frequency in the tables represents a peripheral machine clock frequency. UCC1 is a value to be set in the UCC1 bit of the UTIMC register for the U-TIMER. A dash (-) in the tables means that the baud rate cannot be used because the error exceeds plus minus 1%. The U-Timer reload value is displayed as a decimal value. Table 14.1-3 Example of Setting Values for Baud Rates and U-TIMER Reload Values in Asynchronous (Start-stop Synchronization) Mode Baud rate (bps) ms φ=25MHz φ=20MHz φ=12.5MHz φ=10MHz 1200 833.33 1301(UCC1=0) 1040(UCC1=1) 650(UCC1=0) 520(UCC1=0) 2400 416.67 650(UCC1=0) 520(UCC1=0) 324(UCC1=1) 259(UCC1=1) 4800 208.33 324(UCC1=1) 259(UCC1=1) 162(UCC1=1) 129(UCC1=0) 9600 104.17 161(UCC1=1) 129(UCC1=0) 80(UCC1=1) 64(UCC1=0) 19200 52.08 80(UCC1=1) 64(UCC1=0) 39(UCC1=1) 31(UCC1=1) 38400 26.04 39(UCC1=1) 31(UCC1=1) 19(UCC1=1) - 57600 17.36 26(UCC1=0) 20(UCC1=1) 12(UCC1=1) - 115200 8.681 12(UCC1=1) - - - 10400 96.15 149(UCC1=0) 119(UCC1=0) 74(UCC1=0) 59(UCC1=0) 31250 32.00 49(UCC1=0) 39(UCC1=0) 24(UCC1=0) 19(UCC1=0) 62500 16.00 24(UCC1=0) 19(UCC1=0) 11(UCC1=1) 9(UCC1=0) φ = Peripheral machine clock frequency Note: The error range is -1% to +1%. Table 14.1-4 Example of Setting Values for Baud Rates and U-TIMER Reload Values in CLK Synchronous Mode Baud rate (bps) ms φ=25MHz φ=20MHz φ=12.5MHz φ=10MHz 250k 4.00 49(UCC1=0) 39(UCC1=0) 24(UCC1=0) 19(UCC1=0)) 500k 2.00 24(UCC1=0)) 19(UCC1=0) 11(UCC1=1) 9(UCC1=0) 1M 1.00 11(UCC1=1) 9(UCC1=0) 5* (UCC1=0) 4(UCC1=0) φ = Peripheral machine clock frequency *: The error range is -1% to +1%. 409 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE 14.2 Serial I/O Interface (SIO) This section provides an overview of the serial I/O interface (SIO), describes the register structure and functions, and describes the operation of the SIO. ■ Overview of the Serial I/O Interface (SIO) The serial I/O interface (SIO) consists of a single 8-bit channel. It performs data transfer using clock synchronization. 410 14.2.1 Overview of the Serial I/O Interface (SIO) The serial I/O interface (SIO) allows selection of the data transfer mode from the LSBfirst and MSB-first modes. The MB91F355A/354A/355A/F356B/F357B have a 3 channel serial I/O interface. The MB91F353A/351A/352A/353A have a 2-channel serial I/O interface. ■ Serial I/O Interface Operating Modes The serial I/O interface can operate in the following two modes: • Internal shift clock mode: Data is transferred in synchronization with the internal clock. • External shift clock mode: Data is transferred in synchronization with the clock input from an external pin (SCK). In this mode, data can be transferred by a CPU instruction through manipulation of the general-purpose port sharing the external pin (SCK). ■ Serial I/O Interface (SIO) Registers The serial I/O interface (SIO) registers are shown below. 15 Address : 000024H SMD2 000028H 00002CH 14 SMD1 13 SMD0 12 SIE 11 SIR 10 BUSY 9 STOP 7 - 6 - 5 - 4 - 3 MODE 2 BDS 1 - 0 - 15 14 13 12 11 10 9 8 Address : 000026H 00002AH 00002EH - - - - - - TST1 7 6 5 4 3 2 1 0 Address : 000027H 00002BH 00002FH D7 D6 D5 D4 D3 D2 D1 D0 15 14 13 12 11 10 9 8 MD - - - DIV3 DIV2 DIV1 7 - 6 - 5 - 4 - 3 - 2 - 1 - Address : 000025H 000029H 00002DH Address : 000032H 000034H 000036H Address : 000039H 00003AH 00003BH 8 STRT Serial mode control status register (SMCS) TST0 SIO test register (SES) Serial data register (SDR) DIV0 SIO prescaler control register (CDCR) 0 - DMAC interrupt source clear register (SRCL) 411 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ■ Block Diagram of the Serial I/O Interface (SIO) Figure 14.2-1 shows a block diagram of the serial I/O interface (SIO). Figure 14.2-1 Block Diagram of the Serial I/O Interface Internal data bus (MSB first) D0 to D7 D7 to D0 (LSB first) Initial value Tr ansfer direction selection SI5-7 Read Write SDR (Serial data register) SO5-7 SCK5-7 Shift clock counter Control circuit Internal clock 2 1 0 SMD2 SMD1 SMD0 SI E SIR BUSY STOP STRT MODE BDS SCE PFR register Interrupt request Internal data bus Note: The MB91F353A/351A/352A/353A do not have the SI5, SCK5, and S05 pins. 412 14.2.2 Serial I/O Interface Registers This section describes the configuration and functions of the registers used by the serial I/O interface. ■ Serial Mode Control Status Register (SMCS) The bit configuration of the serial mode control status register (SMCS) is shown below. SMCS 15 Address : 000024H SMD2 000028H R/W 00002CH 14 13 12 11 10 9 8 Initial value: SMD1 R/W SMD0 R/W SIE R/W SIR R/W BUSY R/W STOP R/W STRT R/W 00000010B *1 SMCS Address : 000025H 000029H 00002DH *2 7 6 5 4 3 2 1 0 - - - - MODE R/W BDS R/W - - Initial value: ----00--B *1: Only "0" can be written. *2: Only "0" can be written. "0" is always read. The serial mode control status register (SMCS) controls the operating mode of the serial I/O transfer. The functions of the bits are explained below. Note: The MB91F353A/351A/352A/353A do not have SIO ch5. (Settings of 000024H and 000025H are invalid.) [Bits 15, 14, and 13] Shift clock selection bits (SMD2, SMD1, SMD0: Serial shift clock mode) The shift clock selection bits are used to select the serial shift clock mode as shown below. φ=25MHz div=3 φ=20MHz div=4 φ=10MHz div=5 Divide-by value 0 Setting not allowed 2.5MHz 1MHz 2 0 1 2.08MHz 1.25MHz 500kHz 4 0 1 0 520kHz 312kHz 125kHz 16 0 1 1 260kHz 156kHz 62.5kHz 32 1 0 0 130kHz 78kHz 31.2kHz 64 1 0 1 External shift clock mode 1 1 0 Reserved 1 1 1 Reserved SMD2 SMD1 SMD0 0 0 0 413 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE Setting of the communication prescaler (CDCR) div (Machine clock) MD DIV3 DIV2 DIV1 DIV0 3 1 1 1 0 1 4 1 1 1 0 0 5 1 1 0 1 1 6 1 1 0 1 0 7 1 1 0 0 1 8 1 1 0 0 0 These bits are initialized to "000" upon a reset. These bits must not be updated during data transfer. Five types of internal shift clock and an external shift clock are available. Do not set "110" or "111" in SMD2, SMD1, and SMD0 as these values are reserved. If the external shift clock mode is selected, shift operation can be performed for each instruction through manipulation of the ports that share the SCK5 to SCK7 pins. [bit 12] Serial I/O interrupt enable bit (SIE: Serial I/O interrupt enable) The serial I/O interrupt enable bit controls the serial I/O interrupt request as described below. Value Meaning 0 Serial I/O interrupt disabled [default] 1 Serial I/O interrupt enabled This bit is initialized to "0" upon a reset. This bit is readable and writable. [bit 11] Serial I/O interrupt request bit (SIR: Serial I/O interrupt request) When serial data transfer is completed, "1" is set to this bit. If this bit is set while interrupts are enabled (SIE=1), an interrupt request is issued to the CPU. The clear condition varies with the MODE bit. When "0" is written to the MODE bit, the SIR bit is cleared by writing "0". When "1" is written to the MODE bit, the SIR bit is cleared by reading or writing to SDR. When the system is reset or "1" is written to the STOP bit, the SIR bit is cleared regardless of the MODE bit value. Writing "1" to the SIR bit has no effect. "1" is always read by a read operation of a read-modify-write instruction. 414 [bit 10] Transfer status bit (BUSY) The transfer status bit indicates whether serial transfer is being executed. BUSY Operation 0 Stopped, or standing by for serial data register R/W [default] 1 Serial transfer This bit is initialized to "0" upon a reset. This is a read-only bit. [bit 9] Stop bit (STOP) The stop bit forcibly terminates serial transfer. If "1" is written to this bit (STOP=1), the serial transfer enters the stop state. STOP Operation 0 Normal operation 1 Transfer stop by STOP=1 [default value] This bit is initialized to "1" upon a reset. This bit is readable and writable. [bit 8] Start bit (STRT: Start) The start bit activates serial transfer. Writing "1" to this bit while serial transfer is in the stop state starts serial transfer. Writing "1" to this bit is ignored and writing "0" has no effect while the device is performing serial transfer or waiting for reading or writing of data in the serial shift register. "0" is always read from this bit. [Bit 3] Serial mode selection bit (MODE) The serial mode selection bit is used to select the condition for starting transfer operation from the stop state. This bit must not be updated during a transfer operation. MODE Operation 0 Transfer is started when the STRT bit is set to "1". (Default) 1 Transfer is started when data is read from or written to the serial data register. This bit is cleared to "0" by a reset and can be read and written. Be sure to write "1" to this bit before starting DMA. [Bit 2] Transfer direction select bit (BDS: Bit Direction Select) The transfer direction select bit is used to select the transfer mode for serial data I/O from LSB-first mode (transfer begins with the least significant bit) and MSB-first mode (transfer begins with the most significant bit), as shown below. Value Meaning 0 LSB-first mode (default) 1 MSB-first mode 415 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE Notes: • Be sure to specify the transfer direction before writing data to the serial shift data register (SDR). • The BDS bit is cleared to "0" by a reset. This bit can be read and written [Bits 7 to 4, 1, and 0]: Unused bits These bits are not used. ■ Serial Shift Data Register (SDR) The bit configuration of the serial shift data register (SDR) is shown below. This register must be accessed in byte units. SDR Address : 000027H 00002BH 00002FH 7 D7 R/W 6 D6 R/W 5 D5 R/W 4 D4 R/W 3 D3 R/W 2 D2 R/W 1 D1 R/W 0 D0 R/W Initial value: XXH (undefined) The serial shift data register is a serial data register that holds the serial I/O data to be transferred. During operation, data must not be written to or read from the SDR. Note: The MB91F353A/351A/352A/353A do not have SIO ch5. (Setting of 000027H in the SDR is invalid.) ■ SIO Test Register (SES) The bit configuration of the SIO test register (SES) is shown below. This register must be accessed in byte units. SES Address : 000026H 00002AH 00002EH 15 - 14 - 13 - 12 - 11 - 10 - 9 TST1 R/W 8 TST0 Initial value: ------00B R/W (undefined) [Bits 9 and 8] TST1 and TST0 The TST1 and TST0 bits are used for testing. Always write "0" to these bits. Note: The MB91F353A/351A/352A/353A do not have SIO ch5. (Setting of 000026H in the SES register is invalid.) 416 ■ Serial I/O Prescaler Control Register (CDCR) The bit configuration of the serial I/O prescaler control register (CDCR) is shown below. This register must be accessed in byte units. 15 MD R/W CDCR Address : 000032H 000034H 000036H 14 - 13 - 12 - 11 DIV3 R/W 10 DIV2 R/W 9 DIV1 R/W 8 DIV0 Initial value: 0---1111B R/W Note: The MB91F353A/351A/352A/353A do not have SIO ch5. (Setting of 000032H in the CDCR is invalid.) [Bit 15] Machine clock divide mode select (MD) The machine clock divide mode select bit is the operation enable bit of the communication prescaler. Value Meaning 0 Communication prescaler operation is disabled. (Default) 1 Communication prescaler operation is enabled. [Bits 11 to 8] Divide 3 to divide 0 (DIV3 to DIV0) The divide 3 to divide 0 bits are used to specify the division ratio for the peripheral system clock (CLKP). DIV3 to 0 Division ratio 1101B 3 1100B 4 1011B 5 1010B 6 1001B 7 1000B 8 Note: If the division ratio is changed, wait before starting communication until the time equal to the two divided clock pulses has elapsed for clock stabilization. 417 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ■ DMAC Interrupt Source Clear Register (SRCL) The bit configuration of the DMAC interrupt source clear register (SRCL) is shown below. This register must be accessed in byte units. SRCL Address : 000039H 00003AH 00003BH 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Initial value: --------B (undefined) The DMAC interrupt source clear register is used to clear the SIO interrupt source. If an arbitrary value is written to this register, the source of an interrupt to the DMAC is cleared. This register must be accessed in byte units. After a DMAC interrupt is generated, the DMAC interrupt source is retained until DMAC transfer ends and the DMAC clears the DMAC interrupt source. In interrupt processing that does not activate the DMAC, the DMAC interrupt source is retained even though the serial I/O interrupt request flag has been cleared. For this reason, if the SIO is specified as the DMAC activation source and the DMAC operation is enabled with the DMAC interrupt source retained, the DMAC will be activated even though the serial I/ O interrupt request flag is not set. The result will be unexpected operation. To avoid this error, use this register to clear the DMAC interrupt source before activating the DMAC. In particular, be sure to clear the DMAC interrupt source specially if the DMAC is to be activated for the first time or if the SIO has operated for an interrupt without the DMAC having been activated. (This register is write-only.) Note: The MB91F353A/351A/352A/353A do not have SIO ch5. (Setting of 000039H in the SRCL register is invalid.) 418 14.2.3 Operation of the Serial I/O Interface (SIO) The serial I/O interface (SIO) consists of a serial mode control status register (SMCS) and a serial shift data register (SDR) and is used to input and output 8-bit serial data. ■ Overview of Serial I/O Interface (SIO) Operation For output, the bit contents of the serial shift data register (SDR) are outputted via a serial output pin (SO5 to SO7) in synchronization with the falling edge of the serial shift clock (external or internal clock). For input, the bits of serial data are inputted via a serial input pin (SI5 to SI7) to the serial shift data register (SDR) in synchronization with the rising edge of the serial shift clock. The shift direction (MSB-first mode or LSB-first mode) can be specified by the bit direction select (BDS) bit of the serial mode control status register (SMCS). When serial data transfer ends, the serial I/O interface stops or enters a state in which it stands by for reading of or writing to the serial shift data register. The state after transfer depends on the status of the MODE bit of the serial mode control status register (SMCS). To restore the SIO transfer operation from the stop or standby state, follow the relevant procedure below. 1. To resume operation from the stop state, write "0" to the STOP bit and "1" to the STRT bit. (The STOP and STRT bits can be set simultaneously.) 2. To resume operation from the serial shift data register R/W standby state, read or write to the data register. ■ Shift Clock There are two modes of shift clock: internal or external shift clock. These two modes are selected by setting the SMCS To switch the modes, ensure that serial I/O transfer is stopped. To check whether the serial I/O transfer is stopped, read the BUSY bit. ● Internal shift clock mode In internal shift clock mode, data transfer is based on the internal clock, and a shift clock with a 50% duty ratio can be outputted from the SCK pin as the synchronization timing output. Data is transferred at a rate of one bit per clock pulse. The transfer speed is expressed as follows: A Transfer speed(s) = Internal clock machine cycle (Hz) "A" indicates the clock division ratio specified by the SMD bits of the SMCS register, and is one of the following: (φ/div)/2, (φ/div)/2 2 , (φ/div)/2 4 , (φ/div)/2 5 , (φ/div)/2 6 419 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ● External shift clock mode In external shift clock mode, data is transferred at a rate of 1 bit per clock pulse in synchronization with the external shift clock input via the SCK pin. The transfer speed can be set in a range from DC to 1/(8 peripheral system clock cycles). For example, the transfer speed can be up to 3.125 MHz when 1 peripheral system clock cycle is 0.04 µs. Data can also be transferred at a rate of bits per instruction when the settings below are made. Select external shift clock mode, and write "0" to the bit corresponding to the SCK pin of the port function register (PFR). Write "1" to the direction register for the port sharing the SCK pin to set the port to output mode. After the above setting, when "1" and "0" are written to the port data register (PDR) for the port, the port value output via the SCK pin is fetched as the external clock and transfer operation is performed. Be sure to start the shift clock at the "H" level. Note: The SMCS or SDR must not be written to during serial I/O operation. ■ States of Serial I/O Interface Operation There are four serial I/O operation status: STOP, halt, SDR R/W standby, and transfer. ● STOP The STOP state is initiated upon RESET or when "1" is written to the STOP bit of SMCS. The shift counter is initialized, and "0" is written to SIR. To resume operation from the STOP state, write "0" to STOP and "1" to STRT. (These two bits can be written to simultaneously.) Since the STOP bit overrides the STRT bit, transfer cannot be started by writing "1" to STRT while "1" is written to STOP. ● Halt When transfer is completed while the MODE bit is "0," "0" is set to BUSY and "1" is set to SIR of the SMCS, the counter is initialized, and the system stops. To resume operation from the stop state, write "1" to STRT. ● Serial data register R/W standby When serial transfer is completed while the MODE bit of the SMCS register is "1", the BUSY and SIR bits of the SMCS register are set to "0" and "1", respectively, and the SIO enters the serial data register R/W standby state. If the interrupt enable register is set, an interrupt signal is output from the SIO. To resume operation from the serial data register R/W standby state, data must be read from or written to the serial data register. The BUSY bit is set to "1", and transfer operation starts. ● Transfer "1" is set to the BUSY bit and serial transfer is being performed. According to the MODE bit, the halt state or R/W standby state comes next. Figure 14.2-2 shows the transitions between the operating states. 420 Figure 14.2-2 Extended I/O Serial Interface Operation Transitions STRT=0, BUSY=0 MODE=0 MODE=0 STOP=0 & & STOP=0 STRT=1 & END Tra nsfer Reset STOP=0 & STRT=0 End of transfer STOP STRT=0, BUSY=0 STOP=1 STOP=1 STRT=1, BUSY=1 STOP=0 STOP=1 & STRT=1 Serial data register R/W standby MODE=1 & END & STOP=0 STRT=1, BUSY=0 MODE=1 SDR R/W & MODE=1 Figure 14.2-3 shows the schematic diagram for reading from and writing to the serial data register. Serial data Figure 14.2-3 Schematic Diagram for Reading from and Writing to the Serial Data Register Data bus SOT SIN Data bus Read Write Interrupt output Extended I/O serial interface Read Write CPU (1) (2) Interrupt input Data bus Interrupt controller 1. If "1" is written to MODE, transfer ends according to the shift clock counter. The read/write standby state starts when "1" is written to SIR. If "1" is written to the SIE bit, an interrupt signal is generated. No interrupt signal is generated when SIE is inactive or transfer has been terminated by writing "1" to STOP. 2. Reading or writing to the serial data register clears the interrupt request and starts serial transfer. ■ Shift Operation Start/Stop Timing and I/O Timing Start: Write "0" to the STOP bit and "1" to the STRT bit of SMCS. Stop: The system may stop at the end of transfer or when "1" is written to STOP. - Stop by STOP=1: The system stops with SIR=0 regardless of the MODE bit. - Stop by end of transfer: The system stops with SIR=1 regardless of the MODE bit. Regardless of the MODE bit, the BUSY bit becomes "1" during serial transfer and becomes "0" during stop or R/W standby state. To check the transfer status, read this bit. Figure 14.2-4 shows the timing of starting and stopping the shift operation based on the internal clock. 421 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE Figure 14.2-4 Shift Operation Start/stop Timing (Internal Clock) "1" output SCK5 to SCK7 (Transfer start) STRT (Transfer end) If MODE=0 BUSY S05 to S07 DO0 DO7 (Data maintained) Figure 14.2-5 shows the timing of starting and stopping the shift operation in LSB-first mode based on the external clock. Figure 14.2-5 Shift Operation Start/Stop Timing (External Clock) (LSB First) SCK5 to SCK7 (Transfer start) STRT (Transfer end) If MODE=0 BUSY S05 to S07 DO7 (Data maintained) DO0 Figure 14.2-6 shows the timing of starting and stopping the shift operation for each instruction in external shift clock mode. Figure 14.2-6 Shift Operation Start/Stop Timing (External Shift Clock Mode with Instruction Shift) SCK5 to SCK7 STRT SCK="0" in PDR SCK="0" in PDR SCK="1" in PDR (Transfer end) If MODE=0 BUSY S05 to S07 DO6 DO7 (Data maintained ) Reference: In the instruction shift, when "1" is written to the bit corresponding to SCK of PDR, "H" is outputted. When "0" is written to this bit, "L" is outputted (however, in the case of SCOE=0 at the external shift clock mode selection). 422 Figure 14.2-7 shows the timing of stopping transfer operation when "1" is written to the STOP bit. Figure 14.2-7 Stop Timing when "1" is Written to the STOP Bit "1" output SCK5 to SCK7 (Transfer start) (Transfer stop) STRT If MODE=0 BUSY STOP SO5 to SO7 DO3 DO5 DO4 (Data maintained) Note: DO7 to DO0 indicate output data. During serial data transfer, data is outputted via a serial output pin (SO5 to SO7) at the falling edge of the shift clock, and inputted via a serial input pin (SI5 to SI7) at the rising edge of the shift clock. Figure 14.2-8 shows the timing of the I/O shift operation. Figure 14.2-8 I/O Shift Timing LSB-first mode (The BDS bit is "0".) SCK5 to 7 SIN Input SI5 to 7 D10 D11 D12 D13 SOT Output D14 D15 D16 D17 SO5 to 7 DO0 DO1 DO2 DO4 DO5 DO6 DO7 DO3 MSB-first mode (The BDS bit is "1".) SCK5 to 7 SIN Input SI5 to 7 D17 D16 D15 D14 D13 D12 D11 D10 DO4 DO3 DO2 DO1 DO0 SOT Output SO5 to 7 DO7 DO6 DO5 423 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ■ Interrupt Function The serial I/O interface can generate an interrupt request for the CPU. An interrupt request is outputted to the CPU when both the serial I/O interrupt request (SIR) bit (i.e., interrupt flag) and the serial I/O interrupt enable (SIE) bit of the SMCS register are "1" at the end of data transfer. Figure 14.2-9 shows the timing of interrupt signal output. Figure 14.2-9 Interrupt Signal Output Timing SCK5 to SCK7 (Transfer end) Note: When MODE=1 BUSY SIR SIE=1 SDR RD/WR SO5 to SO7 424 DO6 DO7 (Data is maintained.) 14.3 Input Capture Module This section describes the overview of the input capture module, the configuration and functions of registers, and module operation. ■ Overview of the Input Capture Module The input capture module detects either or both of the rising and falling edges for an externally input signal and stores the 16-bit free-running timer value set at that time in a register. The input capture module can also generate an interrupt when an edge of the input signal is detected. 425 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE 14.3.1 Overview of the Input Capture Module The input capture module consists of an input capture data register and an input capture control register. ■ External Input Pin Corresponding to Each Input Capture Channel An external input pin is assigned to each input capture channel. • The valid edge of the external input signal can be selected from the following three types: • • Rising edge • Falling edge • Both rising and falling edges An interrupt can be generated when a valid edge of an external input signal is detected. The MB91350A has four input capture channels. ■ Input Capture Module Registers The input capture module registers are shown below. 426 15 14 13 12 11 10 9 8 CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 Input capture data register (IPCP) (high-order bits) 7 CP07 6 CP06 5 CP05 4 CP04 3 CP03 2 CP02 1 CP01 0 CP00 Input capture data register (IPCP) (low-order bits) 7 ICP3 6 ICP2 5 ICE3 4 ICE2 3 EG31 2 EG30 1 EG21 0 EG20 Input capture control register (ICS23) Input capture control register (ICS01) 7 6 5 4 3 2 1 0 ICP1 ICP1 ICE1 ICE0 EG11 EG10 EG01 EG00 ■ Input Capture Block Diagram Figure 14.3-1 shows a block diagram of the input capture module. Figure 14.3-1 Input Capture Block Diagram 16-bit timer count value (T15 to T00) Capture data register IN0, 2 Edge detection R-bus ch(0,2) Input pin EG11 EG10 EG01 EG00 EG31 EG30 EG21 EG20 16-bit timer count value (T15 to T00) Capture data register IN1, 3 Edge detection ch(1,3) Input pin ICP1 ICP0 IEC1 IEC0 ICP3 ICP2 IEC3 IEC2 Interrupt Interrupt 427 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE 14.3.2 Input Capture Module Registers This section describes the configuration and functions of the registers used by the input capture operation. The input capture module has the following two types of registers: • Input capture data register (IPCP0 to IPCP3) • Input capture control register (ICS01 and ICS23) ■ Input Capture Data Register (IPCP0 to IPCP3) The bit configuration of the input capture data register (IPCP0 to IPCP3) is shown below. IPCP0 to 3 15 Address : 0000DAH 0000D8H 0000DEH 0000DCH CP15 R 14 CP14 R 13 CP13 R 12 CP12 R 11 CP11 R 10 CP10 R 9 CP09 R 8 Initial value: CP08 R XXXXXXXXB Initial value: XXXXXXXXB 7 6 5 4 3 2 1 0 CP07 R CP06 R CP05 R CP04 R CP03 R CP02 R CP01 R CP00 R The input capture data register is used to store the value of the 16-bit free-running timer on detection of a valid edge of the waveform input via the corresponding external input pin. When this register is reset, its value is undefined. This register must be accessed in 16-bit or 32-bit units. This register cannot be written. ■ Input Capture Control Registers (ICS01 and ICS23) The bit configurations of the input capture control registers (ICS01 and ICS23) are shown below. ICS23 Address : 0000E1H ICS01 Address : 0000E3H 428 15 14 13 12 11 10 9 8 Initial value: ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 00000000B R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Initial value: ICP1 ICP1 ICE1 ICE0 EG11 EG10 EG01 EG00 00000000B R/W R/W R/W R/W R/W R/W R/W R/W [Bits 7 and 6] ICP3 to ICP0 These bits are used as input capture interrupt flags. When a valid edge of the signal input via an external input pin is detected, "1" is written to the corresponding bits in ICP3 to ICP0. If the corresponding interrupt enable bit (ICE3 to ICE0) is set, an interrupt can be generated when the valid edge is detected. Writing "0" to the ICP3 to ICP0 bits clears them. Writing "1" to these bits is invalid. If a read modify write instruction is issued, "1" is always read from each of these bits. ICPn Input capture interrupt flag 0 Valid edge not detected (initial value) 1 Valid edge detected "n" in ICPn indicates an input capture module channel number. [Bits 5 and 4] ICE3 to ICE0 These bits are used to enable an input capture interrupt. If "1" is written to one of these bits, an input capture interrupt is generated when "1" is written to the corresponding interrupt flag (ICP3 to ICP0). ICEn Input capture interrupt 0 Interrupt disabled (initial value) 1 Interrupt enabled "n" in ICEn indicates an input capture module channel number. [Bits 3 to 0] EG31, EG30, EG21, EG20, EG11, EG10, EG01, and EG00 These bits are used to specify the valid edge polarity of external input. These bits are used also to enable an input capture operation. EGn1 EGn0 Edge detection polarity 0 0 No edge detection (stop state; initial value) 0 1 Rising-edge detection 1 0 Falling-edge detection 1 1 Both-edge detection & "n" in EGn1 and EGn0 indicates an input capture module channel number. 429 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE 14.3.3 Input Capture Operation In 16-bit input capture operation, an interrupt can be generated upon detection of at the specified valid edge, fetching the 16-bit free-run timer value and writing it to the capture register. ■ 16-bit Input Capture Operation Figure 14.3-2 shows the timing for data fetching by the input capture module. Figure 14.3-2 Sample of Input Capture Fetch Timing Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Reset Time IN 0 IN 1 IN 2 Data register 0 Data register 1 Data register 2 Undefined 3FFFH BFFFH Undefined Undefined BFFFH Capture 0 interrupt Capture 1 interrupt Capture 2 interrupt Capture 0: Rising edge Capture 1: Falling edge Capture 2: Both edges 7FFFH Generating an interrupt again at a valid edge Clearing the interrupt by software ■ Input Timing for 16-bit Input Capture Figure 14.3-3 shows the timing of signal input for a 16-bit input capture operation. Figure 14.3-3 Input Timing for 16-bit Input Capture φ Counter value Input capture input N N+1 Valid edge Capture signal Capture register Interrupt 430 N+1 14.4 Output Compare This section describes the overview of the output compare module, the configuration and functions of registers, and module operation. ■ Overview of the Output Compare Module The output compare module consists of 16-bit compare registers, compare output latches, and control registers. If the value written to a 16-bit compare register matches the value of the corresponding 16-bit free-running timer, the output compare module reverses the output level of the corresponding pin. It can also generate an interrupt. 431 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE 14.4.1 Features of the Output Compare Module The MB91F355A/355A/354A/F356B/F357B have eight output compare channels. The MB91F353A/351A/352A/353A have two output compare channels. ■ Features of the Output Compare Module The output compare module has the following features: • Eight compare registers can be used independently. An output pin and an interrupt flag are assigned to each compare register. • Two compare registers can be paired to control an output pin. The output level of the output pin can be reversed using two compare registers. • An initial value can be set for each output pin. • An interrupt can be generated for a match when values are compared. • Compare register ch0 is used as the compare clear register for the 16-bit free-running timer. ■ Output Compare Module Registers The output compare module registers are shown below. 432 15 C15 14 C14 13 C13 12 C12 11 C11 10 C10 9 C09 8 C08 Compare register (high-order bits) (OCCP) 7 6 5 4 3 2 1 0 C07 C06 C05 C04 C03 C02 C01 C00 Compare register (low-order bits) (OCCP) 15 - 14 13 - 12 CMOD 11 - 10 9 OTD1 3 - 2 7 6 5 4 ICP1 ICP0 ICE1 ICE0 8 Output control register (high-order bits) OTD0 (OCS) 1 0 CST1 CST0 Output control register (low-order bits) (OCS) ■ Block Diagram of the Output Compare Module Figure 14.4-1 shows a block diagram of the output compare module. Figure 14.4-1 Block Diagram of the Output Compare Module (Only the compare register for channel 0 is used as the free-running timer clear register.) OTD1 OTD0 R-bus Compare register Compare output latch Compare circuit Compare register Output (channels 0, 2, 4, and 6) OTE0 to OTE7 are located in PFR0. CMOD Compare output latch Compare circuit CST1 OTE0,2,4,6 OTE1,3,5,7 Output (channels 1, 3, 5, and 7) CST0 ICP1 ICP0 ICE1 ICE0 16-bit free-running timer Interrupt output Interrupt output 433 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE 14.4.2 Output Compare Module Registers This section describes the configuration and functions of the registers used by the output compare operation. The output compare module has the two types of registers shown below. ■ Compare Register (OCCP0 to OCCP7) The bit configuration of the compare register (OCCP0 to OCCP7) is shown below. CCCP0 to 7 Address : 0000E6H 0000E4H 0000EAH 0000E8H 0000EEH 0000ECH 0000F2H 0000F0H 15 14 13 12 11 10 9 8 Initial value: C15 R/W C14 R/W C13 R/W C12 R/W C11 R/W C10 R/W C09 R/W C08 R/W XXXXH 7 C07 R/W 6 C06 R/W 5 C05 R/W 4 C04 R/W 3 C03 R/W 2 C02 R/W 1 C01 R/W 0 C00 R/W Note: The MB91F353A/351A/352A/353A have two output compare channels (OCCP0 and OCCP2), but do not have OCCP1 and OCCP3 to OCCP7. The compare register is 16 bits, and its value is compared with the value of the 16-bit free-running timer. Because the initial value of the compare register is undefined, be sure to set a value in it before enabling output compare. The output compare register must be accessed in 16-bit or 32-bit units. If the value of the compare register matches the value of the 16-bit free-running timer, a compare signal is generated and the output compare interrupt flag is set. If the corresponding OTE bit of the port function register (PFR0) is set to enable output, the output level corresponding to the compare register is reversed. ■ Output Control Register (OCS0 to OCS7) The bit configuration of the output control register (OCS0 to OCS7) is shown below. OCP01, 23, 45, 67 15 Address : 0000F6H 0000F4H 0000FAH 0000F8H 14 13 12 11 - - - CMOD R/W - 7 6 5 4 3 ICP1 R/W ICP0 R/W ICE1 R/W ICE0 R/W - 10 2 9 8 OTD1 R/W OTD0 R/W 1 0 CST1 R/W CST0 R/W Initial value: 11101100B Initial value: 00001100B Only the output control registers for channels 0 and 1 are explained here. For details of the output control registers for channels 2 to 7, when reading, replace channel number 0 with channel number 2, 4, or 6, and channel number 1 with channel number 3, 5, or 7. 434 Note: The MB91F353A/351A/352A/353A do not have OCS45 and OCS67. [Bits 15 to 13] Unused bits "1" is always read from these bits. [bit 12] CMOD CMOD is used to switch the pin output level reverse mode upon a comparison match while pin output is enabled (OTE1=0 or OTE0=1:PFR0). When CMOD=0 (initial value), the output level of the pin corresponding to the compare register is reversed. • OC0: The level is reversed upon a match with compare register 0. • OC1: The level is reversed upon a match with compare register 1. When CMOD=1, the output level is reversed for the compare register 0 in the same manner as for CMOD=0. The output level of the pin corresponding to compare register 1 (OC1), however, is reversed upon a match with compare register 0 or 1. If compare registers 0 and 1 have the same value, the same operation as with a single compare register is performed. • OC0: The level is reversed upon a match with compare register 0. • OC1: The level is reversed upon a match with compare register 0 or 1. [Bits 11 and 10] Unused bits "1" is always read from these bits. [bits 9 and 8] OTD1 and OTD0 These bits are used to change the pin output level when the output compare register pin output is enabled. The initial value of the compare pin output is "0". Ensure that the compare operation is stopped before a value is written. When read, these bits indicate the output compare pin output value. OTD1 or OTD0 Compare pin output level 0 Sets "0" for the compare pin output. (initial value) 1 Sets "1" for the compare pin output. OTD1: Corresponds to output compare 1. OTD0: Corresponds to output compare 0. 435 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE [bits 7 and 6] ICP1 and ICP0 These bits are used as output compare interrupt flags. "1" is set to these bits when the compare register value matches the 16-bit free-run timer value. While the interrupt request bits (ICE1 and ICE0) are enabled, an output compare interrupt occurs when the ICP1 and ICP0 bits are set to "1". These bits are cleared by writing "0". Writing "1" has no effect. "1" is always read by a read-modify-write instruction. ICP1 or ICP0 Interrupt flag 0 No output compare match (initial value) 1 Output compare match ICP1: Corresponds to output compare 1. ICP0: Corresponds to output compare 0. If an external clock is specified for the free-running timer, a compare match and interrupt occur in the next clock cycle. Therefore, when compare match output and an interrupt are generated, at least one clock pulse must be inputted for the external clock specified for the free-running timer after the comparison matching occurs. [bits 5 and 4] ICE1 and ICE0 These bits are used as output compare interrupt enable bits. While the "1" is written to these bits, an output compare interrupt occurs when an interrupt flag (ICP1 or ICP0) is set. ICE1 or ICE0 Interrupt enable 0 Output compare interrupt disabled (initial value) 1 Output compare interrupt enabled ICE1: Corresponds to output compare 1. ICE0: Corresponds to output compare 0. [bits 3 and 2] Unused bits "1" is always read from these bits. [bits 1 and 0] CST1 and CST0 These bits are used to enable the match with 16-bit free-run timer. Ensure that a value is written to the compare register and output control register before the compare operation is enabled. CST1 or CST0 Comparison with 16-bit free-running timer 0 Compare operation disabled (initial value) 1 Compare operation enabled CST1: Corresponds to output compare 1. CST0: Corresponds to output compare 0. Since output compare is synchronized with the 16-bit free-running timer, stopping the 16-bit free-running timer stops compare operation. 436 14.4.3 Operation of the Output Compare Module In the 16-bit output compare operation, an interrupt request flag can be set and the output level can be reversed when the specified compare register value matches the 16bit free-run timer value. ■ Operation of the 16-bit Output Compare Module The compare operation can be performed for each channel independently (when CMOD = 0). Figure 14.4-2 shows a sample of the waveform that is output when compare registers 0 and 1 are used (initial output value is "0"). Figure 14.4-2 Sample of Output Waveform when Compare Registers 0 and 1 Used (Initial Output Value is "0") Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Reset Compare register 0 value Compare register 1 value OC0 OC1 Compare 0 interrupt Time BFFFH 7FFFH Compare 1 interrupt The output level can be changed using two compare registers (when CMOD=1). Figure 14.4-3 shows a sample of the waveform that is output when compare registers 0 and 1 are used (initial output value is "0"). Figure 14.4-3 Sample of Output Waveform when Compare Registers 0 and 1 Used (Initial Output Value is "0") Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Reset Compare register 0 value Compare register 1 value OC0 OC1 Compare 0 interrupt Time BFFFH 7FFFH Compare 1 interrupt 437 CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE ■ Timing of 16-bit Output Compare Operation The output level can be changed using two pairs of compare registers (when CMOD = 1). In output compare operation, a compare match signal is generated when the free-running timer value matches the specified compare register value. The output value can be reversed and an interrupt can be issued. The output reverse timing upon a compare match is synchronized with the counter count timing. [Compare register write timing] If the value of a compare register is changed, the value is not compared with the counter value. Figure 14.4-4 shows the timing for writing data to a compare register. Figure 14.4-4 Compare Register Write Timing Counter value N+3 N+2 N+1 N No match signal is generated. N+1 M Compare clear register 0 value Compare register 0 write Compare clear register 1 value N+3 L Compare register 1 write Compare 1 stop Compare 0 stop [Compare match and interrupt timing] Figure 14.4-5 shows the timing for compare match and the interrupt. Figure 14.4-5 Timing of Compare Match and Interrupt φ Count clock N Counter value N+1 Compare register value N+3 N+2 N Compare match Pin output Interrupt [Pin output timing] Figure 14.4-6 shows the timing for pin output. Figure 14.4-6 Pin Output Timing Counter value Compare register value Compare match Pin output 438 N N N+1 N N+1 CHAPTER 15 I2C INTERFACE This chapter describes the overview of the I2C interface, the configuration and functions of registers, and operation. 15.1 Overview of the I2C Interface 15.2 I2C Interface Registers 15.3 Explanation of I2C Interface Operation 15.4 Operation Flowcharts 439 CHAPTER 15 I2C INTERFACE 15.1 Overview of the I2C Interface The I2C interface is a serial I/O port that supports the Inter-IC Bus. The I2C interface operates as a master or slave device on the I2C bus. ■ Features of I2C Interface The I2C interface has the following features: 440 • Master or slave sending and receiving • Arbitration function • Clock synchronization function • Slave address and general call address detection function • Transfer direction detection function • Function that generates and detects a repeated START condition • Bus error detection function • 10-bit and 7-bit slave addresses • Slave address reception acknowledge control in master mode • Compound slave addresses available • Interrupt enabled for a transmission or bus error • Standard mode (maximum of 100 kbps) and high-speed mode (maximum of 400 kbps) available 15.1 Overview of the I2C Interface ■ I2C Interface Registers The I2C interface registers are listed below. • Bus control register (IBCR) Address : 000094H Initial value→ • Initial value→ 13 12 11 10 9 Initial value→ Address : 000097H Initial value→ BER BEIE SCC MSS ACK GCAA INTE INT R/W R/W W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 BB R 0 RSC R 0 AL R 0 LRB R 0 TRX R 0 AAS R 0 GCA R 0 ADT R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 TA9 R/W 0 8 TA8 R/W 0 15 R 0 7 6 5 4 3 2 1 0 TA7 R/W TA6 R/W TA5 R/W TA4 R/W TA3 R/W TA2 R/W TA1 R/W TA0 R/W 0 0 0 0 0 0 0 0 13 R 13 12 R 12 11 R 11 10 R 10 9 TM9 R/W 9 8 TM8 R/W 8 10-bit slave address mask register (ITMK) 15 ENTB R/W Initial value→ 15 Address : 000098H 7 Address : 000099H TM7 R/W Initial value→ 1 • 14 RAL R 14 6 5 4 3 2 1 0 TM6 R/W 1 TM5 R/W 1 TM4 R/W 1 TM3 R/W 1 TM2 R/W 1 TM1 R/W 1 TM0 R/W 1 7-bit slave address register (ISBA) Address : 00009BH Initial value→ 441 8 10-bit slave address register (ITBA) Address : 000096H • 14 Bus status register (IBSR) Address : 000095H • 15 7 R 0 6 5 4 3 2 1 0 SA6 R/W 0 SA5 R/W 0 SA4 R/W 0 SA3 R/W 0 SA2 R/W 0 SA1 R/W 0 SA0 R/W 0 CHAPTER 15 I2C INTERFACE • 7-bit slave address mask register (ISMK) 15 ENSB R/W Initial value→ 0 14 13 12 11 10 9 8 SM6 R/W 1 SM5 R/W 1 SM4 R/W 1 SM3 R/W 1 SM2 R/W 1 SM1 R/W 1 SM0 R/W 1 7 6 5 4 3 2 1 0 7D R/W 0 6D R/W 0 5D R/W 0 4D R/W 0 3D R/W 0 2D R/W 0 1D R/W 0 0 R/W 0 15 14 13 12 11 10 9 8 R 0 EN R/W 0 CS4 R/W 1 CS3 R/W 1 CS2 R/W 1 CS1 R/W 1 CS0 R/W 1 7 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 DBL R/W 0 Address : 00009AH • Data register (IDAR) Address : 00009DH Initial value→ • Clock control register (ICCR) Address : 00009EH TEST W Initial value→ 0 • Clock disable register (IDBL) Address : 00009FH Initial value→ 442 15.1 Overview of the I2C Interface ■ Block Diagram of the I2C Interface Figure 15.1-1 is a block diagram of the I2C interface. Figure 15.1-1 Block Diagram of the I2C Interface ICCR 2 I C operation enable EN IDBL Clock enable DBL CLKP ICCR Clock division 2 CS4 CS3 CS2 CS1 CS0 IBSR BB 2 3 4 5 LRB TRX Start-stop condition detection Last Bit Send/ receive Error First Byte Arbitration lost detection AL IBSR IBCR SCL1 SCL0 BER BEIE Interrupt request SDA SDA0 IRQ INTE INT End IBCR SCC MSS ACK GCAA Start Master ACK enable GC-ACK enable Start-stop condition generation IDAR IBSR AAS GCA Slave Slave address Global call comparison ISMK FNSB ITMK ENTB RAL ITBA 443 Shift clock generation Bus busy ADT R-bus Sync Clock selection 2 (1/12) Shift clock edge change timing Repeat start RSC 32 ITMK ISBA ISMK CHAPTER 15 I2C INTERFACE 15.2 I2C Interface Registers This section describes the configuration and functions of registers used by the I2C interface. ■ Overview of the I2C Interface Registers The I2C interface has the following nine types of registers: 444 • Bus status register (IBSR) • Bus control register (IBCR) • Clock control register (ICCR) • 10-bit slave address register (ITBA) • 10-bit slave address mask register (ITMK) • 7-bit slave address register (ISBA) • 7-bit slave address mask register (ISMK) • Data register (IDAR) • Clock disable register (IDBL) 15.2 I2C Interface Register 15.2.1 Bus Status Register (IBSR) The bus status register (IBSR) is read-only. All bits are cleared when the I2C stops operating (EN = 0 in ICCR). ■ Bus Status Register (IBSR) The configuration of the bus status register (IBSR) is shown below. Address : 000095H Initial value→ 7 6 5 4 3 2 1 0 BB R 0 RSC R 0 AL R 0 LRB R 0 TRX R 0 AAS R 0 GCA R 0 ADT R 0 [Bit 7] BB (Bus Busy) This bit indicates the status of the I2C bus. Value Function 0 STOP condition detected 1 START condition detected (bus used) [Bit 6] RSC (Repeated Start Condition) This bit is the repeated START condition detection bit. Value Function 0 Repeated START condition not detected 1 Repeated START condition detected while bus is being used This bit is cleared when the slave address transfer ends (ADT=0) or when the STOP condition is detected. [Bit 5] AL (Arbitration Lost) This bit is the arbitration lost detection bit. Value Function 0 Arbitration lost not detected 1 Arbitration lost detected during master transmission Write "0" to the INT bit or "1" to the MSS bit of the IBCR register to clear this bit. [Arbitration loss is detected if] 445 • The transmission data does not match the data on the SDA line at the rising edge of SCL. • A repeated START condition is generated in the first bit of the data by another master. • The I2C interface cannot generate a START or STOP condition because the SCL line is driven to L by another slave device. CHAPTER 15 I2C INTERFACE [Bit 4] LRB (Last Received Bit) This bit is an acknowledge storage bit that stores an acknowledge from the receiving device. Value Function 0 Slave acknowledge detected 1 Slave acknowledge not detected This bit is rewritten if an acknowledge is detected (reception 9 bits). This bit is cleared if a START or STOP condition is detected. [Bit 3] TRX (Transferring Data) This bit indicates the transmission status during a data transfer. Value Function 0 Data transmission stopped 1 Data transmission in progress This bit is set to "1" if: A START condition occurs in master mode. Transfer of the first byte ends during read access (transmission) in slave mode. Data is being sent in master mode. This bit is set to "0" if: The bus is idle (IBCR BB=0). An arbitration loss occurs. "1" is written to the SCC bit in the mask interrupt status (MSS=1, INT=1). The MSS bit is cleared in the mask interrupt status (MSS=1, INT=1). No acknowledge occurred for the last transfer byte in slave. Data is received in slave mode. Data is received from a slave in master mode. [Bit 2] AAS (Addressed As Slave) This bit is the slave addressing detection bit. Value Function 0 The interface is not specified as a slave. 1 The interface is specified as a slave. This bit is cleared when a (repeated) START or STOP condition is detected. This bit is set when a 7-bit or 10-bit slave address is detected. 446 15.2 I2C Interface Register [Bit 1] GCA (General Call Address) This bit is the general call address (00H) detection bit. Value Function 0 General call address is not received as a slave. 1 General call address is received as a slave. This bit is cleared when a (repeated) START or STOP condition is detected. [Bit 0] ADT (Address Data Transfer) This bit is the slave address reception detection bit. Value Function 0 Received data is not a slave address (or the bus is idle). 1 Received data is a slave address. This bit is set to "1" if a START condition is detected. It is cleared after the second byte if the header section of a slave address is detected during 10-bit write access. Otherwise, it is cleared after the first byte. [After the first or second byte means the following] 447 • Writing "0" to the MSS bit during master interrupt (MSS=1, INT=1:IBCR) • Writing "1" to the SCC bit during master interrupt (MSS=1, INT=1:IBCR) • Clearing the INT bit • Beginning of a transfer bytes that is not used for the transfer destination as master or slave CHAPTER 15 I2C INTERFACE 15.2.2 Bus Control Register (IBCR) All bits except for the BER and BEIE bits are cleared when the I2C stops operating (EN = 0 in ICCR). ■ Bus Control Register (IBCR) The configuration of the bus control register (IBCR) is shown below. Address : 000094H Initial value→ 15 14 13 12 11 10 9 8 BER BEIE SCC MSS ACK GCAA INTE INT R/W R/W W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 [Bit 15] BER (Bus ERror) This bit is the bus error interrupt request flag bit. For a read by a read modify instruction, "1" is always read. During writing Value Function 0 Clears the bus error interrupt request flag. 1 Has no meaning. During reading Value Function 0 Bus error not detected 1 Error condition detected If this bit is set, the EN bit of the CCR register is cleared, the I2C interface is stopped, and data transfer is halted. All bits of the IBSR and IBCR registers except BER and BEIE are cleared. Clear this bit before the I2C interface is enabled (EN = 1) again. [Conditions set this bit to "1"] 1. An illegal START or STOP condition at a specific location is detected (while an slave address or data is being transferred). * 2. The header section of a slave address is received during a 10-bit read access before 10-bit write access with the first byte is performed. * 3. A STOP condition is detected during transfer in master mode. *: When the I2C interface is enabled during transfer, this detection flag is set after the first STOP condition is received to prevent an incorrect bus error report from being issued. 448 15.2 I2C Interface Register [Bit 14] BEIE (Bus Error Interrupt Enable) This bit is the bus error interrupt enable bit. Value Function 0 Bus error interrupt disabled 1 Bus error interrupt enabled An interrupt occurs if this bit is set to "1" and the BER bit is set to "1". [Bit 13] SCC (Start Condition Continue) This bit is the repeated [START] condition generation bit. During writing Value Function 0 Has no meaning. 1 Generates a repeated START condition in master transfer. The read value of this bit is always "0". If "1" is written to this bit in master mode (MSS = 1, INT = 1), a repeated START condition is generated and the INT bit is automatically cleared. [Bit 12] MSS (Master Slave Select) This bit is the master or slave selection bit. Value Function 0 Selects slave mode. 1 Selects master mode. Generates a START condition to enable the value of the IDAR register to be sent as a slave address. • This bit is cleared when arbitration lost occurs during master transmission, causing slave mode to start. • Write "0" to this bit during setting a master interrupt flag (MSS=1, INT=1) to automatically clear the INT bit. Then, generate a [STOP] condition to end the transfer. Note: The MSS bit functions as a direct reset. To detect a STOP condition, check the BB bit of the IBSR register. • If "1" is written to this bit while the bus is idle (MSS = 0, BB = 0), a START condition is generated and the value of IDAR is sent. • If "1" is written to this bit while the bus is busy (BB = 1, TRX = 0, MSS = 0), the I2C interface starts transmission when the bus becomes idle. If the I2C interface is specified as the address for a slave that is accompanied by a write access during this time, the bus becomes idle after the transfer ends. If the interface is transmitting as a slave (IBCR AAS = 1, TRX = 1) during this time, no data is sent even if 449 CHAPTER 15 I2C INTERFACE the bus has become idle. It is important to check whether the I2C interface is specified as a slave (IBSR AAS = 1), and whether data transmission has ended normally (IBCR MSS = 1) at the next interrupt or otherwise data transmission has failed with an error (IBSR AL = 1). Note: When using in the following condition, the transmission of general call address is disabled because it is not received as slave. • In addition to this LSI, there are some other LSIs to be used as master mode on the bus, this device transmits the general call address as a master, and arbitration lost is generated after the second byte. [Bit 11] ACK (ACKnowledge) This bit generates an acknowledge according to the setting of the data receive enable bit. Value Function 0 Acknowledge not generated when data is received 1 Acknowledge generated when data is received • This bit is disabled when a slave address is received in slave mode. When the I2C interface detects a 7bit or 10-bit slave address specification, an acknowledge is returned if the corresponding enable bits (ENTB ITMK, ENSB ISMK) are set. • Write to this bit while an interrupt flag is set (INT = 1), the bus is idle (IBSR BB = 0), or the I2C interface is stopped (ICCR EN = 0). [Bit 10] GCAA (General Call Address Acknowledge) This bit is an acknowledge enable bit used when a general call address is received. Value Function 0 Acknowledge not generated when general call address is received 1 Acknowledge generated when general call address is received Write to this bit while an interrupt flag is set (INT = 1), the bus is idle (IBSR BB = 0), or the I2C interface is stopped (ICCR EN = 0). [Bit 9] INTE (INTerrupt Enable) This bit is the interrupt enable bit. Value Function 0 Interrupts disabled 1 Interrupts enabled When this bit is "1" and the INT bit is "1", the interrupt is generated 450 15.2 I2C Interface Register [Bit 8] INT (INTerrupt) This bit is the transfer end interrupt request flag bit. For a read by a read modify instruction, "1" is read. During writing Value Function 0 Clears the transfer end interrupt request flag. 1 Has no meaning. During reading Value Function 0 Transfer not ended, not the transfer target, or bus is idle. 1 This bit is set to "1" if a one-byte transfer that includes the acknowledge bit is completed and the following conditions are met: • Bus master • The interface was specified as a slave address. • A general call address was received. • Arbitration lost occurred. If the interface is specified as a slave address, this bit is set at the end of slave address reception that includes an acknowledge. If this bit is set to "1", the SCL line is maintained at the "L" level. Write "0" to this bit to clear it and to open the SCL line to transfer the next byte. In master mode, a repeated START or STOP condition is generated. This bit is cleared when the SCC bit or the MSS bit is set to "1". Note: Contention of SCC, MSS, and INT bits If data is simultaneously written to the SCC, MSS, and INT bits, contention occurs between the next-byte transfer, repeated START condition generation, and STOP condition generation. If this situation occurs, the priorities are as follows: 1. Next-byte transfer and STOP condition generation When the INT bit is set to "0" and the MSS bit is set to "0", writing of the MSS bit has precedence and a STOP condition is generated. 2. Next-byte transfer and START condition generation When "0" is written to the INT bit and "1" is written to the SCC bit, writing to the SCC bit has precedence, a repeated START condition is generated, and the value of IDAR is sent. 3. Repeated START condition generation and STOP condition generation When the SCC bit is set to "1" and the MSS bit is set to "0" at the same time, clearing of the MSS bit has precedence. A STOP condition is generated and the I2C interface enters slave mode. 4. When an instruction which generates a start condition is executed (the MSS bit is set to "1") at the timing shown in Figure 15.2-1 and Figure 15.2-2 , arbitration lost detection (AL bit=1) prevents an interrupt (INT bit=1) from being generated. 5. Condition 1 in which an interrupt (INT bit=1) upon detection of "AL bit=1" does not occur 451 CHAPTER 15 I2C INTERFACE When an instruction which generates a start condition is executed (setting the MSS bit in the IBCR register to "1") with no start condition detected (BB bit=0) and with the SDA or SCL pin at the "L" level. Figure 15.2-1 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" does not Occur SCL or SDA pin at "L" level SCL pin "L" SDA pin "L" 1 I2C operation enable state (EN bit=1) Master mode setting (MSS bit=1) Arbitration lost detection (AL bit=1) Bus busy (BB bit) 0 Interrupt (INT bit) 0 6. Condition 2 in which an interrupt (INT bit=1) upon detection of "AL bit=1" does not occur When an instruction which generates a start condition by enabling I2C operation (EN bit=1) is executed (setting the MSS bit in the IBCR register to "1") with the I2C bus occupied by another master. This is because, as shown in Figure 15.2-2 , when the other master on the I2C bus starts communication with I2C disabled (EN bit=0), the I2C bus enters the occupied state with no start condition detected (BB bit =0). 452 15.2 I2C Interface Register Figure 15.2-2 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" does not Occur Start Condition The INT bit interrupt does not occur in the ninth clock cycle. Stop Condition SCL pin SDA pin SLAVE ADDRESS ACK DAT ACK EN bit MSS bit AL bit BB bit 0 INT bit 0 If a symptom as described above can occur, follow the procedure below for software processing. 1) Execute the instruction that generates a start condition (set the MMS bit to "1"). 2) Use, for example, the timer function to wait* for the time for three-bit data transmission at the I2C transfer frequency set in the ICCR register. Example: Time for three-bit data transmission at an I2C transfer frequency of 100 kHz {1/(100 × 103)} × 3=30µs * : When "arbitration lost" is detected, the MSS bit is set to "1" and then the AL bit is set to "1" without failure after the time for three-bit data transmission at the I2C transfer frequency. 3) Check the AL and BB bits in the IBSR register and, if the AL and BB bits are "1" and "0", respectively, set the EN bit in the ICCR register to "0" to initialize I2C. When the AL and BB bits are not so, perform normal processing. 453 CHAPTER 15 I2C INTERFACE A sample flow is given below. Master mode setting Set the MSS bit in the bus control register (IBCR) to "1". Wait* for the time for three-bit data transmission at the I2C transfer frequency set in the clock control register (ICCR). NO BB bit=0 and AL bit=1? YES to normal process Set the EN bit to "0" to initialize I2C. 7. Example of occurrence of an interrupt (INT bit=1) upon detection of "AL bit=1" When an instruction which generates a start condition is executed (setting the MSS bit to "1") with "bus busy" detected (BB bit=1) and arbitration is lost, the INT bit interrupt occurs upon detection of "AL bit=1". Figure 15.2-3 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" Occurs Start Condition Interrupt in the ninth clock cycle SCL pin SDA pin SLAVE ADDRESS ACK DAT EN bit MSS bit AL bit Clearing the AL bit by software BB bit INT bit 454 Releasing the SCL by clearing the INT bit by software 15.2 I2C Interface Register 15.2.3 Clock Control Register (ICCR) Clock control register specifies the enabled operation of I2C interface and the frequency of serial clock. ■ Clock Control Register (ICCR) The configuration of the clock control register (ICCR) is shown below. 15 Address : 00009EH TEST W Initial value→ 0 14 13 12 11 10 9 8 R 0 EN R/W 0 CS4 R/W 1 CS3 R/W 1 CS2 R/W 1 CS1 R/W 1 CS0 R/W 1 [Bit 15] Test bit Be sure to write "0" to it. [Bit 14] Unused bit Be sure to write "0" to it. [Bit 13] EN (ENable) This bit is the enable bit for the I2C interface. Value Function 0 Disabled 1 Enabled When the EN bit is "0", all bits of the IBSR register and IBCR register (except for the BER and BEIE bits) are cleared. A bus error clears this bit (BER = 1 in IBCR). Note: When operation is not allowed, the I2C interface immediately stops sending and receiving. [Bit 12 to 8] CS4 to 0 (Clock Period Select 4 to 0) These bits set the frequency of the serial clock. These bits can be written only when the I2C interface is disabled (EN = 0) or the EN bit is cleared. The frequency of the shift clock, fsck, is set as shown below. fsck= 455 φ n × 12+16 N>0 φ : Peripheral machine clock (= CLKP) CHAPTER 15 I2C INTERFACE Register settings n CS4 CS3 CS2 CS1 CS0 1 0 0 0 0 1 2 0 0 0 1 0 3 0 0 0 1 1 ... ... ... ... ... ... 31 1 1 1 1 1 Setting disabled for CS4 to CS0=00000 Clock frequency CLKP [MHz] 456 100K bps 400K bps n fsck [kHz] n fsck [kHz] 25 20 98 4 396.8 12.5 9 101.6 2 320.5 16.7 13 97.6 3 327.4 8.33 6 95.7 1 308.5 7.14 5 95.2 1 264.4 6.25 4 99.2 1 231.4 15.2 I2C Interface Register 15.2.4 10-bit Slave Address Register (ITBA) Rewrite the 10-bit slave address register (ITBA) while operation is stopped (EN = 0 in ICCR). ■ 10-bit Slave Address Register (ITBA) The configuration of the 10-bit slave address register (ITBA) is shown below. Address : 000096H Initial value→ Address : 000097H Initial value→ 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 TA9 R/W 0 8 TA8 R/W 0 7 6 5 4 3 2 1 0 TA7 R/W 0 TA6 R/W 0 TA5 R/W 0 TA4 R/W 0 TA3 R/W 0 TA2 R/W 0 TA1 R/W 0 TA0 R/W 0 ITBAH ITBAL [Bits 15 to 10] Reserved bits The values read from these bits are "0". [Bits 9 to 0] 10-bit slave address bits (A9 to A0) If a 10-bit address is enabled (ITMK ENTB = 1) when slave address data is received in slave mode, these bits of ITBA and the received address data are compared. An acknowledge is sent to the master after the address header of a 10-bit write access is received. Received data in the first and second bytes and the TBAL register are compared. When a match is detected, an acknowledge signal is sent to the master device and the AAS bit is set. The I2C interface responds to reception of the address header of a 10-bit read access after a repeated START condition is generated. All bits of a slave address are masked according to the ITMK setting. The received slave address is overwritten to the ITBA register. This register is enabled only when the AAS bit (IBSR register) is set to "1". 457 CHAPTER 15 I2C INTERFACE 15.2.5 10-bit Slave Address Mask Register (ITMK) This section describes the 10-bit slave address mask register (ITMK). ■ 10-bit Slave Address Mask Register (ITMK) The configuration of the 10-bit slave address mask register (ITMK) is shown below. 15 ENTB R/W Initial value→ 0 Address : 000098H 7 Address : 000099H TM7 R/W Initial value→ 1 14 RAL R 0 13 R 1 12 R 1 11 R 1 10 R 1 9 TM9 R/W 1 8 TM8 R/W 1 6 5 4 3 2 1 0 TM6 R/W 1 TM5 R/W 1 TM4 R/W 1 TM3 R/W 1 TM2 R/W 1 TM1 R/W 1 TM0 R/W 1 [Bit 15] ENTB (10-bit slave address enable bit) This bit is the 10-bit slave address enable bit. Value Function 0 10-bit slave address disabled 1 10-bit slave address enabled Write to this bit while the I2C interface is stopped (ICCR EN = 0). [Bit 14] RAL (Slave address length bit) This bit indicates the slave address length. Value Function 0 7-bit slave address 1 10-bit slave address If the 10-bit and 7-bit slave address enable bits are both enabled (ENTB =1 and ENSB = 1), this bit can be used to determine whether the transfer length of a 10-bit or 7-bit slave address becomes valid. This bit is valid when the AAS bit (IBSR) is set to "1". This bit is cleared when the interface is disabled (ICCR EN = 0). This bit is read-only. [Bits 13 to 10] Unused bits The values read from these bits are always "1". 458 15.2 I2C Interface Register [Bits 9 to 0] 10-bit slave address mask bits These bits mask the bits of the 10-bit slave address register (ITBA). Write to this register when the I2C interface is disabled (ICCR EN = 0). Value Function 0 This bit is not used for comparison of slave addresses 1 This bit is used for comparison of slave addresses Setting this bit enables transmission of an acknowledge to a compound 10-bit slave address. When using this register for comparison of 10-bit slave addresses, set this bit to "1". The received slave address is overwritten to ITBA. When ASS = 1 (IBSR), the specified slave address can be determined by reading the ITBA register. Each bit of TM9 to "0" of ITMK corresponds to one bit of the ITBA address. If the value of each of the TM9 to 0 bits is "1", the ITBA address becomes valid; if it is "0", the ITBA address becomes invalid. Example: ITBA address is 0010010111B and ITMK address is 1111111100B: The slave address is in the space from 0010010100B to 0010010111B. 459 CHAPTER 15 I2C INTERFACE 15.2.6 7-bit Slave Address Register (ISBA) Rewrite the 7-bit slave address register (ISBA) while operation is stopped (EN = 0 in ICCR). ■ 7-bit Slave Address Register (ISBA) The configuration of the 7-bit slave address register (ISBA) is shown below. Address : 00009BH Initial value→ 7 R 0 6 5 4 3 2 1 0 SA6 R/W 0 SA5 R/W 0 SA4 R/W 0 SA3 R/W 0 SA2 R/W 0 SA1 R/W 0 SA0 R/W 0 [Bit 7] Unused bit The value read from this bit is "0". [Bits 6 to 0] Slave address bits (SA6 to SA0) If a 7-bit slave address is enabled (ISMK ENSB = 1) when slave address data is received in slave mode, these bits of ISBA and the received slave address data are compared. If a slave address match is detected, an acknowledge is sent to the master and the AAS bit is set. The I2C interface returns an acknowledge in response to reception of the address header of a 7-bit read access after a repeated START condition is generated. All bits of a slave address are masked using the setting of the ISMK. The received slave address data is overwritten to the ISBA register. This register is enabled only when AAS (IBSR register) is set to "1". The I2C interface does not compare ISBA and the received slave address when a 10-bit slave address is specified or a general call is received. 460 15.3 Explanation of I2C Operation 15.2.7 7-bit Slave Address Mask Register (ISMK) Rewrite the 7-bit slave address mask register (ISMK) while operation is stopped (EN = 0 in ICCR). ■ 7-bit Slave Address Mask Register (ISMK) The configuration of the 7-bit slave address mask register (ISMK) is shown below. 15 ENSB R/W Initial value→ 0 Address : 00009AH 14 13 12 11 10 9 8 SM6 R/W 1 SM5 R/W 1 SM4 R/W 1 SM3 R/W 1 SM2 R/W 1 SM1 R/W 1 SM0 R/W 1 [Bit 15] ENSB (7-bit slave address enable bit) This bit is the 7-bit slave address enable bit. Value Function 0 7-bit slave address disabled 1 7-bit slave address enabled [Bits 14 to 8] 7-bit slave address mask bits These bits mask the bits of the 7-bit slave address register (ISBA). Value Function 0 This bit is not used for comparison of slave addresses 1 This bit is used for comparison of slave addresses Setting this bit enables transmission of an acknowledge to a compound 7-bit slave address. When using this register for comparison of a 7-bit slave address, set this bit to "1". The received slave address is overwritten to ISBA. When ASS = 1 (IBSR), the specified slave address can be determined by reading the ISBA register. After the I2C interface is enabled, the slave address (ISBA) is rewritten by reception operation. When SMK is rewritten, SMK must be set again to provide the expected operation. Each of the SM6-0 bits of ISMK corresponds to one bit of the ISBA address. If the value of each of the SM6-0 bit is "1", the ISBA address becomes valid; if it is "0", the ISBA address becomes invalid. Example: If ISBA address is 0010111B and ISMK address is 1111100B: The slave address is in the space from 0010100B to 0010111B. 461 CHAPTER 15 I2C INTERFACE 15.2.8 Data Register (IDAR) This section describes the data register (IDAR). ■ Data Register (IDAR) The configuration of the data register (IDAR) is shown below. Address : 00009DH Initial value→ 7 6 5 4 3 2 1 0 7D R/W 0 6D R/W 0 5D R/W 0 4D R/W 0 3D R/W 0 2D R/W 0 1D R/W 0 0 R/W 0 [Bits 7 to 0] Data bits (D7 to D0) Bits D7 to D0 are a data register used for serial transfer. Data is transferred from the MSB. The writing side of this register has a double buffer. While the bus is busy (BB = 1), write data is loaded into the register for serial transfer. When the INT bit (IBCR) is cleared or the bus is idle (IBSR BB = 0), transfer data is loaded into the internal transfer register. Since data is directly read from the register for serial transfer during reading, receive data in this register is valid only while the INT bit (IBCR) is set. 462 15.3 Explanation of I2C Operation 15.2.9 Clock Disable Register (IDBL) This section describes the clock disable register (IDBL). ■ Clock Disable Register (IDBL) The configuration of the clock disable register (IDBL) is shown below. Address : 00009FH Initial value→ 7 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 DBL R/W 0 [Bit 0] Clock disable bit (DBL) This bit specifies whether to supply or stop supply of the operating clock for the I2C interface. This bit can be used in low-power consumption mode. Value Function 0 Supplies the clock for I2C. 1 Stops supply of the clock for I2C. The I2C line is opened. This bit is initialized to "0" at reset. When "1" is written to this bit, the values read from other registers become undefined except the values read from this register (IBDL). Writing to other than this bit (this register) becomes ineffective. Note: When this bit is set to "1", I2C immediately stops even if send and receive operation is in progress. 463 CHAPTER 15 I2C INTERFACE 15.3 Explanation of I2C Interface Operation The I2C bus consists of two bidirectional bus lines used for transfer: one serial data line (SDA) and one serial clock line (SCL). The I2C interface has two corresponding opendrain I/O pins (SDA and SCL), enabling wired logic. ■ START Condition Write "1" to the MSS bit while the bus is open (BB=0, MSS=0) to place the I2C interface in master mode and to generate a START condition. The interface sends the value of the IDAR register as a slave address. Write "1" to the SCC bit while the interrupt flag is set in bus master mode (IBCR MSS =1, INT = 1) to generate a repeated START condition. Write "1" to the MSS bit while the bus is busy (IBSR BB = 1, TRX = 0, IBCR MSS = 0 or INT = 0) to release the bus and start transmission. If a write (reception) access is performed in slave mode, the interface starts transmission after transmission is completed and the bus is released. If the interface is sending data, it does not start transmission even though the bus has been released. The interface must be checked for the following: • Whether the interface is specified as a slave (IBCR MSS=0, IBSR AAS=1) • Whether data byte transmission is normal (IBSR AL=1) when the next interrupt is received ■ STOP Condition Write "0" to the MSS bit in master mode (IBCR MSS = 1, INT = 1) to generate a STOP condition and to place the interface in slave mode. Writing "0" to the MSS bit in any other state is ignored. After the MSS bit is cleared, the interface attempts to generate a STOP condition. However, a STOP condition will not be generated if the SCL line is driven to "L". An interrupt is generated after the next byte is transferred. Note: After "0" is written to the MSS bit, it takes time until a STOP condition is generated. If the I2C interface is disabled (IDAR DBL = 1 or ICCR EN = 0) before the STOP condition is generated, the operation stops immediately and an incorrect clock is generated on the SCL line. Disable the I2C interface (IDAR DBL = 1 or ICCR EN = 0) after checking that a STOP condition has been generated (IBSR BB = 0). 464 15.4 Operation Flowcharts ■ Slave Address Detection In slave mode, BB=1 is set after a START condition is generated. The transmitted data from the master is stored in the IDAR register. [When a 7-bit slave address is enabled] (ISMK ENSB=1) After 8-bit data is received, the IDAR and ISBA register values are compared. At this time, the values are compared with the values of the bits masked with the ISMK register. If the comparison result is a match, the AAS bit is set to "1" and an acknowledge is sent to the master. The value of bit 0 of the received data (bit 0 of the IDAR register after reception) is then inverted and stored in the TRX bit. [When a 10-bit slave address is enabled] (ITMK ENTB=1) If the header section of a 10-bit address (11110, TA1, TA0, write) is detected, an acknowledge is sent to the master, and the value of bit 0 of received data is inverted and stored in the TRX bit. No interrupt occurs at this time. Then, the next data to be transferred and the low-order data of the ITBA register are compared. They are compared with the values of the bits masked with the ISMK register at this time. If the result is a match, the AAS bit is set to "1", an acknowledge is sent to the master, and an interrupt occurs. If the address has been specified as a slave and a repeated START condition is detected, the AAS bit is set to "1" and an interrupt occurs after the header section of a 10-bit address (11110, TA1, TA0, read) is received. The interface has a 10-bit slave address register (ITBA) and a 7-bit slave address register (ISBA). If both registers are enabled (ISMK ENSB = 1, ITMK ENTB = 1), an acknowledge can be sent for the 10-bit and 7-bit addresses. The receive slave address length in slave mode (AAS = 1) is determined by the RAL bit of the ITMK register. In master mode, disabling both registers (ISMK ENSB = 0, ITMK ENTB = 0) can prevent a slave address from being generated for the I2C interface. All slave addresses can be masked by setting the ITMK and ISMK registers. ■ Slave Address Mask The slave address mask registers (ITMK and ISMK) can mask each bit of the slave address registers. A bit set to "1" in the mask register is address-compared while a bit set to "0" is ignored. In slave mode (IBSR AAS = 1), a receive slave address can be read from the ITBA register (for a 10-bit address) or the ISBA register (for a 7-bit address). If the bit mask is cleared, the interface can be used as the bus monitor because it is always accessed as a slave. Note: This feature does not become a real bus monitor because it returns an acknowledge when a slave address is received even though no other slave device is available. 465 CHAPTER 15 I2C INTERFACE ■ Master Addressing In master mode, BB = 1 and TRX = 1 are set after a START condition is generated and the IDAR register contents are outputted starting with the MSB. After address data is sent and an acknowledge is received from a slave device, bit 0 of the send data (bit 0 of the IDAR register after transmission) is inverted and stored in the TRX bit. This operation is also performed for a repeated START condition. Two bytes are sent for a 10-bit slave address during write access. The first byte consists of the header section (11110, A9, A8, 0) that indicates a 10-bit sequence, and the second byte consists of the low-order 8 bits of the slave address (A7 to A0). The 10-bit slave device in the read access state sends the above bytes and generates a repeated START condition as well as the header section (11110, A9, A8, 1) that indicates a read access. 7-bit slave address Write START condition - A6 A5 A4 A3 A2 A1 A0 0 Read START condition - A6 A5 A4 A3 A2 A1 A0 1 10-bit slave access Write START condition - 1 1 1 1 0 A9 A8 0 - A7 A6 A5 A4 A3 A2 A1 A0 Read START condition - 1 1 1 1 0 A9 A8 0 - A7 A6 A5 A4 A3 A2 A1 A0 Repeated START condition - 1 1 1 1 0 A9 A8 1 ■ Arbitration Arbitration occurs if other master devices are also sending data during sending in master mode. If data sent by the local device is 1 and the data on the SDA line is the "L" level, the local device assumes arbitration to have been lost and sets AL=1. AL = 1 is set if the interface detects an unnecessary START condition in the first bit of the data or neither a START condition nor a STOP condition can be generated. If arbitration loss is detected, MSS = 0 and TRX = 0 are set and the device enters slave receive mode and returns an acknowledge when it receives the device's own slave address. ■ Acknowledge The receiving device sends an acknowledge to the sending device. The ACK bit (IBCR) can specify whether an acknowledge is sent when data is received. Even if an acknowledge is not returned from the master during data transmission in slave mode (read access from other master devices), the TRX bit is set to "0" and the device enters receive mode. This allows the master to generate a STOP condition when the slave releases the SCL line. In master mode, an acknowledge from the slave can be checked by reading the LRB bit (IBSR). ■ Bus Error A bus error is recognized and the I2C interface is stopped if: 466 • A violation of the basic convention on the I2C bus during data transfer (including the Ack bit) is detected. • A stop condition in master mode is detected. • A violation of the basic convention on the I2C bus while the bus is idle is detected. 15.4 Operation Flowcharts ■ Communication Error that Causes No Error If an incorrect clock is generated on the SCL line due to noise or some other reason during transmission in master mode, the transmission bit counter of the I2C interface may run quickly, causing the slave to hang while the "L" level appears on the SDA line in the ACK cycle. An error (AL = 1, BER = 1) does not occur for such an incorrect clock. If this situation occurs, perform the following error processing: 1. Determine that when MSS = 1, TRX = 1, INT = 1, and LRB = 1, there is a communication error. 2. Set EN to "0", and then set EN to "1" to cause SCL to generate one clock on a pseudo basis. This action causes the slave to release the bus. The period from when EN is set to "0" until EN is set to "1" must be long enough for the slave to recognize it as a clock (about as long as the H period of a transmission clock). 3. Since IBSR and IBCR are cleared when EN is set to "0", perform retransmission processing from the START condition. At this time, a STOP condition cannot be generated even if BSS is set to "0". Insert an interval equal to or longer than n x 7 x tCPP between the point where EN is set to "1" and the point where MSS is set to "1" (START condition). Example: High-speed mode: 6 x 7 x 40 = about 1.680 µs Standard mode: 27 x 7 x 40 = about 7.560 µs (When CLKP = 25 MHz) Note: When BER is set, it is not cleared even if EN is set to "0". Clear BER, and then retransmit it. ■ Other Items 1. After arbitration lost occurs, check whether or not the local device is addressed using software. When arbitration lost occurs, the device becomes a slave in terms of hardware. However, after one-byte transfer is completed, both the CLK and DATA lines are pulled to "L". Thus, if the device is not addressed, immediately open the CLK and DATA lines. If the device is addressed, open the CLK and DATA lines after preparing for slave transmission or reception. (All of these things must be processed using software.) 2. Since the I2C bus has only one interrupt, an interrupt source is generated when one-byte transfer is completed or when an interrupt condition is met. Since multiple interrupt conditions must be checked using one interrupt, each of the flags must be checked by the interrupt routine. The following lists the interrupt conditions used when one-byte transfer is completed: • The device is a bus master. • The device is an addressed slave. • A general call address is received. • Arbitration lost occurs. 3. When arbitration lost is detected, an interrupt source is generated, not immediately but after one-byte transfer is completed. When arbitration lost is detected, the device becomes a slave in terms of hardware. However, in slave mode, a total of nine clocks must be outputted before an interrupt source can be generated. Thus, since an interrupt source is not immediately generated, no processing can be performed after arbitration lost occurs. 467 CHAPTER 15 I2C INTERFACE 15.4 Operation Flowcharts This section provides operation flowcharts using slave address, data transfer, and receive data as examples. ■ Example of Slave Address and Data Transfer Figure 15.4-1 is an example of slave address and data transfer. Figure 15.4-1 Example of Slave Address and Data Transfer 7-bit slave addressing Transfer data Start Start BER bit clear (set) Interface enable EN=1 Slave address in write access IDAR=S. address <<1+RW MSS=1 INT=0 IDAR = Byte data INT=0 N INT=1? INT=1? Y Y Y BER=1? BER=1? Y Restart and transfer due to check of AAS Bus error ACK? (LRB=0?) AL=1? Y Restart and transfer due to check of AAS N N N Y Preparing for data transfer Transfer completed - The slave does not generate ACK, or the master cannot receive ACK. - First set EN to "0" then perform retransmission. 468 Y N N AL=1? N ACK? (LRB=0?) N Y Transfer of last byte Y N Transfer completed - Generate a repeated START condition or STOP condition. - Check that a STOP condition has been generated (BB = 0), and set EN to "0". Transfer completed Transmission: - The slave does not generate ACK, or the master cannot receive ACK. - Set EN to "0" for retransmission. Reception: Generate a repeated START condition or STOP condition without acknowledge. ■ Example of Receive Data Figure 15.4-2 is an example of receive data. Figure 15.4-2 Example of Receive Data Start Slave address in read access Clear the ACK bit if data is the last read data from the slave. INT=0 INT=1? N Y Y BER=1? Bus error Restart N N Transfer of last byte Y Transfer completed Generates repeated START condition or STOP condition. 469 CHAPTER 15 I2C INTERFACE ■ Interrupt Processing Figure 15.4-3 shows interrupt processing. Figure 15.4-3 Interrupt Processing START INT=1? N Receive interrupt from another module Y BER=1? Y Bus error Restart N Y GCA=1? N N Failure of transfer Retry Y AAS=1? General call detected in slave mode Y Y AL=1? AL=1? N N Y LRB=1? Y Arbitration lost Retransfer ADT=1? No ACK from slave. Generate STOP condition or repeated START condition. N Start to transfer new data upon next interrupt. If required, change ACK bit. N TRX=1? Y Y N TRX=1? N Read receive data from IDAR. If required, change ACK bit. Write next send data to IDAR. Read receive data from IDAR. If required, change ACK bit. Clear INT bit. End of ISR 470 Write next send data to IDAR. Or clear MSS bit. CHAPTER 16 DMA CONTROLLER (DMAC) This chapter describes the DMAC, the configuration and functions of registers, and DMAC operation. 16.1 Overview 16.2 Detailed Explanation of Registers 16.3 Explanation of Operation 16.4 Operation Flowcharts 16.5 Data Path 16.6 DMA External Interface 471 CHAPTER 16 DMA CONTROLLER (DMAC) 16.1 Overview This module implements DMA (Direct Memory Access) transfer on FR family devices. When this module is used to control DMA transfer, various data transfer operations can be executed at high speed by bypassing the CPU, enhancing system performance. ■ Hardware Configuration of the DMAC This module mainly consists of the following blocks: • Five independent DMA channels • 5 channel independent access control circuit • 32-bit address registers (reload specifiable, two registers for each channel) • 16-bit transfer count register (reload specifiable, one register for each channel) • 4-bit block count register (one for each channel) • External transfer request input pins: DREQ0, DREQ1, and DREQ2 (for ch0, 1, and 2 only) Note: The MB91F353A/351A/352A/353A do not have an external interface. • External transfer request acceptance output pins: DACK0, DACK1, and DACK2 (for ch0, 1, and 2 only) Note: The MB91F353A/351A/352A/353A do not have an external interface. • DMA end output pins: DEOP0, DEOP1, and DEOP2 (for ch0, ch1, and ch2 only) Note: The MB91F353A/351A/352A/353A do not have an external interface. • Fly-by transfer (memory to I/O and I/O to memory) (for ch0, ch1, and ch2 only) Note: The MB91F353A/351A/352A/353A do not support fly-by transfer. • 2-cycle transfer ■ Main DMAC Functions Data transfer using this module mainly consists of the following functions: ● Data can be transferred independently over multiple channels (5 channels) • Priority (ch0>ch1>ch2>ch3>ch4) • The priority can be rotated between ch0 and ch1. • DMAC start sources External dedicated pin input (edge detection/level detection for ch0, 1, and 2 only) Note: The MB91F353A/351A/352A/353A do not have an external interface. Built-in peripheral requests (shared interrupt requests, including external interrupts) Software request (register write) 472 • Transfer mode Demand transfer, burst transfer, step transfer, and block transfer Note: The MB91F353A/351A/352A/353A do not support demand transfer. Addressing mode: 32-bit full addressing (increment/decrement/fixed) (The address increment/decrement range is from -255 to + 255.) Data types: Byte, halfword, and word length Single shot/reload selectable ■ Overview of the DMAC Registers Figure 16.1-1 provides an overview of the DMAC registers. Figure 16.1-1 Overview of the DMAC Registers (bit) ch 0 control/status register A DMACA0 00000200H ch 0 control/status register B DMACB0 00000204H ch 1 control/status register A DMACA1 00000208H ch 1 control/status register B DMACB1 0000020CH ch 2 control/status register A DMACA2 00000210H ch 2 control/status register B DMACB2 00000214H ch 3 control/status register A DMACA3 00000218H ch 3 control/status register B DMACB3 0000021CH ch 4 control/status register A DMACA4 00000220H ch 4 control/status register B DMACB4 00000224H All-channel control register DMACR ch 0 transfer source address register DMASA0 00001000H ch 0 transfer destination address register DMADA0 00001004H ch 1 transfer source address register DMASA1 00001008H ch 1 transfer destination address register DMADA1 0000100CH ch 2 transfer source address register DMASA2 00001010H ch 2 transfer destination address register DMADA2 00001014H ch 3 transfer source address register DMASA3 00001018H ch 3 transfer destination address register DMADA3 0000101CH ch 4 transfer source address register DMASA4 00001020H ch 4 transfer destination address register DMADA4 00001024H 31 24 23 16 15 08 07 00 00000240H 473 CHAPTER 16 DMA CONTROLLER (DMAC) ■ Block Diagram Figure 16.1-2 is a block diagram of the DMA controller (DMAC). Figure 16.1-2 Block Diagram of the DMAC Counter Selector Write back Buffer DMA transfer request to the bus controller DTC 2-stage register DTCR DMA activation source selection circuit & request acceptance control Peripheral activation request/stop input External pin activation request/stop input Counter DSS[3:0] DDNO Bus control unit Selector Counter buffer IRQ[4:0] Peripheral interrupt clear MCLREQ TYPE.MOD,WS DDNO register DSAD 2-stage register SADM,SASZ[7:0] SADR Write back Selector address Counter buffer Access 474 State transition circuit DMA control Address counter To bus controller BLK register To interrupt controller Bus control unit Write ERIR,EDIR Selector Read/write control Selector Read Priority circuit Write back DDAD 2-stage register DADM,DASZ[7:0] DADR X-bus Buffer 16.2 Detailed Explanation of Registers This section describes the DMAC registers in detail. ■ Notes on Setting Registers When the DMA controller (DMAC) is set, some bits need to be set while DMA is stopped. If they are set while DMA is in progress (during transfer), correct operation cannot be guaranteed. A marked bit indicates that the bit affects operation if it is set during DMAC transfer. Rewrite this bit while DMAC transfer is stopped (start is disabled or temporarily stopped). The setting of this bit that is made while DMA transfer start is disabled (when the DMAE bit of DMACR is "0" or the DENB bit of DMACA is "0") becomes effective when DMA transfer start is enabled. The setting of this bit that is made while DMA transfer is temporarily stopped (when the DMAH3 to DMAH0 bits of DMACR are not 0000 or the PAUS bit of DMACA is "1") becomes effective when temporary stop is canceled. 475 CHAPTER 16 DMA CONTROLLER (DMAC) 16.2.1 DMAC ch0 to ch4 Control/Status Registers A The DMACA0 to 4 registers control the operation of the DMAC channels. A separate register is provided for each channel. ■ Functions of the DMACA0 to 4 Bits The functions of the DMACA0 to 4 bits are shown below. Address bit 31 30 29 28 27 DENB PAUS STRG cho:0000200H ch1:0000208H ch2:0000210H ch3:0000218H ch4:0000220H bit 15 14 13 26 25 24 23 IS [4 : 0] 11 11 10 22 21 20 19 DDN [3 : 0] 9 8 7 6 5 18 17 16 BLK [3 : 0] 4 3 2 1 0 DTC [15 : 0] (Initial value: 00000000_0000XXXX_XXXXXXXX_XXXXXXXXB) [Bit 31] DENB (Dma ENaBle): DMA operation enable bit This bit, which corresponds to a transfer channel, is used to enable and disable DMA transfer. The activated channel starts DMA transfer when a transfer request is generated and accepted. All transfer requests that are generated for a deactivated channel are disabled. When the transfer on an activated channel reaches the specified count, this bit is set to "0" and transfer stops. The transfer can be forced to stop by writing "0" to this bit. Be sure to stop a transfer forcibly ("0" write) only after temporarily stopping DMA using the PUAS bit [Bit30 of DMACA]. If the transfer is forced to stop without first temporarily stopping DMA, DMA stops but the transferred data cannot be guaranteed. Check whether DMA is stopped using the DSS[2:0] bits [Bit18 to 16 of DMACB]. DENB Function 0 Disables operation of DMA on the corresponding channel (initial value). 1 Enables operation of DMA on the corresponding channel. • If a stop request is accepted during reset: Initialized to "0". • This bit is readable and writable. If the operation of all channels is disabled by Bit15 (DMAE bit) of the DMAC all-channel control register (DMACR), writing "1" to this bit is disabled and the stopped state is maintained. If the operation is disabled by the above bit while it is enabled by this bit, "0" is written to this bit and the transfer is stopped (forced stop). 476 [Bit 30] PAUS (PAUSe): Temporary stop instruction This bit temporarily stops DMA transfer on the corresponding channel. If this bit is set, DMA transfer is not performed before this bit is cleared (While DMA is stopped, the DSS bits are 1xx). If this bit is set before starting, DMA transfer continues to be temporarily stopped. New transfer requests that occur while this bit is set are accepted, but no transfer starts before this bit is cleared (See "16.3.11 Transfer Request Acceptance and Transfer"). PAUS Function 0 Enables DMA operation of the corresponding channel (initial value) 1 Temporarily stops DMA on the corresponding channel. • When reset: Initialized to "0". • This bit is readable and writable. [Bit 29] STRG (Software TRiGger): Transfer request This bit generates a DMA transfer request for the corresponding channel. If "1" is written to this bit, a transfer request is generated when write operation to the register is completed and transfer on the corresponding channel is started. However, if the corresponding channel is not activated, operations on this bit are disabled. Reference: If starting by a write operation to the DMAE bit and a transfer request occurring due to this bit are simultaneous, the transfer request is enabled and transfer is started. If writing of "1" to the PAUS bit and a transfer request occurring due to this bit are simultaneous, the transfer request is enabled, but DMA transfer is not started before "0" is written to the PAUS bit. STRG Function 0 Disabled 1 DMA starting request • When reset: Initialized to "0". • The read value is always "0". • Only a read value of "1" is valid. If "0" is read, operation is not affected. 477 CHAPTER 16 DMA CONTROLLER (DMAC) [Bits 28 to 24] IS4 to 0 (Input Select)*: Transfer Source Selection These bits select the source of the transfer request as listed in the table below. Note that the software transfer request by the STRG bit function is always valid regardless of the settings of these bits. IS 00000 Function Hardware 00001 Setting disabled 01101 Setting disabled 01110* External pin (DREQ) HH level or edge 01111* External pin (DREQ) LL level or edge 10000 UART0 (receiving complete) 10001 UART1 (receiving complete) 10010 UART2 (receiving complete) 10011 UART0 (sending complete) 10100 UART1 (sending complete) 10101 UART2 (sending complete) 10110 External interrupt 0 10111 External interrupt 1 11000 Reload timer 0 11001 Reload timer 1 11010 Reload timer 2 11011 External interrupt 2 11100* SI05 11101 SI06 11110 SI07 11111 A/D *: The MB91F353A/351A/352A/353A do not have external pins or an SI05 transfer source. • When reset: Initialized to "00000". • These bits are readable and writable. If DMA start resulting from an interrupt from a peripheral function is set (IS=1xxxx), disable interrupts from the selected peripheral function with the ICR register. If demand transfer mode is selected, only IS[4:0]=01110, 01111 can be set. Starting by other sources is disabled. 478 External request input is valid only for ch0, 1, and 2. External request input cannot be selected for ch3 and 4. Whether level detection or edge detection is used is determined by the mode setting. (Level detection is selected for demand transfer. For all other cases, edge detection is selected.) When the transfer factor of external interrupt 0 to 2 and A/D interrupt is selected, it is not possible to use it on the condition that the setting of CPU clock and peripheral clock by (DIVR0) of Base Clock Division Setting Register shows in the following. Dividing frequency ratio of CPU clock Dividing frequency ratio of Peripheral clock CLKB dividing frequency ratio = 1 CLKP dividing frequency ratio > 3 CLKB dividing frequency ratio = 2 CLKP dividing frequency ratio > 6 CLKB dividing frequency ratio = 3 CLKP dividing frequency ratio > 9 CLKB dividing frequency ratio = 4 CLKP dividing frequency ratio > 12 CLKB dividing frequency ratio = 5 CLKP dividing frequency ratio > 15 479 CHAPTER 16 DMA CONTROLLER (DMAC) [Bits 23 to 20] DDNO3 to 0 (direct access number): Fly-by function for built-in peripherals These bits specify the built-in peripheral of the transfer destination/source used by the corresponding channel. DDN0 Function 0000 Setting disabled 0001 Unused 0010 Unused 0011 Unused 0100 Unused 0101 Unused 0110 Unused 0111 Unused 1000 Unused 1001 Unused 1010 Unused 1011 Unused 1100 Unused 1101 Unused 1110 Unused 1111 Setting disabled • When reset: Initialized to "0000". • These bits are readable and writable. This function is not supported by the MB91350A. Any data written is ignored. 480 [Bits 19 to 16] BLK3 to 0 (BLocK size): Block size specification These bits specify the block size for block transfer on the corresponding channel. The value specified by these bits becomes the number of words in one transfer unit (more exactly, the repetition count of the data width setting). If block transfer will not be performed, set 01H (size 1). (This register value is ignored during demand transfer. The size becomes "1".) BLK XXXX Function Block size of the corresponding channel • When reset: Not initialized. • These bits are readable and writable. • If "0" is specified for all bits, the block size becomes 16 words. • During reading, the block size is always read (reload value). [Bits 15 to 00] DTC (Dma Terminal Count register): Transfer count register These bits compose a register for storing the transfer count. Each register has 16-bit length. All registers have a dedicated reload register. When the register is used for a channel that is enabled to reload the transfer count register, the initial value is automatically written back to the register when the transfer is completed. DTC XXXX Function Transfer count for the corresponding channel When DMA transfer is started, data in this register is stored in the counter buffer of the DMA-dedicated transfer count counter and is decremented by "1" (subtraction) after each transfer unit. When DMA transfer is completed, the contents of the counter buffer are written back to this register and then DMA ends. Thus, the transfer count value during DMA operation cannot be read. • When reset: Not initialized. • These bits are readable and writable. Always access DTC using halfword length or word length. • During reading, the count value is read. The reload value cannot be read. • When reset: Not initialized. 481 CHAPTER 16 DMA CONTROLLER (DMAC) 16.2.2 DMAC ch0 to ch4 Control/Status Registers B The DMACB0 to 4 registers control the operation of the DMAC channels. A separate register is provided for each channel. ■ Functions of the DMACB0 to 4 Bits The functions of the DMACB0 to 4 bits are shown below. bit 31 30 TYPE [1 : 0] bit 15 14 29 28 27 26 MOD [1 : 0] WS [1 : 0] 13 11 11 10 25 24 23 22 21 20 19 18 SADM DADM DTCR SADR DADR ERIE EDIE 9 8 7 6 SASZ [7 : 0] 5 4 3 17 16 DSS[2 : 0] 2 1 0 DASZ [7 : 0] (Initial value: 00000000_00000000_XXXXXXXX_XXXXXXXXB) [Bits 31 to 30] TYPE (TYPE): Transfer type setting These bits specify the operation type of the corresponding channel as described below. 2-cycle transfer mode: In this mode, the transfer source address (DMASA) and transfer destination address (DMADA) are set and transfer is performed by repeating the read operation and write operation for the number of times specified by the transfer count. All areas can be specified as a transfer source or transfer destination (32bit ADDRESS). Fly-by transfer mode: In this mode, external ↔ external transfer is performed in one cycle by setting a memory address as the transfer destination address (DMADA). Be sure to specify an external area for the memory address. TYPE Function 00 2-cycle transfer (initial value) 01 Fly-by: Memory to I/O transfer 10 Fly-by: I/O to memory transfer 11 Setting disabled • When reset: Initialized to "00". • These bits are readable and writable. *: The MB91F353A/351A/352A/353A do not support fly-by transfer. Setting of the TYP bit to "01" or "10" is not allowed. 482 [Bits 29 to 28] MOD (MODe): Transfer mode setting These bits set the operating mode of the corresponding channel as listed in the table below. MOD Function 00 Block/step transfer mode (initial value) 01 Burst transfer mode 10 Demand transfer mode 11 Setting disabled • When reset: Initialized to "00". • These bits are readable and writable. Note: The MB91F353A/351A/352A/353A do not support demand transfer. Setting of the MOD bit to "10" is not allowed. [Bits 27 to 26] WS (Word Size): Transfer data width selection These bits are used to select the transfer data width of the corresponding channel. Transfer operations are repeated in units of the data width specified in this register for as many times as the specified count. WS Function 00 Byte-width transfer (initial value) 01 Halfword-width transfer 10 Word-width transfer 11 Setting disabled • When reset: Initialized to "00". • These bits are readable and writable. [Bit 25] SADM (Source-ADdr. Count-Mode select): Transfer source address count mode specification This bit specifies the address processing of the transfer source address of the corresponding channel for each transfer operation. An address increment is added or an address decrement is subtracted after each transfer operation according to the specified transfer source address count width (SASZ). When the transfer is completed, the next access address is written to the corresponding address register (DMASA). As a result, the transfer source address register is not updated until DMA transfer is completed. To make the address always the same, specify "0" or "1" for this bit and set the address count width (SASZ and DASZ) to "0". SADM Function 0 Increments the transfer source address. (initial value) 1 Decrements the transfer source address. • When reset: Initialized to "0". • This bit is readable and writable. 483 CHAPTER 16 DMA CONTROLLER (DMAC) [Bit 24] DADM (Destination-ADdr. Count-Mode select): Transfer destination address count mode specification This bit specifies the address processing for the transfer destination address of the corresponding channel in each transfer operation. An address increment is added or an address decrement is subtracted after each transfer operation according to the specified transfer destination address count width (DASZ). When the transfer is completed, the next access address is written to the corresponding address register (DMADA). As a result, the transfer destination address register is not updated until the DMA transfer is completed. To make the address always the same, specify "0" or "1" for this bit and set the address count width (SASZ and DASZ) to "0". DADM Function 0 Increments the transfer destination address. (initial value) 1 Decrements the transfer destination address. • When reset: Initialized to "0". • This bit is readable and writable. [Bit 23] DTCR (DTC-reg. Reload): Transfer count register reload specification This bit controls reloading of the transfer count register for the corresponding channel. If reloading of the counter is enabled by this bit, the count register value is restored to its initial value after transfer is completed, then DMAC stops and starts waiting for a new transfer request (an activation request by STRG or IS setting). (If this bit is "1", the DENB bit is not cleared.) DENB=0 or DMAE=0 must be set to stop the transfer. In either case, the transfer is forcibly stopped. If reloading of the counter is disabled, a single shot operation occurs. In single shot operation, operation stops after the transfer is completed even if reload is specified in the address register. The DENB bit is also cleared in this case. DTCR 484 Function 0 Disables transfer count register reloading (initial value) 1 Enables transfer count register reloading. • When reset: Initialized to "0". • This bit is readable and writable. [Bit 22] SADR (Source-ADdr.-reg. Reload): Transfer source address register reload specification This bit controls reloading of the transfer source address register for the corresponding channel. If this bit enables the reload operation, the transfer source address register value is restored to its initial value after the transfer is completed. If reloading of the counter is disabled, a single shot operation occurs. In single shot operation, operation stops after the transfer is completed even if reload is specified in the address register. The address register value also stops in this case while the initial value is being reloaded. If this bit disables the reload operation, the address register value when the transfer is completed is the address to be accessed next to the final address. (When address increment is specified, the next address is an incremented address.) SADR Function 0 Disables transfer source address register reloading. (initial value) 1 Enables transfer source address register reloading. • When reset: Initialized to "0". • This bit is readable and writable. [Bit 21] DADR (Dest.-ADdr.-reg. Reload): Transfer destination address register reload specification This bit controls reloading of the transfer destination address register for the corresponding channel. If this bit enables reloading, the transfer destination address register value is restored to its initial value after the transfer is completed. The details of other functions are the same as those described for Bit22 (SADR). DADR Function 0 Disables transfer destination address register reloading. (initial value) 1 Enables transfer destination address register reloading. • When reset: Initialized to "0". • This bit is readable and writable. [Bit 20] ERIE (ERror Interrupt Enable): Error interrupt output enable This bit controls the occurrence of an interrupt for termination after an error occurs. The nature of the error that occurred is indicated by DSS2 to "0". Note that an interrupt occurs only for specific termination causes and not for all termination causes. (Refer to bits DSS2-0.) ERIE Function 0 Disables error interrupt request output. (initial value) 1 Enables error interrupt request output. • When reset: Initialized to "0". • This bit is readable and writable. 485 CHAPTER 16 DMA CONTROLLER (DMAC) [Bit 19] EDIE (EnD Interrupt Enable): End interrupt output enable This bit controls the occurrence of an interrupt for normal termination. EDIE Function 0 Disables end interrupt request output. (initial value) 1 Enables end interrupt request output. • When reset: Initialized to "0". • This bit is readable and writable. [Bits 18 to 16] DSS2 to 0 (DMA Stop Status): Transfer stop source indication These bits indicate a code (end code) of 3 bits that indicates the source of stopping or termination of DMA transfer on the corresponding channel. The table below lists the end codes: DSS Function Interrupt 000 Initial value None x01 Address error (underflow/overflow) Error x10 Transfer stop request Error x11 Normal end End 1xx DMA stopped temporarily (due, for example, to DMAH, PAUS bit, and an interrupt) None The code indicating a transfer stop request is set only if the request is received from a peripheral circuit and the external pin DSTP function is used. Notes: • The MB91F353A/351A/352A/353A do not support the external pin DSTP function. • The Interrupt column indicates the type of interrupts that can occur. • When reset: Initialized to "000". • These bits can be cleared by writing "000" to them. • These bits are readable and writable. Note, however, that the only valid written value is "000". [Bits 15 to 8] SASZ (Source Addr count SiZe): Transfer source address count size specification These bits specify the increment or decrement width for the transfer source address (DMASA) of the corresponding channel for each transfer operation. The value set by these bits becomes the address increment/decrement width for each transfer unit. The address increment/decrement width conforms to the instruction in the transfer source address count mode (SADM). SASZ XXXX 486 Function Specify the increment/decrement width of the transfer source address. "0" to "255" • When reset: Not initialized • These bits are readable and writable. [Bits 7 to 0] DASZ (Des Addr count SiZe): Transfer destination address count size specification These bits specify the increment or decrement width for the transfer destination address (DMADA) of the corresponding channel for each transfer operation. The value set by these bits becomes the address increment/decrement width for each transfer unit. The address increment/decrement width conforms to the instruction in the transfer destination address count mode (DADM). DASZ XXXX Function Specify the increment/decrement width of the transfer destination address. "0" to "255" • When reset: Not initialized • These bits are readable and writable. 487 CHAPTER 16 DMA CONTROLLER (DMAC) 16.2.3 DMAC ch0 to ch4 Transfer Source/Transfer Destination Address Setting Registers The DMASA0 to 4 registers and DMADA0 to 4 registers control the operation of the DMAC channels. A separate register is provided for each channel. ■ Functions of the DMASA0 to 4 Bits and DMADA0 to 4 Bits The functions of the DMASA0 to 4 bits and DMADA0 to 4 bits are shown below. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DMASA [31 : 16] bit 15 14 13 11 11 10 9 8 7 DMASA [15 : 0] (Initial value: XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX Bit) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DMADA [31 : 16] bit 15 14 13 11 11 10 9 8 7 DMADA [15 : 0] (Initial value: XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX Bit) DMASA0 to 4 and DMADA0 to 4 are a group of registers used to store transfer source and transfer destination addresses. The length of each register is 32 bits. [Bits 31 to 0] DMASA (DMA Source Addr): Transfer source address setting These bits set the transfer source address. [Bits 31 to 0] DMADA (DMA Destination Addr): Transfer destination address setting These bits set the transfer destination address. If DMA transfer is activated, data in this register is stored in the counter buffer of the DMA-dedicated address counter and then the address is counted according to the settings for the transfer operation. When the DMA transfer is completed, the contents of the counter buffer are written back to this register and then DMA ends. Thus, the address counter value during DMA operation cannot be read. All registers have a dedicated reload register. When the register is used for a channel that is enabled for reloading of the transfer source/transfer destination address register, the initial value is automatically written back to the register when the transfer is completed. Other address registers are not affected. • When reset: Not initialized. • These bits are readable and writable. For this register, be sure to access these bits as 32-bit data. • If these bits are read during transfer, the address before the transfer is read. If they are read after transfer, the next access address is read. Because the reload value cannot be read, it is not possible to read the transfer address in real time. 488 Note: Do not set any of the DMAC’s registers using this register. DMA transfer is not possible for the DMAC’s registers themselves. 489 CHAPTER 16 DMA CONTROLLER (DMAC) 16.2.4 DMAC ch0 to ch4 DMAC All-Channel Control Register The DMACR register controls the operation of all five DMAC channels. Always use byte length to access this register. ■ Functions of the DMACR Bits The functions of the DMACR bits are shown below. bit bit 31 30 29 28 27 26 25 DMAE - - PMO1 15 14 13 11 11 10 9 - - - - - - - 24 23 22 21 20 19 18 17 16 - - - - - - - - 8 7 6 5 4 3 2 1 0 - - - - - - - - - DMAH [3 : 0] (Initial value: 0XX00000_XXXXXXXX_XXXXXXXX_XXXXXXXXB) [Bit 31] DMAE (DMA Enable): DMA operation enable This bit controls the operation of all DMA channels. If DMA operation is disabled with this bit, transfer operations on all channels are disabled regardless of the start/stop settings for each channel and the operating status. Any channel carrying out transfer cancels the requests and stops transfer at a block boundary. All start operations on each channel in a disabled state are disabled. If this bit enables DMA operation, start/stop operations are enabled for all channels. Simply enabling DMA operation with this bit does not activate each channel. DMA operation can be forced to stop by writing "0" to this bit. However, be sure to force stopping ("0" write) only after temporarily stopping DMA using the DMAH[3:0] bits [Bit27-24 of DMACR]. If forced stopping is carried out without first temporarily stopping DMA, DMA stops, but the transfer data cannot be guaranteed. Check whether DMA is stopped using the DSS[2:0] bits [Bit18 to 16 of DMACB]. DMAE 490 Function 0 Disables DMA transfer on all channels. (initial value) 1 Enables DMA transfer on all channels. • When reset: Initialized to "0". • This bit is readable and writable. [Bit 28] PM01 (Priority mode ch0,1 robin): Channel priority rotation This bit is set to alternate priority for each transfer between Channel0 and Channel1. PM01 Function 0 Fixes the priority. ( ch0 > ch1 )(initial value) 1 Alternates priority. ( ch1 > ch0 ) • When reset: Initialized to "0". • This bit is readable and writable. [Bits 27 to 24] DMAH (DMA Halt): DMA temporary stop These bits control temporary stopping of all DMA channels. If these bits are set, DMA transfer is not performed on any channel before these bits are cleared. When DMA transfer is activated after these bits are set, all channels remain temporarily stopped. Transfer requests that occur on channels for which DMA transfer is enabled (DENB=1) while these bits are set are all enabled. The transfer can be started by clearing all these bits. DMAH 0000 Other than 0000 Function Enables the DMA operation on all channels. (initial value) Temporarily stops DMA operation on all channels. • When reset: Initialized to "0". • These bits are readable and writable. [Bits 30, 29, and 23 to 0] (Reserved): Unused bits • A read value is undefined. ■ Other Functions The MB91350A has the DACK, DEOP, and DREQ pins, which can be used for external transfer. These pins can also be used as general-purpose ports. To use the DACK, DEOP, and DREQ pins for external transfer, their operation mode must be switched from the port function to the DMA pin function. To make the switch, set the PFR register. Note: The MB91F353A/351A/352A/353A do not have an external interface. 491 CHAPTER 16 DMA CONTROLLER (DMAC) 16.3 Explanation of Operation This section provides an overview of DMAC operation. It also provides details of transfer request settings and transfer sequences and operational details. ■ Overview of DMAC The DMAC block is a multifunctional DMA controller that controls high-speed data transfer without the use of CPU instructions. It is built into all FR family devices. 492 16.3.1 Overview of Operation This section provides an overview of DMAC operation. ■ Main DMAC Operations Functions can be set for each transfer channel independently. Once starting has been enabled, a channel starts transfer operation only after a specified transfer request has been detected. After a transfer request is detected, a DMA transfer request is outputted to the bus controller and the bus right is acquired by the bus controller before the transfer is started. The transfer is carried out as a sequence conforming to the mode settings made independently for the channel being used. ■ Transfer Mode Each DMA channel performs transfer according to the transfer mode set by the MOD[1:0] bits of its DMACB register. ● Block/step transfer Only a single block transfer unit is transferred in response to one transfer request. DMA then stops requesting the bus controller for transfer until the next transfer request is received. The block transfer unit is the specified block size: (BLK[3:0] of DMACA). ● Burst transfer Transfer in response to one transfer request is carried out continuously for the number of times in the specified transfer count. The specified transfer count is the transfer count: (BLK[3:0] of DMACA X DTC[15:0] of DMACA) X block size. ● Demand transfer Note: The MB91F353A/351A/352A/353A do not support demand transfer. Transfer is carried out continuously until the transfer request input (detected with a level at the DREQ pin) from an external device ends or a specified transfer count is reached. The specified transfer count in a demand transfer is the specified transfer count: (DTC[15:0] of DMACA). The block size is always "1" and the register value is ignored. 493 CHAPTER 16 DMA CONTROLLER (DMAC) ■ Transfer Type ● 2-cycle transfer (normal transfer) The DMA controller operates using as its unit of operation a read operation and a write operation. Data is read from an address in the transfer source register and then written to another address in the transfer destination register. ● Fly-by transfer (memory → I/O) Note: The MB91F353A/351A/352A/353A do not support fly-by transfer. The DMA controller operates using as its unit of operation a read operation. If DMA transfer is performed when fly-by transfer is set, DMA issues a fly-by transfer (read) request to the bus controller and the bus controller lets the external interface carry out the fly-by transfer (read). ● Fly-by transfer (I/O → memory) Note: The MB91F353A/351A/352A/353A do not support fly-by transfer. The DMA controller operates using as its unit of operation a write operation. Otherwise, operation is the same as fly-by transfer (memory → I/O) operation. Access areas used for MB91F355A/F356B/F357B/355A fly-by transfer must be external areas. ■ Transfer Address The following types of addressing are available and can be set independently for each channel transfer source and transfer destination. The method for specifying the address setting register (DMASA/DMADA) for a 2-cycle transfer and the method for a fly-by transfer are different. ● Specifying the address for a 2-cycle transfer The value read from a register (DMASA/DMADA) in which an address has been set in advance is used as the address for access. After receiving a transfer request, DMA stores the address from the register in the temporary storage buffer and then starts transfer. After each transfer (access) operation, the next access address is generated (increment/decrement/fixed selectable) by the address counter and then restored to the temporary storage buffer. Because the contents of the temporary storage buffer are written back to the register (DMASA/DMADA) after each block transfer unit is completed, the address register (DMASA/DMADA) value is updated after each block transfer unit is completed, making it impossible to determine the address in real time during transfer. ● Specifying the address for a fly-by transfer Note: The MB91F353A/351A/352A/353A do not support fly-by transfer. In a fly-by transfer, the value read from the transfer destination address register (DMADA) is used as the address for access. The transfer source address register (DMASA) is ignored. Be sure to specify an external area as the address to be set. After receiving a transfer request, DMA stores the address from the register in the temporary storage buffer and then starts transfer. 494 After each transfer (access) operation, the next access address is generated (increment/decrement/fixed selectable) by the address counter and then restored to the temporary storage buffer. Because the contents of this temporary storage buffer are written back to the register (DMADA) after each block transfer unit is completed, the address register (DMADA) value is updated after each block transfer unit is completed, making it impossible to determine the address in real time during transfer. ■ Transfer Count and Transfer End ● Transfer count The transfer count register is decremented (-1) after each block transfer unit is completed. When the transfer count register becomes "0", counting for the specified transfer ends, and the transfer stops with the end code displayed or is reactivated (1). Like the address register, the transfer count register is updated only after each block transfer unit. If transfer count register reloading is disabled, the transfer ends. If reloading is enabled, the register is initialized and then waits for transfer (DTCR of DMACB) ● Transfer end Listed below are the sources for transfer end. When transfer ends, a source is indicated as the end code (DSS[2:0] of DMACB). • End of the specified transfer count (DMACA:BLK[3:0] x DMACA:DTC[15:0]) => Normal end • A transfer stop request from a peripheral circuit or the external pin (DSTP) occurred => Error • An address error occurred => Error • A reset occurred => Reset The transfer stop source is indicated (DSS) and the transfer end interrupt or error interrupt for the end source is generated. 495 CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.2 Setting a Transfer Request The following three types of transfer requests are provided to activate DMA transfer: • External transfer request pin • Built-in peripheral request • Software request Software requests can always be used regardless of the settings for other requests. ■ External Transfer Request Pin A transfer request is generated by input to the input pin prepared for a channel. The MB91350A supports channels 0 to 2 (DREQ0, 1, and 2). If the input is valid at this point, the following sources are selected depending on the settings for the transfer type and the start source: [Edge detection] If the transfer type is block, step, or burst transfer, select edge detection: • Falling edge detection: Set with the transfer source selection register. Set when the IS4 to IS0 bits of DMACA are 01110. • Rising edge detection: Set with the transfer source selection register. Set when the IS4 to IS0 bits of DMACA are 01111. If the transfer type is demand transfer, select level detection: • "H" level detection:Set with the transfer source selection register. Set when the IS4 to IS0 bits of DMACA are 01110. • "L" level detection: Set with the transfer source selection register. Set when the IS4 to IS0 bits of DMACA are 01111. Note: The MB91F353A/351A/352A/353A cannot use the external transfer request pin. ■ Built-in Peripheral Request A transfer request is generated by an interrupt from the built-in peripheral circuit. For each channel, set the peripheral’s interrupt by which a transfer request is generated (when the IS4 to IS0 bits of DMACA are 1xxxx). The built-in peripheral request cannot be used together with an external transfer request. Note: Because an interrupt request used in a transfer request seems like an interrupt request to the CPU, disable interrupts from the interrupt controller (ICR register). ■ Software Request A transfer request is generated by writing to the trigger bit of a register (STRG of DMACA). The software request is independent of the above two types of transfer request and can always be used. If a software request occurs concurrently with activation (transfer enable request), a DMA transfer request is outputted to the bus controller immediately and transfer is started. 496 16.3.3 Transfer Sequence The transfer type and the transfer mode that determine, for example, the operation sequence after DMA transfer has started can be set independently for each channel (Settings for TYPE[1:0] and MOD[1:0] of DMACB). ■ Selection of the Transfer Sequence The following sequence can be selected with a register setting: • Burst 2-cycle transfer • Demand 2-cycle transfer Note: The MB91F353A/351A/352A/353A do not support demand 2-cycle transfer. • Block/step 2-cycle transfer • Burst fly-by transfer Note: The MB91F353A/351A/352A/353A do not support burst fly-by transfer. • Demand fly-by transfer Note: The MB91F353A/351A/352A/353A do not support demand fly-by transfer. • Block/step fly-by transfer Note: The MB91F353A/351A/352A/353A do not support block/step fly-by transfer. ■ Burst 2-Cycle Transfer In a burst 2-cycle transfer, as many transfers as specified by the transfer count are performed continuously for one transfer source. For a 2-cycle transfer, all 32-bit areas can be specified using a transfer source/ transfer destination address. A peripheral transfer request, software transfer request, or external pin (DREQ) edge input detection request can be selected as the transfer source. Table 16.3-1 lists the specifiable transfer addresses for burst 2-cycle transfer. Table 16.3-1 Specifiable Transfer Addresses for Burst 2-Cycle Transfer Transfer source addressing Direction Transfer destination addressing All 32-bit areas specifiable → All 32-bit areas specifiable [Features of a burst transfer] • When one transfer request is received, transfer is performed continuously until the transfer count register reaches 0. The transfer count is the transfer count x block size (BLK[3:0] of DMACA x DTC[15:0] of DMACA). • Another request occurring during transfer is ignored. • If the reload function of the transfer count register is enabled, the next request is accepted after transfer ends. • If a transfer request for another channel with a higher priority is received during transfer, the channel is switched at the boundary of the block transfer unit. Processing resumes only after the transfer request for the other channel is cleared. 497 CHAPTER 16 DMA CONTROLLER (DMAC) Figure 16.3-1 shows an example of burst transfer. Figure 16.3-1 Example of Burst Transfer Transfer request ( edge) Bus operation DA SA CPU Transfer count SA DA 4 3 SA DA 2 SA DA CPU 1 0 Transfer end ■ Burst Fly-by Transfer A burst fly-by transfer has the same features as a 2-cycle transfer except that the transfer area can only be external areas, and the transfer unit is read (memory → I/O) or write (I/O → memory) only. Table 16.3-2 lists the specifiable transfer addresses for burst fly-by transfer. Table 16.3-2 Specifiable Transfer Addresses for Burst Fly-by Transfer Transfer source addressing Direction Transfer destination addressing Specification not required (invalid) None External area ■ Demand Transfer 2-Cycle Transfer A demand transfer sequence is generated only if "H" level or "L" level of an external pin is selected as a transfer request. (Select the level with IS[3:0] of DMACA.) [Features of a continuous transfer] • Each transfer operation of a transfer request is checked. While the external input level is within the range of the specified transfer request levels, transfer is performed continuously without the request being cleared. If the external input changes, the request is cleared and the transfer stops at the transfer boundary. This operation is repeated for the number of times specified by the transfer count. • Otherwise, operations are the same as those of a burst transfer. Figure 16.3-2 shows an example of demand transfer. Figure 16.3-2 Example of Demand Transfer Transfer request ("H" level) Bus operation Transfer count CPU DA SA 32 SA DA CPU DA SA 1 0 Transfer end (Example of demand transfer where demand transfer is started by "H" level detection at an external pin, the number of blocks is "1", and the transfer count is "3".) 498 Table 16.3-3 lists the specifiable transfer addresses for demand transfer 2-cycle transfer. Table 16.3-3 Specifiable Transfer Addresses for Demand Transfer 2-Cycle Transfer Transfer source address Direction Transfer destination address External area → External area External area → Built-in I/O External area → Built-in RAM Built-in I/O → External area Built-in RAM → External area For a demand transfer, be sure to set an external area address for the transfer source or transfer destination or both. Since DMA transfer is adjusted to the external bus timing in demand transfer mode, access to external areas is always needed. Since the SDRAM area is not supported as a transfer source/transfer destination during demand transfer, this area cannot be set. ■ Demand Transfer Fly-by Transfer A demand transfer fly-by transfer has the same features as a 2-cycle transfer except that the transfer area can only be external areas, and the transfer unit is read (memory → I/O) or write (I/O → memory) only. Table 16.3-4 lists the specifiable transfer addresses for demand transfer fly-by transfer. Table 16.3-4 Specifiable Transfer Addresses for Demand Transfer Fly-by Transfer Transfer source addressing Direction Transfer destination addressing Specification not required (invalid) None External area ■ Step/Block Transfer 2-Cycle Transfer For a step/block transfer (Transfer for each transfer request is performed as many times as the specified block count), all 32-bit areas can be specified as the transfer source/transfer destination address. Table 16.3-5 lists the specifiable transfer addresses for step/block transfer 2-cycle transfer. Table 16.3-5 Specifiable Transfer Addresses for Step/Block Transfer 2-Cycle Transfer Transfer source addressing Direction Transfer destination addressing All 32-bit areas specifiable → All 32-bit areas specifiable 499 CHAPTER 16 DMA CONTROLLER (DMAC) ■ Step Transfer If "1" is set as the block size, a step transfer sequence is generated. [Features of a step transfer] • If a transfer request is received, the transfer request is cleared after one transfer operation and then the transfer is stopped (The DMA transfer request to the bus controller is canceled). • Another request occurring during transfer is ignored. • If a transfer request for another channel with a higher priority is received during transfer, the channel is switched after the transfer is stopped and then restarted. Priority in a step transfer is valid only if transfer requests occur simultaneously. ■ Block Transfer If any value other than "1" is specified as the block size, a block transfer sequence is generated. [Features of a block transfer] • The block transfer has the same features as those of a step transfer except that one transfer unit consists of multiple transfer cycle counts (number of blocks). Figure 16.3-3 shows an example of block transfer. Figure 16.3-3 Example of Block Transfer Transfer request ( Bus operation Number of blocks edge) CPU SA DA SA DA CPU 21 Transfer count 0 2 SA DA SA DA 1 2 1 Transfer end (Example of block transfer where block transfer is started by rising-edge detection at an external pin, the number of blocks is "2", and the transfer count is "2".) ■ Step/Block Transfer 2-Cycle Transfer Fly-by Transfer This transfer has the same features as those of a 2-cycle transfer except that the transfer area can only be external areas, and the transfer unit is read (memory → I/O) or write (I/O → memory) only. Table 16.3-6 lists the specifiable transfer addresses for step/block transfer 2-cycle transfer fly-by transfer. Table 16.3-6 Specifiable Transfer Addresses for Step/Block Transfer 2-Cycle Transfer Flyby Transfer 500 Transfer source addressing Direction Transfer destination addressing Specification not required (invalid) None External area 16.3.4 General Aspects of DMA Transfer This section describes DMA transfer. ■ Block Size The unit and increment for transfer data is a set of (the number set in the block size specification register x data width) data. Since the amount of data transferred in one transfer cycle is determined by the value specified as the data width, one transfer unit is consists of the number of transfer cycles for the specified block size. If a transfer request with a higher priority is received during transfer or if a temporary stop request for a transfer occurs, the transfer stops only at the transfer unit boundary, whether or not the transfer is a block transfer. This arrangement makes it possible to protect data for which division or temporary stopping is not desirable. However, if the block size is large, response time increases. Transfer stops immediately only when a reset occurs, in which case the data being transferred cannot be guaranteed. ■ Reload Operation In this module, the following three types of reloading can be set for each channel: (1) Transfer count register reloading After transfer is performed the specified number of times, the initial value is set in the transfer count register again and waiting for a start request starts. Set this type of reloading when the entire transfer sequence is to be performed repeatedly. If reload is not specified, the count register value remains "0" after the transfer is performed the specified number of times and no further transfer is performed. (2) Transfer source address register reloading After transfer is performed the specified number of times, the initial value is set in the transfer source address register again. Set this type of reloading when transfer is to be repeated from a fixed area in the transfer source address area. If reload is not specified, the transfer source address register value after the transfer is performed the specified number of times becomes the next address. Use this type when the address area is not fixed. (3) Transfer destination address register reloading After transfer is performed the specified number of times, the initial value is set in the transfer destination address register again. Set this type of reloading when transfer is to be repeated to a fixed area in the transfer destination address area. (The processing hereafter is the same as described in "Transfer source address register reloading" above.) 501 CHAPTER 16 DMA CONTROLLER (DMAC) If only reloading of the transfer source/transfer destination register is enabled, restart after transfer is performed the specified number of times is not implemented and only the values of each address register are set. [Special examples of operating mode and the reload operation] If transfer is performed in continuous transfer mode by external pin input level detection and transfer count register reloading is used, transfer continues by reloading even though transfer ends during continuous input. Also in this case, an end code is set. If it is preferable that processing stops when data transfer ends and starts after input is detected again, do not specify reload. For a transfer in burst, block, or step transfer mode, transfer stops temporarily after reload when data transfer ends. Transfer does not start until new transfer request input is detected. 502 16.3.5 Addressing Mode Specify the transfer destination/transfer source address independently for each transfer channel. This section describes the specification method. Specify the addresses based on the transfer sequence. ■ Address Register Specifications In 2-cycle transfer mode, set the transfer source address in the transfer source address setting register (DMASA) and the transfer destination address in the transfer destination address setting register (DMADA). In fly-by transfer mode, specify the memory address in the transfer source address setting register (DMASA). In this case, the value in the transfer destination address setting register (DMADA) is ignored. [Features of the Address Register] • This register has the maximum 32-bit length. With 32-bit length, all space in the memory map can be accessed. [Function of the Address Register] • The address register is read in each access operation and the read value is sent to the address bus. • At the same time, the address for the next access is calculated by the address counter and the address register is updated using the calculated address. • For address calculation, increment or decrement is selected independently for each channel, transfer destination, and transfer source. The address increment/decrement width is specified by the address count size register (SASZ/DASZ of DMACB). • If reloading is not enabled, the address resulting from the address calculation of the last address remains in the address register when the transfer ends. • If reloading is enabled, the initial value of the address is reloaded. Note: If an overflow or underflow occurs as a result of 32-bit length full address calculation, an address error is detected and transfer on the relevant channel is stopped. (Refer to the description for the items related to the end code). 503 CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.6 Data Types Select the data length (data width) transferred in one transfer operation from the following: • Byte • Halfword • Word ■ Access Address Since the word boundary specification is also observed in DMA transfer, different low-order bits are ignored if an address with a different data length is specified for the transfer destination/transfer source address. • Word: The actual access address has a 4-byte length starting with "00" as the lowest-order 2 bits. • Halfword: The actual access address has 2-byte length starting with "0" as the lowest-order bit. • Byte: The actual access address and the addressing match. If the lowest-order bits in the transfer source address and transfer destination address are different, the addresses as set are output on the internal address bus. However, each transfer target on the bus is accessed after the addresses are corrected according to the above rules. 504 16.3.7 Transfer Count Control Specify the transfer count within the range of the maximum 16-bit length (1 to 65536). Set the transfer count value in the transfer count register (DTC of DMACA). ■ Transfer Count Registers and Reload Operation The register value is stored in the temporary storage buffer when the transfer starts and is decremented by the transfer count counter. When the counter value becomes "0", transfer end for the specified count is detected, and the transfer on the channel is stopped or waiting for a restart request starts (when reload is specified). [Features of the group of transfer count registers:] • Each register has 16-bit length. • All registers have a dedicated reload register. • If transfer is activated when the register value is "0", transfer is performed 65536 times. [Reload operation] • The reload operation can be used only if reloading is enabled in a register that allows reloading. • When transfer is activated, the initial value of the count register is saved in the reload register. • If the transfer count counter counts down to "0", end of transfer is reported and the initial value is read from the reload register and written to the count register. 505 CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.8 CPU Control When a DMA transfer request is accepted, DMA issues a transfer request to the bus controller. The bus controller passes the right to use the internal bus to DMA at a break in bus operation and DMA transfer starts. ■ DMA Transfer and Interrupts During DMA transfer, interrupts are generally not accepted until the transfer ends. If a DMA transfer request occurs during interrupt processing, the transfer request is accepted and interrupt processing is stopped until the transfer is completed. If, as an exception, an NMI request or an interrupt request with a higher level than the hold suppress level set by the interrupt controller occurs, DMAC temporarily cancels the transfer request via the bus controller at a transfer unit boundary (one block) to temporarily stop the transfer until the interrupt request is cleared. In the meantime, the transfer request is retained internally. After the interrupt request is cleared, DMAC issues a transfer request to the bus controller again to acquire the right to use the bus and then restarts DMA transfer. ■ Suppressing DMA When an interrupt source with a higher priority occurs during DMA transfer, an FR family device interrupts the DMA transfer and branches to the relevant interrupt routine. This feature is valid as long as there are any interrupt requests. When all interrupt sources are cleared, the suppression feature no longer works and the DMA transfer is restarted by the interrupt processing routine. Thus, if you want to suppress restart of DMA transfer after clearing interrupt sources in the interrupt source processing routine at a level that interrupts DMA transfer, use the DMA suppress function. The DMA suppress function can be activated by writing any value other than "0" to the DMAH[3:0] bits of the DMA all-channel control register and can be stopped by writing "0" to these bits. This function is mainly used in the interrupt processing routines. Before the interrupt sources in an interrupt processing routine are cleared, the DMA suppress register is incremented by "1". If this is done, then no DMA transfer is performed. After interrupt processing, decrement the DMAH[3:0] bits by "1" before returning. If multiple interrupts have occurred, DMA transfer continues to be suppressed since the DMAH[3:0] bits are not "0" yet. If a single interrupt has occurred, the DMAH[3:0] bits become "0". DMA requests are then enabled immediately. Notes: • Since the register has only 4 bits, this function cannot be used for multiple exceeding 15 levels. • Be sure to assign the priority of the DMA tasks at a level that is at least 15 levels higher than other interrupt levels. 506 16.3.9 Hold Arbitration When a device is operating in external bus extended mode, an external hold function can be used. The relationship between external hold requests and DMA transfer requests by this module when the hold function can be used is described below. ■ DMA Transfer Request During External Hold The DMA transfer is started but when an external bus area is accessed, DMA transfer is temporarily stopped. When the external hold is released, DMA transfer is restarted. ■ External Hold Request During DMA Transfer The device is externally held. When an external bus area is accessed by DMA transfer, DMA transfer is temporarily stopped. When the external hold is released, DMA transfer is restarted. ■ Simultaneous Occurrence of a DMA Transfer Request and an External Hold Request The device is externally held and internal DMA transfer is started. When an external bus area is accessed by DMA transfer, DMA transfer is temporarily stopped. When the external hold is released, DMA transfer is restarted. 507 CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.10 Operation from Starting to End/Stopping Starting of DMA transfer is controlled independently for each channel, but before transfer starts, the operation of all channels needs to be enabled. ■ Enabling Operation for All Channels Before activating each DMAC channel, operation for all channels needs to be enabled in advance with the DMA operation enable bit (DMAE of DMACR). All start settings and transfer requests that occurred before operation is enabled are invalid. ■ Starting Transfer The transfer operation can be started by the operation enable bit of the control register for each channel. If a transfer request to an activated channel is accepted, the DMA transfer operation is started in the specified mode. ■ Starting from a Temporary Stop If a temporary stop occurs before starting with channel-by-channel or all-channel control, the temporary stopped state is maintained even though the transfer operation is started. If transfer requests occur in the meantime, they are accepted and retained. When temporary stopping is released, transfer is started. 508 16.3.11 Transfer Request Acceptance and Transfer This section describes transfer request acceptance and transfer. ■ Transfer Request Acceptance and Transfer Sampling for transfer requests set for each channel starts after starting. If edge detection is selected for the external pin start source and a transfer request is detected, the request is retained within DMAC until the clear conditions are met (when the external pin start source is selected for block, step, or burst transfer). If level detection or peripheral interrupt start is selected for the external pin start source, DMAC continues the transfer until all transfer requests are cleared. When they are cleared, DMAC stops the transfer after one transfer unit (demand transfer or peripheral interrupt start). Since peripheral interrupts are handled as level detection, use interrupt clear by DMA to handle the interrupts. Transfer requests are always accepted while other channel requests are being accepted and transfer performed. The channel that will be used for transfer is determined for each transfer unit after priority has been checked. 509 CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.12 Clearing Peripheral Interrupts by DMA This DMA has a function that clears peripheral interrupts. This function works when peripheral interrupt is selected as the DMA start source (when IS[4:0]=1xxxx). Peripheral interrupts are cleared only for the set start sources. That is, only the peripheral functions set by IS[4:0] are cleared. ■ Timing for Clearing Interrupts During DMA The timing for clearing an interrupt depends on the transfer mode. (See Section "16.4 Flowcharts"). Operation [Block/step transfer] If block transfer is selected, a clear signal is generated after one block (step) transfer. [Burst transfer] If burst transfer is selected, a clear signal is generated after transfer is performed the specified number of times. [Demand transfer] Since only start requests from external pins are supported in demand transfer, no clear signal is generated. 510 16.3.13 Temporary Stopping This section describes the temporary stopping of DMA transfer. ■ Setting of Temporary Stopping by Writing to the Control Register (Set Independently for Each Channel or all Channels Simultaneously) If temporary stopping is set using the temporary stop bit, transfer on the corresponding channel is stopped until release of temporary stopping is set again. You can check the DSS bits for temporary stopping. Transfer is restarted when temporary stopping is canceled. ■ NMI/Hold Suppress Level Interrupt Processing If an NMI request or an interrupt request with a higher level than the hold suppress level occurs, all channels on which transfer is in progress are stopped at the boundary of the transfer unit and the bus right is released to give priority to NMI/interrupt processing. Transfer interrupts accepted during NMI/interrupt processing are retained, initiating a wait for completion of NMI processing. Channels for which requests are retained restart transfer after NMI/interrupt processing is completed. 511 CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.14 Operation End/Stopping The end of DMA transfer is controlled independently for each channel. It is also possible to disable operation for all channels at once. ■ Transfer End If reloading is disabled, transfer is stopped, "Normal end" is displayed as the end code, and all transfer requests are disabled after the transfer count register becomes "0" (Clear the DENB bit of DMACA). If reloading is enabled, the initial value is reloaded, "Normal end" is displayed as the end code, and a wait for transfer requests starts again after the transfer count register becomes "0" (Do not clear the DENB bit of DMACA). ■ Disabling All Channels If the operation of all channels is disabled with the DMA operation enable bit DMAE, all DMAC operations, including operations on active channels, are stopped. Then, even if the operation of all channels is enabled again, no transfer is performed unless a channel is restarted. In this case, no interrupt whatever occurs. 512 16.3.15 Stopping Due To an Error In addition to normal end after transfer for the number of times specified, stopping as the result of various types of errors and the forced stopping are provided. ■ Transfer Stop Requests from Peripheral Circuits Depending on the peripheral circuit that outputs a transfer request, a transfer stop request is issued when an error is detected (Example: Error when data is received at or sent from a communications system peripheral). The DMAC, when it receives such a transfer stop request, displays "Transfer stop request" as the end code and stops the transfer on the corresponding channel. IS Function 00000 Hardware Transfer stop request None 01111 External pin "L" level or edge 10000 UART0 (Reception completed) 10010 UART2 (Reception completed) 10011 UART0 (Transmission completed) 11111 A/D Yes None * For details of the conditions under which a transfer stop request is generated, see the specifications for each peripheral circuit. ■ Occurrence of an Address Error Inappropriate addressing occurring in an addressing mode is detected as an address error. An example of inappropriate addressing is an overflow or underflow that occurs in the address counter when a 32-bit address is specified. If an address error is detected, "An address error occurred" is displayed as the end code and transfer on the corresponding channel is stopped. 513 CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.16 DMAC Interrupt Control Independent of peripheral interrupts that become transfer requests, interrupts can also be outputted for each DMAC channel. ■ Interrupts That Enable DMAC Interrupt Control Outputs • Transfer end interrupt: Occurs only when operation ends normally. • Error interrupt: Transfer stop request due to a peripheral circuit (error due to a peripheral) Occurrence of address error (error due to software) All of these interrupts are outputted according to the meaning of the end code. An interrupt request can be cleared by writing "000" to DSS2 to "0" (end code) of DMACS. Be sure to clear the end code by writing "000" before restarting. If reloading is enabled, the transfer is automatically restarted. At this point, however, the end code is not cleared and is retained until a new end code is written when the next transfer ends. Since only one end source can be displayed in an end code, the result after considering the order of priority is displayed when multiple sources occur simultaneously. The interrupt that occurs at this point conforms to the displayed end code. The following shows the priority for displaying end codes (in order of decreasing priority): 514 • Reset • Clearing by writing "000" • Peripheral stop request or external pin input (DSTP) stop request • Normal end • Stopping when address error detected • Channel selection and control 16.3.17 DMA Transfer during Sleep The DMAC can also operate in sleep mode. This section describes DMA transfer in sleep mode. ■ Notes on DMA Transfer in Sleep Mode If you anticipate operations during sleep mode, note the following: 1. Since the CPU is stopped, DMAC registers cannot be rewritten. Make settings before sleep mode is entered. 2. The sleep mode is released by an interrupt. Thus, if a peripheral interrupt is selected as the DMAC start source, interrupts must be disabled by the interrupt controller. Similarly, if you do not want to release sleep mode with a DMAC end interrupt, disable DMAC end interrupts. 515 CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.18 Channel Selection and Control Up to five channels can be simultaneously set as transfer channels. In general, an independent function can be set for each channel. ■ Priority Among Channels Since DMA transfer is possible only on 1 channel at a time, priority must be set for the channels. Two modes, fixed and rotation, are provided as the priority settings and can be selected for each channel group (described later). ● Fixed mode The order of priority is fixed by channel number, with priority decreasing from ch0 to ch4: (ch0 > ch1 > ch2 > ch3 > ch4) If a transfer request with a higher priority is received during a transfer, the transfer channel becomes the channel with the higher priority when the transfer for the transfer unit (number set in the block size specification register x data width) ends. When higher priority transfer is completed, transfer is restarted on the previous channel. Figure 16.3-4 shows DMA transfer in fixed mode. Figure 16.3-4 DMA Transfer in Fixed Mode ch0 transfer request ch1 transfer request Bus operation Transfer ch ch0 transfer end ch1 transfer end 516 CPU SA DA ch1 SA DA ch0 SA DA ch0 SA DA ch1 CPU ● Rotation mode (ch.0 to ch.1 only) When operation is enabled, the initial states have the same order that they would have in fixed mode, but at the end of each transfer operation, the priority of the channels is reversed. Thus, if more than one transfer request is outputted at the same time, the channel is switched after each transfer unit. This mode is effective when continuous or burst transfer is set. Figure 16.3-5 shows DMA transfer in rotation mode. Figure 16.3-5 DMA Transfer in Rotation Mode ch0 transfer request ch1 transfer request Bus operation CPU Transfer ch SA DA ch1 SA DA SA ch0 DA ch1 SA DA CPU ch0 ch0 transfer end ch1 transfer end ■ Channel Group Set the selection priority as explained in the table below. Table 16.3-7 lists the settings for DMA selection priority. Table 16.3-7 Setting DMA Selection Priority MODE Priority Remarks Fixed ch0 > ch1 − Rotation ch0 > ch1 ch0 < ch1 The initial state is the top row. If transfer occurs for the top row, the priority is reversed. 517 CHAPTER 16 DMA CONTROLLER (DMAC) 16.3.19 Supplement on External Pin and Internal Operation Timing This section provides supplementary information about external pins and internal operation timing. ■ Minimum Effective Pulse Width of the DREQ Pin Input. (The MB91F353A/351A/352A/353A do not have 0, 1, and 2 channels.) Operation in all transfer modes (i.e., burst, step, block, and demand transfer) requires a minimum effective pulse width of five system clock cycles (five cycles of external bus clock [CLKT]). Note: DACK output does not indicate acceptance of DREQ input. DREQ input is always accepted if DMA is enabled but transfer has not started. Therefore, it is not necessary to retain DREQ input until DACK output is asserted (except in demand transfer mode). ■ Negate Timing of the DREQ Pin Input when a Demand Transfer Request is Stopped ● For 2-cycle transfer For a demand transfer, be sure to set an address in an external area for the transfer source, the transfer destination, or both. • For transfer between external circuits: When accessing the transfer source for the last DMA transfer, negate DREQ while the external WR pin output is at the "L" level. If DREQ is negated after the period when DACK and WR are at the "L" level, the next transfer may be executed. • For transfer between external and internal circuits: When accessing the transfer source for the last DMA transfer, negate DREQ while the external RD pin output is at the "L" level If DREQ is negated after the period when DACK and RD are at the "L" level, the next transfer may be executed. 518 Figure 16.3-6 shows a negate timing example of the DREQ pin input for 2-cycle external transfer → internal transfer. Figure 16.3-6 Negate Timing Example of the DREQ Pin Input for 2-cycle External Transfer → Internal Transfer Bus operation Area CPU SA DA SA DA *1 *2 *1 *2 CPU SA DA SA DA *1 *2 *1 *2 *1: External *2: Internal External D bus DACK DEOP RD WR DREQ (H level) • For transfer between internal and external circuits: When accessing the transfer source for the last DMA transfer, negate DREQ while the external WR pin output is at the "L" level. If DREQ is negated after the period when DACK and WR are at the "L" level, the next transfer may be executed. ● For fly-by (read/write) transfer For a demand transfer, be sure to set an address in an external area for the transfer destination. • For fly-by (read) transfer: After the IOWR pin output for the last DMA transfer goes to the "H" level, negate DREQ while the external RD pin output is at the "L" level. If DREQ is negated after the period when DACK and RD are at the "L" level, the next transfer may be executed. • For fly-by (write) transfer: After the external WR pin output for the last DMA transfer goes to the "H" level, negate DREQ while IORD is at the "L" level. If DREQ is negated after the period when DACK and IORD are at the "L" level, the next transfer may be executed. Figure 16.3-7 shows an example of the timing for negating the DREQ pin input for fly-by (write) transfer. Figure 16.3-7 Example of the Timing for Negating the DREQ Pin Input for Fly-by (Write) Transfer Bus operation Area CPU DA DA DA DA * * * * CPU DA DA DA DA * * * * *: External External D bus DACK DEOP RD WR IORD DREQ (H level) 519 CHAPTER 16 DMA CONTROLLER (DMAC) ■ Timing of the DREQ Pin Input for Continuing Transfer Over the Same Channel ● For burst, step, block, and demand transfers Operation in which transfer is continued over the same channel by the DREQ pin input cannot be guaranteed. If DREQ is reasserted at the fastest timing to clear requests retained internally after the transfer ends, at least one system clock cycle (one CLK output cycle) is provided to detect transfer requests for other channels. If, as a result, a transfer request for another channel with a higher priority is detected, transfer on that channel will be started. Even if DREQ is reasserted earlier, it is ignored because the transfer has not been completed. If no transfer requests for other channels occur, transfer over the same channel is restarted by reasserting DREQ when the DACK pin output is asserted. ■ Timing of DACK Pin Output The DACK output of this DMAC indicates that transfer with respect to an accepted transfer request is being performed. The output of DACK is basically synchronized with the address output of external bus access timing. To use DACK output, it is necessary to enable the DACK output with a port. ■ Timing of the DEOP Pin Output The DEOP output of this DMA indicates that DMA transfer for the specified number of times of the accepted channel has been completed. DEOP output is outputted when access to an external area of the last transfer block starts. Thus, if any value other than "1" is set (block transfer mode) as the block size, DEOP is outputted when the last data of the last block is transferred. In this case, the acceptance of the next DREQ is already started even during transfer (before DEOP output) if the DACK pin output is asserted. The DEOP output is synchronized with external bus access timing controlled with RD or WR. However, if the transfer source/transfer destination is internal access, DEOP is not outputted. The DEOP output is used, it is necessary to enable the DEOP output using the port resister. ■ Timing of the DSTP Pin Input Operation in all transfer modes (i.e., burst, step, block, and demand transfer) requires a minimum effective pulse width of five system clock cycles (=1/2θ, two cycles of the CPU system clock). As with DREQ, we recommend that you use DSTP input timing in synchronization with external access (Use the DACK output and the signal decoded by RD or WR). Use the pin input to force DMA transfer to stop. Although transfer can be forced to stop by using this pin input, the status register (DSS[2:0] of DMACB) indicates "Transfer stop request" and is handled as an error. If interrupts are enabled, interrupts will occur. Since this function is shared with the DEOP pin, both functions cannot be used. Set switching of functions with the port register. 520 ■ If an External Pin Transfer Request is Reentered During Transfer ● For burst, step, and block transfers While the DACK signal is asserted within the DMAC, the next transfer request, if it is entered, is disabled. However, since operation of the external bus control unit and operation of the DMAC are not completely synchronous, the circuit must be initialized to create DREQ pin input using DACK and DEOP output to enable transfer requests by using DREQ input. ● For a demand transfer If reloading of the transfer count register is specified when transfer for as many transfers as specified has been completed, another transfer request is accepted. ■ If Another Transfer Request Occurs During Block Transfer No request is detected before the transfer of the specified blocks is completed. At the block boundaries, transfer requests accepted at that time are evaluated and then transfer on the channel with the highest priority is performed. ■ Transfer Between External I/O and External Memory As targets of transfer by the DMAC, external I/O and external memory are not distinguished. Specify an external I/O as a fixed external address. To perform fly-by transfer, set the address of external memory in the transfer destination address register. For external I/O, use the signal decoded by the DACK output and RD or WR. ■ AC Characteristics of DMAC DREQ pin input, DACK pin output, and DEOP pin output are provided as the external pins related to the DMAC. Output timing is synchronized with external bus access. (Refer to the AC standard for the DMAC.) 521 CHAPTER 16 DMA CONTROLLER (DMAC) 16.4 Operation Flowcharts Figure 16.4-1 to Figure 16.4-3 show operation flowcharts for DMA transfer. ■ Operation Flowchart for Block Transfer Figure 16.4-1 Block Transfer DMA stop DENB=>0 DENB=1 Reload enable Activation request wait Activation request Load the initial address, transfer count, and number of blocks Calculate the address for transfer source address access One-time access for fly-by Calculate the address for transfer destination address access Number of blocks - 1 BLK=0 Transfer count - 1 Write back the address, transfer count, and number of blocks Only when the peripheral interrupt activation source is selected Interrupt clear Interrupt cleared DTC=0 DMA transfer end DMA interrupted Block transfer - Can be activated by all activation sources (selection). - Can access all areas. - The number of blocks can be set. - Interrupt clear is issued when transfer of the specified number of blocks is completed. - The DMA interrupt is issued when transfer for the number of times specified is completed. 522 ■ Operation Flowchart for Burst Transfer Figure 16.4-2 Burst Transfer DMA stop DENB=>0 DENB=1 Reload enable Activation request wait Load the initial address, transfer count, and number of blocks Calculate the address for transfer source address access One-time access for fly-by Calculate the address for transfer destination address access Number of blocks - 1 BLK=0 Transfer count - 1 DTC=0 Write back the address, transfer count, and number of blocks Only when the peripheral interrupt activation source is selected Interrupt clear Interrupt cleared DMA transfer end DMA interrupted Burst transfer - Can be activated by all activation sources (selection). - Can access all areas. - The number of blocks can be set. - Interrupt clear and the DMA interrupt are issued when transfer for the number of times specified is completed. 523 CHAPTER 16 DMA CONTROLLER (DMAC) ■ Operation Flowchart for Demand Transfer Figure 16.4-3 Demand Transfer DMA stop DENB=>0 None Reload enable DENB=1 Activation request wait Activation request Load the initial address, transfer count, and number of blocks Calculate the address for transfer source address access One-time access for fly-by Calculate the address for transfer destination address access Transfer count - 1 Write back the address, transfer count, and number of blocks DTC=0 Interrupt clear DMA transfer end Only when the peripheral interrupt activation source is selected Interrupt cleared DMA interrupted Demand transfer - Only requests (level detection) from the external pin (DREQ) are accepted. Activation by other sources is disabled. - Access to an external area is required (since access to an external area becomes the next activation source). - The number of blocks is always "1", regardless of the settings. - Interrupt clear and the DMA interrupt are issued when transfer for the number of times specified is completed. 524 16.5 Data Path This section shows the flow of data during different types of transfer operation. ■ Flow of Data During 2-Cycle Transfer Figure 16.5-1 to Figure 16.5-6 show the flow of data during 2-cycle transfer. Figure 16.5-1 External Area → External Area Transfer CPU Read cycle I-bus D-bus X-bus Bus controller Data buffer MB91xxx X-bus Bus controller D-bus Data buffer F-bus RAM DMAC Write cycle I-bus External bus I/F DMAC CPU MB91xxx External bus I/F External area => external area transfer F-bus I/O RAM I/O Figure 16.5-2 External Area → Internal RAM Area Transfer CPU Read cycle I-bus D-bus X-bus Bus controller Data buffer F-bus RAM MB91xxx DMAC Write cycle I-bus X-bus Bus controller D-bus Data buffer External bus I/F DMAC CPU MB91xxx External bus I/F External area => internal RAM area transfer F-bus I/O RAM I/O 525 CHAPTER 16 DMA CONTROLLER (DMAC) Figure 16.5-3 External Area → Internal I/O Area Transfer CPU Read cycle I-bus D-bus X-bus Bus controller Data buffer MB91xxx DMAC Write cycle I-bus X-bus Bus controller D-bus Data buffer F-bus RAM External bus I/F DMAC CPU MB91xxx External bus I/F External area => built-in I/O area transfer F-bus I/O RAM I/O Figure 16.5-4 Internal I/O Area → Internal RAM Area Transfer X-bus Bus controller D-bus Data buffer X-bus Bus controller D-bus F-bus RAM DMAC Write cycle I-bus CPU Read cycle I-bus CPU MB91xxx DMAC External bus I/F MB91xxx Data buffer External bus I/F Built-in I/O area => internal RAM area transfer F-bus I/O RAM I/O Figure 16.5-5 Internal RAM Area → External Area Transfer X-bus Bus controller D-bus Data buffer F-bus RAM 526 DMAC Write cycle I-bus CPU Read cycle I-bus CPU MB91xxx DMAC External bus I/F MB91xxx X-bus Bus controller D-bus Data buffer F-bus I/O RAM I/O External bus I/F Internal RAM area => external area transfer Figure 16.5-6 Internal RAM Area → Internal I/O Area Transfer X-bus Bus controller D-bus Data buffer DMAC Write cycle I-bus CPU Read cycle I-bus CPU MB91xxx DMAC External bus I/F MB91xxx X-bus Bus controller D-bus Data buffer F-bus RAM External bus I/F Internal RAM area => built-in I/O area transfer F-bus I/O RAM I/O ■ Flow of Data During Fly-By Transfer Figure 16.5-7 and Figure 16.5-8 show the flow of data during fly-by transfer. Figure 16.5-7 Fly-by Transfer (Memory → I/O) CPU X-bus Bus controller D-bus Data buffer memory DMAC Read cycle I-bus I/O write by RD or DACK F-bus RAM Memory read by RD or CSx I/O I/O MB91xxx External bus I/F Fly-by transfer (memory to I/O) Fly-by transfer by SDRAM disabled 527 CHAPTER 16 DMA CONTROLLER (DMAC) Figure 16.5-8 Fly-by Transfer (I/O → Memory) DMAC CPU Read cycle I-bus X-bus Bus controller D-bus Data buffer memory MB91xxx External bus I/F Fly-by transfer (I/O to memory) I/O read by WR or DACK I/O I/O F-bus RAM Memory write by WR or CSx Fly-by transfer by SDRAM disabled 528 16.6 DMA External Interface This section describes the DMA external interface. Note: The MB91F353A/351A/352A/353A do not have a DMA external interface. ■ Overview of DMA External Interface Operation DMA ch0 to ch2 have DMA-dedicated pins (DREQ, DACK, and DEOP). • DREQ DREQ is a DMA transfer request input pin used to execute demand transfer. Input "1" to request transfer. • DACK DACK becomes active ("L" output) when the DMA accesses external area through the external interface. • DEOP DEOP becomes active ("L" output) in synchronization with the last access operation when all DMA transfer operations have ended. • IORD IORD becomes active when the transfer direction I/O → memory is selected for fly-by transfer. • IOWR IOWR becomes active when the transfer direction memory → I/O is selected for fly-by transfer. ■ Examples of Operation (Simple Waveforms) ● 2-cycle transfer (external → external transfer and transfer count = 2) Figure 16.6-1 shows a simple waveform for 2-cycle transfer (external → external transfer and transfer count = 2). Figure 16.6-1 Simple Waveform for 2-Cycle Transfer (External → External Transfer and Transfer Count = 2) A24 - A0 #RD1 #WR1 #RD2 #WR2 RD WR EOP DACK CS1 1st read 1st write 2nd read 2nd write 529 CHAPTER 16 DMA CONTROLLER (DMAC) ● Fly-by transfer (I/O → memory transfer and transfer count = 3) Figure 16.6-2 shows a simple waveform for fly-by transfer (I/O → memory transfer and transfer count = 3). Figure 16.6-2 Simple Waveform for Fly-by Transfer (I/O → Memory Transfer and Transfer Count = 3) A24 to A0 CPU #1 #2 #3 RD WR IORD EOP DACK CS1 CPU read 1st fly-by 2nd fly-by 3rd fly-by ● Fly-by transfer (memory → I/O transfer and transfer count = 3) Figure 16.6-3 shows a simple waveform for fly-by transfer (memory → I/O transfer and transfer count = 3). Figure 16.6-3 Simple Waveform for Fly-by Transfer (Memory → I/O Transfer and Transfer Count = 3) A24 to A0 CPU #1 #2 #3 RD WR IOWR EOP DACK CS1 CPU read 1st fly-by 2nd fly-by 3rd fly-by ■ Timing of DREQx Pin Input The DREQx pin is a DMA activation request signal. When the DREQx pin also functions as a port, use the PFR register to enable DREQ input. ● Timing 1. Except for demand transfer, set edge detection as the DMA activation source. There are no requirements regarding the rise/fall timing, but the DREQ signal retention time must be at least three clock cycles. To request transfer again, input the request after DMA transfer has ended (request after DEOP output). Requests input before DEOP output are sometimes ignored. Figure 16.6-4 shows a DREQx edge request (2-cycle transfer). 2. For demand transfer, set level detection as the DMA activation source. There are no requirements regarding the start of activation, but for stopping, synchronization with RD/WR of DMA transfer is necessary. The sensing timing is the rise of MCLK of the last external access operation. Figure 16.6-5 shows a DREQx level request (2-cycle transfer). 530 Figure 16.6-4 DREQx Edge Request (2-Cycle Transfer) MCLK DREQ A24 - 0 #RD1 #WR1 #RD2 #WR2 RD WR DEOP CPU operation CPU DMA transfer 3 cycles or more Next request after DEOP output Figure 16.6-5 DREQx Level Request (2-Cycle Transfer) MCLK DREQ A24 - 0 #RD1 #WR1 #RD2 #WR2 RD WR CPU operation DMA transfer CPU Sensing point of 3rd transfer request In these cases, the transfer source/destination for 2-cycle transfer is the external area. Therefore, to stop at the second DMA transfer, negate after the fall of #RD2 but before the final MCLK rise of #WR2. 531 CHAPTER 16 DMA CONTROLLER (DMAC) ■ FR30 Compatible Mode of DACK The FR30-compatible mode of this DACK sets the DACK timing to the same timing as that of FR30 family DMA. Use the PFR register corresponding to the DACK pin to set FR30-compatible mode. Match the PFR setting to the transfer mode (fly-by or 2-cycle) of the corresponding DMA channel. Note: When FR30-compatible mode is set for 2-cycle transfer, transfer is synchronized with RD or WR/ WRn. To use WR, set TYPE3-0 of the external interface ACR register to 0x1x to enable WR. Figure 16.6-6 shows a setting example for transfer in 2-cycle transfer mode. Figure 16.6-7 shows a setting example for transfer in fly-by transfer mode. Setting Examples: Figure 16.6-6 Setting Example for Transfer in 2-Cycle Transfer Mode RD DQMU/L WR/WRn Same timing as chip select DACK(AKxx=111) DACK(AKxx=001) Setting not allowed for 2-cycle transfer DACK(AKxx=010) DACK(AKxx=011) DACK(AKxx=100) DACK(AKxx=101) DACK(AKxx=110) AKxx : The setting value of the PFR register corresponding to the DMA channel. Figure 16.6-7 Setting Example for Transfer in Fly-by Transfer Mode RD DQMU/L WR/WRn IORD IOWR DACK(AKxx=111) Same timing as chip select DACK(AKxx=001) DACK(AKxx=010) Setting not allowed for fly-by transfer DACK(AKxx=011) Setting not allowed for fly-by transfer DACK(AKxx=100) Setting not allowed for fly-by transfer DACK(AKxx=101) Setting not allowed for fly-by transfer DACK(AKxx=110) Setting not allowed for fly-by transfer Memory -> I/O I/O -> memory Memory -> I/O I/O -> memory AKxx : The setting value of the PFR register corresponding to the DMA channel. 532 CHAPTER 17 FLASH MEMORY This chapter provides an outline of flash memory and explains its register configuration, register functions, and operations. 17.1 Outline of Flash Memory 17.2 Flash Memory Registers 17.3 Explanation of Flash Memory Operation 17.4 Automatic Algorithm of Flash Memory 17.5 Writing to and Erasing Flash Memory 533 CHAPTER 17 FLASH MEMORY 17.1 Outline of Flash Memory The MB91F355A, MB91F353A and MB91F357B each contain two 256K bytes flash memories for a combined total flash memory capacity of 512K bytes. The MB91F356B contains two 128K bytes Flash memories for combined total flash memory capacity of 256K bytes. The internal flash memory operates on a single power supply voltage of 3.3 V. The internal flash memory can be erased by sector, batch-erased (all sectors erased), and written in halfword (16 bits) units via the FR-CPU. ■ Outline of Flash Memory The flash memory employed is an internal 256K bytes/128K bytes flash memory that operates on 3.3 V. The flash memory employed here is the same (except for the capacity and sector structure) as the Fujitsu MBM29LV400C flash memory. The flash memory supports writing with a device-external ROM writer. Along with this manual, refer to the MBM29LV400C Data Sheet. In addition to the features equivalent to the MBM29LV400C, instructions and data can be read in word units (32 bits) when the flash memory is used as FR-CPU internal ROM, enabling high-speed device operation. The MB91F355A, MB91F353A, MB91F356B and MB91F357B each contain two flash memories. The MB91F355A, MB91F353A, MB91F356B and MB91F357B support the following features by combining the internal flash memories and the FR-CPU interface circuits: • Features for use as CPU memory, for storing programs and data (referred to hereafter as CPU mode.) - Accessibility through 32-bit bus when used as ROM - Allowing read, write, and erase (automatic program algorithm*) by the CPU instruction • Features of a single flash memory product equivalent to MBM29LV400 (referred to hereafter as FLASH mode.) - Allowing read, write, or erase (automatic program algorithm *) by a ROM writer This section explains use of the flash memory accessed from the FR-CPU. For information on using the flash memory accessed from a ROM writer, see the instruction manual provided with the ROM writer. *: Automatic program algorithm: embedded AlgorithmTM Note: Embedded AlgorithmTM is a trademark of Advanced Micro Devices, Inc. 534 ■ Block Diagram of Flash Memory Figure 17.1-1 shows a block diagram of flash memory. Figure 17.1-1 Block Diagram of Flash Memory Detection of rising edge RDY/BUSYX RESETX BYTEX OEX Generation of control signal 256 KB/128KB flash memory (2 installed) WEX RDY WF Bus control signal RDYEG CEX FA17 to 0 DI15 to 0 D031 to 0 Address buffer Data buffer FA17 to 0 FD31 to 0 FR-F bus (instruction/data) ■ Memory Map of Flash Memory Flash memory employs different address mapping depending on whether accessed in FLASH mode or CPU mode. Figure 17.1-3 shows the memory map of flash memory in each mode. Figure 17.1-2 Memory Map of MB91F353A/355A/F356B/F357B Flash Memory Flash memory mode CPU mode 0000_0000H I/O, etc 0008_0000H 32-bit 32-bit Internal ROM 1 Internal ROM 2 0010_0000H 512K bytes 0010_0000H 8-bit/16-bit Internal ROM 1 256K bytes 0014_0000H External Internal ROM 2 256K bytes 0017_FFFFH FFFF_FFFFH 535 CHAPTER 17 FLASH MEMORY Figure 17.1-3 Memory Map of MB91F356B Flash Memory Flash memory mode CPU mode 0000_0000H I/O, etc 000C_0000H 32-bit 32-bit Internal ROM 1 Internal ROM 2 256K bytes 8-bit/16-bit 0010_0000H External 0010_0000H Access is not allowed 0011_0000H Internal ROM 1 0012_0000H Access is not allowed 0013_0000H Internal ROM 1 0014_0000H 0015_0000H Access is not allowed Internal ROM 2 0016_0000 64K bytes H 0017_0000H Access is not allowed Internal ROM 2 0017_FFFF H FFFF_FFFFH In CPU mode, the two 32-bit flash memories are connected in parallel and mapped as a high-order ROM (ROM 1) and low-order ROM (ROM 2) for 64-bit access. In FLASH mode, ROM 1 and ROM 2 are switched using A18. Instead of using A18 from the ROM writer, a switch will be connected and used to switch the two 256K bytes/128K bytes flash memories. 536 ■ Sector Address Table of Flash Memory [Flash memory sector maps] The flash memory sector maps are shown below. • CPU mode (MB91F355A,MB91F353A and MB91F357B) 0xFFFFFH 0xF0000H 0xEF000H 0xE8000H 0xE7FFFH 0xE0000H 0xDFFFFH 0xC0000H 0xBFFFFH 0x80000H SAA9(16K) SAA4(16K) SAB9(16K) SAB4(16K) SAA8(8K) SAA3(8K) SAB8(8K) SAB3(8K) SAA7(8K) SAA2(8K) SAB7(8K) SAB2(8K) SAA6(32K) SAA1(32K) SAB6(32K) SAB1(32K) SAA5(64K) SAA0(64K) SAB5(64K) SAB0(64K) 31...24, 23...16 15......8, 7......0 +0/+1 • ROM1 31...24, 23...16 15......8, 7......0 +2/+3 +4/+5 +6/+7 FLASH mode(MB91F355A,MB91F353A and MB91F357B) 0x13FFFFH 0x13C000H 0x13BFFFH 0x13A000H 0x139FFFH 0x138000H 0x137FFFH 0x130000H 0x12FFFFH 0x120000H 0x11FFFFH 0x11C000H 0x11BFFFH 0x11A000H 0x119FFFH 0x118000H 0x117FFFH 0x110000H 0x10FFFFH 0x100000H SAA9(16K) SAB9(16K) SAA8(8K) SAB8(8K) SAA7(8K) SAB7(8K) SAA6(32K) SAB6(32K) SAB5(64K) SAA5(64K) ROM2 ROM1 SAA4(16K) SAB4(16K) SAA3(8K) SAB3(8K) SAA2(8K) SAB2(8K) SAA1(32K) SAB1(32K) SAA0(64K) SAB0(64K) 15......8, 7......0 15......8, 7......0 A18 • ROM2 0 1 CPU mode (Accessing to SAA0, SAA5, SAB0, and SAB5 is disabled.) (MB91F356B) 0xFFFFFH 0xF0000H 0xEF000H 0xE8000H 0xE7FFFH 0xE0000H 0xDFFFFH 0xC0000H 0xBFFFFH 0x80000H SAA9(16K) SAA4(16K) SAB9(16K) SAB4(16K) SAA8(8K) SAA3(8K) SAB8(8K) SAB3(8K) SAA7(8K) SAA2(8K) SAB7(8K) SAB2(8K) SAA6(32K) SAA1(32K) SAB6(32K) SAB1(32K) 31...24, 23...16 15......8, 7......0 +0/+1 +2/+3 ROM1 ROM2 31...24, 23...16 15......8, 7......0 +4/+5 +6/+7 Note: When WE bit of FLCR register is "1", 32-bit width access is disabled. 537 CHAPTER 17 FLASH MEMORY • FLASH mode (Accessing to SAA0, SAA5, SAB0, and SAB5 is disabled.) (MB91F356B) 0x13FFFFH 0x13C000H 0x13BFFFH 0x13A000H 0x139FFFH 0x138000H 0x137FFFH 0x130000H 0x12FFFFH 0x120000H 0x11FFFFH 0x11C000H 0x11BFFFH 0x11A000H 0x119FFFH 0x118000H 0x117FFFH 0x110000H 0x10FFFFH 0x100000H SAA9(16K) SAB9(16K) SAA8(8K) SAB8(8K) SAA7(8K) SAB7(8K) SAA6(32K) SAB6(32K) SAB4(16K) SAA3(8K) SAB3(8K) SAA2(8K) SAB2(8K) SAA1(32K) SAB1(32K) 15......8, 7......0 A18 ROM2 ROM1 SAA4(16K) 15......8, 7......0 0 ROM 1 and ROM 2 are switched using the A18 pin. 512K bytes/256K bytes flash memory. 1 ROM 1 and ROM 2 are not handled as a single Switch between the 256K bytes/128K bytes flash memories by connecting a switch to the A18 pin instead of using A18 from the ROM writer. 538 17.2 Flash Memory Registers This section describes the configuration and functions of the registers used for flash memory. ■ Overview of Flash Memory Registers There are the two following types of flash memory registers: • FLCR: Flash control/status register (CPU mode) • FLWC: Flash memory wait register 539 CHAPTER 17 FLASH MEMORY 17.2.1 Flash Control/Status Register (FLCR) (CPU mode) The flash control/status register (FLCR) (CPU mode) indicates the operating status of flash memory. The FLCR controls writing to flash memory. The FLCR can be accessed only in CPU mode. Do not use read modify write instructions to access this register. ■ Configuration of the Flash Control/Status Register (FLCR) (CPU Mode) The configuration of the flash control/status register (FLCR) (CPU mode) is shown below. Address : 00007000H Initial value→ 7 6 5 R/W (0) R/W (1) R/W (1) 4 3 RDYEG RDY R R (0) (X) 2 1 0 R/W (0) WE R/W (0) R/W (0) [Bit 7] Reserved: Reserved bit Always set this bit to "0." [Bits 6 and 5] Reserved: Reserved bits Always set these bits to "1." [Bit 4] RDYEG The end of the flash memory automatic algorithm (i.e., write, erase) sets this bit to "1". Reading clears this bit. Value • 540 Explanation 0 The end of the automatic algorithm has not been detected. 1 The end of the automatic algorithm has been detected. This bit is initialized to "0" by a reset. [Bit 3] RDY This bit indicates the operation status of the automatic algorithm (write/erase). When this bit is set to "0," writing or erasure is in progress with the automatic algorithm and no write and erase command can be accepted. Moreover, data cannot be read from any address in flash memory. The read data indicates the flash memory status as listed in the table below. Value Explanation 0 Writing or erasing is in process, flash memory is not ready to accept a new write/erase command, and no data can be read from a flash memory address. 1 Flash memory is ready to accept a new write/erase command and data can be read from a flash memory address. • This bit is not initialized during a reset. (The value of this bit depends on flash memory status.) • Only read operation is possible, but write operation does not affect this bit. [Bit 2] Reserved: Reserved bit Always set this bit to "0." 541 CHAPTER 17 FLASH MEMORY [Bit 1] WE (Write Enable) This bit controls the writing of data and commands to flash memory in CPU mode. When this bit is "0", data and commands cannot be written to flash memory. In addition, data can be read from flash memory at faster speeds (32-bit, 16-bit, and 8-bit access are enabled). When this bit is "1", data and commands can be written to flash memory and the automatic algorithm can be activated. However, data is read from flash memory at slower speeds (only 16-bit and 8-bit access are enabled). If this bit is rewritten, confirm that the RDY bit has stopped the automatic algorithm (write/erase). When the RDY bit is set to "0," the value of this bit cannot be changed. Writing is enabled regardless of this bit in FLASH mode. Value Explanation 0 Writing to flash memory is disabled and data is read from flash memory in 32-bit access mode. 1 Writing to flash memory is enabled and data is read from flash memory in 16-bit access mode. • This bit is initialized to "0" during reset. • Read and write operations are enabled. Note: If the WE bit of the FLCR register is changed, be sure to dummy-read the FLCR register immediately after the WE bit is changed. Operation will be unpredictable if a dummy read is not performed. Example: STB R1,@R2 // WE change LDUB @R2,R1 // Dummy read The register numbers are arbitrary. [Bit 0] Reserved: Reserved bit Always set this bit to "0." 542 17.2.2 Flash Memory Wait Register (FLWC) The flash memory wait register (FLWC) controls the wait status of flash memory access in CPU mode. ■ Configuration of the Flash Memory Wait Register (FLWC) The configuration of the flash memory wait register (FLWC) is shown below. Address : 00007004H Initial value→ 7 6 5 4 3 2 1 0 R (0) R/W (0) FAC1 R/W (0) FAC0 R/W (1) R/W (0) WTC2 R/W (0) WTC1 R/W (1) WTC0 R/W (1) [Bits 7 and 6] Reserved: Reserved bits Always set these bits to "0." [Bits 5 and 4] FAC1 and FAC0 These bits control internal pulse generation for flash control. For the MB91F355A, MB91F353A, MB91F356B and MB91F357B, these bits set the ATDIN/EQIN pulse width. FAC1 FAC0 ATDIN EQIN 0 0 0.5 CLKB clock 1.0 CLKB clock Setting not allowed 0 1 1.0 CLKB clock 1.5 CLKB clock Initial value 1 0 1.5 CLKB clock 2.0 CLKB clock Setting not allowed 1 1 2.0 CLKB clock 2.5 CLKB clock Setting not allowed • In a reset, the FAC1 bit is initialized to "0" and the FAC0 bit is initialized to "1". • For the MB91F355A, MB91F353A, MB91F356B and MB91F357B, always set the FAC1 bit to "0" and the FAC0 bit to "1". [Bit 3] Reserved: Reserved bit Always set this bit to "0." 543 CHAPTER 17 FLASH MEMORY [Bits 2 to 0] WTC2, WTC1, and WTC0 (wait cycle bits) These bits control the wait status of flash memory. WTC2 544 WTC1 WTC0 Wait count VDD = 3.0V@50MHz WE bit 0 WE bit 1 VDD = 2.7V@50MHz WE bit 0 WE bit 1 0 0 0 - Setting not allowed Setting not allowed Setting not allowed Setting not allowed 0 0 1 1 Setting not allowed Setting not allowed Setting not allowed Setting not allowed 0 1 0 2 Operation allowed Setting not allowed Setting not allowed Setting not allowed 0 1 1 3 Operation allowed Setting not allowed Operation allowed Setting not allowed 1 0 0 4 Operation allowed Operation allowed Operation allowed Operation allowed 1 0 1 5 Operation allowed Operation allowed Operation allowed Operation allowed 1 1 0 6 Operation allowed Operation allowed Operation allowed Operation allowed 1 1 1 7 Operation allowed Operation allowed Operation allowed Operation allowed Initial value • In a reset, the WTC2 bit is initialized to "0", the WTC1 bit is initialized to "1", and the WTC0 bit is initialized to "1". • For the MB91F355A/F353A/F356B/F357B, it becomes the above by the minimum operating supply voltage and the operable wait count. In addition, the operable wait count varies according to the setting state of the WE bit the FLCR register. 17.3 Explanation of Flash Memory Operation This section describes flash memory operation. ■ Flash Memory Access Modes The following two types of access mode are available for the FR-CPU: • ROM mode: One word (32 bits) can be read but not written in a single cycle. • Programming mode: Access to data with a length defined in words (32 bits) is prohibited but writing data with a length defined in half-words (16 bits) is enabled. ■ FR-CPU ROM Mode (32 Bits, Read only) In this mode, the flash memory serves as FR-CPU internal ROM. This mode enables to read one word (32 bits) in one cycle but does not enable to write to flash memory or to start the automatic algorithm. • • Mode specification • When specifying this mode, set the "WE" bit of the FLCR register to "0". • This mode is always set after a reset releases at CPU run time. • This mode can be set only when the CPU is running. Detailed operation In this mode, one word (32 bits) can be read from the flash memory area in one cycle. • Restrictions • Address assignment and endians in this mode differ from those for writing with the ROM writer. • In this mode, commands and data cannot be written to flash memory together. 545 CHAPTER 17 FLASH MEMORY ■ FR-CPU Programming Mode (16 Bits, Read/Write Enabled) This mode enables data to be written and erased. As one word (32 bits) cannot be accessed in one cycle, program execution in flash memory is disabled in this mode. • • • Mode specification • When specifying this mode, set the "WE" bit of the FLCR register to "1". • When a reset releases at CPU run time, the "WE" bit indicates "0". When setting this mode, set the "WE" bit to "1". If the "WE" bit is set again to "0" through a writing operation or because of a reset, the device enters ROM mode. • When the "RDY" bit of the FLCR register is "0", the "WE" bit cannot be rewritten. When rewriting the "WE" bit, ensure that the "RDY" bit is set to "1". Detailed operation • One half-word (16 bits) can be read from the flash memory area in one cycle. • The automatic algorithm can be started by writing a command to flash memory. When the automatic algorithm starts, data can be written to or erased from flash memory. For details on the automatic algorithm, see Section "17.4 Automatic Algorithm of Flash Memory". Restrictions • Address assignment and endians in this mode differ from those for writing with the ROM writer. • This mode inhibits reading data in words (32 bits). • The MB91F355A, MB91F353A, MB91F356B and MB91F357B each contain two 256K bytes/128K bytes flash memories. Each flash memory (ROM 1 and ROM 2) must be controlled independently. For details, see Section "17.4.1 Command Sequence". ■ Automatic Algorithm Execution Status When the automatic algorithm is started in CPU programming mode, the operation status of the automatic algorithm can be checked using the internal ready/busy signal (RDY/BUSYX). The level of this signal can be read as the RDY bit in the FLCR register. When the RDY bit is set to "0," data is being written or erased with the automatic algorithm, and no write or erase command can be accepted. Moreover, data cannot be read from any address in flash memory. Data read with the RDY bit set to "0" is a hardware sequence flag to indicate flash memory status. 546 17.4 Automatic Algorithm of Flash Memory This section describes the command sequence of the flash memory automatic algorithm, the method used to check the operating status of the automatic algorithm, and writing to and erasing flash memory. ■ Overview of the Flash Memory Automatic Algorithm The flash memory automatic algorithm can be started using a read/reset, write, chip erase, or sector erase command. The sector erase command can temporarily stop and restart the automatic algorithm. 547 CHAPTER 17 FLASH MEMORY 17.4.1 Command Sequence This section describes the command sequence for starting the automatic algorithm. ■ Automatic Algorithm Command Sequence At the start of the automatic algorithm, one to six half-words (16 bits) are written continuously. This data is called the command. If the address and data to be written are invalid or are written in an incorrect sequence, the flash memory is reset to read mode. Note: The MB91F355A, MB91F353A, MB91F357B and MB91F357B each contain two 256K bytes flash memories, and MB91F356B contains two 129K bytes flash memories. Note that the command addresses are different by each flash memory. In addition, chip erase must be executed for ROM 1 and ROM 2 to erase the entire 512K bytes/256K bytes area. Table 17.4-1 lists commands that can be used to write data to or erase data from flash memory. When writing data using FR-CPU, write data with halfwords (16 bits). (The table lists the addresses in CPU mode.) Table 17.4-1 Command Sequence Command sequence Bus write cycle ROM First bus write cycle Address Data Second bus write cycle Third bus write cycle Fourth bus write cycle Address Data Address Data Address Data Fifth bus write cycle Sixth bus write cycle Address Data Address Data Read/Reset 1 Com-mon *xxxx FO Read/Reset 3 ROM1 *AAAA AA *5552 55 *AAAA FO (RA) (RD) ROM2 *AAAE AA *5556 55 *AAAE FO (RA) (RD) ROM1 *AAAA AA *5552 55 *AAAA AO (PA) (PD) ROM2 *AAAE AA *5556 55 *AAAE AO (PA) (PD) ROM1 *AAAA AA *5552 55 *AAAA 80 *AAAA AA *5552 55 *AAAA 10 ROM2 *AAAE AA *5556 55 *AAAE 80 *AAAE AA *5556 55 *AAAE 10 ROM1 *AAAA AA *5552 55 *AAAA 80 *AAAA AA *5552 55 (SA) 30 ROM2 *AAAE AA *5556 55 *AAAE 80 *AAAE AA *5556 55 (SA) 30 Write Chip Erase Sector Erase 4 6 6 Temporary Sector Erase Stop When an address (*XXXX) and data (B0) are inputted, erasing of the sector currently being erased is temporarily stopped. Sector Erase Restart When an address (*XXXX) and data (30) are inputted, erasing is restarted after erasing of the sector has been temporarily stopped. - In the command sequence, set the high-order 16-bit addresses as arbitrary flash memory spaces. (In Table 17.4-1, the high-order addresses are indicated by an asterisk.) - The commands are the same for word mode and byte mode. The data of bits that are not listed in the table is arbitrary. - All addresses and data are represented in hexadecimal notation. (RA): Read address (PA): Write address (SA): Sector address (Specify any address in a sector.) (RD): Read data (PD): Write data - The temporary sector erase stop (B0H) and sector erase restart (30H) commands are valid only during a sector erase operation. - Both types of reset commands can reset either flash memory in read mode. 548 ■ Read/Reset Command Set flash memory into read/reset mode. The flash memory remains in reading state until another command is entered. When the power is turned on, flash memory is automatically set to the read or reset state. In this case, data can be read without a command of the automatic algorithm. Upon returning to read mode after the time limit is exceeded, note that a read/reset command sequence can be issued. Data is read from flash memory in the next read cycle. ■ Program (Write) In CPU programming mode, data is basically written in half-word units. The write operation is performed in four cycles of bus operation. The command sequence has two "unlock" cycles, which are followed by a write setup command and a write data cycle. Writing to memory starts in the last write cycle. After an automatic write algorithm command sequence was executed, it becomes unnecessary to control the flash memory externally. The flash memory itself internally generates write pulses to check the margin of the cells to which data is written. The data polling function compares bit 7 of the original data with bit 7 of the written data, and if these bits are the same, the automatic write operation ends (see "■Hardware Sequence Flag" in Section "17.4.2 Checking the Automatic Algorithm Operating Status"). The automatic write operation then returns to the read mode and accepts no more write addresses. After that, the flash memory requests the next valid address. In this manner, the data polling function indicates a write operation in memory. During a write operation, all commands written to the flash memory are ignored. If a hardware reset starts during write operation, the data at the address for writing may become invalid. Writing operations can be performed in any address sequence and outside of sector boundaries. However, write operations cannot change a data item "0" to "1". If a "0" is overwritten with a "1", the data polling algorithm either determines that the elements are defective, or that "1" has been written. In the latter case, however, the respective data item is read as "0" in reset or read mode. A data item "0" can be changed to "1" only after an erase operation. ■ Chip Erase The chip erase command sequence ("erase all sectors simultaneously") is executed in six access cycles. First, two "unlock" cycles are executed, then a "Setup" command is written. After two more "unlock" cycles, the chip erase command is entered. During the chip erase command sequence, the user does not have to write to flash memory before the erase operation. When the automatic erase algorithm is executed, flash memory checks cell states by writing a pattern of zeros before automatically erasing the contents of all cells (preprogram). In this operation, flash memory does not have to be controlled externally. The automatic erase operation starts with the write operation of the command sequence and ends when bit 7 is set to "1", where flash memory returns to the read mode. The chip erase time can be expressed as follows: time for sector erase x number of all sectors + time for writing to the chip (preprogram). 549 CHAPTER 17 FLASH MEMORY ■ Sector Erase The sector erase command sequence is executed in six access cycles. First, two "unlock" cycles are executed, then a "Setup" command is written. After two more "unlock" cycles, the sector erase command is entered in the sixth cycle for starting the sector erase operation. The next sector erase command can be accepted within a time-out period of 50 µs after the last sector erase command is written. As already mentioned, multiple sector erase commands can be accepted during the six bus cycles of the writing operation. During the command sequence, sector erase commands (30H) for sectors whose contents are to be erased simultaneously are written consecutively to the addresses for these sectors. The sector erase operation itself starts from the end of the time-out period of 50 µs after the last sector erase command is written. When the contents of multiple sectors are erased simultaneously, the subsequent sector erase commands must be input within the 50 µs time-out period to ensure that they are accepted. For checking whether the succeeding sector erase command is valid, read bit 3 (see "■Hardware Sequence Flag" in Section "17.4.2 Checking the Automatic Algorithm Operating Status"). During the time-out period, any command other than sector erase and temporarily stop erase is reset at read time, and the preceding command sequence is ignored. In the case of the temporary stop erase command, the contends of the sector are erased again and the erase operation is completed. Any combination and number of sector addresses can be entered in the sector erase buffers. The user does not have to write to flash memory before the sector erase operation. Flash memory automatically writes to all cells in a sector whose data is automatically erased (preprogram). When the contents of a sector are erased, the other cells remain intact. In these operations, flash memory does not have to be controlled externally. The automatic sector erase operation starts from the end of the 50 µs time-out period after the last sector erase command is written. When bit 7 is set to "1", the automatic sector erase operation ends and flash memory returns to the read mode. At this time, other commands are ignored. The data polling function is enabled for any sector address in which data has been erased. The time required for erasing the data of multiple sectors can be expressed as follows: time for sector erase + time for sector write (preprogram) × number of erased sectors. 550 ■ Temporarily Stop Erase The temporarily stop erase command temporarily stops the automatic algorithm in flash memory when the user is erasing the data of a sector, thereby making it possible to write data to and read data from the other sectors that is not subject to the erase operation. This command is valid only during the sector erase operation and ignored during chip erase and write operations. The temporarily stop erase command (B0H) is effective only during sector erasure operation that includes the sector erase time-out period after a sector erase command (30H) is issued. When this command is entered within the time-out period, waiting for time-out ends and the erase operation is suspended. The erase operation is restarted when a restart erase command was written. The temporarily stop erase and restart erase commands can be entered with any address. When a temporarily stop erase command is entered during sector erase operation, the flash memory needs a maximum of 20 µs to stop the erase operation. When flash memory enters temporary erase stop mode, a ready or busy signal is output, bit 7 outputs "1", and bit 6 stops to toggle. For checking whether the erase operation has stopped, enter the address of the sector whose data is being erased and read the values of bit 6 and bit 7. At this time, another temporarily stop erase command entry is ignored. When the erase operation stops, flash memory enters the temporary erase stop and read mode. Data reading is enabled in this mode for sectors that are not subject to temporary erase. Other than that, there is no difference from the standard read operation. In this mode, bit 2 toggles for consecutive reading operations from sectors subject to temporary erase stop. After the temporary erase stop and read mode is entered, the user can write to flash memory by writing a write command sequence. The write mode in this case is the temporary erase stop and write mode. In this mode, data write operations become valid for sectors that are not subject to temporary erase stop. Other than that, there is no difference from the standard byte writing operation. In this mode, bit 2 toggles for consecutive reading operations from sectors that are subject to temporary erase stop. The temporary erase stop bit (bit 6) can be used to detect this operation. Note that bit 6 can be read from any address, but bit 7 must be read from write addresses. To restart the sector erase operation, a restart erase command (30H) must be entered. Another restart command entry is ignored in this case. On the other hand, a temporarily stop erase command can be entered after flash memory restarts the erase operation. 551 CHAPTER 17 FLASH MEMORY 17.4.2 Checking the Automatic Algorithm Operating Status Flash memory is provided with hardware to indicate the internal operation status of flash memory and the completion of write/erase operations in the automatic algorithm. The automatic algorithm can check the operating status of internal flash memory using the hardware sequence flag described below. ■ Ready/Busy Signal (RDY/BUSYX) The flash memory uses the ready/busy signal in addition to the hardware sequence flag to indicate whether the internal automatic algorithm is running. The ready/busy signal is connected to the flash memory interface circuit, where it can be read via the "RDY" bit of the flash memory control/status register. When the value of the "RDY" bit is "0", the flash memory is executing a write or erase operation, where new write and erase commands are not accepted. When the value of the "RDY" bit is "1", the flash memory is in read/write or erase operation wait state. ■ Hardware Sequence Flag The hardware sequence flag is shown below. During half-word read 15 (Undefined) 8 During byte read (from odd address only) 7 Hardware sequence flag 0 7 Hardware sequence flag 0 Note Reading in units of words is disabled. (Only use this function in FR-CPU programming mode.) For obtaining the hardware sequence flag as data, read an arbitrary address (an odd address in byte access) from flash memory when the automatic algorithm is executed. The data contains five validity bits which indicate the status of the automatic algorithm. When the automatic algorithm is executed for ROM1, specify an address in ROM1. When executed for ROM2, specify an address in ROM2. bit (In half-word and byte access) 7 6 5 DPOLL TOGGLE TLOVER 4 (Undefined) 3 2 SETIMR TOGGL2 1 0 (Undefined) (Undefined) The hardware sequence flag becomes invalid in FR-CPU ROM mode. Always use FR-CPU programming mode and read only in half-words or bytes. Table 17.4-2 lists the possible statuses of the hardware sequence flag. 552 Table 17.4-2 Statuses of the Hardware Sequence Flag Status Executing DPOLL TOGGLE TLOVER SETIMR TOGGL2 Automatic write operation Reverse data Toggle 0 0 1 Automatic erase operation 0 Toggle 0 1 Toggle Temporary erase stop mode Temporary erase stop and read (from sectors in temporary erase stop) 1 1 0 0 Toggle*1 Temporary erase stop and read (from sectors not in temporary erase stop) Data Data Data Data Data Reverse data Toggle*2 0 0 1*3 Reverse data Toggle 1 0 1 Temporarily erase stop mode 0 Toggle 1 1 *4 Write operation in temporarily erase stop mode 0 Toggle 1 1 *4 Temporary erase stop and read (to sectors in temporary erase stop) Time limit exceeded Automatic write operation *1: TOGGLE2 toggles continuous read operations from sectors in temporary erase stop status. *2: TOGGLE toggles continuous read operations from any address. *3: During temporary erase stop status and write operations, TOGGLE2 indicates "1" while reading the address for write operation. However, TOGGLE2 toggles continuous read operations from sectors in temporary erase stop status. *4: TOGGLE2 toggles continuous read operations for sectors under write/erase operation, but does not toggle read operations for other sectors while TLOVER indicates "1," meaning that the time limit is exceeded. The bits listed in the table is the following meaning: [Bit 7] DPOLL: Data polling [Bit 6] TOGGLE: Toggle bit [Bit 5] TLOVER: Time limit exceeded [Bit 3] SETIMR: Sector erase timer [Bit 2] TOGGL2: Toggle bit 2 Each bit is briefly described below: 553 CHAPTER 17 FLASH MEMORY [bit 7] DPOLL (Data polling flag) This flag is used with the data polling function to report that the automatic algorithm is being executed or terminated. ● Automatic write operation status When read access is performed while the automatic write algorithm is being executed, flash memory outputs the inversion of bit 7 of the last data written regardless of the address indicated by the address signal. When read access is performed at the end of the automatic write algorithm, flash memory outputs bit 7 of the read data to the address indicated by the address signal. ● Chip/sector erase operation status When read access is performed while the erase/sector erase algorithm is being executed for a sector erase, flash memory outputs "0" from the chip currently being erased. For a chip erase, flash memory outputs "0" regardless of the address indicated by the address signal. Similarly, flash memory outputs "1" at the end of the erase/sector erase algorithm. ● Temporary sector erase stop status When read access is performed during temporary sector erase stop status, flash memory outputs "1" when the address indicated by the address signal is included in the sector in erase status. If the address is not included in the sector in erase status, flash memory outputs bit 7 of the read value to the address. For checking whether a sector is in temporary sector erase stop status and which sector is in erase status, read this bit and the toggle bit flag. Note: Read access to a specified address is ignored while the automatic algorithm is active. Values can be output to other bits after data polling flag operation terminates in data read operation. Therefore, when data is to be read after terminating the automatic algorithm, confirm that data polling is terminated in the current read access. [bit 6]: TOGGLE (Toggle bit flag) As with the data polling flag, this flag is used with the toggle bit function to mainly report that the automatic algorithm is being executed or terminated. ● Write or chip/sector erase operation status When continuous read operations are performed while the automatic write algorithm or chip/sector erase algorithm is being executed, flash memory outputs "1" and "0" toggle results to bit 6 regardless of the address indicated by the address signal. When continuous read operations are performed at the end of the automatic write algorithm or chip/sector erase algorithm, flash memory stops bit 6 from toggling and outputs bit 6 (DATA: 6) of the data read from the address indicated by the address signal. 554 ● Temporary sector erase stop status When a read operation is performed during a temporary sector erase stop operation, flash memory outputs "1" if the address indicated by the address signal is included in the sector in erase state. If the address is not included in the sector in erase state, flash memory outputs the data of bit 6 (DATA:6) of the read value at the address indicated by the address signal. Reference: If a write target sector is protected from rewriting during a write operation, the toggle bit tries to toggle for about 2 µs and stops toggling without changing data. If all selected sectors are protected from rewriting during a erase operation, the toggle bit tries to toggle for about 100 µs and the system returns to read/reset status without changing data. [bit 5] TLOVER (Time limit over flag) This flag is used to report that a time (number of internal pulses) specified internally with flash memory is exceeded while the automatic algorithm is being executed. ● Write or chip/sector erase operation status When read access is performed within a specified time (necessary for write or erase) after activating the automatic write or chip/sector erase algorithm, flash memory outputs "0." If read access is performed beyond the specified time, flash memory outputs "1." Because these output operations are not affected by whether the automatic algorithm is being executed or terminated, these operations can be used to check whether write or erase operation is successful. If flash memory outputs "1" while the automatic algorithm is being executed with the data polling function or toggle bit function, consider the write operation to be unsuccessful. For example, when "1" is written to a flash memory address where "0" is written, failure occurs. Flash memory is locked and the automatic algorithm is not terminated. Thus, valid data is not outputted from the data polling flag. The toggle bit flag does not stop toggling, the time limit is exceeded, and "1" is outputted to the TLOVER flag. This status indicates that flash memory was not used correctly, not that it was defective. Execute a reset command. [Bit 4] SETIMR Sector erase timer flag This flag is used to report that sector erasure is being awaited after starting a sector erase command. ● Sector erase operation status When read access is performed within a sector erase wait period after starting a sector erase command, flash memory outputs "0" regardless of the address indicated by the address signal of the target sector. If read access is performed beyond the wait period, flash memory outputs "1" regardless of the address. When "1" is set in this flag while the data polling or toggle bit function indicates that the automatic erase algorithm is being executed, an internally controlled erase operation has started. The writing of subsequent sector erase code and commands other than erase temporary stop is ignored until erase operation terminates. When this flag is "0", flash memory accepts another sector erase code entry. In this case, it is recommended to check the status of this flag by software before writing the succeeding sector erase code. If this flag is "1" at the second time of status check, the additional sector erase code may not be accepted. 555 CHAPTER 17 FLASH MEMORY ● Sector erase operation status When a read operation is performed during a temporary sector erase stop operation, flash memory outputs "1" if the address indicated by the address signal is included in the sector that is subject to the erase operation. If the address is not included in the sector that is subject to the erase operation, flash memory outputs the data of bit 3 (DATA:3) of the read value at the address indicated by the address signal. [bit 6] TOGGL2 (Toggle bit flag 2) Together with toggle bit 6, this toggle bit flag is used with the toggle bit function to report whether flash memory is under automatic erase operation or in temporary erase stop status. ● Write or chip/sector erase operation status This bit toggles the same way as bit 2. ● Temporary sector erase stop operation status When continuous read access is performed from a sector in temporary erase stop status while flash memory is in temporary erase stop status and read mode, bit 2 toggles. When continuous read access is performed from a sector not subject to a temporary erase stop operation while flash memory is in temporary erase stop status and write mode, bit 2 becomes "1." Unlike bit 2, bit 6 only toggles in normal write and erase operations, or in temporary erase stop status and write operation. Reference: For example, bit 2 and bit 6 are used together to detect a temporary erase stop and read mode (bit 2 toggles but bit 6 does not). Bit 2 is also used to detect sectors that are subject to erase operations. If data is read from a sector that is subject to an erase operation for the flash memory, bit 2 toggles. 556 17.5 Writing to and Erasing Flash Memory This section explains how to issue a command to start the automatic algorithm for a read/reset, write, chip erase, sector erase, temporary sector erase stop, or sector erase restart operation in flash memory. ■ Overview of Flash Memory Write/Erase The automatic algorithm can be executed for the following operations in flash memory by executing bus write cycles for the corresponding command sequence: • Read/reset • Write • Chip erase • Sector erase • Temporary stop of sector erase • Sector erase restart The write cycles for each bus must always be executed continuously. In addition, termination of the automatic algorithm can be checked using the data polling function. Flash memory is set again to read/reset status after the automatic algorithm terminates normally. 557 CHAPTER 17 FLASH MEMORY 17.5.1 Read/Reset Status This section explains how to issue read/reset commands to set flash memory into read/ reset status. ■ Reading/Resetting Flash Memory The read/reset operation becomes possible by continuously sending read/reset commands (listed in the command sequence table) to target sectors in flash memory. A bus operation is performed one or three times with a read/reset command sequence. There is no essential difference between these two sequences. Read/reset status is the initial status of flash memory, and flash memory is set in this status at power-on or when a command terminates normally. In this status, the system waits for a command other than read/reset to be entered. Data can be read using normal read access in this status. Programs can be accessed from the CPU the same way the programs in mask ROM are accessed. The read/reset command is not necessary for reading data in normal read access. This command is required, however, to initialize the automatic algorithm if a command does not terminate normally. 558 17.5.2 Data Writing This section explains how to issue a write command to write data to flash memory. ■ Writing Data to Flash Memory The automatic data write algorithm can be started by continuously sending write commands (listed in the command sequence table) to target sectors in flash memory. The automatic algorithm and automatic writing start when writing data to the target address terminates in the fourth cycle. ■ How to Specify Address Data can be written by freely specifying the order of addresses where data is to be written. Moreover, data can be written beyond sector boundaries. Note that items of data can only be written with each write command in units of half-words. ■ Notes on Writing Data Data "0" cannot be changed to "1" in a write operation. If data "1" is overwritten, the data polling algorithm or toggle operation does not terminate, and the flash memory device is considered defective. An error is assumed with the time limit over flag if the specified write time is exceeded, or if only data "1" is apparently written, although data "0" is read in read/reset status. Data "0" can be changed to "1" only with an erase operation. All commands are ignored during automatic writing. If a hardware reset is activated during writing, the data being written is not guaranteed. ■ Write Procedure Figure 17.5-1 shows an example of the write procedure. The status of the automatic algorithm in flash memory can be checked using the hardware sequence flag. In the example in Figure 17.5-1 , the data polling flag (DPOLL) is used to check for termination of the write operation. Data for the flag check is read from the address where the last data was written. The data polling flag (DPOLL) changes together with the time limit over flag (TLOVER). Therefore, DPOLL must be rechecked even though TLOVER is set to "1." The toggle bit flag (TOGGLE) also stops toggling simultaneously when the value of TLOVER is changed to "1." Therefore, this flag must also be rechecked. 559 CHAPTER 17 FLASH MEMORY Figure 17.5-1 Example of Write Procedure Writing start Enable writing to flash memory with WE (bit 1) in FLCR. Write command sequence AAAAA (ROM1)/AAAAE (ROM2) D5552 (ROM1)/D5556 (ROM2) AAAAA (ROM1)/AAAAE (ROM2) Write address AA 55 A0 write data Read internal address. Next address Data polling (DPOLL) Dat Dat 0 Time limit (TLOVER) 1 Read internal address. Dat Data polling (DPOLL) Dat Write error Last address No Yes Disable writing to flash memory with WE (bit 1) in FLCR. Check hardware sequence flag Writing completion 560 17.5.3 Data Erasure (Chip Erasure) This section explains how to issue chip erase commands to erase all items of data in flash memory. ■ Erasing Data (Chip Erase) From Flash Memory All items of data can be erased from flash memory by continuously sending chip erase commands (listed in the command sequence table) to target sectors in flash memory. Six bus operations are necessary to execute a chip erase operation. The operation starts when the sixth write cycle is completed. The user need not write any value to flash memory before chip erase operation. Flash memory automatically writes "0" to erase all cells during the automatic erase algorithm is being executed. 561 CHAPTER 17 FLASH MEMORY 17.5.4 Data Erasure (Sector Erasure) This section explains how to issue sector erase commands to erase specified sectors in flash memory. Erasure in sector units is possible and two or more sectors can be specified with this command. Specified sectors can be erased from flash memory by continuously sending sector erase commands (listed in the command sequence table) to the sectors in the flash memory. ■ How to Specify Sectors A sector erase operation can be performed with six bus operations. A 50-µs sector erase wait period starts when a sector erase code (30H) is written to an even-numbered address accessible in the target sector in the sixth cycle. To erase another sector, a sector code (30H) must be written in the same cycle the same way. ■ Note on Specifying Two or More Sectors A sector erase operation starts when the 50 µs sector erase wait period terminates after the final sector erase code is written. Therefore, when two or more sectors are to be specified, the address and erase code of each target sector must be entered within 50 µs (in the sixth cycle of the command sequence) after specifying the preceding sector. Note that an address and erase code not entered within 50 µs may not be accepted. The sector erase timer (hardware sequence flag: SETIMR) can be used to check the validity of a written sector erase code. The address at which the read sector erase timer is written should indicate the target sector. ■ Sector Erase Procedure The hardware sequence flag can be used to check the status of the automatic algorithm in flash memory. Figure 17.5-2 shows an example of the sector erase procedure. In this example, the toggle bit flag (TOGGLE) is used to check for termination of the erase operation. Note that data for the flag check is read from the sector to be erased. The toggle bit flag (TOGGLE) stops toggling simultaneously when the value of the time limit over flag (TLOVER) changes to "1." Therefore, TOGGLE must be rechecked even though TLOVER is set to "1." Because the data polling flag (DPOLL) also changes with TLOVER, it must also be rechecked. 562 Figure 17.5-2 Sector Erase Procedure Erase start start Erase Enable erasure in flash memory with WE (bit 1) in FLCR. Sector erase timer 1 (SETIMR) Erase command sequence AAAAA (ROM1)/AAAAE (ROM2) D5552 (ROM1)/D5556 (ROM2) AAAAA (ROM1)/AAAAE (ROM2) AAAAA (ROM1)/AAAAE (ROM2) D5552 (ROM1)/D5556 (ROM2) 0 AA 55 80 AA 55 Enter code (30H) to sector to be erased. Yes Is there another sector to be erased? No Internal address read 1 Internal address read Next sector Internal address read 2 Yes Toggle bit (TOGGLE) data 1 = data 2? No Check with hardware sequence flag 0 Time limit (TLOVER) 1 Internal address read 1 Internal address read 2 No Toggle bit (TOGGLE) data 1 = data 2? Yes Erasure error Is final sector erased? No Yes (Bit 1) Disable erasure in flash memory Erase completion 563 CHAPTER 17 FLASH MEMORY 17.5.5 Temporary Sector Erase Stop This section explains how to issue temporary sector erase stop commands to temporarily stop a sector erase operation in flash memory. Data can be read from a sector not being erased by using this command. ■ Temporarily Stopping Sector Erase in Flash Memory To temporarily stop a sector erase operation in flash memory, send the temporary sector erase stop command listed in Table 17.4-1 to the target sector in flash memory. Data can be read from a sector being erased by using the temporary sector erase stop command to temporarily stop the erasure. Data can only be read from the sector; data cannot be written there. This command is only effective during sector erasure that includes an erase wait period. It is ignored during chip erase operation and write operation. A sector erase operation is stopped temporarily by writing a temporary erase stop code (B0 H). The address where the temporary erase stop code is written should indicate an address in flash memory. A temporary sector erase stop command issued during temporary erase stop status is ignored. If a temporary sector erase stop command is entered during a sector erase wait period, the sector erase wait is immediately canceled and erase operation in progress is stopped. If a temporary sector erase stop command is entered during a sector erase operation after the sector erase wait period elapses, sector erase operation is stopped temporarily after up to 20-µs elapse. Before issuing a sector erase temporary stop command, wait for 20µs after issuing the sector erase command or sector erase resume command. 564 17.5.6 Sector Erase Restart This section explains how to issue sector erase restart commands to restart a temporarily stopped sector erase operation in flash memory. ■ Restarting Sector Erase in Flash Memory To restart a temporarily stopped sector erase operation, send the sector erase restart command listed in Table 17.4-1 to the target sector in flash memory. The sector erase restart command can restart a sector erase operation that has temporarily been stopped with the temporary sector erase stop command. Restart operation starts when an erase restart code (30H) is written. The address where the erase restart code is written should indicate an address in flash memory. Sector erase restart commands issued during a sector erase operation are ignored. 565 CHAPTER 17 FLASH MEMORY 566 CHAPTER 18 MB91F355A/F353A/F356B/ F357B SERIAL PROGRAMMING CONNECTION This chapter shows the serial onboard writing connection (Fujitsu standard) using the AF220/AF210/ AF120/AF110 Flash Microcontroller Programmer by Yokogawa Digital Computer Corporation. 18.1 Basic Configuration of MB91F355A/F353A/F356B/F357B Serial Programming Connection 18.2 Pins Used for Fujitsu Standard Serial Onboard Writing 18.3 Examples of Serial Programming Connection 18.4 System Configuration of Flash Microcontroller Programmer 18.5 Other Precautionary Information 567 CHAPTER 18 MB91F355A/F353A/F356B/F357B SERIAL PROGRAMMING CONNECTION 18.1 Basic Configuration of MB91F355A/F353A/F356B/F357B Serial Programming Connection Fujitsu standard serial onboard writing uses the AF220/AF210/AF120/AF110 Flash Microcontroller Programmer by Yokogawa Digital Computer Corporation. ■ Basic Configuration of MB91F355A/F353A/F356B/F357B Serial Programming Connection Fujitsu standard serial onboard writing uses the AF220/AF210/AF120/AF110 flash microcontroller programmer by Yokogawa Digital Computer Corporation. Either a program operating in single-chip mode or a program operating in internal ROM external bus mode is selected to write. Figure 18.1-1 shows the basic configuration of MB91F355A/353A/F356B/F357B serial programming connection. Figure 18.1-1 Basic Configuration of MB91F355A/F353A/F356B/F357B Serial Programming Connection Host interface cable RS232C Common general-purpose cable (AZ210) AF220/AF210/ AF120/AF110 Flash Microcontroller Programmer + memory card CLK synchronous serial connection MB91F355A/F353A/ F356B/F357B User system Operable in stand-alone mode Note: In the MB91351A, MB91352A, MB91353A, MB91354A and MB91355A writing to flash memory is disabled because it is the mask product. Reference: For information on the functions of and operational procedures related to the flash microcontroller programmer (AF220/AF210/AF120/AF110), the general-purpose common cable (AZ210) for connection, and the connector, contact Yokogawa Digital Computer Corporation. 568 18.2 Pins Used for Fujitsu Standard Serial Onboard Writing This section describes pins used for Fujitsu standard serial onboard writing. ■ Pins Used for Fujitsu Standard Serial Onboard Writing Table 18.2-1 shows the functions of pins used for Fujitsu standard serial onboard writing. Table 18.2-1 Function of Pins Used for Fujitsu Standard Serial Onboard Writing Pin Function Description MD2, MD1, MD0 Mode pin Set to enter the flash serial programming mode. Flash serial programming mode: MD2 = 1, MD1 = 0, MD0 = 0 Reference: Single chip mode: MD2 = 0, MD1 = 0, MD0 = 0 PN0, PN2 Programming program start pin Input a" L" level to PN0 and a "H" level to PN2. INIT Reset pin SI3 Serial data input pin SO3 Serial data output pin SCK3 Serial clock input pin VCC Power voltage supply pin The programming voltage is supplied from the user system. Note: Do not connect with the power supply of the user system. VSS GND pin Must be shared with GND of the flash microcontroller programmer. - Use ch3 resource of UART for CLK sync mode. To use the PN0, PN2, SI3, SO3, and SCK3 pins within the user system as well, the control circuit shown in the Figure 18.2-1 is required. (Using the flash microcontroller programmer’s /TICS signal, the user circuit can be disconnected in serial programming mode.) Connect with AF220/AF210/AF120/AF110 under the power-off state of the user system. Figure 18.2-1 Control Circuit when Using by User System AF220/AF210/ AF120/AF110 Write control pin MB91F355A/F353A/F356B/F357B Write control pin 10 kΩ AF220/AF210/ AF120/AF110 /TICS pin User 569 CHAPTER 18 MB91F355A/F353A/F356B/F357B SERIAL PROGRAMMING CONNECTION 18.3 Examples of Serial Programming Connection This section shows examples of serial programming connections. ■ Examples of Serial Programming Connections Figure 18.3-1 and Figure 18.3-2 show examples of serial programming connections. Figure 18.3-1 Example of Serial Programming Connection for MB91F353A User system AF200 Flash Microcontroller Programmer MB91F353A (LQFP-120) Connector DX10-28S Pull-UP or Pull-DOWN connection selected by the MODE. (19) TAUX3 MD2 52 MD1 53 TMODE (12) TAUX (23) WDT (18) /TICS (10) MD0 54 PN0 70 In serial programming mode, synchronous communication = "H" PN2 71 User circuit /TRES (5) TTXD (13) SI3 TRXD (27) SO3 103 TCK (6) SCK3 104 TVcc (2) INTX 55 Vcc (19,44,56, 77,95) Power supplied from user (3.3 V) (14,15, 1,28) GND Pins 3, 4, 9, 11, 16, 17, 18, 20, 24, 25, and 26 are open. DX10-28S: write angle type 102 Vss (18,40,43, 59,76,96 112) Pin 14 Pin 1 DX10-28S Pin 28 Pin 15 Pin assignments of connector (Hirose Electric) Note : Pull-UP or Pull-DOWN Resistor : all 10 kΩ 570 Figure 18.3-2 Example of Serial Programming Connection for MB91F355A, MB91F356B and MB91F357B AF200 Flash Microcontroller Programmer User system MB91F355A (LQFP-176), MB91F356B (LQFP-176), MB91F357B (LQFP-176) Connector DX10-28S Pull-UP or Pull-DOWN connection selected by the MODE. (19) TAUX3 MD2 138 MD1 139 TMODE (12) TAUX (23) WDT (18) /TICS (10) MD0 140 PN0 81 In serial programming mode, synchronous communication = "H" PN2 83 User circuit /TRES (5) INTX 144 TTXD (13) SI3 125 TRXD (27) SO3 126 TCK (6) SCK3 127 TVcc (2) Vcc (18,36,46,62, 66,80,97,115, 142,146,163, 176) Power supplied from user (3.3 V) (14,15, 1,28) GND Pins 3, 4, 9, 11, 16, 17, 18, 20, 24, 25, and 26 are open. DX10-28S: write angle type Vss (17,35,45,64, 65,79,93,96 114,136,145 162,175) Pin 14 Pin 1 DX10-28S Pin 28 Pin 15 Pin assignments of connector (Hirose Electric) Note : Pull-UP or Pull-DOWN Resistor : all 10 kΩ 571 CHAPTER 18 MB91F355A/F353A/F356B/F357B SERIAL PROGRAMMING CONNECTION 18.4 System Configuration of Flash Microcontroller Programmer This section describes the system configuration of AF220/AF210/AF120/AF110 Flash Microcontroller Programmer by Yokogawa Digital Computer Corporation. ■ System Configuration of the Flash Microcontroller Programmer Table 18.4-1 shows the system configuration of AF220/AF210/AF120/AF110 Flash Microcontroller Programmer by Yokogawa Digital Computer Corporation and Inquiries for Yokogawa Digital Computer Corporation. Table 18.4-1 System Configuration of the Flash Microcontroller Programmer Type Main body Function AF220/AC4P Model with built-in Ethernet interface /100 V to 220 V power adapter AF210/AC4P Standard model /100 V to 220 V power adapter AF120/AC4P Model with built-in single key Ethernet interface /100 V to 220 V power adapter AF110/AC4P Single key model /100 V to 220 V power adapter AZ221 Programmer dedicated RS232C cable for PC/AT AZ210 Standard target probe (a) length: 1 m FF201 Fujitsu F2MC-16LX flash microcontroller control module AZ290 Remote controller /P2 2M bytes PC Card (Option) FLASH memory capacity up to 128K bytes supported /P4 4M bytes PC Card (Option) FLASH memory capacity of up to 512K bytes supported Inquiries: Yokogawa Digital Computer Corporation Telephone number: +81-42-333-6224 572 18.5 Other Precautionary Information This section shows notes of MB91F355A/F353A/F356B/F357B serial programming connections. ■ Notes of MB91F355A/F353A/F356B/F357B Serial Programming Connections ● Oscillation Clock Frequency For write operations on flash memory, the range of the oscillation clock frequency that can be used is between 10.0 MHz and 12.5 MHz. ● Port State for Write Operations on Flash Memory The ports for the flash memory writing via a serial programmer are in the initial state in the single-chip mode except the pin used write operations. 573 CHAPTER 18 MB91F355A/F353A/F356B/F357B SERIAL PROGRAMMING CONNECTION 574 CHAPTER 19 DATA INTERNAL RAM/ INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS This chapter describes the access restriction functions for data internal RAM/instruction internal RAM. 19.1 Overview 19.2 Explanation of Registers 19.3 Explanation of Operation 575 CHAPTER 19 DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS 19.1 Overview The access restriction functions limit the available area of the internal RAM area installed on the device. In initial device state, the available area is limited to 4K bytes. To use more than 4K bytes requires that the settings of these functions be changed. ■ Data Internal RAM/Instruction Internal RAM Access Restriction Function Registers The registers used by the data internal RAM/instruction internal RAM access restriction functions are as follows: Address 00000390H Address 00000280H DRLR FRLR ■ Block Diagram of the Data Internal RAM/Instruction Internal RAM Access Restriction Functions Figure 19.1-1 is a block diagram of the data internal RAM/instruction internal RAM access restriction functions. Figure 19.1-1 Block Diagram of the Data Internal RAM/Instruction Internal RAM Access Restriction Functions Bus control signal Read value D-bus RAM control circuit Write value DRLR Register value RAM control signal Bus control signal D-bus (data) D-bus RAM Bus control signal Read value F-bus RAM control circuit Write value FRLR Register value RAM control signal Bus control signal F-bus (instruction/data) F-bus RAM 576 19.2 Explanation of Registers This section describes the registers used by the data internal RAM/instruction internal RAM access restriction functions. ■ DRLR: Data RAM Limit Control Register (D-Bus RAM Limit Control Register) The configuration of the data RAM limit control register is shown below: Address : 00000390H Initial value 7 6 5 4 3 2 1 0 - - - - - - DL1 0 DL0 1 (R/W) [Bits 7 to 2] Reserved bits These bits are reserved bits. If writing data to these bits, be sure to write "0". The values read from these bits are undefined. [Bits 1, 0] DL1 and DL0 These bits limit the RAM area available for the stack. DL1 DL0 Explanation 0 0 (Setting not allowed) 0 1 The 4K bytes area at addresses 40000H to 40FFFH can be used (initial value). 1 0 The 8K bytes area at addresses 40000H to 41FFFH can be used. 1 1 The 16K bytes area at addresses 40000H to 43FFFH can be used. Note: Do not set a value that exceeds the RAM capacity installed on the device. If the setting is rewritten, insert at least one NOP instruction immediately after that processing. 577 CHAPTER 19 DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS ■ FRLR: Instruction RAM Limit Control Register (F-Bus RAM Limit Control Register) The configuration of the instruction RAM limit control register is shown below: Address : 00000280H Initial value 7 6 5 4 3 2 1 0 - - - - - - FL1 0 FL0 1 (R/W) [Bits 7 to 2] Reserved bits These bits are reserved bits. If writing data to these bits, be sure to write "0". The values read from these bits are undefined. [Bits 1, 0] FL1 and FL0 These bits limit the RAM area available for executing instructions. FL1 FL0 Explanation 0 0 (Setting not allowed) 0 1 The 4K bytes area at addresses 3F000H to 3FFFFH can be used (initial value). 1 0 The 8K bytes area at addresses 3E000H to 3FFFFH can be used. 1 1 The 16K bytes area at addresses 3C000H to 3FFFFH can be used. Note: Do not set a value that exceeds the RAM capacity installed on the device. If the setting is rewritten, insert at least one NOP instruction immediately after that processing. 578 19.3 Explanation of Operation This section describes the operation of the data internal RAM/instruction internal RAM access restriction functions. ■ Operation of the Data Internal RAM/Instruction Internal RAM Access Restriction Functions These functions limit the available area of the internal RAM area installed on the device. Writing to RAM area that has been specified as unavailable is not allowed. In addition, the values read from the unavailable area are undefined. In the initial device state, the available data RAM area and instruction RAM area are each limited to 4K bytes. To use more than 4K bytes requires that the settings of these functions be changed. 579 CHAPTER 19 DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS 580 APPENDIX The appendixes describe the I/O map, interrupt vectors, and pin states in each CPU state and provide instruction lists. APPENDIX A I/O Map APPENDIX B Interrupt Vector APPENDIX C Pin States in Each CPU State APPENDIX D Instruction Lists 581 APPENDIX APPENDIX A I/O Map The registers of the peripheral functions installed on the device are assigned the addresses listed in Table A-1. ■ Reading the I/O Map address 000000H register +1 +2 PDR1[R/W]B PDR2[R/W]B XXXXXXXX XXXXXXXX +0 PDR0[R/W]B XXXXXXXX +3 PDR3[R/W]B XXXXXXXX block T-unit Port Data Register Read/write attribute Access unit (B: byte, H: halfword, W: word) Initial value of register after reset Register name (column 1 of the register is at address 4n, column 2 is at address 4n + 1...) Leftmost register address (For word-length access, column 1 of the register becomes the MSB of the data.) The initial value of bits in a register are indicated as follows: 1: Initial value "1" 0: Initial value "0" X: Initial value "X" - : A physical register does not exist at the location. 582 APPENDIX A I/O Map ■ Correspondence between the Memory Space Area and Peripheral Resource Registers Table A-1 I/O Map (1 / 10) Address Register +0 +1 000000H ________ ________ 000004H PDR4[R/W]B XXXXXXXX 000008H 00000CH 000010H 000014H +2 +3 PDR3[R/W]B XXXXXXXX PDR5[R/W]B XXXXXXXX PDR2[R/W]B XXXXXXXX PDR6[R/W]B XXXXXXXX PDR8[R/W]B --XXXXXX PDR9[R/W]B ---XXXXX PDRA[R/W]B ----XXXX PDRB[R/W]B*3 XXXXXXXX PDRC[R/W]B*3 -----XXX ________ PDRH[R/W]B --XXXXXX PDRI[R/W]B --XXXXXX PDRL[R/W]B ------XX PDRM[R/W]B --XXXXXX PDRJ[R/W]B*3 XXXXXXXX PDRN[R/W]B --XXXXXX ________ ________ ________ ________ SES5[R/W]B*3 ------00 SES6[R/W]B ------00 SES7[R/W]B ------00 SDR5[R/W]B*3 XXXXXXXX SDR6[R/W]B XXXXXXXX SDR7[R/W]B XXXXXXXX PDRG[R/W]B*3 --XXXXXX PDRK[R/W]B XXXXXXXX 000018H PDRO[R/W]B XXXXXXXX 00001CH ________ 000020H ________ 000024H *3 PDRP[R/W]B ----XXXX ________ SMCS5[R/W]B,H*3 00000010----00-- 00002CH SMCS6[R/W]B,H 00000010----00-SMCS7[R/W]B,H 00000010----00-- 000030H ________ ________ 000034H CDCR6[R/W]B 0---1111 ________ *1 000038H ________ 00003CH ________ 000028H SRCL5[W]B*3 -------________ 000048H EIRR0[R/W]B,H,W ENIR0[R/W]B,H,W 00000000 00000000 DICR[R/W]B,H,W HRCL[R/W]B,H,W -------0 0--11111 TMRLR0[W]H,W XXXXXXXXXXXXXXXX 00004CH ________ 000050H TMRLR1[W]H,W XXXXXXXXXXXXXXXX 000054H ________ 000040H 000044H ________ CDCR5[R/W]B*3 0---1111 CDCR7[R/W]B 0---1111 ________ *1 Block T-unit port data register*3 R-bus port data register*3 Reserved SIO5*3 SIO6 SIO7 SIO ________ *1 prescaler 5*3 SIO prescaler 6, 7 SRCL6[W]B -------- SRCL7[W]B -------- SIO5 to 7*3 ________ ________ Reserved ELVR0[R/W]B,H,W 00000000 Extint (INT0 to 7) ________ DLYI/I-unit TMR0[R]H,W XXXXXXXXXXXXXXXX TMCSR0[R/W]B,H,W ----000000000000 TMR1[R]H,W XXXXXXXXXXXXXXXX TMCSR1[R/W]B,H,W ----000000000000 Reload timer 0 Reload timer 1 *1: This is a test register. Access is not allowed. *3: The MB91F353A/351A/352A/353A do not have this register. Access is not allowed. 583 APPENDIX Table A-1 I/O Map (2 / 10) Address Register +0 +1 000058H TMRLR2[W]H,W XXXXXXXXXXXXXXXX 00005CH ________ 000060H 000064H 000068H 00006CH 000070H 000074H 000078H 00007CH 000080H 000084H SIDR0[R] SORR0[W]B,H,W XXXXXXXX UTIM0[R]H(UTIMR0[W]H) 0000000000000000 SIDR1[R] SSR1[R/W]B,H,W SORR1[W]B,H,W 00001000 XXXXXXXX UTIM1[R]H(UTIMR1[W]H) 0000000000000000 SIDR2[R] SSR2[R/W]B,H,W SORR2[W]B,H,W 00001000 XXXXXXXX UTIM2[R]H(UTIMR2[W]H) 0000000000000000 ADCS2[R/W]B,H,W ADCS1[R/W]B,H,W 0000XX00 000X0000 ADTH0[R]B,H,W ADTL0[R]B,H,W 000000XX XXXXXXXX ADTH2[R]B,H,W ADTL2[R]B,H,W 000000XX XXXXXXXX DACR2[R/W]B,H,W ________ *3 -------0 SSR0[R/W]B,H,W 00001000 0000A0H 0000A4H DRCL0[W]B -------- UTIMC0[R/W]B 000001 SCR1[R/W]B,H,W 00000100 SMR1[R/W]B,H,W 00--0--- DRCL1[W]B -------- UTIMC1[R/W]B 000001 SCR2[R/W]B,H,W 00000100 SMR2[R/W]B,H,W 00--0--- DRCL2[W]B UTIMC2[R/W]B -------000001 ADCT[R/W]H,W XXXXXXXX_XXXXXXXX ADTH1[R]B,H,W ADTL1[R]B,H,W 000000XX XXXXXXXX ADTH3[R]B,H,W ADTL3[R]B,H,W 000000XX XXXXXXXX DACR1[R/W]B,H,W DACR0[R/W]B,H,W -------0 -------0 ________ ________ ________ 000090H 00009CH SMR0[R/W]B,H,W 00--0--- ________ 00008CH 000098H SCR0[R/W]B,H,W 00000100 DADR1[R/W]B,H,W XXXXXXXX ________ ________ IBCR[R]B,H,W IBSR[R]B,H,W 00000000 00000000 ITMK[R/W]B,H,W 0011111111111111 IDAR[R/W]B,H,W ________*1 00000000 ________ ________*1 ________*1 ________ 0000A8H TMRLR3[W]H,W XXXXXXXXXXXXXXXX 0000ACH ________ ________*1 Block Reload timer 2 UART0 U-timer/UART0 UART1 U-timer/UART1 UART2 U-timer/UART2 A/D converter D/A converter*3 DADR0[R/W]B,H,W D/A converter*3 XXXXXXXX ________ Reserved ________*1 ITBA[R/W]B,H,W 0000000000000000 ISMK[R/W]B,H,W ISBA[R/W]B,H,W 01111111 00000000 ICCR[R/W]B,H,W IDBL[R/W]B,H,W 00011111 -------0 ________ ________*1 ________*1 TMR3[R]H,W XXXXXXXXXXXXXXXX TMCSR3[R/W]B,H,W ----000000000000 *1: This is a test register. Access is not allowed. *3: The MB91F353A/351A/352A/353A do not have this register. Access is not allowed. 584 +3 TMR2[R]H,W XXXXXXXXXXXXXXXX TMCSR2[R/W]B,H,W ----000000000000 DADR2[R/W]B,H,W*3 XXXXXXXX ________ 000088H 000094H +2 Reserved I2C interface Reserved Reload timer 3 APPENDIX A I/O Map Table A-1 I/O Map (3 / 10) Address 0000B0H 0000B4H 0000B8H 0000BCH 0000C0H 0000C4H 0000C8H 0000CCH 0000D0H 0000D4H 0000D8H 0000DCH 0000E0H Register +0 +1 +2 +3 RCR1[W]B,H,W*3 00000000 CCRH0[R/W]B,H,W 00000000 RCR0[W]B,H,W 00000000 CCRL0[R/W]B,H,W 00001000 UDCR1[R]B,H,W*3 00000000 UDCR0[R]B,H,W 00000000 CSR0[R/W]B,H,W 00000000 CCRH1[R/W]B,H,W*3 CCRL1[R/W]B,H,W*3 00000000 00001000 ________ ________ SIDR3[R] SORR3[W]B,H,W XXXXXXXX UTIM3[R]H(UTIMR3[W]H) 0000000000000000 SIDR4[R] SSR4[R/W]B,H,W*3 SORR4[W]B,H,W*3 00001000 XXXXXXXX SSR3[R/W]B,H,W 00001000 UTIM4[R]H(UTIMR4[W]H)*3 0000000000000000 *3 ________ ________ CSR1[R/W]B,H,W*3 00000000 ________ SCR3[R/W]B,H,W 00000100 SMR3[R/W]B,H,W 00--0--- ________ UTIMC3[R/W]B 000001 ________ SCR4[R/W]B,H,W*3 00000100 *3 EIRR1[R/W]B,H,W ENIR1[R/W]B,H,W 00000000 00000000 TCDT[R/W]H,W 0000000000000000 IPCP1[R]H,W XXXXXXXXXXXXXXXX IPCP3[R]H,W XXXXXXXXXXXXXXXX ICS23[R/W]B,H,W ________ 00000000 *3 ELVR1[R/W]B,H,W 00000000 TCCS[R/W]B,H,W ________ 00000000 IPCP0[R]H,W XXXXXXXXXXXXXXXX IPCP2[R]H,W XXXXXXXXXXXXXXXX ICS01[R/W]B,H,W ________ 00000000 0000E4H OCCP1[R/W]H,W*3 XXXXXXXXXXXXXXXX OCCP0[R/W]H,W XXXXXXXXXXXXXXXX 0000E8H OCCP3[R/W]H,W*3 XXXXXXXXXXXXXXXX OCCP2[R/W]H,W XXXXXXXXXXXXXXXX 0000ECH OCCP5[R/W]H,W*3 XXXXXXXXXXXXXXXX OCCP4[R/W]H,W*3 XXXXXXXXXXXXXXXX OCCP7[R/W]H,W*3 XXXXXXXXXXXXXXXX OCS23[R/W]B,H,W 1110110000001100 OCCP6[R/W]H,W*3 XXXXXXXXXXXXXXXX OCS01[R/W]B,H,W 1110110000001100 0000F0H 0000F4H 0000F8H 0000FCH 000100H to 000114H 000118H 00011CH OCS67[R/W]B,H,W*3 1110110000001100 ________ ________ OCS45[R/W]B,H,W*3 1110110000001100 ________ ________ ________ ________ ________ ________ GCN20[R/W]B 00000000 ________ GCN10[R/W]H 0011001000010000 ________ 8/16-bit Up/ Down counter 0, 1*3 Reserved UART3 U-timer/UART3 SMR4[R/W]B,H,W*3 UART4*3 00--0--UTIMC4[R/W]B*3 000001 ________ Block ________ U-timer/UART4 *3 Ext int (INT8-15)*3 16-bit freerunning timer 16-bit ICU 16-bit OCU*3 Reserved Reserved PPG control 0 Reserved *3: The MB91F353A/351A/352A/353A do not have this register. Access is not allowed. 585 APPENDIX Table A-1 I/O Map (4 / 10) Address 000120H 000124H 000128H 00012CH 000130H 000134H 000138H 00013CH 000140H 000144H Register +0 +1 PTMR0[R]H,W 1111111111111111 PDUT0[W]H,W XXXXXXXXXXXXXXXX PTMR1[R]H,W *3 1111111111111111 PDUT1[W]H,W*3 XXXXXXXXXXXXXXXX PTMR2[R]H,W 1111111111111111 PDUT2[W]H,W XXXXXXXXXXXXXXXX PTMR3[R]H,W*3 1111111111111111 PDUT3[W]H,W*3 XXXXXXXXXXXXXXXX PTMR4[R]H,W 1111111111111111 PDUT4[W]H,W XXXXXXXXXXXXXXXX 000148H PTMR5[R]H,W*3 1111111111111111 00014CH PDUT5[W]H,W*3 XXXXXXXXXXXXXXXX 000150H to 0001FCH 000200H 000204H 000208H 00020CH +2 PCSR0[W]H,W XXXXXXXXXXXXXXXX PCNH0[R/W]B,H,W PCNL0[R/W] 00000000 000000X0 PCSR1[W]H,W *3 XXXXXXXXXXXXXXXX 586 Block PPG0 PPG1*3 PCNH1[R/W]B,H,W*3 PCNL1[R/W]B,H,W*3 00000000 00000000 PCSR2[W]H,W XXXXXXXXXXXXXXXX PPG2 PCNH2[R/W]B,H,W PCNL2[R/W]B,H,W 00000000 00000000 PCSR3[W]H,W*3 XXXXXXXXXXXXXXXX PPG3*3 PCNH3[R/W]B,H,W*3 PCNL3[R/W]B,H,W*3 00000000 00000000 PCSR4[W]H,W XXXXXXXXXXXXXXXX PPG4 PCNH4[R/W]B,H,W PCNL4[R/W]B,H,W 00000000 00000000 PCSR5[W]H,W*3 XXXXXXXXXXXXXXXX PCNH5[R/W]B,H,W*3 00000000 ________ PCNL5[R/W]B,H,W*3 00000000 PPG5*3 Reserved DMACA0[R/W]B,H,W *4 000000000000XXXXXXXXXXXXXXXXXXXX DMACB0[R/W]B,H,W 0000000000000000XXXXXXXXXXXXXXXX DMACA1[R/W]B,H,W *4 000000000000XXXXXXXXXXXXXXXXXXXX DMACB1[R/W]B,H,W 0000000000000000XXXXXXXXXXXXXXXX DMACA2[R/W]B,H,W *4 000000000000XXXXXXXXXXXXXXXXXXXX DMACB2[R/W]B,H,W 000214H 0000000000000000XXXXXXXXXXXXXXXX *3: The MB91F353A/351A/352A/353A do not have this register. Access is not allowed. *4: The 16 low-order bits (DTC[15:0]) of DMACA0 to 4 can not be byte-accessed. 000210H +3 DMAC APPENDIX A I/O Map Table A-1 I/O Map (5 / 10) Address Register +0 +1 +2 +3 DMACA3[R/W]B,H,W *4 000000000000XXXXXXXXXXXXXXXXXXXX DMACB3[R/W]B,H,W 0000000000000000XXXXXXXXXXXXXXXX 000218H 00021CH DMACA4[R/W]B,H,W *4 000000000000XXXXXXXXXXXXXXXXXXXX DMACB4[R/W]B,H,W 0000000000000000XXXXXXXXXXXXXXXX ________ 000220H 000224H 000228H 00022CH to 00023CH ________ 000240H DMACR[R/W]B 0XX00000XXXXXXXXXXXXXXXXXXXXXXXX 000244H to 00027CH ________ 000280H FRLR[R/W]B,H,W ------01 *2 ________ 000284H to 00038CH 000390H DRLR[R/W]B,H,W ------01 *2 0003F0H 0003F4H 0003F8H 0003FCH Reserved DMAC Reserved ________ ________ ________ Limit on F-Bus RAM capacity Reserved ________ ________ Limit on D-Bus RAM capacity ________ Reserved BSD0[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX BSD1[R/W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX BSDC[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX BSRR[R] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Bit search module DDRH[R/W]B --000000 DDRI[R/W]B --000000 000404H DDRG[R/W]B*3 --000000 DDRK[R/W]B 00000000 DDRL[R/W]B ------00 DDRM[R/W]B --000000 000408H DDRO[R/W]B 00000000 DDRP[R/W]B*3 ---- 0000 00040CH DMAC ________ 000394H to 0003ECH 000400H Block DDRJ[R/W]B*3 00000000 DDRN[R/W]B --000000 ________ R-bus data direction register*3 ________ *2: Immediately after release of a reset, the available internal RAM area is limited by the functions described in CHAPTER 19 "DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS". In addition, if the setting for available area is rewritten, insert at least one NOP instruction immediately after that processing. *3: The MB91F353A/351A/352A/353A do not have this register. Access is not allowed. *4: The 16 low-order bits (DTC[15:0]) of DMACA0 to 4 can not be byte-accessed. 587 APPENDIX Table A-1 I/O Map (6 / 10) Address Register +0 +1 +2 +3 000410H PFRG[R/W]B*3 --00-00- PFRH[R/W]B --00-00- PFRI[R/W]B --00-00- ________ 000414H ________ PFRL[R/W]B ------00 PFRM[R/W]B --00-00- PFRN[R/W]B --000000 000418H PFRO[R/W]B 00000000 PFRP[R/W]B*3 ----0000 PCRG[R/W]B*3 --000000 PCRH[R/W]B --000000 PCRI[R/W]B --000000 ________ 000424H ________ ________ PCRM[R/W]B --000000 PCRN[R/W]B --000000 000428H PCRO[R/W]B 00000000 PCRP[R/W]B*3 ----0000 ________ ________ 000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H 00046CH ________ ICR00[R/W]B,H,W ---11111 ICR04[R/W]B,H,W ---11111 ICR08[R/W]B,H,W ---11111 ICR12[R/W]B,H,W ---11111 ICR16[R/W]B,H,W ---11111 ICR20[R/W]B,H,W ---11111 ICR24[R/W]B,H,W ---11111 ICR28[R/W]B,H,W ---11111 ICR32[R/W]B,H,W ---11111 ICR36[R/W]B,H,W ---11111 ICR40[R/W]B,H,W ---11111 ICR44[R/W]B,H,W ---11111 ICR01[R/W]B,H,W ---11111 ICR05[R/W]B,H,W ---11111 ICR09[R/W]B,H,W ---11111 ICR13[R/W]B,H,W ---11111 ICR17[R/W]B,H,W ---11111 ICR21[R/W]B,H,W ---11111 ICR25[R/W]B,H,W ---11111 ICR29[R/W]B,H,W ---11111 ICR33[R/W]B,H,W ---11111 ICR37[R/W]B,H,W ---11111 ICR41[R/W]B,H,W ---11111 ICR45[R/W]B,H,W ---11111 000470H to 00047CH ICR02[R/W]B,H,W ---11111 ICR06[R/W]B,H,W ---11111 ICR10[R/W]B,H,W ---11111 ICR14[R/W]B,H,W ---11111 ICR18[R/W]B,H,W ---11111 ICR22[R/W]B,H,W ---11111 ICR26[R/W]B,H,W ---11111 ICR30[R/W]B,H,W ---11111 ICR34[R/W]B,H,W ---11111 ICR38[R/W]B,H,W ---11111 ICR42[R/W]B,H,W ---11111 ICR46[R/W]B,H,W ---11111 588 R-bus pull-up control register*3 Reserved ICR03[R/W]B,H,W ---11111 ICR07[R/W]B,H,W ---11111 ICR11[R/W]B,H,W ---11111 ICR15[R/W]B,H,W ---11111 ICR19[R/W]B,H,W ---11111 ICR23[R/W]B,H,W ---11111 ICR27[R/W]B,H,W ---11111 ICR31[R/W]B,H,W ---11111 ICR35[R/W]B,H,W ---11111 ICR39[R/W]B,H,W ---11111 ICR43[R/W]B,H,W ---11111 ICR47[R/W]B,H,W ---11111 Interrupt control unit ________ TBCR[R/W]B,H,W 00XXXX00 DIVR0[R/W]B,H,W 000484H 00000011 OSCCR[R/W]B 000488H XXXXXXX0 *3: The MB91F353A/351A/352A/353A do not have this register. Access is not allowed. 000480H register*3 Reserved 000420H 00042CH to 00043CH R-bus port function ________ ________ 00041CH Block RSRR[R/W]B,H,W STCR[R/W]B,H,W 10000000 00110011 CLKR[R/W]B,H,W WPR[W]B,H,W 00000000 XXXXXXXX ________ CTBR[W]B,H,W XXXXXXXX DIVR1[R/W]B,H,W 00000000 ________ Clock control unit Oscillation control APPENDIX A I/O Map Table A-1 I/O Map (7 / 10) Address Register Block +0 +1 +2 +3 00048CH WPCR[R/W]B 00---000 ________ ________ ________ 000490H OSCR[R/W]B 00---000 ________ ________ ________ 000494H RSTOP0[W]B 00000000 ________ RSTOP1[W]B 00000000 ________ RSTOP2[W]B 00000000 ________ RSTOP3[W]B -----000 ________ 000498H 00049CH to 0005FCH ________ DDR3[R/W]B 00000000 DDR5[R/W]B 00000000 DDR9[R/W]B ---00000 DDRA[R/W]B ----0000 DDRB[R/W]B*3 00000000 ________ ________ 000604H DDR4[R/W]B 00000000 000608H DDR8[R/W]B --000000 000610H 000614H ________ DDRC[R/W]B*3 -----000 ________ ________ ________ ________ ________ ________ PFR6[R/W]B 11111111 ________ *3 PFR8[R/W]B --1--0-- PFR9[R/W]B ---010-1 PFRA[R/W]B ----1111 00061CH PFRB2[R/W]B*3 00----00 PFRC[R/W]B*3 ---00000 ________ ________ 000620H ________ ________ PCR2[R/W]B 00000000 PCR3[R/W]B 00000000 PFRB1[R/W]B 00000000 000624H PCR4[R/W]B 00000000 PCR5[R/W]B 00000000 PCR6[R/W]B 00000000 ________ 000628H PCR8[R/W]B --000000 PCR9[R/W]B 00000000 PCRA[R/W]B 00000000 PCRB[R/W]B*3 00000000 00062CH PCRC[R/W]B*3 -----000 ________ ________ ________ ________ ASR0[R/W]H,W ACR0[R/W]B,H,W 0000000000000000 1111XX0000000000 *3: The MB91F353A/351A/352A/353A do not have this register. Access is not allowed. 000640H Reserved T-unit data direction register*3 ________ 000618H 000630H to 00063CH Main clock oscillation stabilization wait timer Peripheral stop control Reserved DDR2[R/W]B 00000000 DDR6[R/W]B 00000000 000600H 00060CH Watch timer T-unit port function register*3 T-unit pull-up control register*3 Reserved T-unit 589 APPENDIX Table A-1 I/O Map (8 / 10) Address 000644H 000648H 00064CH 000650H 000654H 000658H 00065CH 000660H 000664H 000668H 00066CH Register +0 +1 +2 ASR1[R/W]H,W 0000000000000000 ASR2[R/W]H,W 0000000000000000 ASR3[R/W]H,W 0000000000000000 ASR4[R/W]H,W 0000000000000000 ASR5[R/W]H,W 0000000000000000 ASR6[R/W]H,W 0000000000000000 ASR7[R/W]H,W 0000000000000000 AWR0[R/W]B,H,W 0111111111111111 AWR2[R/W]B,H,W XXXXXXXXXXXXXXXX AWR4[R/W]B,H,W XXXXXXXXXXXXXXXX AWR6[R/W]B,H,W XXXXXXXXXXXXXXXX ACR1[R/W]B,H,W XXXXXXXXXXXXXXXX ACR2[R/W]B,H,W XXXXXXXXXXXXXXXX ACR3[R/W]B,H,W XXXXXXXXXXXXXXXX ACR4[R/W]B,H,W XXXXXXXXXXXXXXXX ACR5[R/W]B,H,W XXXXXXXXXXXXXXXX ACR6[R/W]B,H,W XXXXXXXXXXXXXXXX ACR7[R/W]B,H,W XXXXXXXXXXXXXXXX AWR1[R/W]B,H,W XXXXXXXXXXXXXXXX AWR3[R/W]B,H,W XXXXXXXXXXXXXXXX AWR5[R/W]B,H,W XXXXXXXXXXXXXXXX AWR7[R/W]B,H,W XXXXXXXXXXXXXXXX 000670H ________ 000674H ________ 000678H IOWR0[R/W]B,H,W XXXXXXXX IOWR1[R/W]B,H,W XXXXXXXX CSER[R/W]B,H,W 000000001 ________ 00067CH 000680H 000684H to 0007F8H 0007FCH 000800H to 000AFCH IOWR2[R/W]B,H,W XXXXXXXX ________ ________ ________ MODR[W] *5 XXXXXXXX Block T-unit ________ TCR[W]B,H,W 00000000 ________ Reserved ________ ________ *5: This register is accessed by mode vector fetch. It can not be accessed during normal operation. 590 +3 ________ Reserved APPENDIX A I/O Map Table A-1 I/O Map (9 / 10) Address 000B00H 000B04H 000B08H 000B0CH 000B10H 000B14H to 000B1CH 000B20H 000B24H 000B28H 000B2CH 000B30H 000B34H 000B38H 000B3CH 000B40H 000B44H 000B48H 000B4CH 000B50H 000B54H 000B58H 000B5CH 000B60H 000B64H 000B68H 000B6CH Register +0 ESTS0[R/W] X0000000 ECTL0[R/W] 0X000000 ECNT0[W] XXXXXXXX +1 ESTS1[R/W] XXXXXXXX ECTL1[R/W] 00000000 ECNT1[W] XXXXXXXX EWPT[R] 0000000000000000 EDTR0[W] XXXXXXXXXXXXXXXX +2 +3 ESTS2[R] 1XXXXXXX ECTL2[W] 000X0000 EUSA[W] XXX00000 Block ________ ECTL3[R/W] 00X00X11 EDTC[W] 0000XXXX ________ EDTR1[W] XXXXXXXXXXXXXXXX ________ EIA0[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EIA1[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EIA2[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EIA3[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EIA4[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EIA5[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EIA6[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EIA7[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EDTA[R/W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EDTM[R/W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EOA0[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EOA1[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EPCR[R/W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EPSR[R/W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EIAM0[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EIAM1[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EOAM0/EODM0[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EOAM1/EODM1[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EOD0[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX EOD1[W] XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX DSU (EVA chip only) DSU (EVA chip only) 591 APPENDIX Table A-1 I/O Map (10 / 10) Address Register +0 +1 +2 +3 Block 000B70H to 000BFCH ________ 000C00H Test register (access is not allowed.) Interrupt control unit 000C04H to 000C14H Test register (access is not allowed.) R-bus test 000C18H to 000FFCH ________ Reserved DMASA0[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA0[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA1[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA1[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA2[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA2[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA3[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA3[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA4[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA4[R/W]W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H 001024H 001028H to 001FFCH 00700CH 007010H 007004H 007008H 007014H to 0070FFH 592 DMAC DMAC ________ FLCR[R/W] 0110X000 FLWC[R/W] 00010011 ________ 007000H Reserved Reserved ________ ________ ________ ________ ________ ________ ________ ________ ________ ________ ________ ________ ________ ________ ________ ________ ________ ________ Flash memory Reserved APPENDIX A I/O Map *1: This is a test register. Access is not allowed. *2: Immediately after release of a reset, the available internal RAM area is limited by the functions described in CHAPTER 19 "DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS". In addition, if the setting for available area is rewritten, insert at least one NOP instruction immediately after that processing. *3: The MB91F353A/351A/352A/353A do not have this register. Access is not allowed. *4: The 16 low-order bits (DTC [15:0]) of DMACA0 to 4 cannot be byte-accessed. *5: This register is accessed by mode vector fetch. It cannot be accessed during normal operation. 593 APPENDIX APPENDIX B Interrupt Vector Table B-1 shows the interrupt vector table, which gives the interrupt sources and interrupt vector/interrupt control register allocations for the MB91350A. ■ Interrupt Vectors Table B-1 Interrupt Vector Table (1 / 3) Interrupt number Interrupt level Offset TBR default address RN 00 - 3FCH 000FFFFCH - 01 - 3F8H 000FFFF8H - 2 02 - 3F4H 000FFFF4H - 3 03 - 3F0H 000FFFF0H - Reserved for system 4 04 - 3ECH 000FFFECH - Reserved for system 5 05 - 3E8H 000FFFE8H - 000FFFE4H - Interrupt source Decimal Hexadecimal Reset 0 Mode vector 1 Reserved for system Reserved for system Reserved for system 6 06 - 3E4H No-coprocessor trap 7 07 - 3E0H 000FFFE0H - Coprocessor error trap 8 08 - 3DCH 000FFFDCH - INTE instruction 9 09 - 3D8H 000FFFD8H - Instruction break exception 10 0A - 3D4H 000FFFD4H - 000FFFD0H - Operand break trap 11 0B - 3D0H Step trace trap 12 0C - 3CCH 000FFFCCH - NMI request (tool) 13 0D - 3C8H 000FFFC8H - Undefined instruction exception 14 0E 000FFFC4H - 15 0F 15(FH), fixed 3C4H NMI request 3C0H 000FFFC0H - 000FFFBCH 6 External Interrupt 0 16 10 ICR00 3BCH External Interrupt 1 17 11 ICR01 3B8H 000FFFB8H 7 000FFFB4H 11 External Interrupt 2 18 12 ICR02 3B4H External Interrupt 3 19 13 ICR03 3B0H 000FFFB0H - External interrupt 4 20 14 ICR04 3ACH 000FFFACH - External interrupt 5 21 15 ICR05 3A8H 000FFFA8H - External interrupt 6 22 16 ICR06 3A4H 000FFFA4H - 000FFFA0H - External interrupt 7 23 17 ICR07 3A0H Reload Timer 0 24 18 ICR08 39CH 000FFF9CH 8 Reload Timer 1 25 19 ICR09 398H 000FFF98H 9 Reload Timer 2 26 1A ICR10 394H 000FFF94H 10 UART0 (reception completed) 27 1B ICR11 390H 000FFF90H 0 000FFF8CH 1 UART1 (reception completed) 28 1C ICR12 38CH UART2 (reception completed) 29 1D ICR13 388H 000FFF88H 2 UART0 (transmission completed) 30 1E ICR14 384H 000FFF84H 3 UART1 (transmission completed) 31 1F ICR15 380H 000FFF80H 4 UART2 (transmission completed) 32 20 ICR16 37CH 000FFF7CH 5 - DMAC0 (end or error) 33 21 ICR17 378H 000FFF78H DMAC1 (end or error) 34 22 ICR18 374H 000FFF74H - ICR19 370H 000FFF70H - DMAC2 (end or error) 594 35 23 APPENDIX B Interrupt Vector Table B-1 Interrupt Vector Table (2 / 3) Interrupt source DMAC3 (end or error) Interrupt number Decimal Hexadecimal 36 24 Interrupt level Offset TBR default address RN ICR20 36CH 000FFF6CH - DMAC4 (end or error) 37 25 ICR21 368H 000FFF68H - A/D 38 26 ICR22 364H 000FFF64H 15 39 27 ICR23 360H 000FFF60H - 40 28 ICR24 35CH 000FFF5CH - I2C UART4 (reception completed)*1 *1 41 29 ICR25 358H 000FFF58H 12 42 2A ICR26 354H 000FFF54H 13 SI07 43 2B ICR27 350H 000FFF50H 14 UART3 (reception completed) 44 2C ICR28 34CH 000FFF4CH - 000FFF48H - 000FFF44H - SI05 SI06 UART3 (transmission completed) Reload timer 3/main clock oscillation stabilization wait timer Timebase timer overflow External interrupts 8 to 15 Watch counter *1 U/D counter 0 *1 45 2D ICR29 348H 46 2E ICR30 344H 47 2F ICR31 340H 000FFF40H - 48 30 ICR32 33CH 000FFF3CH - 49 31 ICR33 338H 000FFF38H - 50 32 ICR34 334H 000FFF34H - 51 33 ICR35 330H 000FFF30H - 52 34 ICR36 32CH 000FFF2CH - PPG2/3 53 35 ICR37 328H 000FFF28H - PPG4/5 54 36 ICR38 324H 000FFF24H - 000FFF20H - U/D counter 1 PPG0/1 16-bit free-running timer 55 37 ICR39 320H ICU0 (fetch) 56 38 ICR40 31CH 000FFF1CH - ICU1 (fetch)/UART4 (transmission completed) *2 ICU2/3 (fetch) 57 39 ICR41 318H 000FFF18H - 58 3A ICR42 314H 000FFF14H - OCU0/1 (match) 59 3B ICR43 310H 000FFF10H - 000FFF0CH - OCU2/3 (match) 60 3C ICR44 30CH OCU4/5 (match) *1 61 3D ICR45 308H 000FFF08H - 000FFF04H - *1 OCU6/7 (match) Delayed interrupt source bit 62 3E ICR46 304H 63 3F ICR47 300H 000FFF00H - 000FFEFCH - Reserved for system (used by REALOS) 64 40 - 2FCH Reserved for system (used by REALOS) 65 41 - 2F8H 000FFEF8H - Reserved for system 66 42 - 2F4H 000FFEF4H - Reserved for system 67 43 - 2F0H 000FFEF0H - Reserved for system 68 44 - 2ECH 000FFEECH - 000FFEE8H - Reserved for system 69 45 - 2E8H Reserved for system 70 46 - 2E4H 000FFEE4H - Reserved for system 71 47 - 2E0H 000FFEE0H - Reserved for system 72 48 - 2DCH 000FFEDCH - Reserved for system 73 49 - 2D8H 000FFED8H - 000FFED4H - Reserved for system 74 4A - 2D4H Reserved for system 75 4B - 2D0H 000FFED0H - 000FFECCH - Reserved for system 76 4C - 2CCH Reserved for system 77 4D - 2C8H 000FFEC8H - Reserved for system 78 4E - 2C4H 000FFEC4H - 595 APPENDIX Table B-1 Interrupt Vector Table (3 / 3) Interrupt source Interrupt number Interrupt level Offset TBR default address RN Decimal Hexadecimal Reserved for system 79 4F - 2C0H 000FFEC0H - Used in INT instruction 80 to 255 50 to FF - 2BCH to 000H 000FFEBCH to 000FFC00H - *1: The MB91F353A/351A/352A/353A do not have this interrupt source. *2: The MB91F353A/351A/352A/353A do not have UART4 (transmission completed). 596 APPENDIX C Pin States in Each CPU State APPENDIX C Pin States in Each CPU State Table C-1 explains the terms used in the pin state lists. Table C-2 and Table C-3 list the pin states in each CPU state. ■ Explanation of Terms Used in the Pin State Lists Table C-1 explains the terms used for pin states. Table C-1 Explanation of Terms Used in the Pin State Lists Term Explanation Input enabled The input function can be used. Input always "0" External input is blocked by the input gate immediately after the pin and "0" is propagated internally. Hi-Z output The pin-driving transistor is set to the drive-disabled state and the pin is set to high impedance. Output maintained The output state immediately before this mode is set continues as the output state. That is, if an output internal peripheral is operating, output is performed based on the internal peripheral. If output using a port is being performed, that type of output is maintained. Previous state maintained For output, the output state immediately before this mode is set continues as the output state. For input, the previous input state is maintained. 597 APPENDIX ■ Pin States in Each CPU State Table C-2 Pin States in External Bus Mode (1 / 3) At initialization (INIT) Stop mode, watch mode Initial value PIN No. 1 to 8 Port name P20 to P27 Spec-ifiedfunction name D16 to D23 Function name External ROM mode vector (MD2 to 0 = 001) Internal ROM mode vector (MD2 to 0 = 000) Hi-Z output/ input enabled - D24 to D31 D24 to D31 19 to 26 - A00 to A07 A00 to A07 Hi-Z output Same as at left Same as at left A08 to A15 A08 to A15 37 to 44 P60 to P67 A16 to A23 A16 to A23 P: Previous state maintained F: Address output WR1 P: Previous state maintained F (WR1): "H" output F (IN3): Previous state maintained WR1/IN3 FF output "H" output 168 - WR0 WR0 167 - RD RD 165 P82 P81 P82 P: Previous state maintained F (BRQ): Input disabled F (IN2): Previous state maintained BGRNT/IN1 P81 P: Previous state maintained F (BGRNT): "H" output F (IN1): Previous state maintained BRQ/IN2 Hi-Z output/ input enabled P80 158 to 161 PA0 to PA3 CS0 to CS3 CS0 to CS3 "H" output P: Previous state maintained F: CS output SYSCLK When asserted: "L" output When negated: CLK output P: Previous state maintained F: SYSCLK output 598 Previous state maintained "L" output P: Previous state maintained F: SREN = 0: H output SREN = 1: Hi-Z output RDY/IN0 SYSCLK BRQ input P: Previous state maintained F: RDY input P80 P90 "H" output *3 Hi-Z output/ input always "0" P: Previous state maintained F (RDY): RDY input F (IN0): Previous state maintained 164 170 P: Previous state maintained F: Hi-Z output P: Previous state maintained F: "H" output *3 Previous state maintained Hi-Z output/ input enabled 166 P: Previous state maintained F: Hi-Z output Same as at left Address output - P85 HIZ=1 Output maintained or Hi-Z 27 to 34 169 Bus open (BGRNT) HIZ=0 P: Previous state maintained F: Output maintained or Hi-Z P20 to P27 9 to 16 Sleep mode, subclock sleep mode P: Previous state maintained F: "H" or "L" output P: Previous state maintained F: CLK output Remarks APPENDIX C Pin States in Each CPU State Table C-2 Pin States in External Bus Mode (2 / 3) At initialization (INIT) Stop mode, watch mode Initial value PIN No. Port name Spec-ifiedfunction name Function name External ROM mode vector (MD2 to 0 = 001) Internal ROM mode vector (MD2 to 0 = 000) Sleep mode, subclock sleep mode Bus open (BGRNT) HIZ=0 HIZ=1 Previous state maintained Previous state maintained Previous state maintained P92 P: Previous state maintained F: "H" output P: Previous state maintained F: "H" output P: Previous state maintained F: CLK output *3 - P93 Previous state maintained Previous state maintained Previous state maintained P94 AS P94 P: Previous state maintained F: LBAX output 150 PB0 DREQ0 PB0 151 PB1 DACK0 PB1 152 PB2 DEOP0/ DSTP0 PB2 153 PB3 DREQ1 PB3 154 PB4 DACK1 PB4 155 PB5 DEOP1/ DSTP1 PB5 156 PB6 IOWR PB6 157 PB7 IORD PB7 147 PC0 DREQ2 PC0 148 PC1 DACK2 PC1 149 PC2 DEOP2/ DSTP2 PC2 171 P91 - P91 172 P92 MCLK 173 P93 174 PG0 SI4 PG0 129 PG1 SO4 PG1 130 PG2 SCK4 PG2 131 PG3 SI5 PG3 132 PG4 SO5 PG4 133 PG5 SCK5 PG5 122 PH0 SI2 PH0 123 PH1 SO2 PH1 124 PH2 SCK2 PH2 125 PH3 SI3 PH3 126 PH4 SO3 PH4 127 PH5 SCK3 PH5 P: Previous state maintained F: "H" output *3 Hi-Z output/ input always "0" Hi-Z output/input enabled Previous state maintained 128 Remarks Previous state maintained Previous state maintained 599 APPENDIX Table C-2 Pin States in External Bus Mode (3 / 3) At initialization (INIT) Stop mode, watch mode Initial value PIN No. Port name Spec-ifiedfunction name Function name 116 PI0 SI0 PI0 117 PI1 SO0 PI1 118 PI2 SCK0 PI2 119 PI3 SI1 PI3 120 PI4 SO1 PI4 121 PI5 SCK1 PI5 106 to 113 PJ0 to PJ7 INT8 to INT15 *1 98 to 103 PK0 to PK7 INT0 to INT5 INT6/ FRCK INT7/ATG External ROM mode vector (MD2 to 0 = 001) Internal ROM mode vector (MD2 to 0 = 000) Sleep mode, subclock sleep mode Bus open (BGRNT) HIZ=0 HIZ=1 Previous state maintained Hi-Z output/ input always "0" PJ0 to PJ7 P: Previous state maintained F: Input enabled P: Hi-Z output F: Input enabled PK0 to PK7 P: Previous state maintained F: Input enabled P: Hi-Z output F: Input enabled *1 94 PL0 SDA PL0 95 PL1 SCL PL1 87 PM0 SI6/AIN0/ TRG0 PM0 88 PM1 SO6/BIN0/ TRG1 PM1 89 PM2 SCK6/ PM2 ZIN0/TRG2 90 PM3 SI7/AIN1/ TRG3 PM3 PM4 91 PM4 SO7/BIN1/ TRG4 92 PM5 SCK7/ PM5 ZIN1/TRG5 81 to 86 PN0 to PN5 PPG0 to PPG5 71 to 78 PO0 to PO7 OC0 to OC7 PO0 to PO7 67 to 70 PP0 to PP3 TOT0 to TOT3 PP0 to PP3 50 to 61 - AN0 to AN11 AN0 to AN11 47 to 49 - DA0 to DA2 DA0 to DA2 Remarks Previous state maintained Hi-Z output/input enabled Previous state maintained Previous state maintained Hi-Z output/ input always "0" Input disabled Input disabled "L" level output "L" level output PN0 to PN5 Input disabled "L" level output Previous state maintained Previous state maintained P: General-purpose port selected, F: Specified function selected *1: The input enabled state for INT0 to INT15 means that input is enabled during Hi-Z output state. This pin can be used to return from the stop state. *2: Output is undefined immediately after power-on. *3: When SREN = "1" is set for all CSs, output becomes Hi-Z. 600 APPENDIX C Pin States in Each CPU State Table C-3 Pin States in Single-Chip Mode (1 / 2) At initialization (INIT) Pin No. Port name Specified-function name Initial value Function name 1 to 8 P20 to P27 - P20 to P27 9 to 16 P30 to P37 - P30 to P37 19 to 26 P40 to P47 - P40 to P47 27 to 34 P50 to P57 - P50 to P57 37 to 44 P60 to P67 - P60 to P67 164 P80 IN0 165 P81 IN1 166 P82 IN2 167 to 168 P83 to P84 - 169 P85 IN3 170 to 174 P90 to P94 - P90 to P94 158 to 161 PA0 to PA3 - PA0 to PA3 150 to 157 PB0 to PB7 - PB0 to PB7 147 to 149 PC0 to PC2 - PC0 to PC2 128 PG0 SI4 PG0 129 PG1 SO4 PG1 130 PG2 SCK4 PG2 131 PG3 SI5 PG3 132 PG4 SO5 PG4 133 PG5 SCK5 PG5 122 PH0 SI2 PH0 123 PH1 SO2 PH1 124 PH2 SCK2 PH2 125 PH3 SI3 PH3 126 PH4 SO3 PH4 127 PH5 SCK3 PH5 116 PI0 SI0 PI0 117 PI1 SO0 PI1 118 PI2 SCK0 PI2 119 PI3 SI1 PI3 Internal ROM mode vector (MD2 to 0 = 000) Stop mode, watch mode Sleep mode, subclock sleep mode Re-marks HIZ=0 HIZ=1 P80 to P85 Hi-Z output/input Previous state enabled maintained Previous state maintained Hi-Z output/ input always "0" 601 APPENDIX Table C-3 Pin States in Single-Chip Mode (2 / 2) At initialization (INIT) Pin No. Port name Specified-function name Initial value Function name 120 PI4 SO1 PI4 121 PI5 SCK1 PI5 106 to 113 PJ0 to PJ7 98 to 105 PK0 to PK7 INT8 to INT15 * INT0 to INT5 INT6/FRCK INT7/ATG Internal ROM mode vector (MD2 to 0 = 000) Stop mode, watch mode Sleep mode, subclock sleep mode Re-marks HIZ=0 Previous state maintained HIZ=1 Hi-Z output/ input always "0" PJ0 to PJ7 P: Previous state P: Hi-Z output maintained F: Input F: Input enabled enabled PK0 to PK7 P: Previous state P: Hi-Z output maintained F: Input F: Input enabled enabled * 94 PL0 SDA PL0 95 PL1 SCL PL1 87 PM0 SI6/AIN0/TRG0 PM0 88 PM1 SO6/BIN0/ TRG1 PM1 89 PM2 SCK6/ZIN0/ TRG2 PM2 90 PM3 SI7/AIN1/TRG3 PM3 91 PM4 SO7/BIN1/ TRG4 PM4 92 PM5 SCK7/ZIN1/ TRG5 PM5 81 to 86 PN0 to PN5 PPG0 to PPG5 PN0 to PN5 71 to 78 PO0 to PO7 OC0 to OC7 PO0 to PO7 67 to 70 PP0 to PP3 TOT0 to TOT3 PP0 to PP3 50 to 61 - AN0 to AN11 AN0 to AN11 47 to 49 - DA0 to DA2 DA0 to DA2 Hi-Z output/input Previous state enabled maintained Previous state maintained Hi-Z output/ input always "0" Input disabled Input disabled Input disabled "L" level output "L" level output "L" level output P: General-purpose port selected, F: Specified function selected * : The input enabled state for INT0 to INT15 means that input is enabled during output Hi-Z state. This pin can be used to return from the stop state. 602 APPENDIX D Instruction Lists APPENDIX D Instruction Lists Table D-1 explains the addressing mode symbols. Figure D-1 shows the instruction format. Table D-2 to Table D-21 list the FR family instructions by instruction type. ■ How to Read the Instruction Lists Mnemonic ADD *ADD , , 1. Type OP CYCLE NZVC Operation Remarks Rj, Rj #s5, Rj A C , , AG A4 , , 1 1 , , CCCC CCCC , , Ri + Rj → Rj Ri + s5 → Ri , , - 2. 3. 4. 5. 6. 7. 1.Instruction name. • An asterisk (*) indicates an extended instruction that is not contained in the CPU specifications and is obtained by extension of or addition to the assembler. 2.Symbols indicating addressing modes that can be specified for the operand. • For the meaning of symbols, see "Addressing Mode Symbols". 3.Instruction format. 4.Instruction code in hexadecimal notation. 5.Number of machine cycles. The minimum for a, b, c, and d is 1 cycle. • a: Memory access cycle that may be extended by the Ready function., b: Memory access cycle that may be extended by the Ready function. However, the cycle is interlocked if a direct instruction references a register intended for an LD operation, increasing the number of execution cycles by 1., c: Interlocked if the direct instruction is an instruction that reads or writes to R15, SSP, or USP, or an instruction in instruction format A. The number of execution cycles increases by 1 or 2., d: Interlocked if the direct instruction references MDH/MDL. The number of execution cycles increases to 2. 6.Indicates a flag change. • Flag change C: Change -: No change 0: Clear 1: Set • Flag meaning N: Negative flag Z: Zero flag V: Overflow flag C: Carry flag 7.Instruction operation. 603 APPENDIX ■ Addressing Mode Symbols Table D-1 explains the addressing mode symbols. Table D-1 Explanation of Addressing Mode Symbols Symbol Ri Rj R13 Ps Rs Cri CRj #i8 #i20 #i32 #s5 #s10 #u4 #u5 #u8 #u10 @dir8 @dir9 @dir10 label9 label12 label20 label32 @Ri @Rj @(R13,Rj) @(R14,disp10) @(R14,disp9) @(R14,disp8) @(R15,udisp6) @Ri+ @R13+ @SP+ @-SP (reglist) 604 Meaning Register direct (R0 to R15, AC, FP, SP) Register direct (R0 to R15, AC, FP, SP) Register direct (R13, AC) Register direct (program status register) Register direct (TBR, RP, SSP, USP, MDH, MDL) Register direct (CR0 to CR15) Register direct (CR0 to CR15) Unsigned 8-bit immediate (-128 to 255) Note: -128 to -1 is handled as 128 to 255. Unsigned 20-bit immediate (-0X80000 to 0XFFFFF) Note: -0X7FFFF to -1 is handled as 0X7FFFF to 0XFFFFF. Unsigned 32-bit immediate (-0X80000000 to 0XFFFFFFFF) Note: -0X80000000 to -1 is handled as 0X80000000 to 0XFFFFFFFF. Signed 5-bit immediate (-16 to 15) Signed 10-bit immediate (-512 to 508, multiples of 4 only) Unsigned 4-bit immediate (0 to 15) Unsigned 5-bit immediate (0 to 31) Unsigned 8-bit immediate (0 to 255) Unsigned 10-bit immediate (0 to 1020, multiples of 4 only) Unsigned 8-bit direct address (0 to 0XFF) Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only) Unsigned 10-bit direct address (0 to 0X3FC, multiples of 4 only) Signed 9-bit branch address (-0X100 to 0XFC, multiples of 2 only) Signed 12-bit branch address (-0X800 to 0X7FC, multiples of 2 only) Signed 20-bit branch address (-0X80000 to 0X7FFFF) Signed 32-bit branch address (-0X80000000 to 0X7FFFFFFF) Register indirect (R0 to R15, AC, FP, SP) Register indirect (R0 to R15, AC, FP, SP) Register relative indirect (RjR0 to R15, AC, FP, SP) Register relative indirect (disp10: -0X200 to 0X1FC, multiples of 4 only) Register relative indirect (disp9: -0X100 to 0XFE multiples of 2 only) Register relative indirect (disp8: -0X80 to 0X7F) Register relative indirect (udisp6: 0 to 60, multiples of 4 only) Register indirect with post-increment (R0 to R15, AC, FP, SP) Register indirect with post-increment (R13, AC) Stack pop Stack push Register list APPENDIX D Instruction Lists ■ Instruction Format Figure D-1 shows the instruction format. Figure D-1 Instruction Format MSB A B LSB 16 bit OP Rj Ri 8 4 4 OP i8/08 Ri 4 8 4 C OP u4/m4 Ri 8 4 4 ADD, ADDN, CMP, LSL, LSR, and ASR instructions only *C' OP s5/u5 Ri 7 5 4 u8/rel8/dir/reglist D OP E OP SUB-OP Ri 8 4 4 F OP rel11 5 11 605 APPENDIX Table D-2 Addition and Subtraction Mnemonic Type OP CYCLE NZVC Operation ADD Rj, Ri *ADD #s5, Ri A C’ A6 A4 1 1 CCCC CCCC Ri + Rj → Ri Ri + s5 → Ri ADD #u4, Ri ADD2 #u4, Ris ADDN Rj, Ri ADDN Rj, Ri *ADDN #s5, Ri C C A A C’ A4 A5 A7 A2 A0 1 1 1 1 1 CCCC CCCC CCCC ------- Ri + extu(i4) → Ri Ri + extu(i4) → Ri Ri + Rj + c → Ri Ri + Rj → Ri Ri + s5 → Ri ADDN #u4, Ri ADDN2 #u4, Ri SUB Rj, Ri SUBC Rj, Ri SUBN Rj, Ri C C A A A A0 A1 AC AD AE 1 1 1 1 1 ------CCCC CCCC ---- Ri + extu(i4) → Ri Ri + extu(i4) → Ri Ri - Rj → Ri Ri - Rj - c → Ri Ri - Rj → Ri Remarks The assembler treats the highestorder bit as the sign. Zero extension Minus extension Addition with carry The assembler treats the highestorder bit as the sign. Zero extension Minus extension Addition with carry Table D-3 Comparison Type OP CYCLE NZVC CMP Rj, Ri *CMP #s5, Ri Mnemonic A C’ AA A8 1 1 CCCC CCCC Ri - Rj Ri - s5 Operation CMP #u4, Ri CMP2 #u4, Ri C C A8 A9 1 1 CCCC CCCC Ri - extu(i4) Ri - extu(i4) Remarks The assembler treats the highestorder bit as the sign. Zero extension Minus extension Table D-4 Logic Operations Mnemonic AND Rj, Ri AND Rj, @Ri ANDH Rj, @Ri ANDB Rj, @Ri OR Rj, Ri OR Rj, @Ri ORH Rj, @Ri ORB Rj, @Ri EOR Rj, Ri EOR Rj, @Ri EORH Rj, @Ri EORB Rj, @Ri 606 Type OP CYCLE NZVC A A A A A A A A A A A A 82 84 85 86 92 94 95 96 9A 9C 9D 9E 1 1+2a 1+2a 1+2a 1 1+2a 1+2a 1+2a 1 1+2a 1+2a 1+2a CC-CC-CC-CC-CC-CC-CC-CC-CC-CC-CC-CC-- Operation Ri &= Rj (Ri) &= Rj (Ri) &= Rj (Ri) &= Rj Ri | = Rj (Ri) | = Rj (Ri) | = Rj (Ri) | = Rj Ri ^ = Rj (Ri) ^ = Rj (Ri) ^ = Rj (Ri) ^ = Rj Remarks Word Word Halfword Byte Word Word Halfword Byte Word Word Halfword Byte APPENDIX D Instruction Lists Table D-5 Bit Manipulation Mnemonic Type OP CYCLE NZVC Operation BANDL #u4, @Ri C 80 1+2a ---- (Ri)&=(0xF0+u4) BANDH #u4, @Ri C 81 1+2a ---- (Ri)&=((u4<<4)+0x0F) ---- (Ri)&=u8 *BAND #u8, @Ri*1 BORL #u4, @Ri C 90 1+2a ---- (Ri) | = u4 BORH #u4, @Ri C 91 1+2a ---- (Ri) | = (u4<<4) ---- (Ri) | = u8 *BOR #u8, @Ri*2 BEORL #u4, @Ri C 98 1+2a ---- (Ri) ^ = u4 BEORH #u4, @Ri C 99 1+2a ---- (Ri) ^ = (u4<<4) ---- (Ri) ^ = u8 2+a 0C-- (Ri) & u4 *BEOR #u8, @Ri*3 BTSTL #u4, @Ri C 88 Remarks Low-order 4 bits are manipulated. High-order 4 bits are manipulated. Low-order 4 bits are manipulated. High-order 4 bits are manipulated. Low-order 4 bits are manipulated. High-order 4 bits are manipulated. Low-order 4 bits are manipulated. BTSTH #u4, @Ri C 89 2+a CC-(Ri) & (u4<<4) High-order 4 bits are manipulated. *1: The assembler generates BANDL if the bit is set at u8&0x0F, and BANDH if the bit is set at u8&0xF0. In some cases, both BANDL and BANDH may be generated. *2: The assembler generates BORL if the bit is set at u8&0x0F, and BORH if the bit is set at u8&0xF0. In some cases, both BORL and BORH are generated. *3: The assembler generates BEORL if the bit is set at u8&0x0F, and BEORH if the bit is set at u8&0xF0. In some cases, both BEORL and BEORH are generated. Table D-6 Multiplication and Division Mnemonic MUL Rj,Ri MULU Rj,Ri MULH Rj,Ri MULUH Rj,Ri DIV0S Ri DIV0U Ri DIV1 Ri DIV2 Ri DIV3 DIV4S Type OP CYCLE NZVC A A A A E E E E E E AF AB BF BB 97-4 97-5 97-6 97-7 9F-6 9F-7 5 5 3 3 1 1 d 1 1 1 36 CCCCCCCC-CC--------C-C -C-C -------C-C Operation Ri * Rj → MDH,MDL Ri * Rj → MDH,MDL Ri * Rj → MDL Ri * Rj → MDL Remarks 32bit*32bit=64bit No sign 16bit*16bit=32bit No sign Step operation 32bit/32bit=32bit MDL / Ri → MDL, MDL % Ri → MDH -C-C MDL / Ri → MDL, *DIVU Ri *2 MDL % Ri → MDH *1: DIV0S, DIV1 x 32, DIV2, DIV3, or DIV4S is generated. The instruction code length becomes 72 bytes. *2: DIV0U or DIV1 x 32 is generated. The instruction code length becomes 66 bytes. *DIV Ri *1 607 APPENDIX Table D-7 Shift Mnemonic Type OP CYCLE NZVC Operation A C’ C C A C’ C C A C’ C C B6 B4 B4 B5 B2 B0 B0 B1 BA B8 B8 B9 1 1 1 1 1 1 1 1 1 1 1 1 CC-C CC-C CC-C CC-C CC-C CC-C CC-C CC-C CC-C CC-C CC-C CC-C Ri << Rj → Ri Ri << u5 → Ri Ri << u4 → Ri Ri <<(u4+16) → Ri Ri >> Rj → Ri Ri >> u5 → Ri Ri >> u4 → Ri Ri >>(u4+16) → Ri Ri >> Rj → Ri Ri >> u5 → Ri Ri >> u4 → Ri Ri >>(u4+16) → Ri LSL Rj, Ri *LSL #u5, Ri (u5:0 to 31) LSL #u4, Ri LSL2 #u4, Ri LSR Rj, Ri *LSR #u5, Ri (u5:0 to 31) LSR #u4, Ri LSR2 #u4, Ri ASR Rj, Ri *ASR #u5, Ri (u5:0 to 31) ASR #u4, Ri ASR2 #u4, Ri Remarks Logical shift Logical shift Arithmetic shift Table D-8 Immediate Value Set/16-Bit/32-Bit Immediate Value Transfer Type OP CYCLE NZVC LDI:32 #i32, Ri LDI:20 #i20, Ri Mnemonic E C 9F-8 9B 3 2 ------- i32 → Ri i20 → Ri Operation LDI:8 #i8, Ri B C0 1 ---- i8 → Ri Remarks High-order 12 bits are zero-extended. High-order 24 bits are zero-extended. {i8 | i20 | i32} → Ri *LDI # {i8 | i20 | i32} ,Ri * * : If the immediate data is represented as absolute values, the assembler selects automatically from i8, i20, and i32. If immediate data contains a relative value or external reference symbol, i32 is selected. Table D-9 Memory Load Mnemonic LD @Rj, Ri LD @(R13,Rj), Ri LD @(R14,disp10), Ri LD @(R15,udisp6), Ri LD @R15+, Ri LD @R15+, Rs Type OP CYCLE NZVC A A B C E E 04 00 20 03 07-0 07-8 b b b b b b ------------------- Operation (Rj) → Ri (R13+Rj) → Ri (R14+disp10) → Ri (R15+udisp6) → Ri (R15) → Ri,R15+=4 (R15) → Rs, R15+=4 Remarks Rs: Special register * LD @R15+, PS E 07-9 1+a+b CCCC (R15) → PS, R15+=4 Zero extension LDUH @Rj, Ri A 05 b ---(Rj) →Ri Zero extension LDUH @(R13,Rj), Ri A 01 b ---(R13+Rj) →Ri Zero extension LDUH @(R14,disp9), Ri B 40 b ---(R14+disp9) →Ri Zero extension LDUB @Rj, Ri A 06 b ---(Rj) →Ri Zero extension LDUB @(R13,Rj), Ri A 02 b ---(R13+Rj) →Ri Zero extension LDUB @(R14,disp8), Ri B 6 b ---(R14+disp8) →Ri * : In the o8 and o4 fields of the hardware specifications, the assembler calculates values and sets them as shown below: disp10/4 → o8, disp9/2 → o8, disp8 → o8; disp10, disp9, and disp8 have a sign. udisp6/4 → o4; udisp6 has no sign. 608 APPENDIX D Instruction Lists Table D-10 Memory Store Mnemonic STRi, @Rj STRi, @(R13,Rj) STRi, @(R14,disp10) STRi, @(R15,udisp6) STRi, @-R15 STRs, @-R15 Type OP CYCLE NZVC A A B C E E 14 10 3 13 17-0 17-8 a a a a a a ------------------- Operation Remarks Ri → (Rj) Ri → (R13+Rj) Ri → (R14+disp10) Ri → (R15+udisp6) R15-=4,Ri → (R15) R15-=4, Rs → (R15) Word Word Word Rs: Special register * STPS, @-R15 E 17-9 a ---R15-=4, PS → (R15) STHRi, @Rj A 15 a ---Halfword Ri → (Rj) Halfword STHRi, @(R13,Rj) A 11 a ---Ri → (R13+Rj) STHRi, @(R14,disp9) B 5 a ---Halfword Ri → (R14+disp9) Byte STBRi, @Rj A 16 a ---Ri → (Rj) Byte STBRi, @(R13,Rj) A 12 a ---Ri → (R13+Rj) STBRi, @(R14,disp8) B 7 a ---Byte Ri → (R14+disp8) * : In the o8 and o4 fields of the hardware specifications, the assembler calculates values and sets them as shown below: disp10/4 → o8, disp9/2 → o8, disp8 → o8; disp10, disp9, and disp8 have a sign. udisp6/4 → o4; udisp6 has no sign. Table D-11 Register-to-Register Transfer Mnemonic MOVRj, Ri Type OP CYCLE NZVC A 8B 1 ---- Rj → Ri ---------CCCC Rs → Ri Ri → Rs PS → Ri Ri → PS MOVRs, Ri A B7 1 MOVRi, Rs A B3 1 MOVPS, Ri E 17-1 1 MOVRi, PS E 07-1 c * : Special register Rs: TBR, RP, USP, SSP, MDH, and MDL Operation Remarks Transfer between general-purpose registers Rs: Special register Rs: Special register * 609 APPENDIX Table D-12 Normal Branch (No Delay) Mnemonic Type OP CYCLE NZVC Operation JMP @Ri E 97-0 2 ---- Ri → PC CALL label12 F D0 2 ---- PC+2→RP , CALL @Ri E 97-1 2 ---- PC+2→RP ,Ri→PC 97-2 2 ---- RP → PC 1F 3+3a CCCC Remarks PC+2+(label12-PC-2)→PC RET INT #u8 D Return SSP-=4,PS → (SSP), SSP-=4,PC+2 → (SSP), 0→ I flag,0 → S flag, (TBR+0x3FC-u8x4) → PC INTE E 9F-3 SSP-=4,PS → (SSP), 3+3a For emulator SSP-=4,PC+2 → (SSP), 0 → S flag, (TBR+0x3D8) →PC RETI E 97-3 2+2a CCCC BRA label9 DD E0 2 ---- BNO label9 BEQ label9 D E1 E2 1 2/1 ------- BNE label9 BC label9 BNC label9 BN label9 BP label9 BV label9 BNV label9 BLT label9 BGE label9 BLE label9 BGT label9 BLS label9 BHI label9 DD DD DD DD DD D E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 ---------------------------------------- (R15) → PC,R15-=4, (R15) → PS,R15-=4 DD PC+2+(label9-PC-2) →PC No branch if(Z==1) then PC+2+(label9-PC-2) →PC ↑ s/Z==0 ↑ s/C==1 ↑ s/C==0 ↑ s/N==1 ↑ s/N==0 ↑ s/V==1 ↑ s/V==0 ↑ s/V xor N==1 ↑ s/V xor N==0 ↑ s/(V xor N) or Z==1 ↑ s/(V xor N) or Z==0 ↑ s/C or Z==1 ↑ s/C or Z==0 Notes: • "2/1" under CYCLE indicates 2 when branching occurs and 1 when branching does not occur. • In the rel11 and rel8 fields of the hardware specifications, the assembler calculates values and sets them as shown below: (label12-PC-2)/2 → rel11, (label9-PC-2)/2 → rel8; label12 and label9 have a sign. • To execute the RETI instruction, the S flag must be 0. 610 APPENDIX D Instruction Lists Table D-13 Delayed Branch Mnemonic JMP:D @Ri CALL:D label12 CALL:D @Ri RET:D BRA:D label9 BNO:D label9 BEQ:D label9 Type OP CYCLE NZVC Operation Remarks E FE 9F-0 D8 9F-1 1 1 1 ---------- Ri → PC PC+4→RP,PC+2+(label12-PC-2)→PC PC+4→RP,Ri→PC E D D D 9F-2 F0 F1 F2 1 1 1 1 ------------- RP → PC PC+2+(label9-PC-2) →PC No branch if(Z==1) then PC+2+(label9-PC-2) →PC ↑ s/Z==0 ↑ s/C==1 ↑ s/C==0 ↑ s/N==1 ↑ s/N==0 ↑ s/V==1 ↑ s/V==0 ↑ s/V xor N==1 ↑ s/V xor N==0 ↑ s/(V xor N) or Z==1 ↑ s/(V xor N) or Z==0 ↑ s/C or Z==1 ↑ s/C or Z==0 Return BNE:D label9 D F3 1 ---BC:D label9 D F4 1 ---BNC:D label9 D F5 1 ---BN:D label9 D F6 1 ---BP:D label9 D F7 1 ---BV:D label9 D F8 1 ---BNV:D label9 D F9 1 ---BLT:D label9 D FA 1 ---BGE:D label9 D FB 1 ---BLE:D label9 D FC 1 ---BGT:D label9 D FD 1 ---BLS:D label9 D FE 1 ---BHI:D label9 D FF 1 ---Notes: • In the rel11 and rel8 fields of the hardware specifications, the assembler calculates values and sets them as shown below: (label12-PC-2)/2 → rel11, (label9-PC-2)/2 → rel8; label12 and label9 have a sign. • A delayed branch always occurs after the next instruction (delay slot) is executed. • Instructions that can be placed in the delay slot are all 1-cycle, a-, b-, c-, and d-cycle instructions. Multicycle instructions cannot be placed in the delay slot. 611 APPENDIX Table D-14 Other Instructions Mnemonic NOP ANDCCR #u8 Type OP CYCLE NZVC E DD 9F-A 83 1 c ---CCCC ORCCR #u8 STILM #u8 ADDSP #s10 EXTSB Ri *1 EXTUB Ri Operation Remarks No change CCR and u8 → CCR CCR or u8 → CCR 93 c CCCC D 87 1 ---- D A3 1 ---- E 97-8 1 ---- Sign extension 8 → 32bit E 97-9 1 ---- Zero extension 8 → 32bit i8 → ILM R15 += s10 ILM immediate set ADD SP instruction EXTSH Ri E 97-A 1 ---- Sign extension 16 → 32bit EXTUH Ri E 97-B 1 ---- Zero extension 16 → 32bit LDM0 (reglist) D 8C ---- (R15) → reglist, R15 increment Load multi R0-R7 LDM1 (reglist) D 8D ---- (R15) → reglist, R15 increment Load multi R8-R15 ---- (R15) → reglist, R15 increment R15 decrement, reglist → (R15) R15 decrement, reglist → (R15) R15 decrement, reglist → (R15) Load multi R0-R15 *LDM (reglist)*2 STM0 (reglist) D 8E ---- STM1 (reglist) D 8F ------- *STM (reglist)*3 ENTER #u10 *4 D LEAVE E 0F 1+a ---- R14 → (R15 - 4), Store multi R0-R7 Store multi R8-R15 Store multi R0-R15 Entry processing of a function R15 - 4 → R14, R15 - u10 → R15 9F-9 b ---- R14 + 4 → R15, Exit processing of a function Ri → TEMP For semaphore management Byte data (R15 - 4) → R14 XCHB @Rj, Ri A 8A 2a ---- (Rj) → Ri TEMP → (Rj) *1: For s10, the assembler calculates s10/4 and then changes to s8 to set a value. s10 has a sign. *2: If any of R0 to R7 is specified in reglist, LDM0 is generated. If any of R8 to R15 is generated, LDM1 is generated. In some cases, both LDM0 and LDM1 are generated. *3: If any of R0 to R7 is specified in reglist, STM0 is generated. If any of R8 to R15 is generated, STM1 is generated. In some cases, both STM0 and STM1 are generated. *4: For u10, the assembler calculates u10/4 and then changes to u8 to set a value. u10 has a sign. Notes: • The number of execution cycles of LDM0(reglist) and LDM1(reglist) can be calculated as a×(n-1)+b+1 cycles if the number of specified registers is n. • The number of execution cycles of STM0(reglist) and STM1(reglist) can be calculated as a×n+1 cycles if the number of specified registers is n. 612 APPENDIX D Instruction Lists Table D-15 20-Bit Normal Branch Macro Instructions Mnemonic Operation Remarks Address of the next instruction → RP, Ri: Temporary register (See Reference 1) *BRA20 label20,Ri label20 → PC Ri: Temporary register (See Reference 2) *BEQ20 label20,Ri if(Z==1) then label20 → PC ↑ s/Z==0 ↑ s/C==1 ↑ s/C==0 ↑ s/N==1 ↑ s/N==0 ↑ s/V==1 ↑ s/V==0 ↑ s/V xor N==1 ↑ s/V xor N==0 ↑ s/(V xor N) or Z==1 ↑ s/(V xor N) or Z==0 ↑ s/C or Z==1 ↑ s/C or Z==0 Ri: Temporary register (See Reference 3) *CALL20 label20,Ri label20 → PC *BNE20 label20,Ri ↑ *BC20 label20,Ri ↑ *BNC20 label20,Ri ↑ *BN20 label20,Ri ↑ *BP20 label20,Ri ↑ *BV20 label20,Ri ↑ *BNV20 label20,Ri ↑ *BLT20 label20,Ri ↑ *BGE20 label20,Ri ↑ *BLE20 label20,Ri ↑ *BGT20 label20,Ri ↑ *BLS20 label20,Ri ↑ *BHI20 label20,Ri ↑ References : 1. CALL20 (1) If label20-PC-2 is between -0x800 and +0x7fe, create an instruction as shown below: CALL label12 (2) If label20-PC-2 is outside the range in (1) or contains an external reference symbol, create an instruction as shown below: LDI:20 #label20,Ri CALL @Ri 2. BRA20 (1) If label20-PC-2 is between -0x100 and +0xfe, create an instruction as shown below: BRA label9 (2) If label20-PC-2 is outside the range in (1) or contains an external reference symbol, create an instruction as shown below: LDI:20 #label20,Ri JMP @Ri 3. Bcc20 (1) If label20-PC-2 is between -0x100 and +0xfe, create an instruction as shown below: Bcc label9 (2) If label20-PC-2 is outside the range in (1) or contains an external reference symbol, create an instruction as shown below: Bxcc false xcc is the opposite condition of cc. LDI:20 #label20,Ri JMP @Ri false: 613 APPENDIX Table D-16 20-Bit Delayed Branch Macro Instructions Mnemonic *CALL20:D label20,Ri Operation Address of the next instruction → RP, label20 → PC label20 → PC if(Z==1) then label20 → PC ↑ s/Z==0 ↑ s/C==1 ↑ s/C==0 ↑ s/N==1 ↑ s/N==0 ↑ s/V==1 ↑ s/V==0 ↑ s/V xor N==1 ↑ s/V xor N==0 ↑ s/(V xor N) or Z==1 ↑ s/(V xor N) or Z==0 ↑ s/C or Z==1 ↑ s/C or Z==0 Remarks Ri: Temporary register (See Reference 1) *BRA20:D label20,Ri Ri: Temporary register (See Reference 2) Ri: Temporary register (See Reference 3) *BEQ20:D label20,Ri ↑ *BNE20:D label20,Ri *BC20:D label20,Ri ↑ *BNC20:D label20,Ri ↑ *BN20:D label20,Ri ↑ *BP20:D label20,Ri ↑ *BV20:D label20,Ri ↑ *BNV20:D label20,Ri ↑ *BLT20:D label20,Ri ↑ *BGE20:D label20,Ri ↑ *BLE20:D label20,Ri ↑ *BGT20:D label20,Ri ↑ *BLS20:D label20,Ri ↑ *BHI20:D label20,Ri ↑ References : 1. CALL20:D (1) If label20-PC-2 is between -0x800 and +0x7fe, create an instruction as shown below: CALL:D label12 (2) If label20-PC-2 is outside the range in (1) or contains an external reference symbol, create an instruction as shown below: LDI:20 #label20,Ri CALL:D @Ri 2. BRA20 (1) If label20-PC-2 is between -0x100 and +0xfe, create an instruction as shown below: BRA :D label9 (2) If label20-PC-2 is outside the range in (1) or contains an external reference symbol, create an instruction as shown below: LDI:20 #label20,Ri JMP:D @Ri 3. Bcc20:D (1) If label20-PC-2 is between -0x100 and +0xfe, create an instruction as shown below: Bcc:D label9 (2) If label20-PC-2 is outside the range in (1) or contains an external reference symbol, create an instruction as shown below: Bxcc false xcc is the opposite condition of cc. LDI:20 #label20,Ri JMP:D @Ri false: 614 APPENDIX D Instruction Lists Table D-17 32-Bit Normal Branch Macro Instructions Mnemonic *CALL32 label32,Ri Operation Address of the next instruction → RP, label20 → PC label32 → PC if(Z==1) then label20 → PC ↑ s/Z==0 ↑ s/C==1 ↑ s/C==0 ↑ s/N==1 ↑ s/N==0 ↑ s/V==1 ↑ s/V==0 ↑ s/V xor N==1 ↑ s/V xor N==0 ↑ s/(V xor N) or Z==1 ↑ s/(V xor N) or Z==0 ↑ s/C or Z==1 ↑ s/C or Z==0 Remarks Ri: Temporary register (See Reference 1) *BRA32 label32,Ri Ri: Temporary register (See Reference 2) Ri: Temporary register (See Reference 3) *BEQ32 label32,Ri ↑ *BNE32 label32,Ri ↑ *BC32 label32,Ri ↑ *BNC32 label32,Ri ↑ *BN32 label32,Ri ↑ *BP32 label32,Ri ↑ *BV32 label32,Ri ↑ *BNV32 label32,Ri ↑ *BLT32 label32,Ri ↑ *BGE32 label32,Ri ↑ *BLE32 label32,Ri ↑ *BGT32 label32,Ri ↑ *BLS32 label32,Ri ↑ *BHI32 label32,Ri References : 1. CALL32 (1) If label32-PC-2 is between -0x800 and +0x7fe, create an instruction as shown below: CALL label12 (2) If label32-PC-2 is outside the range in (1) or contains an external reference symbol, create an instruction as shown below: LDI:32 #label32,Ri CALL @Ri 2. BRA32 (1) If label32-PC-2 is between -0x100 and +0xfe, create an instruction as shown below: BRA label9 (2) If label32-PC-2 is outside the range in (1) or contains an external reference symbol, create an instruction as shown below: LDI:32 #label32,Ri JMP @Ri 3. Bcc32 (1) If label32-PC-2 is between -0x100 and +0xfe, create an instruction as shown below: Bcc label9 (2) If label32-PC-2 is outside the range in (1) or contains an external reference symbol, create an instruction as shown below: Bxcc false xcc is the opposite condition of cc. LDI:32 #label32,Ri JMP @Ri32 false: 615 APPENDIX Table D-18 32-Bit Delayed Branch Macro Instructions Mnemonic *CALL32:D label32,Ri Operation Address of the next instruction → RP, label20 → PC label32 → PC if(Z==1) then label20 → PC ↑s/Z==0 ↑s/C==1 ↑ s/C==0 ↑ s/N==1 ↑ s/N==0 ↑ s/V==1 ↑ s/V==0 ↑ s/V xor N==1 ↑ s/V xor N==0 ↑ s/(V xor N) or Z==1 ↑ s/(V xor N) or Z==0 ↑ s/C or Z==1 ↑ s/C or Z==0 Remarks Ri: Temporary register (See Reference 1) *BRA32:D label32,Ri Ri: Temporary register (See Reference 2) Ri: Temporary register (See Reference 3) *BEQ32:D label32,Ri ↑ *BNE32:D label32,Ri ↑ *BC32:D label32,Ri ↑ *BNC32:D label32,Ri *BN32:D label32,Ri ↑ ↑ *BP32:D label32,Ri ↑ *BV32:D label32,Ri ↑ *BNV32:D label32,Ri ↑ *BLT32:D label32,Ri ↑ *BGE32:D label32,Ri ↑ *BLE32:D label32,Ri ↑ *BGT32:D label32,Ri ↑ *BLS32:D label32,Ri *BHI32:D label32,Ri ↑ References : 1. CALL32:D (1) If label32-PC-2 is between -0x800 and +0x7fe, create an instruction as shown below: CALL:D label12 (2) If label32-PC-2 is outside the range in (1) or contains an external reference symbol, create an instruction as shown below: LDI:32 #label32,Ri CALL:D @Ri 2 BRA32:D 2. BRA32:D (1) If label32-PC-2 is between -0x100 and +0xfe, create an instruction as shown below: BRA:D label9 (2) If label32-PC-2 is outside the range in (1) or contains an external reference symbol, create an instruction as shown below: LDI:32 #label32,Ri JMP:D @Ri 3 Bcc32:D 3. Bcc32:D (1) If label32-PC-2 is between -0x100 and +0xfe, create an instruction as shown below: Bcc:D label9 (2) If label32-PC-2 is outside the range in (1) or contains an external reference symbol, create an instruction as shown below: Bxcc false xcc is the opposite condition of cc. LDI:32 #label32,Ri JMP:D @Ri32 false: 616 APPENDIX D Instruction Lists Table D-19 Direct Addressing Mnemonic Type OP CYCLE NZVC Operation DMOV @dir10, R13 D 08 b ---(dir10) → R13 DMOV R13, @dir10 D 18 a ---R13 → (dir10) DMOV @dir10, @R13+ D 0C 2a ---(dir10) → (R13),R13+=4 DMOV @R13+, @dir10 D 1C 2a ---(R13) → (dir10),R13+=4 DMOV @dir10, @-R15 D 0B 2a ---R15-=4,(R15) → (dir10) DMOV @R15+, @dir10 D 1B 2a ---(R15) → (dir10),R15+=4 DMOVH @dir9, R13 D 09 b ---(dir9) → R13 DMOVH R13, @dir9 D 19 a ---R13 → (dir9) DMOVH @dir9, @R13+ D 0D 2a ---(dir9) → (R13),R13+=2 DMOVH @R13+, @dir9 D 1D 2a ---(R13) → (dir9),R13+=2 DMOVB @dir8, R13 D 0A b ---(dir8) → R13 DMOVB R13, @dir8 D 1A a ---R13 → (dir8) DMOVB @dir8, @R13+ D 0E 2a ---(dir8) → (R13),R13++ DMOVB @R13+, @dir8 D 1E 2a ---(R13) → (dir8),R13++ Note: In the dir8, dir9, and dir10 fields, the assembler calculates values and sets them as shown below: dir8 → dir, dir9/2 → dir, dir10/4 → dir; dir8, dir9, and dir10 have no sign. Remarks Word Word Word Word Word Word Halfword Halfword Halfword Halfword Byte Byte Byte Byte Table D-20 Resource Instructions Type OP CYCLE NZVC LDRES @Ri+, #u4 Mnemonic C BC a ---- STRES #u4, @Ri+ C BD a ---- Operation (Ri) → u4 resource Ri+=4 u4 resource → (Ri) Ri+=4 Remarks u4: Channel number u4: Channel number Note: This instruction cannot be used for the MB91350A because it has no resource with a channel number. 617 APPENDIX Table D-21 Coprocessor Control Instructions Mnemonic COPOP #u4, #u8, CRj, Cri COPLD #u4, #u8, Rj, Cri COPST #u4, #u8, CRj, Ri COPSV #u4, #u8, CRj, Ri Type OP CYCLE NZVC E E E E 9F-C 9F-D 9F-E 9F-F 2+a 1+2a 1+2a 1+2a ------------- Operation Operation instruction Rj → CRi CRj → Ri CRj → Ri Remarks No error trap *: {CRi|CRj}:=CR0|CR1|CR2|CR3|CR4|CR5|CR6|CR7|CR8|CR9|CR10|CR11|CR12|CR13|CR14|CR15 u4:= Channel specified u8:= Channel specified Note: The MB91350A cannot use the coprocessor control instructions because it does not have a coprocessor. 618 INDEX INDEX The index follows on the next page. This is listed in alphabetic order. 619 INDEX Index Numerics 0 Detection 0 Detection ...................................................... 360 0 Detection Data Register (BSD0) ..................... 358 0 Detection Data Register 0 Detection Data Register (BSD0) ..................... 358 1 Detection 1 Detection ...................................................... 360 1 Detection Data Register (BSD1) ..................... 358 1 Detection Data Register 1 Detection Data Register (BSD1) ..................... 358 10-bit Slave Address Mask Register 10-bit Slave Address Mask Register (ITMK) ...... 458 10-bit Slave Address Register 10-bit Slave Address Register (ITBA) ................ 457 16-bit 32-bit/16-bit Bus Converter................................. 52 16-bit Free-running Timer Block Diagram of the 16-bit Free-running Timer ................................................. 279 Clearing of the Counter for the 16-bit Free-running Timer ................................................. 284 Overview of the 16-bit Free-running Timer......... 278 Timing of 16-bit Free-running Timer Counting .......................................................... 285 Timing of Clearing of the 16-bit Free-running Timer ................................................. 285 16-bit Free-running Timer Register 16-bit Free-running Timer Registers................... 279 16-bit Input Capture 16-bit Input Capture Operation .......................... 430 Input Timing for 16-bit Input Capture ................ 430 16-bit Output Compare Operation of the 16-bit Output Compare Module............................................... 437 Timing of 16-bit Output Compare Operation....... 438 16-bit Reload Register 16-bit Reload Register (TMRLR)....................... 291 16-bit Reload Timer Block Diagram of the 16-bit Reload Timer ......... 288 Overview of the 16-bit Reload Timer ................. 286 620 16-bit Reload Timer Register 16-bit Reload Timer Registers........................... 287 16-bit Timer Register 16-bit Timer Register (TMR) ............................ 291 2-Cycle Transfer 2-Cycle Transfer (External -> I/O) (TYP[3:0] = 0000B, AWR = 0008H, and IOWR = 00H) ..................................... 226 2-Cycle Transfer (I/O -> External) (TYP[3:0] = 0000B, AWR = 0008H, and IOWR = 00H) ..................................... 227 2-Cycle Transfer (The Timing is the Same for Internal RAM -> External I/O and RAM and for External I/O and RAM -> Internal RAM.) (TYP[3:0] = 0000B, AWR = 0008H, and IOWR = 00H) ..................................... 225 Flow of Data During 2-Cycle Transfer ............... 525 Step/Block Transfer 2-Cycle Transfer ................ 499 Step/Block Transfer 2-Cycle Transfer Fly-by Transfer ............................................. 500 32-bit 32-bit/16-bit Bus Converter ................................ 52 7-bit Slave Address Mask Register 7-bit Slave Address Mask Register (ISMK) ........ 461 7-bit Slave Address Register 7-bit Slave Address Register (ISBA).................. 460 8/16-bit Up/Down Counter Block Diagram of the 8/16-bit Up/Down Counters/Timers (ch0)......................... 250 Block Diagram of the 8/16-bit Up/Down Counters/Timers (ch1)......................... 251 Characteristics of the 8/16-bit Up/Down Counters/Timers ................................. 247 List of Registers of the 8/16-bit Up/Down Counters/Timers ................................. 248 Overview of the 8/16-bit Up/Down Counters/Timers ................................. 246 8-bit D/A Converter 8-bit D/A Converter Registers ........................... 380 Block Diagram of the 8-bit D/A Converter ......... 381 Features of the 8-bit D/A Converter ................... 380 INDEX A A/D Converter A/D Converter ..................................................... 4 A/D Converter Registers................................... 366 Block Diagram of the A/D Converter ................. 365 Features of the A/D Converter........................... 364 A/D Converter Register A/D Converter Registers................................... 366 Overview of the A/D Converter Registers .......... 364 AC Characteristic AC Characteristics of DMAC............................ 521 Access Address Access Address................................................ 504 Access Mode Access Mode ..................................................... 90 Accessing Accessing Data .................................................. 41 Accessing I/O Ports............................................ 35 Acknowledge Acknowledge................................................... 466 Acquiring the Bus Right Acquiring the Bus Right ................................... 229 ACR Configuration of Area Configuration Registers 0 to 7 (ACR0 to ACR7) ................................ 169 Activation Setting Procedure Activation Setting Procedure............................. 320 ADCS Bit Configuration of the Control Status Register (ADCS1)............................................ 367 Bit Configuration of the Control Status Register (ADCS2)............................................ 370 ADCT Bit Configuration of the Conversion Time Setting Register (ADCT) ................................ 373 Recommended ADCT Register Value ................ 374 Additional Information Additional Information ..................................... 295 Address Error Occurrence of an Address Error......................... 513 Address Register Address Register Specifications......................... 503 Address/Data Multiplex Access Normal Access and Address/Data Multiplex Access ............................................... 176 Addressing Mode Symbol Addressing Mode Symbols ............................... 604 ADT Overview of the Data Registers (ADTHx and ADTLx) ......................... 375 All Channels Enabling Operation for All Channels ................. 508 Another Transfer Request If Another Transfer Request Occurs During Block Transfer ..............................................521 Arbitrary Width Up/Down Counting with an Arbitrary Width when the Reload and Compare Functions are Started ................................................262 Arbitration Arbitration .......................................................466 Area Configuration Register Configuration of Area Configuration Registers 0 to 7 (ACR0 to ACR7).................................169 Area Select Register Configuration of ASR0 to ASR3 (Area Select Registers).........................168 Area Wait Register Configuration of AWR0 to AWR3 (Area Wait Registers)...........................175 Arithmetic Operation Arithmetic Operation ..........................................53 Arrays Manipulation of Arrays Other than Character-type Arrays Using Character String Operation Functions ..............................................39 ASR Configuration of ASR0 to ASR3 (Area Select Registers).........................168 Example of Setting ASRs and ASZ[3:0] .............186 Asynchronous Mode Asynchronous (Start-stop Synchronization) Mode..................................................400 ASZ Example of Setting ASRs and ASZ[3:0] .............186 Automatic Algorithm Automatic Algorithm Command Sequence .........548 Automatic Algorithm Execution Status ...............546 Overview of the Flash Memory Automatic Algorithm ...........................................547 Auto-Wait Timing Auto-Wait Timing (TYP[3:0]=0000B,AWR=2008H) ..........208 AWR Configuration of AWR0 to AWR3 (Area Wait Registers)...........................175 B Base Clock Division Setting Register Base Clock Division Setting Register 0 (DIVR0) .............................................125 Base Clock Division Setting Register 1 (DIVR1) .............................................126 Basic Block Diagram Basic Block Diagram of the I/O Port ..................232 621 INDEX Basic Condition Basic Conditions for Starting External Access Using Prefetch .............................................. 218 Basic Programming Model Basic Programming Model.................................. 55 Basic Timing Basic Timing (For Successive Accesses) (TYP[3:0]=0000B,AWR=0008H) .......... 205 Baud Rate Calculation of Baud Rate .................................. 275 Example of Setting Baud Rates and U-TIMER Reload Values................................................ 409 Big Endian Big Endian Data Format.................................... 190 Bus Width of Big Endian Data........................... 192 Bit Configuration Bit Configuration of Enable Interrupt Request Register (ENIRn) ................................ 345 Bit Configuration of External Level Register (ELVRn) .......................................................... 347 Bit Configuration of the Control Status Register (ADCS1) ............................................ 367 Bit Configuration of the Control Status Register (ADCS2) ............................................ 370 Bit Configuration of the Conversion Time Setting Register (ADCT)................................. 373 Bit Configuration of the External Interrupt Request Register (EIRRn)................................. 346 Bit Configuration of the Hold Request Cancellation Request Register (HRCL) .................... 331 Bit Configuration of the Interrupt Control Register (ICR) ................................................. 329 Bit Manipulation Logical Operation and Bit Manipulation ............... 54 Bit Ordering Bit Ordering....................................................... 64 Bit Search Module Bit Search Module.............................................. 34 Bit Search Module (Used by REALOS).................. 3 Bit Search Module Registers ............................. 357 Block Diagram of the Bit Search Module ........... 357 Overview of the Bit Search Module ................... 356 Block Diagram Basic Block Diagram of the I/O Port .................. 232 Block Diagram................................................. 474 Block Diagram of Clock Generation Controller .......................................................... 111 Block Diagram of Flash Memory....................... 535 Block Diagram of Peripheral Stop Control.......... 155 Block Diagram of the 16-bit Free-running Timer ................................................. 279 Block Diagram of the 16-bit Reload Timer ......... 288 Block Diagram of the 8/16-bit Up/Down Counters/Timers (ch0) ......................... 250 622 Block Diagram of the 8/16-bit Up/Down Counters/Timers (ch1)......................... 251 Block Diagram of the 8-bit D/A Converter ......... 381 Block Diagram of the A/D Converter................. 365 Block Diagram of the Bit Search Module ........... 357 Block Diagram of the Data Internal RAM/ Instruction Internal RAM Access Restriction Functions ........................................... 576 Block Diagram of the Delayed Interrupt Module ......................................................... 353 Block Diagram of the External Bus Interface ...... 164 Block Diagram of the External Interrupt and NMI Controller................................... 343 Block Diagram of the I2C Interface.................... 443 Block Diagram of the Interrupt Controller .......... 327 Block Diagram of the Main Clock Oscillation Stabilization Wait Timer...................... 149 Block Diagram of the Output Compare Module ......................................................... 433 Block Diagram of the PPG Timer (Overall Configuration and One Channel) .......... 300 Block Diagram of the Serial I/O Interface (SIO) ......................................................... 412 Block Diagram of the UART ............................ 389 Block Diagram of the U-TIMER ....................... 269 Block Diagram of the Watch Timer ................... 143 Input Capture Block Diagram............................ 427 MB91355A/354A/F355A/F356B/F357B Block Diagram ................................................. 8 MB91F353A/353A/352A/351A Block Diagram ............................................................. 7 Block Size Block Size....................................................... 501 Block Transfer Block Transfer................................................. 500 If Another Transfer Request Occurs During Block Transfer ............................................. 521 Operation Flowchart for Block Transfer ............. 522 Step/Block Transfer 2-Cycle Transfer Fly-by Transfer ............................................. 500 Branch Branch .............................................................. 53 Branch Instructions with Delay Slot..................... 68 Overview of Branch Instructions ......................... 67 BSD 0 Detection Data Register (BSD0) ..................... 358 1 Detection Data Register (BSD1) ..................... 358 BSDC Change Point Detection Data Register (BSDC) ......................................................... 359 BSRR Detection Result Register (BSRR) ..................... 359 Built-in Peripheral Request Built-in Peripheral Request ............................... 496 INDEX Burst 2-Cycle Transfer Burst 2-Cycle Transfer ..................................... 497 Burst Fly-by Transfer Burst Fly-by Transfer ....................................... 498 Burst Length Burst Length Setting and Prefetch Efficiency .......................................................... 219 Burst Transfer Operation Flowchart for Burst Transfer.............. 523 Bus Control Register Bus Control Register (IBCR) ............................ 448 Bus Converter 32-bit/16-bit Bus Converter................................. 52 Harvard/Princeton Bus Converter ........................ 52 Bus Error Bus Error ........................................................ 466 Bus Interface Bus Interface ....................................................... 2 Control Signals on the Ordinary Bus Interface .......................................................... 189 Bus Mode Bus Mode.......................................................... 90 Bus Mode 0 (Single-chip Mode).......................... 91 Bus Mode 1 (Internal-ROM/External-bus Mode) ............................................................ 91 Bus Mode 2 (External-ROM/External-bus Mode) ............................................................ 91 Bus Right Releasing the Bus Right.................................... 228 Bus Status Register Bus Status Register (IBSR) ............................... 445 Bus Width Bus Width of Big Endian Data .......................... 192 Bus Width of Little Endian Data........................ 199 Busy Ready/Busy Signal (RDY/BUSYX)................... 552 BUSYX Ready/Busy Signal (RDY/BUSYX)................... 552 Byte Access Byte Access..................................................... 203 Byte Ordering Byte Ordering .................................................... 64 Overview of Byte Ordering ............................... 188 C Calculation Calculation of Baud Rate .................................. 275 CCR CCR (Condition Code Register) .......................... 58 Counter Control Register High/Low ch0 (CCR H/L ch0) ................................... 252 Counter Control Register High/Low ch1 (CCR H/L ch1) ................................... 256 CDCR Serial I/O Prescaler Control Register (CDCR) ..........................................................417 Change Point Detection Change Point Detection.....................................361 Change Point Detection Data Register Change Point Detection Data Register (BSDC) ..........................................................359 Channel Group Channel Group .................................................517 Character String Operation Manipulation of Arrays Other than Character-type Arrays Using Character String Operation Functions ..............................................39 Specification of the -K lib Option when Character String Operation Functions are Used .......40 Characteristic Characteristics of PPG Timer.............................298 Characteristics of the 8/16-bit Up/Down Counters/Timers ..................................247 Character-type Array Manipulation of Arrays Other than Character-type Array Using Character String Operation Functions ..............................................39 Chip Erase Chip Erase .......................................................549 Erasing Data (Chip Erase) From Flash Memory ..........................................................561 Chip Select Enable Register Configuration of the Chip Select Enable Register (CSER)...............................................183 Clear Sequence Operation Initialization Reset (RST) Clear Sequence ..............................................98 Setting Initialization Reset (INIT) Clear Sequence ..............................................98 Clearing Clearing of the Counter for the 16-bit Free-running Timer .................................................284 Clearing/Updating the Prefetch Buffer ................220 Timing of Clearing of the 16-bit Free-running Timer .................................................285 Clearing Interrupt Timing for Clearing Interrupts During DMA .......510 CLK CLK Synchronous Mode ...................................401 CLK Synchronous Mode CLK Synchronous Mode ...................................401 CLKB CPU Clock (CLKB)..........................................108 CLKP Peripheral Clock (CLKP) ..................................109 CLKR Clock Source Control Register (CLKR) ..............120 623 INDEX CLKT External Bus Clock (CLKT) .............................. 109 Clock Control Register Clock Control Register (ICCR).......................... 455 Clock Controller Clock Controller................................................. 34 Clock Disable Register Clock Disable Register (IDBL).......................... 463 Clock Generation Block Diagram of Clock Generation Controller .......................................................... 111 Clock Mode Note on Operating in PLL Clock Mode ................ 33 Clock Operation Clock Operation ............................................... 292 Clock Source Control Register Clock Source Control Register (CLKR).............. 120 Clock Supply Operation of Clock Supply Function .......... 147, 153 Command Sequence Automatic Algorithm Command Sequence ......... 548 Communication Error Communication Error that Causes No Error ........ 467 Compare Reload and Compare Functions ......................... 261 Up/Down Counting with an Arbitrary Width when the Reload and Compare Functions are Started................................................ 262 Compare Register Compare Register (OCCP0 to OCCP7) .............. 434 Comparison Comparison of Functions ...................................... 6 Condition Code Register CCR (Condition Code Register)........................... 58 Configuration Configuration of Area Configuration Registers 0 to 7 (ACR0 to ACR7) ................................ 169 Configuration of ASR0 to ASR3 (Area Select Registers) ........................ 168 Configuration of AWR0 to AWR3 (Area Wait Registers) .......................... 175 Configuration of General Control Register 10 .......................................................... 310 Configuration of General Control Register 20 .......................................................... 313 Configuration of Interrupt Control Register (ICR) ............................................................ 75 Configuration of PPG Cycle Setting Register (PCSR)............................................... 307 Configuration of PPG Duty Setting Register (PDUT) .............................................. 308 Configuration of PPG Timer Register (PTMR) .......................................................... 309 624 Configuration of the Chip Select Enable Register (CSER) .............................................. 183 Configuration of the Flash Control/Status Register (FLCR) (CPU Mode) .......................... 540 Configuration of the Flash Memory Wait Register (FLWC) ............................................. 543 Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR3)............................ 181 Configuration of the Terminal and Timing Control Register (TCR) ................................... 184 Configurations of Control Status Registers ......... 303 Connection Connection Between the MB91350A Device and the Endian Areas ...................................... 200 Continuing Transfer Timing of the DREQ Pin Input for Continuing Transfer Over the Same Channel .......... 520 Control Register Setting of Temporary Stopping by Writing to the Control Register (Set Independently for Each Channel or all Channels Simultaneously) .................................. 511 Control Signal Control Signals on the Ordinary Bus Interface ......................................................... 189 Control Signals on the Time Division I/O Interface............................................. 189 Control Status Register Bit Configuration of the Control Status Register (ADCS1)............................................ 367 Bit Configuration of the Control Status Register (ADCS2)............................................ 370 Configurations of Control Status Registers ......... 303 Control Status Register (TMCSR) ..................... 289 Conversion Time Setting Register Bit Configuration of the Conversion Time Setting Register (ADCT) ................................ 373 Coprocessor Error Trap Coprocessor Error Trap ...................................... 89 Correspondence Correspondence between the Memory Space Area and Peripheral Resource Registers .............. 583 Counter Block Diagram of the 8/16-bit Up/Down Counters/Timers (ch0)......................... 250 Characteristics of the 8/16-bit Up/Down Counters/Timers ................................. 247 Clearing of the Counter for the 16-bit Free-running Timer................................................. 284 Counter Control Register High/Low ch0 (CCR H/L ch0) ................................... 252 Counter Control Register High/Low ch1 (CCR H/L ch1) ................................... 256 Counter Status Register 0/1 (CSR0/1) ................ 256 INDEX List of Registers of the 8/16-bit Up/Down Counters/Timers ................................. 248 Operating States of the Counter ......................... 295 Other Interval Timers and Counters ....................... 4 Overview of the 8/16-bit Up/Down Counters/Timers ................................. 246 PC (Program Counter) ........................................ 61 Counter Control Register Counter Control Register High/Low ch0 (CCR H/L ch0) ................................... 252 Counter Control Register High/Low ch1 (CCR H/L ch1) ................................... 256 Counter Status Register Counter Status Register 0/1 (CSR0/1) ................ 256 CPU Configuration of the Flash Control/Status Register (FLCR) (CPU Mode)........................... 540 CPU.................................................................. 52 CPU Clock (CLKB) ......................................... 108 FR CPU Features ................................................. 2 FR-CPU Programming Mode (16 Bits,Read/Write Enabled)............... 546 FR-CPU ROM Mode (32 Bits,Read only) .......... 545 Pin States in Each CPU State ............................ 598 CS CS -> RD/WR Setup (TYP[3:0] =0101B, AWR=100BH) ....... 217 CS Delay Setting (TYP[3:0]=0000B, AWR=000CH) ........ 211 Setting of CS -> RD/WR Setup and of RD/WR -> CS Hold (TYP[3:0]=0000B,AWR=000BH) .......................................................... 212 CSER Configuration of the Chip Select Enable Register (CSER) .............................................. 183 CSR Counter Status Register 0/1 (CSR0/1) ................ 256 CTBR Timebase Counter Clear Register (CTBR).......... 119 D D/A Control Register DACR0 (D/A Control Register 0)...................... 383 DACR1 (D/A Control Register 1)...................... 383 DACR2 (D/A Control Register 2)...................... 383 D/A Converter D/A Converter ..................................................... 4 Features of the 8-bit D/A Converter ................... 380 D/A Converter Output Voltage Logical Expressions for D/A Converter Output Voltage .............................................. 384 D/A Data Register DADR0 (D/A Data Register 0).......................... 382 DADR1 (D/A Data Register 1).......................... 382 DADR2 (D/A Data Register 2) ..........................382 DACK FR30 Compatible Mode of DACK .....................532 Timing of DACK Pin Output .............................520 DACR DACR0 (D/A Control Register 0) ......................383 DACR1 (D/A Control Register 1) ......................383 DACR2 (D/A Control Register 2) ......................383 DADR DADR1 (D/A Data Register 1) ..........................382 DADR2 (D/A Data Register 2) ..........................382 DADR0 DADR0 (D/A Data Register 0) ..........................382 Data Direction Register Data Direction Registers (DDR).........................235 Data Internal RAM/Instruction Block Diagram of the Data Internal RAM/ Instruction Internal RAM Access Restriction Functions ............................................576 Data Internal RAM/Instruction Internal RAM Access Restriction Data Internal RAM/Instruction Internal RAM Access Restriction Function Registe .................576 Data Internal RAM/Instruction Internal RAM Access Restriction Operation of the Data Internal RAM/ Instruction Internal RAM Access Restriction Functions ............................................579 Data RAM Limit Control Register DRLR: Data RAM Limit Control Register (D-Bus RAM Limit Control Register) ..........................................................577 Data Register Data Register (IDAR) .......................................462 Overview of the Data Registers (ADTHx and ADTLx)..........................375 Data Transfer Example of Slave Address and Data Transfer ..........................................................468 D-bus D-bus Memory ...................................................34 D-Bus RAM Limit Control Register DRLR: Data RAM Limit Control Register (D-Bus RAM Limit Control Register) ..........................................................577 DDR Data Direction Registers (DDR).........................235 Debugger Emulator and Monitor Debuggers ........................43 Precautions on the Debuggers ..............................36 Simulator Debugger ............................................43 Delay Slot Branch Instructions with Delay Slot .....................68 Instructions not Using a Delay Slot ......................71 625 INDEX Limitations on Operation with Delay Slot ............. 69 Operation with Delay Slot ................................... 68 Operation without Delay Slot .............................. 71 Delayed Interrupt Overview of the Delayed Interrupt Module ......... 352 Register for the Delayed Interrupt Module .......... 353 Delayed Interrupt Module Block Diagram of the Delayed Interrupt Module .......................................................... 353 Delayed Interrupt Module Register Delayed Interrupt Module Register (DICR: Delayed Interrupt Module Register) ................... 354 Demand Transfer Operation Flowchart for Demand Transfer.......... 524 Demand Transfer 2-Cycle Transfer Demand Transfer 2-Cycle Transfer .................... 498 Demand Transfer Fly-by Transfer Demand Transfer Fly-by Transfer ...................... 499 Demand Transfer Request Negate Timing of the DREQ Pin Input when a Demand Transfer Request is Stopped .......................................................... 518 DEOP Timing of the DEOP Pin Output ........................ 520 Detail Details of the Interrupt Controller Registers ........ 328 Details of the Registers for the External Interrupt and NMI Controller ................................... 344 Detailed Explanation Detailed Explanation of the Peripheral Stop Control Registers ............................................ 156 Detection Result Register Detection Result Register (BSRR) ..................... 359 Device Device Operating States.................................... 135 Device States ................................................... 134 Device Initialization Overview of Reset (Device Initialization) ............. 94 DICR Delayed Interrupt Module Register (DICR: Delayed Interrupt Module Register) ................... 354 DLYI Bit of DICR............................................ 355 Direct Addressing Direct Addressing............................................... 54 Direct Addressing Area....................................... 46 Disabling All Channels Disabling All Channels ..................................... 512 Divide-By Rate Initializing the Divide-By Rate .......................... 110 Setting the Divide-By Rate................................ 110 DIVR Base Clock Division Setting Register 0 (DIVR0) ............................................. 125 626 Base Clock Division Setting Register 1 (DIVR1) ............................................ 126 DLYI Bit DLYI Bit of DICR ........................................... 355 DMA DMA Fly-by Transfer (I/O -> Memory) (TYP[3:0] = 0000B, AWR = 0008H, and IOWR = 51H) ..................................... 213 DMA Fly-By Transfer (Memory -> I/O) (TYP[3:0]=0000B, AWR=0008H, and IOWR=41H) ....................................... 223 DMA Fly-by Transfer (Memory -> I/O) (TYP[3:0] = 0000B, AWR = 0008H, and IOWR = 51H) ..................................... 214 DMA Transfer and Interrupts ............................ 506 DMA Transfer Request During External Hold ......................................................... 507 DMAC (DMA Controller) .................................... 3 External Hold Request During DMA Transfer ......................................................... 507 Notes on DMA Transfer in Sleep Mode ............. 515 Overview of DMA External Interface Operation ........................................... 529 Simultaneous Occurrence of a DMA Transfer Request and an External Hold Request .............. 507 Suppressing DMA............................................ 506 Timing for Clearing Interrupts During DMA ...... 510 DMA External Interface Overview of DMA External Interface Operation ........................................... 529 DMA Fly-by Transfer DMA Fly-by Transfer (I/O -> Memory) (TYP[3:0]=0000B,AWR=0008H,and IOWR=41H) ....................................... 222 DMA Transfer DMA Transfer and Interrupts ............................ 506 External Hold Request During DMA Transfer ......................................................... 507 Notes on DMA Transfer in Sleep Mode ............. 515 DMA Transfer Request DMA Transfer Request During External Hold ......................................................... 507 Simultaneous Occurrence of a DMA Transfer Request and an External Hold Request .............. 507 DMAC AC Characteristics of DMAC............................ 521 Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR3)............................ 181 DMAC (DMA Controller) .................................... 3 Hardware Configuration of the DMAC .............. 472 Interrupts That Enable DMAC Interrupt Control Outputs .............................................. 514 Main DMAC Functions .................................... 472 Main DMAC Operations .................................. 493 Overview of DMAC......................................... 492 Overview of the DMAC Registers ..................... 473 INDEX DMAC Interrupt Control Output Interrupts That Enable DMAC Interrupt Control Outputs .............................................. 514 DMAC Interrupt Source Clear Register DMAC Interrupt Source Clear Register (SRCL) .......................................................... 418 DMAC Register Overview of the DMAC Registers ..................... 473 DMACA Functions of the DMACA0 to 4 Bits .................. 476 DMACB Functions of the DMACB0 to 4 Bits .................. 482 DMACR Functions of the DMACR Bits .......................... 490 DMADA Functions of the DMASA0 to 4 and DMADA0 to 4 Bits.................................................... 488 DMASA Functions of the DMASA0 to 4 and DMADA0 to 4 Bits.................................................... 488 Double Type Use of the Double Type and Long Double Type ............................................................ 40 DRCL DRCL ............................................................. 398 DREQ Minimum Effective Pulse Width of the DREQ Pin Input. ................................................. 518 Negate Timing of the DREQ Pin Input when a Demand Transfer Request is Stopped .......................................................... 518 Timing of the DREQ Pin Input for Continuing Transfer Over the Same Channel .......... 520 DREQx Timing of DREQx Pin Input ............................. 530 DRLR DRLR: Data RAM Limit Control Register (D-Bus RAM Limit Control Register) .......................................................... 577 DSTP Timing of the DSTP Pin Input........................... 520 E EIRRn Bit Configuration of the External Interrupt Request Register (EIRRn) ................................ 346 EIT EIT Causes........................................................ 72 EIT Interrupt Levels ........................................... 73 EIT Vector Table ............................................... 80 Features of EIT .................................................. 72 Priority of EIT Causes to Be Accepted ................. 84 Return from EIT ................................................ 72 ELVRn Bit Configuration of External Level Register (ELVRn) ..........................................................347 Emulator Emulator and Monitor Debuggers ........................43 Enabling Operation Enabling Operation for All Channels ..................508 Endian Area Connection Between the MB91350A Device and the Endian Areas.......................................200 ENIRn Bit Configuration of Enable Interrupt Request Register (ENIRn).................................345 Erase Overview of Flash Memory Write/Erase .............557 Sector Erase Procedure......................................562 Temporarily Stop Erase.....................................551 Erasing Data Erasing Data (Chip Erase) From Flash Memory ..........................................................561 Error Bus Error .........................................................466 Communication Error that Causes No Error ........467 Coprocessor Error Trap .......................................89 Non-detection of Errors.......................................42 Occurrence of an Address Error .........................513 Example Example of Connection with External Devices ..........................................................196 Example of Receive Data ..................................469 Example of Setting ASRs and ASZ[3:0] .............186 Example of Setting Baud Rates and U-TIMER Reload Values ................................................409 Example of Slave Address and Data Transfer ..........................................................468 Example of System Construction (Using Mode 1) ...................................407 Example of Using the Hold Request Cancellation Request Function (HRCR)....................338 Examples of Methods Used to Perform All-L and All-H PPG Output ...............................319 Examples of Operation (Simple Waveforms).......529 Examples of Serial Programming Connections ..........................................................570 Explanation Explanation of Terms Used in the Pin State Lists ...................................................597 Explanation of the Main Clock Oscillation Stabilization Wait Timer Register..........150 External Bus Bus Mode 1 (Internal-ROM/External-bus Mode) ............................................................91 Bus Mode 2 (External-ROM/External-bus Mode) ............................................................91 Setting the External Bus ......................................33 627 INDEX External Bus Access External Bus Access ......................................... 193 External Bus Clock External Bus Clock (CLKT) .............................. 109 External Bus Interface Block Diagram of the External Bus Interface ...... 164 Features of the External Bus Interface ................ 162 Procedure for Setting the External Bus Interface ............................................. 230 Register Overview of External Bus Interface....... 167 External Bus Interface Register List of External Bus Interface Registers.............. 166 External Clock Note on Using an External Clock ......................... 32 External Device Example of Connection with External Devices .......................................................... 196 External Hold DMA Transfer Request During External Hold .......................................................... 507 External Hold Request External Hold Request During DMA Transfer .......................................................... 507 Simultaneous Occurrence of a DMA Transfer Request and an External Hold Request............... 507 External I/O and External Memory Transfer Between External I/O and External Memory ............................................. 521 External Input Pin External Input Pin Corresponding to Each Input Capture Channel.................................. 426 External Interrupt Block Diagram of the External Interrupt and NMI Controller ................................... 343 Details of the Registers for the External Interrupt and NMI Controller ................................... 344 External Interrupt and NMI Controller Registers ............................................ 342 External Interrupt Request Level........................ 349 Operating Procedure for an External Interrupt .......................................................... 348 Operation of an External Interrupt...................... 348 External Interrupt Request Level External Interrupt Request Level........................ 349 External Interrupt Request Register Bit Configuration of the External Interrupt Request Register (EIRRn)................................. 346 External Level Register Bit Configuration of External Level Register (ELVRn) .......................................................... 347 External Pin Transfer Request If an External Pin Transfer Request is Reentered During Transfer................................... 521 628 External Transfer Request Pin External Transfer Request Pin ........................... 496 External Wait With External Wait (TYP[3:0]=0101B,AWR=1008H).......... 216 Without External Wait (TYP[3:0]=0100B and AWR=0008H) ......................................................... 215 External Wait Timing External Wait Timing (TYP[3:0]=0001B,AWR=2008H).......... 209 External-ROM Bus Mode 2 (External-ROM/External-bus Mode) ........................................................... 91 F F-Bus RAM Limit Control Register FRLR: Instruction RAM Limit Control Register (F-Bus RAM Limit Control Register) ......................................................... 578 Feature Features .......................................................... 387 Features of EIT .................................................. 72 Features of I2C Interface................................... 440 Features of the 8-bit D/A Converter ................... 380 Features of the A/D Converter........................... 364 Features of the External Bus Interface................ 162 Features of the Internal Architecture .................... 50 Features of the Output Compare Module ............ 432 Flash Control/Status Register Configuration of the Flash Control/Status Register (FLCR) (CPU Mode) .......................... 540 Flash Memory Block Diagram of Flash Memory ...................... 535 Configuration of the Flash Memory Wait Register (FLWC) ............................................. 543 Erasing Data (Chip Erase) From Flash Memory ......................................................... 561 Flash Memory ................................................... 35 Flash Memory Access Modes............................ 545 Memory Map of Flash Memory......................... 535 Outline of Flash Memory.................................. 534 Overview of Flash Memory Registers ................ 539 Overview of Flash Memory Write/Erase ............ 557 Overview of the Flash Memory Automatic Algorithm .......................................... 547 Reading/Resetting Flash Memory ...................... 558 Restarting Sector Erase in Flash Memory ........... 565 Sector Address Table of Flash Memory.............. 537 Temporarily Stopping Sector Erase in Flash Memory ............................................. 564 Writing Data to Flash Memory.......................... 559 Flash Memory Register Overview of Flash Memory Registers ................ 539 INDEX Flash Memory Wait Register Configuration of the Flash Memory Wait Register (FLWC) ............................................. 543 Flash Microcontroller Programmer System Configuration of the Flash Microcontroller Programmer........................................ 572 FLCR Configuration of the Flash Control/Status Register (FLCR) (CPU Mode)........................... 540 Flow Flow of Data During 2-Cycle Transfer ............... 525 Flow of Data During Fly-By Transfer ................ 527 FLWC Configuration of the Flash Memory Wait Register (FLWC) ............................................. 543 Fly-By Transfer Flow of Data During Fly-By Transfer ................ 527 Step/Block Transfer 2-Cycle Transfer Fly-by Transfer ............................................. 500 FR FR CPU Features ................................................. 2 FR30 Compatible Mode FR30 Compatible Mode of DACK..................... 532 FR-CPU FR-CPU Programming Mode (16 Bits,Read/Write Enabled)............... 546 FR-CPU ROM Mode (32 Bits,Read only) .......... 545 Free-running Timer Block Diagram of the 16-bit Free-running Timer................................................. 279 Timing of 16-bit Free-running Timer Counting .......................................................... 285 Timing of Clearing of the 16-bit Free-running Timer................................................. 285 FRLR FRLR: Instruction RAM Limit Control Register (F-Bus RAM Limit Control Register) .......................................................... 578 Fujitsu Standard Serial Onboard Pins Used for Fujitsu Standard Serial Onboard Writing .............................................. 569 Function Functions of the DMACA0 to 4 Bits .................. 476 Functions of the DMACB0 to 4 Bits .................. 482 Functions of the DMACR Bits .......................... 490 Functions of the DMASA0 to 4 Bits and DMADA0 to 4 Bits ................................................. 488 General-Purpose Register General-Purpose Registers...................................56 Generation Generation of Internal Operating Clock ..............104 H Halfword Access Halfword Access ..............................................202 Handling Handling of NC and Open Pins ............................33 Hardware Configuration Hardware Configuration of the DMAC ...............472 Hardware Configuration of the Interrupt Controller ...........................................324 Hardware Sequence Flag Hardware Sequence Flag ...................................552 Harvard/Princeton Bus Converter Harvard/Princeton Bus Converter.........................52 Hold Request Cancel Request Hold Request Cancellation Request (HRLC: Hold Request Cancel Request) ......................337 Hold Request Cancellation Request Example of Using the Hold Request Cancellation Request Function (HRCR)....................338 Hold Request Cancellation Request (HRLC: Hold Request Cancel Request) ......................337 Hold Request Cancellation Request Register Bit Configuration of the Hold Request Cancellation Request Register (HRCL) .....................331 Hold Suppress Level Interrupt NMI/Hold Suppress Level Interrupt Processing ..........................................................511 How to How to Read the Instruction Lists ......................603 How to Specify Address ....................................559 How to Specify Sectors .....................................562 HRCL Bit Configuration of the Hold Request Cancellation Request Register (HRCL) .....................331 HRCR Example of Using the Hold Request Cancellation Request Function (HRCR)....................338 HRLC Hold Request Cancellation Request (HRLC: Hold Request Cancel Request) ......................337 I G General Control Register Configuration of General Control Register 10 .......................................................... 310 Configuration of General Control Register 20 .......................................................... 313 I Flag I Flag.................................................................74 I/O 2-Cycle Transfer (External -> I/O) (TYP[3:0] = 0000B, AWR = 0008H, and IOWR = 00H) ......................................226 629 INDEX 2-Cycle Transfer (I/O -> External) (TYP[3:0] = 0000B, AWR = 0008H, and IOWR = 00H)...................................... 227 2-Cycle Transfer (The Timing is the Same for Internal RAM -> External I/O and RAM and for External I/O and RAM -> Internal RAM.) (TYP[3:0] = 0000B, AWR = 0008H, and IOWR = 00H)...................................... 225 Accessing I/O Ports ............................................ 35 Basic Block Diagram of the I/O Port .................. 232 Block Diagram of the Serial I/O Interface (SIO) .......................................................... 412 Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR3) ............................ 181 Control Signals on the Time Division I/O Interface ............................................. 189 DMA Fly-by Transfer (I/O -> Memory) (TYP[3:0] = 0000B, AWR = 0008H, and IOWR = 51H)...................................... 213 DMA Fly-by Transfer (I/O -> Memory) (TYP[3:0]=0000B,AWR=0008H, and IOWR=41H) ....................................... 222 DMA Fly-By Transfer (Memory -> I/O) (TYP[3:0]=0000B, AWR=0008H, and IOWR=41H) ....................................... 223 DMA Fly-by Transfer (Memory -> I/O) (TYP[3:0] = 0000B, AWR = 0008H, and IOWR = 51H)...................................... 214 I/O Pins ........................................................... 165 I/O Ports.............................................................. 5 I/O Ports With Pull-up Resistors ........................ 232 Overview of Serial I/O Interface (SIO) Operation ........................................... 419 Overview of the Serial I/O Interface (SIO).......... 410 Reading the I/O Map ........................................ 582 Serial I/O Interface (SIO) Registers.................... 411 Serial I/O Interface Operating Modes ................. 411 Serial I/O Prescaler Control Register (CDCR) .......................................................... 417 Shift Operation Start/Stop Timing and I/O Timing ............................................... 421 States of Serial I/O Interface Operation .............. 420 Transfer Between External I/O and External Memory ............................................. 521 I/O Map Reading the I/O Map ........................................ 582 I/O Port Accessing I/O Ports ............................................ 35 Basic Block Diagram of the I/O Port .................. 232 I/O Wait Register Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR3) ............................ 181 I2C Block Diagram of the I2C Interface .................... 443 Features of I2C Interface ................................... 440 630 I2C Bus Interface (400 kbps Supported) ................. 5 I2C Interface Registers ..................................... 441 Overview of the I2C Interface Registers ............. 444 I2C Interface Register I2C Interface Registers ..................................... 441 Overview of the I2C Interface Registers ............. 444 IBCR Bus Control Register (IBCR) ............................ 448 IBSR Bus Status Register (IBSR) ............................... 445 ICCR Clock Control Register (ICCR) ......................... 455 ICR Bit Configuration of the Interrupt Control Register (ICR) ................................................. 329 Configuration of Interrupt Control Register (ICR) ........................................................... 75 Mapping of Interrupt Control Register (ICR) ........ 75 ICS Input Capture Control Registers (ICS01 and ICS23).............................. 428 IDAR Data Register (IDAR)....................................... 462 IDBL Clock Disable Register (IDBL) ......................... 463 If an External Pin Transfer Request is Reentered If an External Pin Transfer Request is Reentered During Transfer .................................. 521 If Another Transfer Request Occurs If Another Transfer Request Occurs During Block Transfer ............................................. 521 ILM ILM.................................................................. 61 Interrupt Level Mask (ILM) Register ................... 74 INIT INIT Pin Input (Settings Initialization Reset Pin) ........................................................... 96 Setting Initialization Reset (INIT) Clear Sequence.............................................. 98 Settings Initialization Reset (INIT) ...................... 95 Initial Value Initial Values and Functions of the Port Function Registers (PFRs) ................................. 238 Mapping of Variables with Initial Values ............. 38 Initialization INIT Pin Input (Settings Initialization Reset Pin) ........................................................... 96 Operation Initialization Reset (RST) .................... 95 Operation Initialization Reset (RST) Clear Sequence.............................................. 98 Overview of Reset (Device Initialization)............. 94 Setting Initialization Reset (INIT) Clear Sequence.............................................. 98 Settings Initialization Reset (INIT) ...................... 95 INDEX Initializing Initializing the Divide-By Rate .......................... 110 Input Capture 16-bit Input Capture Operation .......................... 430 External Input Pin Corresponding to Each Input Capture Channel ................................. 426 Input Capture Block Diagram............................ 427 Input Capture Data Register (IPCP0 to IPCP3) .......................................................... 428 Overview of the Input Capture Module .............. 425 Input Capture Control Register Input Capture Control Registers (ICS01 and ICS23).............................. 428 Input Capture Data Register Input Capture Data Register (IPCP0 to IPCP3) .......................................................... 428 Input Capture Module Register Input Capture Module Registers ........................ 426 Input Select [Bits 28 to 24] IS4 to 0 (Input Select): Transfer Source Selection .................... 478 Input Timing Input Timing for 16-bit Input Capture ................ 430 Input-Output Circuit Input-Output Circuit Types ................................. 27 Instruction Block Diagram of the Data Internal RAM/ Instruction Internal RAM Access Restriction Functions ........................................... 576 Branch Instructions with Delay Slot..................... 68 Data Internal RAM/Instruction Internal RAM Access Restriction Function Registers.............. 576 FRLR: Instruction RAM Limit Control Register (F-Bus RAM Limit Control Register) .......................................................... 578 How to Read the Instruction Lists...................... 603 Instruction Format............................................ 605 Instructions not Using a Delay Slot ...................... 71 Operation of INT Instruction ............................... 87 Operation of INTE Instruction............................. 87 Operation of RETI Instruction ............................. 89 Operation of the Data Internal RAM/ Instruction Internal RAM Access Restriction Functions ........................................... 579 Operation of Undefined Instruction Exception ...... 88 Other Types of Instructions................................. 54 Overview of Branch Instructions ......................... 67 Instruction RAM Limit Control Register FRLR: Instruction RAM Limit Control Register (F-Bus RAM Limit Control Register) .......................................................... 578 INT Operation of INT Instruction ............................... 87 INTE Operation of INTE Instruction............................. 87 Internal Architecture Features of the Internal Architecture.....................50 Overview of Internal Architecture ........................49 Structure of the Internal Architecture....................51 Internal Memory Internal Memory...................................................3 Internal Operating Clock Generation of Internal Operating Clock ..............104 Internal RAM Internal RAM .....................................................35 Internal RAM Access Restriction Block Diagram of the Data Internal RAM/ Instruction Internal RAM Access Restriction Functions ............................................576 Internal-ROM Bus Mode 1 (Internal-ROM/External-bus Mode) ............................................................91 Interrupt Bit Configuration of Enable Interrupt Request Register (ENIRn).................................345 Bit Configuration of External Level Register (ELVRn) ..........................................................347 Bit Configuration of the External Interrupt Request Register (EIRRn) .................................346 Bit Configuration of the Interrupt Control Register (ICR)..................................................329 Block Diagram of the Delayed Interrupt Module ..........................................................353 Block Diagram of the External Interrupt and NMI Controller....................................343 Block Diagram of the Interrupt Controller...........327 Configuration of Interrupt Control Register (ICR) ............................................................75 Delayed Interrupt Module Register (DICR: Delayed Interrupt Module Register) ...................354 Details of the Interrupt Controller Registers ........328 Details of the Registers for the External Interrupt and NMI Controller....................................344 DMA Transfer and Interrupts.............................506 DMAC Interrupt Source Clear Register (SRCL) ..........................................................418 EIT Interrupt Levels............................................73 External Interrupt and NMI Controller Registers.............................................342 External Interrupt Request Level ........................349 Hardware Configuration of the Interrupt Controller ...........................................324 Interrupt Controller ...............................................4 Interrupt Function .............................................424 Interrupt Generation Timing ..............................267 Interrupt Level Mask (ILM) Register....................74 Interrupt Number ..............................................355 Interrupt Processing ..........................................470 Interrupt Sources and Timing Chart....................318 Interrupt Stack....................................................78 Interrupt Vectors ..............................................594 631 INDEX Interrupts That Enable DMAC Interrupt Control Outputs .............................................. 514 Level Mask for Interrupt and NMI ....................... 74 Main Clock Oscillation Stabilization Wait Timer Interrupt ............................................. 152 Major Functions of the Interrupt Controller......... 324 NMI (Non Maskable Interrupt) .......................... 336 NMI/Hold Suppress Level Interrupt Processing .......................................................... 511 Occurrence of Interrupts and Timing for Setting Flags .................................................. 402 Operating Procedure for an External Interrupt .......................................................... 348 Operation of an External Interrupt...................... 348 Operation of User Interrupt/NMI ......................... 86 Overview of the Delayed Interrupt Module ......... 352 Register for the Delayed Interrupt Module .......... 353 Timing for Clearing Interrupts During DMA....... 510 Watch Timer Interrupt ...................................... 146 Interrupt Control Register Bit Configuration of the Interrupt Control Register (ICR) ................................................. 329 Configuration of Interrupt Control Register (ICR) ............................................................ 75 Mapping of Interrupt Control Register (ICR) ........ 75 Interrupt Controller Block Diagram of the Interrupt Controller .......... 327 Hardware Configuration of the Interrupt Controller ........................................... 324 Major Functions of the Interrupt Controller......... 324 Interrupt Controller Register Details of the Interrupt Controller Registers ........ 328 Interrupt Controller Registers ............................ 325 Interrupt Enable Register Bit Configuration of Enable Interrupt Request Register (ENIRn) ................................ 345 Interrupt Generation Timing Interrupt Generation Timing .............................. 267 Interrupt Level Mask Interrupt Level Mask (ILM) Register ................... 74 Interrupt Number Interrupt Number.............................................. 355 Interrupt Source Interrupt Sources and Timing Chart ................... 318 Interrupt Vector Interrupt Vectors .............................................. 594 Interval Time Interval Time ................................................... 143 Interval Timer Operation of Interval Timer Function ......... 146, 152 IOWR Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR3) ............................ 181 632 IPCP Input Capture Data Register (IPCP0 to IPCP3) ......................................................... 428 IS [Bits 28 to 24] IS4 to 0 (Input Select): Transfer Source Selection .................... 478 ISBA 7-bit Slave Address Register (ISBA).................. 460 ISMK 7-bit Slave Address Mask Register (ISMK) ........ 461 ITBA 10-bit Slave Address Register (ITBA)................ 457 ITMK 10-bit Slave Address Mask Register (ITMK) ...... 458 K -K lib Option Specification of the -K lib Option when Character String Operation Functions are Used....... 40 L Latch-up Preventing a Latch-up ........................................ 32 Level Mask Level Mask for Interrupt and NMI....................... 74 Limitation Limitations on Operation with Delay Slot............. 69 List List of External Bus Interface Registers ............. 166 List of Peripheral Stop Control Registers............ 155 List of Pin Functions .......................................... 13 List of Registers of the 8/16-bit Up/Down Counters/Timers ................................. 248 Little Endian Bus Width of Little Endian Data........................ 199 Little Endian Data Format................................. 198 Mapping of the Stack to the Little-endian Area ........................................................... 40 Overview of Little Endian Method .................... 197 Precautions on Using the Little-Endian Area ........ 37 Load Load and Store .................................................. 53 Logical Expression Logical Expressions for D/A Converter Output Voltage .............................................. 384 Logical Operation Logical Operation and Bit Manipulation .............. 54 Long Double Type Use of the Double Type and Long Double Type ........................................................... 40 Low-power Consumption Mode Low-power Consumption Mode .......................... 34 INDEX M Main Clock Wait Time after Switching From the Subclock to the Main Clock ........................................ 107 Main Clock Oscillation Stabilization Wait Timer Block Diagram of the Main Clock Oscillation Stabilization Wait Timer...................... 149 Explanation of the Main Clock Oscillation Stabilization Wait Timer Register ......... 150 Main Clock Oscillation Stabilization Wait Timer Interrupt ............................................. 152 Operation of the Main Clock Oscillation Stabilization Wait Timer ......................................... 153 Precautions on Using the Main Clock Oscillation Stabilization Wait Timer...................... 154 Time Intervals for Main Clock Oscillation Stabilization Wait Timer...................... 149 Main DMAC Function Main DMAC Functions .................................... 472 Main DMAC Operation Main DMAC Operations................................... 493 Major Function Major Functions of the Interrupt Controller ........ 324 Manipulation Manipulation of Arrays Other than Character-type Arrays Using Character String Operation Functions ............................................. 39 Mapping Mapping of Interrupt Control Register (ICR) ........ 75 Mapping of the Stack to the Little-endian Area ............................................................ 40 Mapping of Variables with Initial Values ............. 38 Master Addressing Master Addressing ........................................... 466 MCLK MCLK and SYSCLK ......................................... 33 MD Mode Pins (MD0 to MD2) .................................. 33 Memory D-bus Memory .................................................. 34 DMA Fly-by Transfer (I/O -> Memory) (TYP[3:0]=0000B,AWR=0008H, and IOWR=41H) ....................................... 222 Memory Map Memory Map............................................... 46, 66 Memory Map of Flash Memory......................... 535 Memory Space Correspondence between the Memory Space Area and Peripheral Resource Registers .............. 583 Minimum Effective Pulse Width Minimum Effective Pulse Width of the DREQ Pin Input. ................................................. 518 Mode 1 Example of System Construction (Using Mode 1) ...................................407 Mode Pin Mode Pins..........................................................92 Mode Pins (MD0 to MD2)...................................33 Mode Register Mode Register (MODR)......................................92 MODR Mode Register (MODR)......................................92 Monitor Emulator and Monitor Debuggers ........................43 Multiply Multiply & Divide Register .................................63 N NC Handling of NC and Open Pins ............................33 Negate Timing Negate Timing of the DREQ Pin Input when a Demand Transfer Request is Stopped ..........................................................518 NMI Block Diagram of the External Interrupt and NMI Controller....................................343 Details of the Registers for the External Interrupt and NMI Controller....................................344 External Interrupt and NMI Controller Registers.............................................342 Level Mask for Interrupt and NMI .......................74 NMI ................................................................349 NMI (Non Maskable Interrupt) ..........................336 NMI/Hold Suppress Level Interrupt Processing ..........................................................511 Operation of User Interrupt/NMI..........................86 NMI Controller Register External Interrupt and NMI Controller Registers.............................................342 No Error Communication Error that Causes No Error ........467 No-coprocessor Trap No-coprocessor Trap...........................................89 Non Maskable Interrupt NMI (Non Maskable Interrupt) ..........................336 Non-detection Non-detection of Errors.......................................42 Normal Normal and Synchronous Standby Operations ..........................................................142 Normal Reset Operation ....................................102 Normal Access Normal Access and Address/Data Multiplex Access ................................................176 633 INDEX Note Note for the Case of Using No Subclock............... 33 Note on Operating in PLL Clock Mode ................ 33 Note on Specifying Two or More Sectors ........... 562 Note on Using an External Clock ......................... 32 Notes of PS Register........................................... 35 Notes on DMA Transfer in Sleep Mode.............. 515 Notes on Setting Registers................................. 475 Notes on Writing Data ...................................... 559 O OCCP Compare Register (OCCP0 to OCCP7) .............. 434 Occurrence Occurrence of an Address Error......................... 513 Occurrence of Interrupts and Timing for Setting Flags .................................................. 402 OCS Output Control Register (OCS0 to OCS7)........... 434 One Prefetch Access Operation Unit for One Prefetch Access Operation ............. 219 Open Pin Handling of NC and Open Pins............................ 33 Operating Mode Operating Modes of the UART .......................... 399 Overview of Operating Modes............................. 90 Serial I/O Interface Operating Modes ................. 411 Operating Procedure Operating Procedure for an External Interrupt .......................................................... 348 Operating State Operating States of the Counter ......................... 295 Operation 16-bit Input Capture Operation .......................... 430 Enabling Operation for All Channels.................. 508 Examples of Operation (Simple Waveforms) ...... 529 Limitations on Operation with Delay Slot ............. 69 Logical Operation and Bit Manipulation ............... 54 Operation Flowchart for Block Transfer ............. 522 Operation Initialization Reset (RST) .................... 95 Operation Initialization Reset (RST) Clear Sequence .............................................. 98 Operation of an External Interrupt...................... 348 Operation of Clock Supply Function .......... 147, 153 Operation of INT Instruction ............................... 87 Operation of INTE Instruction ............................. 87 Operation of Interval Timer Function ......... 146, 152 Operation of RETI Instruction ............................. 89 Operation of Step Trace Trap .............................. 88 Operation of the 16-bit Output Compare Module............................................... 437 Operation of the Data Internal RAM/ Instruction Internal RAM Access Restriction Functions............................................ 579 634 Operation of the Main Clock Oscillation Stabilization Wait Timer......................................... 153 Operation of the Watch Timer ........................... 148 Operation of Undefined Instruction Exception ...... 88 Operation of User Interrupt/NMI ......................... 86 Operation with Delay Slot................................... 68 Operation without Delay Slot .............................. 71 Overview of DMA External Interface Operation ........................................... 529 Overview of Serial I/O Interface (SIO) Operation ........................................... 419 PLL Operation Enable ...................................... 105 Reload Operation ............................................. 501 Transfer Count Registers and Reload Operation ......................................................... 505 Unit for One Prefetch Access Operation............. 219 Operation Flowchart Operation Flowchart for Block Transfer ............. 522 Operation Flowchart for Burst Transfer.............. 523 Operation Flowchart for Demand Transfer ......... 524 Optional Clear Optional Clear and Temporary Stopping of a Prefetch Access ............................................... 219 Ordering Bit Ordering ...................................................... 64 Byte Ordering.................................................... 64 Overview of Byte Ordering............................... 188 OSCCR Oscillation Control Register (OSCCR)............... 128 Oscillation Control Register Oscillation Control Register (OSCCR)............... 128 Oscillation Stabilization Wait Selecting an Oscillation Stabilization Wait Time .................................................. 100 Sources of an Oscillation Stabilization Wait ......... 99 Other Feature Other Features ..................................................... 5 Other Function Other Functions ............................................... 491 Other Interval Timer Other Interval Timers and Counters ....................... 4 Other Item Other Items ..................................................... 467 Other Type Other Types of Instructions................................. 54 Outline Outline of Flash Memory.................................. 534 Output Compare Features of the Output Compare Module ............ 432 Overview of the Output Compare Module .......... 431 Output Compare Module Block Diagram of the Output Compare Module ......................................................... 433 INDEX Output Compare Module Register Output Compare Module Registers .................... 432 Output Control Register Output Control Register (OCS0 to OCS7) .......... 434 Output Pin Output Pin Function ......................................... 294 Overall Configuration Block Diagram of the PPG Timer (Overall Configuration and One Channel) .......... 300 Overview Overview of Branch Instructions ......................... 67 Overview of Byte Ordering ............................... 188 Overview of Device State Control ..................... 133 Overview of DMA External Interface Operation ........................................... 529 Overview of DMAC......................................... 492 Overview of Flash Memory Registers ................ 539 Overview of Flash Memory Write/Erase ............ 557 Overview of Internal Architecture ....................... 49 Overview of Little Endian Method..................... 197 Overview of Operating Modes ............................ 90 Overview of Reset (Device Initialization)............. 94 Overview of Serial I/O Interface (SIO) Operation ........................................... 419 Overview of the 16-bit Free-running Timer ........ 278 Overview of the 16-bit Reload Timer ................. 286 Overview of the 8/16-bit Up/Down Counters/Timers ................................. 246 Overview of the A/D Converter Registers .......... 364 Overview of the Bit Search Module ................... 356 Overview of the Data Registers (ADTHx and ADTLx) ......................... 375 Overview of the Delayed Interrupt Module......... 352 Overview of the DMAC Registers ..................... 473 Overview of the Flash Memory Automatic Algorithm........................................... 547 Overview of the I2C Interface Registers ............. 444 Overview of the Input Capture Module .............. 425 Overview of the Output Compare Module .......... 431 Overview of the Serial I/O Interface (SIO) ......... 410 Overview of the UART .................................... 386 Overview of the U-TIMER ............................... 268 Register Overview of External Bus Interface ...... 167 P Package Dimension MB91F353A/351A/352A/353A Package Dimensions ............................................................ 10 MB91F355/354A/355A/F356B/F357B Package Dimensions (Reference Diagram) ............. 9 PC PC (Program Counter) ........................................ 61 PCR Pull-up Control Registers (PCR)........................ 236 PCSR Configuration of PPG Cycle Setting Register (PCSR) ...............................................307 PDR Port Data Registers (PDR) .................................234 PDUT Configuration of PPG Duty Setting Register (PDUT) ..............................................308 Peripheral Circuit Transfer Stop Requests from Peripheral Circuits...............................................513 Peripheral Clock Peripheral Clock (CLKP) ..................................109 Peripheral Resource Correspondence between the Memory Space Area and Peripheral Resource Registers ...............583 Peripheral Stop Control Block Diagram of Peripheral Stop Control ..........155 Peripheral Stop Control Register Detailed Explanation of the Peripheral Stop Control Registers.............................................156 List of Peripheral Stop Control Registers ............155 PFR Port Function Registers (PFR) ...........................237 PFRs Initial Values and Functions of the Port Function Registers (PFRs)..................................238 Pin Function List of Pin Functions ...........................................13 Pin Layout Pin Layout of the MB91F353A/351A/352A/353A ............................................................12 Pin Layout of the MB91F355A/354A/355A/ F356B/F357B........................................11 Pin State Explanation of Terms Used in the Pin State Lists ...................................................597 Pin States in Each CPU State .............................598 PLL PLL Operation Enable.......................................105 Wait Time after Enabling a PLL ........................106 PLL Clock Mode Note on Operating in PLL Clock Mode.................33 PLL Multiply-by Rate PLL Multiply-by Rate .......................................105 Wait Time after Changing the PLL Multiply-by Rate....................................................106 Port Data Register Port Data Registers (PDR) .................................234 Port Function Register Initial Values and Functions of the Port Function Registers (PFRs)..................................238 Port Function Registers (PFR) ...........................237 635 INDEX Power Supply Power Supply Pins ............................................. 32 Power-On Power-on........................................................... 33 Source Oscillation Input at Power-on ................... 33 Wait Time after Power-On ................................ 106 PPG Block Diagram of the PPG Timer (Overall Configuration and One Channel)........... 300 Examples of Methods Used to Perform All-L and All-H PPG Output ............................... 319 Registers of the PPG Timer ............................... 299 PPG Cycle Setting Register Configuration of PPG Cycle Setting Register (PCSR)............................................... 307 PPG Duty Setting Register Configuration of PPG Duty Setting Register (PDUT) .............................................. 308 PPG Timer Characteristics of PPG Timer ............................ 298 PPG Timer Registers ........................................ 302 PPG Timer Register Configuration of PPG Timer Register (PTMR) .......................................................... 309 PPG Timer Registers ........................................ 302 Precaution Precautions ...................................................... 314 Precautions for Using the Watch Timer .............. 148 Precautions on the Debuggers.............................. 36 Precautions on Using the Little-Endian Area......... 37 Precautions on Using the Main Clock Oscillation Stabilization Wait Timer ...................... 154 Prefetch Basic Conditions for Starting External Access Using Prefetch .......................................................... 218 Burst Length Setting and Prefetch Efficiency .......................................................... 219 Clearing/Updating the Prefetch Buffer................ 220 Optional Clear and Temporary Stopping of a Prefetch Access................................................ 219 Prefetch............................................................. 35 Reading from the Prefetch Buffer ...................... 220 Unit for One Prefetch Access Operation ............. 219 Prefetch-enabled Area Restrictions on Prefetch-enabled Areas............... 221 Priority Priority Among Channels.................................. 516 Priority of EIT Causes to Be Accepted ................. 84 Priority Decision Priority Decision .............................................. 332 Procedure Procedure for Setting the External Bus Interface ............................................. 230 636 Program Program (Write)............................................... 549 Program Counter PC (Program Counter) ........................................ 61 Program Status PS (Program Status) ........................................... 57 PS PS (Program Status) ........................................... 57 PS Register Notes of PS Register .......................................... 35 PTMR Configuration of PPG Timer Register (PTMR) ......................................................... 309 Pull-up Pull-up Control .................................................. 34 Pull-up Control Register Pull-up Control Registers (PCR)........................ 236 Pull-up Resistor I/O Ports With Pull-up Resistors........................ 232 Pulse Width Minimum Effective Pulse Width of the DREQ Pin Input. ................................................. 518 Q Quartz Oscillation Circuit Quartz Oscillation Circuit ................................... 32 R RAM 2-Cycle Transfer (The Timing is the Same for Internal RAM -> External I/O and RAM and for External I/O and RAM -> Internal RAM.) (TYP[3:0] = 0000B, AWR = 0008H, and IOWR = 00H) ..................................... 225 Data Internal RAM/Instruction Internal RAM Access Restriction Function Registers.............. 576 DRLR: Data RAM Limit Control Register (D-Bus RAM Limit Control Register) ......................................................... 577 FRLR: Instruction RAM Limit Control Register (F-Bus RAM Limit Control Register) ......................................................... 578 Internal RAM .................................................... 35 Operation of the Data Internal RAM/ Instruction Internal RAM Access Restriction Functions ........................................... 579 RCR Reload/Compare Register 0/1 (RCR 0/1)............ 258 RD CS -> RD/WR Setup (TYP[3:0] =0101B, AWR=100BH) ....... 217 INDEX Setting of CS -> RD/WR Setup and of RD/WR -> CS Hold (TYP[3:0]=0000B,AWR=000BH) .......................................................... 212 RDY Ready/Busy Signal (RDY/BUSYX)................... 552 Reactivation When Reactivation is Disabled .................. 315, 317 Read Read/Reset Command ...................................... 549 Read -> Write Timing Read -> Write Timing (TYP[3:0]=0000B,AWR=0048H).......... 206 Reading Reading from the Prefetch Buffer ...................... 220 Reading the I/O Map ........................................ 582 Reading/Resetting Flash Memory ...................... 558 Ready Ready/Busy Signal (RDY/BUSYX)................... 552 REALOS Bit Search Module (Used by REALOS) ................. 3 Receive Data Example of Receive Data.................................. 469 Recommended ADCT Register Recommended ADCT Register Value ................ 374 Register 0 Detection Data Register (BSD0) ..................... 358 1 Detection Data Register (BSD1) ..................... 358 10-bit Slave Address Mask Register (ITMK) ...... 458 10-bit Slave Address Register (ITBA)................ 457 16-bit Free-running Timer Registers .................. 279 16-bit Reload Register (TMRLR) ...................... 291 16-bit Reload Timer Registers ........................... 287 16-bit Timer Register (TMR) ............................ 291 7-bit Slave Address Mask Register (ISMK) ........ 461 7-bit Slave Address Register (ISBA).................. 460 8-bit D/A Converter Registers ........................... 380 A/D Converter Registers................................... 366 Address Register Specifications......................... 503 Base Clock Division Setting Register 0 (DIVR0)............................................. 125 Base Clock Division Setting Register 1 (DIVR1)............................................. 126 Bit Configuration of Enable Interrupt Request Register (ENIRn) ................................ 345 Bit Configuration of External Level Register (ELVRn) .......................................................... 347 Bit Configuration of the Control Status Register (ADCS1)............................................ 367 Bit Configuration of the Control Status Register (ADCS2)............................................ 370 Bit Configuration of the Conversion Time Setting Register (ADCT) ................................ 373 Bit Configuration of the External Interrupt Request Register (EIRRn) ................................ 346 Bit Configuration of the Hold Request Cancellation Request Register (HRCL) .....................331 Bit Configuration of the Interrupt Control Register (ICR)..................................................329 Bit Search Module Registers..............................357 Bus Control Register (IBCR) .............................448 Bus Status Register (IBSR)................................445 CCR (Condition Code Register) ...........................58 Change Point Detection Data Register (BSDC) ..........................................................359 Clock Control Register (ICCR) ..........................455 Clock Disable Register (IDBL) ..........................463 Clock Source Control Register (CLKR) ..............120 Compare Register (OCCP0 to OCCP7)...............434 Configuration of Area Configuration Registers 0 to 7 (ACR0 to ACR7).................................169 Configuration of ASR0 to ASR3 (Area Select Registers).........................168 Configuration of AWR0 to AWR3 (Area Wait Registers)...........................175 Configuration of General Control Register 10 ..........................................................310 Configuration of General Control Register 20 ..........................................................313 Configuration of Interrupt Control Register (ICR) ............................................................75 Configuration of PPG Cycle Setting Register (PCSR) ...............................................307 Configuration of PPG Duty Setting Register (PDUT) ..............................................308 Configuration of PPG Timer Register (PTMR) ..........................................................309 Configuration of the Chip Select Enable Register (CSER)...............................................183 Configuration of the Flash Control/Status Register (FLCR) (CPU Mode) ...........................540 Configuration of the Flash Memory Wait Register (FLWC)..............................................543 Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR3) ............................181 Configuration of the Terminal and Timing Control Register (TCR) ....................................184 Configurations of Control Status Registers..........303 Control Status Register (TMCSR) ......................289 Correspondence between the Memory Space Area and Peripheral Resource Registers ...............583 Counter Control Register High/Low ch0 (CCR H/L ch0)....................................252 Counter Control Register High/Low ch1 (CCR H/L ch1)....................................256 Counter Status Register 0/1 (CSR0/1).................256 DACR0 (D/A Control Register 0) ......................383 DACR1 (D/A Control Register 1) ......................383 DACR2 (D/A Control Register 2) ......................383 DADR0 (D/A Data Register 0) ..........................382 DADR1 (D/A Data Register 1) ..........................382 DADR2 (D/A Data Register 2) ..........................382 637 INDEX Data Direction Registers (DDR) ........................ 235 Data Internal RAM/Instruction Internal RAM Access Restriction Function Registers .............. 576 Data Register (IDAR) ....................................... 462 Delayed Interrupt Module Register (DICR: Delayed Interrupt Module Register) ................... 354 Detailed Explanation of the Peripheral Stop Control Registers ............................................ 156 Details of the Interrupt Controller Registers ........ 328 Details of the Registers for the External Interrupt and NMI Controller ................................... 344 Detection Result Register (BSRR) ..................... 359 DMAC Interrupt Source Clear Register (SRCL) .......................................................... 418 DRLR: Data RAM Limit Control Register (D-Bus RAM Limit Control Register) .......................................................... 577 Explanation of the Main Clock Oscillation Stabilization Wait Timer Register ......... 150 External Interrupt and NMI Controller Registers ............................................ 342 FRLR: Instruction RAM Limit Control Register (F-Bus RAM Limit Control Register) .......................................................... 578 General-Purpose Registers .................................. 56 I2C Interface Registers...................................... 441 Initial Values and Functions of the Port Function Registers (PFRs) ................................. 238 Input Capture Control Registers (ICS01 and ICS23) .............................. 428 Input Capture Data Register (IPCP0 to IPCP3) .......................................................... 428 Input Capture Module Registers......................... 426 Interrupt Controller Registers ............................ 325 Interrupt Level Mask (ILM) Register ................... 74 List of External Bus Interface Registers.............. 166 List of Peripheral Stop Control Registers ............ 155 List of Registers of the 8/16-bit Up/Down Counters/Timers.................................. 248 Mapping of Interrupt Control Register (ICR) ........ 75 Mode Register (MODR) ..................................... 92 Multiply & Divide Register ................................. 63 Notes of PS Register........................................... 35 Notes on Setting Registers................................. 475 Oscillation Control Register (OSCCR) ............... 128 Output Compare Module Registers .................... 432 Output Control Register (OCS0 to OCS7)........... 434 Overview of Flash Memory Registers ................ 539 Overview of the A/D Converter Registers........... 364 Overview of the Data Registers (ADTHx and ADTLx) ......................... 375 Overview of the DMAC Registers ..................... 473 Overview of the I2C Interface Registers.............. 444 Port Data Registers (PDR)................................. 234 Port Function Registers (PFR) ........................... 237 PPG Timer Registers ........................................ 302 Pull-up Control Registers (PCR) ........................ 236 638 Recommended ADCT Register Value................ 374 Register for the Delayed Interrupt Module.......... 353 Register Overview of External Bus Interface ...... 167 Registers of the PPG Timer............................... 299 Reload Register (UTIMR) ................................ 271 Reload/Compare Register 0/1 (RCR 0/1)............ 258 Reset Source Register/Watchdog Timer Control Register (RSRR) ................................. 112 SCR (System Condition Code Register) ............... 60 Serial Control Register (SCR) ........................... 391 Serial I/O Interface (SIO) Registers ................... 411 Serial I/O Prescaler Control Register (CDCR) ......................................................... 417 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR)................................. 394 Serial Mode Control Status Register (SMCS) ......................................................... 413 Serial Mode Register (SMR) ............................. 390 Serial Shift Data Register (SDR) ....................... 416 Serial Status Register (SSR).............................. 395 Setting of Temporary Stopping by Writing to the Control Register (Set Independently for Each Channel or all Channels Simultaneously) .................................. 511 SIO Test Register (SES) ................................... 416 Standby Control Register (STCR)...................... 114 Table Base Register (TBR) ................................. 79 TBR (Table Base Register) ................................. 61 Timebase Counter Clear Register (CTBR).......... 119 Timebase Counter Control Register (TBCR) ...... 117 Timer Control Status Register (TCCS) ............... 281 Timer Data Register (TCDT) ............................ 280 Transfer Count Registers and Reload Operation ......................................................... 505 UART Registers .............................................. 388 Up/Down Count Register 0/1 (UDCR 0/1) ......... 258 U-TIMER Control Register (UTIMC)................ 272 U-TIMER Registers ......................................... 269 U-TIMER Registers (UTIM)............................. 270 Watch Timer Control Register........................... 144 Watchdog Reset Postpone Register (WPR)......... 124 Writing Data to the Up/Down Count Register (UDCR) ............................................. 264 Releasing Releasing the Bus Right.................................... 228 Reload Reload and Compare Functions ......................... 261 Up/Down Counting with an Arbitrary Width when the Reload and Compare Functions are Started ............................................... 262 Reload Operation Reload Operation ............................................. 501 Transfer Count Registers and Reload Operation ......................................................... 505 Reload Register Reload Register (UTIMR) ................................ 271 INDEX Reload/Compare Register Reload/Compare Register 0/1 (RCR 0/1)............ 258 Reset INIT Pin Input (Settings Initialization Reset Pin) ............................................................ 96 Normal Reset Operation ................................... 102 Operation Initialization Reset (RST) .................... 95 Operation Initialization Reset (RST) Clear Sequence.............................................. 98 Overview of Reset (Device Initialization)............. 94 Read/Reset Command ...................................... 549 Reset Source Register/Watchdog Timer Control Register (RSRR) ................................. 112 Setting Initialization Reset (INIT) Clear Sequence.............................................. 98 Settings Initialization Reset (INIT) ...................... 95 Software Reset (STCR: SRST Bit Writing) .......... 97 Synchronous Reset Operation............................ 102 Watchdog Reset ................................................. 97 Watchdog Reset Postpone Register (WPR)......... 124 Reset Operation Normal Reset Operation ................................... 102 Synchronous Reset Operation............................ 102 Reset Source Register Reset Source Register/Watchdog Timer Control Register (RSRR) ................................. 112 Resetting Reading/Resetting Flash Memory ...................... 558 Restarting Sector Erase Restarting Sector Erase in Flash Memory ........... 565 Restore Save/Restore Processing ................................... 362 Restriction Restriction on Section Types ............................... 42 Restrictions on Prefetch-enabled Areas .............. 221 RETI Operation of RETI Instruction ............................. 89 Return Return from EIT ................................................ 72 Return from Standby ........................................ 348 Return from Standby Mode (Sleep/Stop) ............ 338 Return Pointer RP (Return Pointer)............................................ 62 ROM FR-CPU ROM Mode (32 Bits,Read only) .......... 545 RP RP (Return Pointer)............................................ 62 RSRR Reset Source Register/Watchdog Timer Control Register (RSRR) ................................. 112 RST Operation Initialization Reset (RST) .................... 95 Operation Initialization Reset (RST) Clear Sequence.............................................. 98 S Save Save/Restore Processing....................................362 Scan Conversion Mode Scan Conversion Mode .....................................377 SCR SCR (System Condition Code Register)................60 Serial Control Register (SCR) ............................391 SDR Serial Shift Data Register (SDR) ........................416 Section Sections .............................................................41 Section Type Restriction on Section Types ...............................42 Sector Address Table Sector Address Table of Flash Memory ..............537 Sector Erase Restarting Sector Erase in Flash Memory............565 Sector Erase .....................................................550 Sector Erase Procedure......................................562 Temporarily Stopping Sector Erase in Flash Memory..............................................564 Selecting Selecting an Oscillation Stabilization Wait Time...................................................100 Selecting a Clock Selecting a Clock for the UART.........................399 Selecting Counting Mode Selecting Counting Mode ..................................259 Selection Selection of Source Clock .................................104 Selection of the Transfer Sequence.....................497 Serial Control Register Serial Control Register (SCR) ............................391 Serial I/O Interface Block Diagram of the Serial I/O Interface (SIO) ..........................................................412 Overview of Serial I/O Interface (SIO) Operation............................................419 Overview of the Serial I/O Interface (SIO) ..........410 Serial I/O Interface (SIO) Registers ....................411 Serial I/O Interface Operating Modes .................411 States of Serial I/O Interface Operation...............420 Serial I/O Prescaler Control Register Serial I/O Prescaler Control Register (CDCR) ..........................................................417 Serial Input Data Register Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) .................................394 Serial Mode Control Status Register Serial Mode Control Status Register (SMCS) ..........................................................413 639 INDEX Serial Mode Register Serial Mode Register (SMR) ............................. 390 Serial Output Data Register Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) ................................. 394 Serial Programming Connection Basic Configuration of MB91F355A/353A/356B Serial Programming Connection ........... 568 Examples of Serial Programming Connections .......................................................... 570 Notes of MB91F355A/F353A/F356B/F357B Serial Programming Connections ................... 573 Serial Shift Data Register Serial Shift Data Register (SDR)........................ 416 Serial Status Register Serial Status Register (SSR) .............................. 395 SES SIO Test Register (SES).................................... 416 Setting Setting Initialization Reset (INIT) Clear Sequence .............................................. 98 Setting of Temporary Stopping by Writing to the Control Register (Set Independently for Each Channel or all Channels Simultaneously) .................................. 511 Setting the Divide-By Rate................................ 110 Setting the External Bus...................................... 33 Settings Initialization Reset (INIT)....................... 95 Setting Initialization Wait Time after Setting Initialization ................. 106 Setting of CS -> RD/WR Setup Setting of CS -> RD/WR Setup and of RD/WR -> CS Hold (TYP[3:0]=0000B,AWR=000BH) .......................................................... 212 Setting of RD/WR -> CS Hold Setting of CS -> RD/WR Setup and of RD/WR -> CS Hold (TYP[3:0]=0000B,AWR=000BH) .......................................................... 212 Setting Register Notes on Setting Registers................................. 475 Shift Clock Shift Clock ...................................................... 419 Shift Operation Shift Operation Start/Stop Timing and I/O Timing ............................................... 421 SIDR Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) ................................. 394 Simple Waveforms Examples of Operation (Simple Waveforms) ...... 529 Simulator Simulator Debugger............................................ 43 640 Simultaneous Occurrence Simultaneous Occurrence of a DMA Transfer Request and an External Hold Request .............. 507 Single Conversion Mode Single Conversion Mode .................................. 376 Single-chip Bus Mode 0 (Single-chip Mode).......................... 91 SIO Block Diagram of the Serial I/O Interface (SIO) ......................................................... 412 Overview of Serial I/O Interface (SIO) Operation ........................................... 419 Overview of the Serial I/O Interface (SIO) ......... 410 Serial I/O Interface (SIO) Registers ................... 411 SIO..................................................................... 4 SIO Test Register SIO Test Register (SES) ................................... 416 Slave Address 10-bit Slave Address Mask Register (ITMK) ...... 458 10-bit Slave Address Register (ITBA)................ 457 7-bit Slave Address Mask Register (ISMK) ........ 461 7-bit Slave Address Register (ISBA).................. 460 Example of Slave Address and Data Transfer ......................................................... 468 Slave Address Mask ......................................... 465 Slave Address Detection Slave Address Detection ................................... 465 Sleep Return from Standby Mode (Sleep/Stop) ............ 338 Sleep Mode Notes on DMA Transfer in Sleep Mode ............. 515 Sleep Mode ..................................................... 138 SMCS Serial Mode Control Status Register (SMCS) ......................................................... 413 SMR Serial Mode Register (SMR) ............................. 390 SODR Serial Input Data Register (SIDR)/Serial Output Data Register (SODR)................................. 394 Software Request Software Request ............................................. 496 Software Reset Software Reset (STCR: SRST Bit Writing) .......... 97 Source Sources of an Oscillation Stabilization Wait ......... 99 Source Clock Selection of Source Clock................................. 104 Source Oscillation Input Source Oscillation Input at Power-on ................... 33 Specification Specification of the -K lib Option when Character String Operation Functions are Used....... 40 INDEX SRCL DMAC Interrupt Source Clear Register (SRCL) .......................................................... 418 SRST Software Reset (STCR: SRST Bit Writing) .......... 97 SSP SSP (System Stack Pointer) ................................ 62 System Stack Pointer (SSP) ................................ 77 SSR Serial Status Register (SSR).............................. 395 Stack Interrupt Stack ................................................... 78 Mapping of the Stack to the Little-endian Area ............................................................ 40 Standby Return from Standby ........................................ 348 Standby Control Register Standby Control Register (STCR)...................... 114 Standby Mode Return from Standby Mode (Sleep/Stop) ............ 338 Standby Operation Normal and Synchronous Standby Operations .......................................................... 142 Start Shift Operation Start/Stop Timing and I/O Timing ............................................... 421 START Condition............................................ 464 Starting Starting from a Temporary Stop ........................ 508 Starting External Access Basic Conditions for Starting External Access Using Prefetch .......................................................... 218 Starting Transfer Starting Transfer .............................................. 508 Start-stop Synchronization Asynchronous (Start-stop Synchronization) Mode ................................................. 400 State Device Operating States.................................... 135 Device States................................................... 134 Explanation of Terms Used in the Pin State Lists................................................... 597 Overview of Device State Control ..................... 133 Pin States in Each CPU State ............................ 598 States of Serial I/O Interface Operation .............. 420 Status Automatic Algorithm Execution Status .............. 546 Bit Configuration of the Control Status Register (ADCS1)............................................ 367 Bit Configuration of the Control Status Register (ADCS2)............................................ 370 Bus Status Register (IBSR) ............................... 445 Configuration of the Flash Control/Status Register (FLCR) (CPU Mode) ...........................540 Configurations of Control Status Registers..........303 Control Status Register (TMCSR) ......................289 Counter Status Register 0/1 (CSR0/1).................256 PS (Program Status)............................................57 Serial Mode Control Status Register (SMCS) ..........................................................413 Serial Status Register (SSR) ..............................395 Timer Control Status Register (TCCS)................281 STCR Software Reset (STCR: SRST Bit Writing) ...........97 Standby Control Register (STCR) ......................114 Step Step/Block Transfer 2-Cycle Transfer Fly-by Transfer ..............................................500 Step Trace Trap Operation of Step Trace Trap...............................88 Step Transfer Step Transfer....................................................500 Step/Block Transfer Step/Block Transfer 2-Cycle Transfer.................499 Stop Return from Standby Mode (Sleep/Stop).............338 Shift Operation Start/Stop Timing and I/O Timing................................................421 Starting from a Temporary Stop .........................508 STOP Condition ...............................................464 Transfer Stop Requests from Peripheral Circuits...............................................513 Stop Mode Stop Mode .......................................................140 Wait Time after Returning from Stop Mode ........107 Stopping Setting of Temporary Stopping by Writing to the Control Register (Set Independently for Each Channel or all Channels Simultaneously)...................................511 Store Load and Store ...................................................53 Structure Structure Assignment ..........................................39 Structure of the Internal Architecture....................51 Subclock Note for the Case of Using No Subclock ...............33 Wait Time after Switching From the Subclock to the Main Clock .........................................107 Subclock Switching Subclock Switching ............................................34 Successive Access Basic Timing (For Successive Accesses) (TYP[3:0]=0000B,AWR=0008H) ..........205 641 INDEX Suppressing Suppressing DMA ............................................ 506 Switching Wait Time after Switching From the Subclock to the Main Clock......................................... 107 Switching Shared Port Switching Shared Port Functions ......................... 35 Synchronization Asynchronous (Start-stop Synchronization) Mode ................................................. 400 Synchronous Normal and Synchronous Standby Operations .......................................................... 142 Synchronous Reset Operation............................ 102 Synchronous Write Enable Output Timing Synchronous Write Enable Output Timing (TYP[3:0]=0000B,AWR=0000H) .......... 210 SYSCLK MCLK and SYSCLK.......................................... 33 System Condition Code Register SCR (System Condition Code Register) ............... 60 System Configuration System Configuration of the Flash Microcontroller Programmer ........................................ 572 System Construction Example of System Construction (Using Mode 1)................................... 407 System Stack Pointer SSP (System Stack Pointer)................................. 62 System Stack Pointer (SSP)................................. 77 T Table Base Register Table Base Register (TBR).................................. 79 TBR (Table Base Register).................................. 61 TBCR Timebase Counter Control Register (TBCR) ....... 117 TBR Table Base Register (TBR).................................. 79 TBR (Table Base Register).................................. 61 TCCS Timer Control Status Register (TCCS) ............... 281 TCDT Timer Data Register (TCDT)............................. 280 TCR Configuration of the Terminal and Timing Control Register (TCR).................................... 184 Temporarily Stop Erase Temporarily Stop Erase .................................... 551 Temporarily Stopping Sector Erase Temporarily Stopping Sector Erase in Flash Memory ............................................. 564 642 Temporary Stop Starting from a Temporary Stop ........................ 508 Temporary Stopping Optional Clear and Temporary Stopping of a Prefetch Access ............................................... 219 Setting of Temporary Stopping by Writing to the Control Register (Set Independently for Each Channel or all Channels Simultaneously) .................................. 511 Terminal and Timing Control Register Configuration of the Terminal and Timing Control Register (TCR) ................................... 184 Time Division I/O Interface Control Signals on the Time Division I/O Interface............................................. 189 Time Interval Time Intervals for Main Clock Oscillation Stabilization Wait Timer...................... 149 Timebase Counter Timebase Counter ............................................ 129 Timebase Counter Clear Register Timebase Counter Clear Register (CTBR).......... 119 Timebase Counter Control Register Timebase Counter Control Register (TBCR) ...... 117 Timer Block Diagram of the 8/16-bit Up/Down Counters/Timers (ch0)......................... 250 Characteristics of the 8/16-bit Up/Down Counters/Timers ................................. 247 List of Registers of the 8/16-bit Up/Down Counters/Timers ................................. 248 Other Interval Timers and Counters ....................... 4 Overview of the 8/16-bit Up/Down Counters/Timers ................................. 246 Various Timers .................................................... 3 Timer Control Status Register Timer Control Status Register (TCCS) ............... 281 Timer Data Register Timer Data Register (TCDT) ............................ 280 Timing Timing for Clearing Interrupts During DMA ...... 510 Timing of 16-bit Free-running Timer Counting ......................................................... 285 Timing of 16-bit Output Compare Operation ...... 438 Timing of Clearing of the 16-bit Free-running Timer................................................. 285 Timing of DACK Pin Output ............................ 520 Timing of DREQx Pin Input ............................. 530 Timing of the DEOP Pin Output........................ 520 Timing of the DREQ Pin Input for Continuing Transfer Over the Same Channel .......... 520 Timing of the DSTP Pin Input........................... 520 Timing Chart Interrupt Sources and Timing Chart ................... 318 INDEX TMCSR Control Status Register (TMCSR) ..................... 289 TMR 16-bit Timer Register (TMR) ............................ 291 TMRLR 16-bit Reload Register (TMRLR) ...................... 291 Transfer Transfer Between External I/O and External Memory ............................................. 521 Transfer Request Acceptance and Transfer ......... 509 Transfer Address Transfer Address.............................................. 494 Transfer Count Transfer Count and Transfer End....................... 495 Transfer Count Register Transfer Count Registers and Reload Operation .......................................................... 505 Transfer End Transfer Count and Transfer End....................... 495 Transfer End.................................................... 512 Transfer Mode Transfer Mode ................................................. 493 Transfer Request Acceptance Transfer Request Acceptance and Transfer ......... 509 Transfer Sequence Selection of the Transfer Sequence .................... 497 Transfer Source Selection [Bits 28 to 24] IS4 to 0 (Input Select): Transfer Source Selection .................... 478 Transfer Stop Request Transfer Stop Requests from Peripheral Circuits .............................................. 513 Transfer Type Transfer Type .................................................. 494 Two or More Sectors Note on Specifying Two or More Sectors ........... 562 U UART Block Diagram of the UART............................. 389 Operating Modes of the UART.......................... 399 Overview of the UART .................................... 386 Selecting a Clock for the UART ........................ 399 UART................................................................. 4 UART Registers .............................................. 388 UART Register UART Registers .............................................. 388 UDCR Up/Down Count Register 0/1 (UDCR 0/1) ......... 258 Writing Data to the Up/Down Count Register (UDCR) ............................................. 264 Undefined Instruction Exception Operation of Undefined Instruction Exception ...... 88 Underflow Operation Underflow Operation ........................................293 Unit Unit for One Prefetch Access Operation..............219 Unused Input Pin Unused Input Pins...............................................32 Up/Down Count Register Up/Down Count Register 0/1 (UDCR 0/1) ..........258 Writing Data to the Up/Down Count Register (UDCR)..............................................264 Up/Down Counting Up/Down Counting with an Arbitrary Width when the Reload and Compare Functions are Started ................................................262 Updating Clearing/Updating the Prefetch Buffer ................220 Use Use of the Double Type and Long Double Type ............................................................40 Used Bit Search Module (Used by REALOS) ..................3 Explanation of Terms Used in the Pin State Lists ...................................................597 Pins Used for Fujitsu Standard Serial Onboard Writing ...............................................569 Specification of the -K lib Option when Character String Operation Functions are Used .......40 USP USP (User Stack Pointer) ....................................62 UTIM U-TIMER Registers (UTIM) .............................270 UTIMC U-TIMER Control Register (UTIMC) ................272 U-TIMER Block Diagram of the U-TIMER ........................269 Overview of the U-TIMER ................................268 U-TIMER Registers ..........................................269 U-TIMER Registers (UTIM) .............................270 U-TIMER Control Register U-TIMER Control Register (UTIMC) ................272 U-TIMER Register U-TIMER Registers ..........................................269 U-TIMER Registers (UTIM) .............................270 U-TIMER Reload Value Example of Setting Baud Rates and U-TIMER Reload Values ................................................409 UTIMR Reload Register (UTIMR) .................................271 V Various Timer Various Timers.....................................................3 643 INDEX Vector Table EIT Vector Table ............................................... 80 W Wait Time Wait Time after Changing the PLL Multiply-by Rate ................................................... 106 Wait Time after Enabling a PLL ........................ 106 Wait Time after Power-On ................................ 106 Wait Time after Returning from Stop Mode........ 107 Wait Time after Setting Initialization ................. 106 Wait Time after Switching From the Subclock to the Main Clock......................................... 107 Watch Timer Block Diagram of the Watch Timer.................... 143 Operation of the Watch Timer ........................... 148 Precautions for Using the Watch Timer .............. 148 Watch Timer Interrupt ...................................... 146 Watch Timer Control Register Watch Timer Control Register ........................... 144 Watchdog Reset Watchdog Reset ................................................. 97 Watchdog Reset Postpone Register Watchdog Reset Postpone Register (WPR) ......... 124 Watchdog Timer Control Register Reset Source Register/Watchdog Timer Control Register (RSRR) ................................. 112 When Reactivation is Disabled When Reactivation is Disabled .................. 315, 317 When Reactivation is Enabled When Reactivation is Enabled ................... 316, 317 644 With External Wait With External Wait (TYP[3:0]=0101B,AWR=1008H).......... 216 Without External Wait Without External Wait (TYP[3:0]=0100B and AWR=0008H) ......................................................... 215 Word Access Word Access ................................................... 201 Word Alignment Word Alignment ................................................ 65 WPR Watchdog Reset Postpone Register (WPR)......... 124 WR CS -> RD/WR Setup (TYP[3:0] =0101B, AWR=100BH) ....... 217 Setting of CS -> RD/WR Setup and of RD/WR -> CS Hold (TYP[3:0]=0000B,AWR=000BH) ......................................................... 212 Write Overview of Flash Memory Write/Erase ............ 557 Program (Write)............................................... 549 Write -> Write Timing (TYP[3:0]=0000B,AWR=0018H).......... 207 Write Procedure............................................... 559 Writing Data Notes on Writing Data...................................... 559 Writing Data to Flash Memory.......................... 559 Writing Data to the Up/Down Count Register (UDCR) ............................................. 264 CM71-10121-3E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL FR60 32-BIT MICROCONTROLLER MB91350A Series HARDWARE MANUAL November 2007 the third edition Published FUJITSU LIMITED Edited Strategic Business Development Dept Electronic Devices