PI6C3Q991, PI6C3Q993 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 3.3V Programmable Skew PLL Clock Driver SuperClock Features Description PI6C3Q99X family provides following products: PI6C3Q991: 32-pin PLCC version PI6C3Q993: 28-pin QSOP version Inputs are 5V I/O Tolerant 4 pairs of programmable skew outputs Low skew: 200ps same pair; 250ps all outputs Selectable positive or negative edge synchronization: Excellent for DSP applications Synchronous output enable Output frequency: 3.75 MHz to 85 MHz 2x, 4x, 1/2, and 1/4 outputs 3 skew grades: 3-level inputs for skew and PLL range control PLL bypass for DC testing External feedback, internal loop filter 12mA balanced drive outputs Low Jitter: < 200ps peak-to-peak Industrial temperature range Pin-to-pin compatible with IDT QS5V991 and QS5V993 Available in 32-pin PLCC and 28-pin QSOP The PI6C3Q99X family is a high fanout 3.3V PLL-based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The PI6C3Q991 has 8 programmable skew outputs in 4 banks of 2, while the PI6C3Q993 has 6 programmable skew outputs and 2 zero skew outputs. Skew is controlled by 3-level input signals that may be hardwired to appropriate HIGH-MID-LOW levels. When the GND/sOE pin is held low, all the outputs are synchronously enabled. However, if GND/sOE is held high, all the outputs except 3Q0 and 3Q1 are synchronously disabled. Furthermore, when the V CCQ /PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When VCCQ /PE is held low, all the outputs are synchronized with the negative edge of REF. Both devices have LVTTL outputs with 12mA balanced drive outputs. Pin Configurations PI6C3Q993 3Q0 FS VCCQ REF GND TEST 2F1 PI6C3Q991 5 4 3 2 1 32 31 30 29 6 7 8 28 27 26 9 10 11 12 32-Pin J 25 24 23 22 13 21 14 15 16 17 18 19 20 FS 2F0 GND/sOE 1F1 1F0 VCCN 1Q0 1Q1 GND GND 3F0 3F1 VCCQ/PE VCCN 4Q1 4Q0 GND 3Q1 3Q0 VCCN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-Pin Q 28 27 26 25 24 GND 23 22 21 20 19 18 17 16 15 1F1 TEST 2F1 2F0 GND/sOE 1F0 VCCN 1Q0 1Q1 GND GND 2Q0 2Q1 VCCN FB VCCN 2Q1 2Q0 FB 3Q1 3Q0 3F1 4F0 4F1 VCCQ/PE VCCN 4Q1 4Q0 GND GND REF VCCQ 1 PS8449A 10/09/00 PI6C3Q991, PI6CQ3993 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Logic Block Diagrams PI6C3Q993 PI6C3Q991 GND/sOE GND/sOE Skew Select 3 3 Skew Select 1Q1 3 1F1:0 VCCQ/PE Skew Select REF 1Q0 3 2Q1 Skew Select 3 3 REF 3Q1 Skew Select 3 3 2Q1 2F1:0 Skew Select 3 FS 2Q0 3 PLL 3 3F1:0 FS 3 FB 3Q0 3 1F1:0 Skew Select 2F1:0 PLL FB 1Q1 3 VCCQ/PE 2Q0 3 1Q0 3Q0 3Q1 3 3F1:0 4Q0 4Q0 4Q1 4Q1 4F1:0 Pin Descriptions Pin Name Type Functional D e s cription REF IN Reference Clock input FB IN Feedback Input TEST(1) IN When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see table 3) remain in effect. Set LO W for normal operation. GND/sO E(1) IN Synchronous O utput Enable. When HIGH, it stops clock outputs (except 3Q 0 and 3Q 1) in a LO W state - 3Q 0 or 3Q 1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and GND/sO E is HIGH, the nF [1:0] pins act as output disable controls for individual banks when nF [1:0] = LL. Set GND/sO E LO W for normal operation. VCCQ/PE IN Selectable positive or negative edge control. When LO W/HIGH the outputs are synchronized with the negative/positive edge of the reference clock. nF [1:0] IN 3- level inputs for selecting 1 of 9 skew taps or frequency range. FS IN Selects appropriate oscillator circuit based on anticipated frequency range. See table 2 nQ [1:0] O UT 4 output banks of 2 outputs, with programmable skew. O n the PI6C3Q 993 4Q 1:0 are fixed zero skew outputs. VCCN PWR Power supply for output buffers VCCQ PWR Power supply for phase locked loop and other internal circuitry GND PWR Ground Note: 1. When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] =LL functioning as an output disable control for individual output banks. Skew selections (see Table 3) remain in effect unless nF[1:0] = LL. 2 PS8449A 10/09/00 PI6C3Q991, PI6C3Q993 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Programmable Skew External Feedback Output skew with respect to the REF input is adjustable to compensate for PCB trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit tU which is of the order of a nanosecond (see Table 2). There are 9 skew configurations available for each output pair. These configurations are choosen by the nF1:0 control pins. In order to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW) are used, they are intended for but not restricted to hard-wiring. Undriven 3-level inputs default to the MID level. Where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. The Skew Selection Table (Table 3) shows how to select specific skew taps by using the nF1:0 control pins. By providing external feedback, the PI6C3Q99X family gives users flexibility with regard to skew adjustment. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes. Table 2. PLL Programmable Skew Range and Resolution Table FS = LOW FS = M ID FS = HIGH Timing unit calculation (tU) 1/(44xFNOM) 1/(26xFNOM) 1/(16xFNOM) VCO frequency range (FNOM)(1,2) 15 to 35 MHz 25 to 60 MHz 40 to 85 MHz Skew adjustment range(3) Max. adjustment ±9.09ns ±49° ±14% ±9.23ns ±83° ±23% Example 1, FNOM = 15 MHz tU = 1.52ns Example 2, FNOM = 25 MHz tU = 0.91ns tU = 1.54ns Example 3, FNOM = 30 MHz tU = 0.76ns tU = 1.28ns ±9.38ns ±135° ±37% Example 4, FNOM = 40 MHz tU = 0.96ns tU = 1.56ns Example 5, FNOM = 50 MHz tU = 0.77ns tU = 1.25ns Example 6, FNOM = 80 MHz Comme nts ns Phase degrees % of cycle time tU = 0.78ns Notes: 1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FS value based on input frequency range allows the PLL to operate in its sweet spot where jitter is lowest. 2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided output as the FB input. 3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed 4tU in addition to whatever skew value is programmed for those outputs. Max adjustment range applies to output pairs 3 and 4 where ±6 tU skew adjustment is possible and at the lowest FNOM value. 3 PS8449A 10/09/00 PI6C3Q991, PI6CQ3993 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Table 3. Skew Selection Table for Output Pairs nF1:0 Ske w (Pair #1, #2) Ske w (Pair #3) Ske w (Pair #4)(1) LL(2) 4tU Divide by 2 Divide by 2 LM 3tU 6tU 6tU LH 2tU 4tU 4tU ML 1tU 2tU 2tU MM Zero skew Zero skew Zero skew MH +1tU +2tU +2tU HL +2tU +4tU +4tU HM +3tU +6tU +6tU HH +4tU Divide by 4 Inverted(3) Notes: 1. Programmable skew on pair #4 is not applicable for the PI6C993. 2. LL disables outputs if TEST = MID and GND/ sOE = HIGH. 3. When pair #4 is set to HH (inverted), GND/sOE disables pair #4 HIGH when VCCQ /PE = HIGH, GND/sOE disables pair #4 LOW when VCCQ / PE = LOW Table 4. Absolute Maximum Ratings Supply Voltage to ground ........................................................ 0.5V to 7.0V DC input Voltage VI .................................................................... 0.5V to VCC + 0.5V Maximum Power Dissipation at TA = 85°C, PLCC ......................... 0.80 watts QSOP ....................... 0.66 watts TSTG Storage temperature ....................................................65°C to 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 5. Recommended Operating Range Symbol D e s cription PI6C3Q99X PI6C3Q99X-5 (Indus trial) PI6C399X-2 (Comme rcial) M in. M ax. M in. M ax. Units VCC Power Supply Voltage 3.0 3.6 3.0 3.6 V TA Ambient O perating Temperature 40 85 0 70 °C 4 PS8449A 10/09/00 PI6C3Q991, PI6C3Q993 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Table 6. DC Characteristics Over Operating Range Symbol Parame te r Te s t Condition M in. VIH Input HIGH Voltage Guaranteed Logic HIGH (REF, FB inputs only) 2.0 VIL Input LOW Voltage Guaranteed Logic LOW (REF, FB inputs only) VIHH Input HIGH Voltage(1) 3- Level Inputs Only VCC 0.6 VIMM Input MID Voltage(1) 3- Level Inputs Only VCC/2 0.3 VILL Input LOW Voltage(1) 3- Level Inputs Only 0.6 IIN Input Leakage Current (REF, FB inputs only) VIN = VCC or GND, VCC = Max. 5 I3 3- Level Input DC Current (TEST, FS, nF1:0) VIN = VCC VIN = VCC/2 VIN = GND M ax. Units 0.8 V VCC/2 +0.3 HIGH Level MID Level LOW Level 200 50 200 IPU Input Pull- Up Current (VCCQ/PE) VCC = Max., VIN = GND 100 IPD Input Pull- Down Current (GND/sOE) VCC = Max., VIN = VCC 100 VOH Output HIGH Voltage VCC = Min., IOH = 12mA VOL Output LOW Voltage VCC = Min., IOL = 12mA µA 2.2 V 0.55 Note: 1. These inputs are normally wired to VCC , GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are switched, the function and timing of the outputs may glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved. Table 7. Power Supply Characteristics Symbol Parame te r Te s t Condition Typ. M ax. Units ICCQ Quiescent Power Supply Current VCC = Max., TEST = Mid., REF = LO W, GND/sOE = LOW, All outputs unloaded 8.0 15 mA ∆ICC Power Supply Current per Input HIGH(1) VCC = Max., VIN = 3.0V 1.0 30 µA ICCD Dynamic Power Supply Current per Output(1) VCC = Max., CL = 0pF 55 90 µA/MHz IC Total Power Supply Current(1) VCC = 3.3V, FREF = 20 MHz, CL = 160pF(2) 29 IC Total Power Supply Current(1) 160pF(2) 42 IC Total Power Supply Current(1) VCC = 3.3V, FREF = 66 MHz, CL = 160pF(2) 76 VCC = 3.3V, FREF = 33 MHz, CL = mA Notes: 1. Guaranteed by characterization but not production tested. 2. For 8 outputs each loaded with 20pF. 5 PS8449A 10/09/00 PI6C3Q991, PI6CQ3993 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Table 8. Capacitance (TA = 25°C, f = 1 MHz, VIN = 0V) QSOP CIN PLCC Typ. M ax. Typ. M ax. 4 6 5 7 Units pF VCC 150Ω Output 20pF 150Ω ≤1ns tORISE ≤1ns 3.0V 2.0V Vth=1.5V 0.8V 0V 2.0V 0.8V tOFALL tPWH tPWL LVTTL Output Waveform LVTTL Input Test Waveform AC Test Loads and Waveforms 6 PS8449A 10/09/00 PI6C3Q991, PI6C3Q993 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Table 9. Switching Characteristics Over Operating Range PI6C3Q991-2 PI6C3Q993-2 D e s cription Symbol FNOM tRPWH tRPWL tU M in. VCO frequency range tDEV tPD M ax. M in. see Table 2 3.0 3.0 3.0 REF pulse 3.0 3.0 3.0 Programmable skew time unit see Table 3 (1,2,3) Zero output skew (all outputs) CL = O utput skew (rise- rise, fall- fall, same class outputs) (1,5) O utput skew (rise- fall, nominal- inverted, divided- divided) O utput skew (rise- rise, fall- fall, different class outputs) (1,5) O utput skew (rise- fall, nominal- divided, divided- inverted) Device- to- device skew (1,5) (1,5) see Table 3 ns see Table 3 0.20 0.1 0.25 0.1 0.25 0.1 0.25 0.25 0.5 0.3 0.75 0.25 0.50 0.6 0.7 0.6 1.0 0.30 1.2 0.5 1.2 1.0 1.5 0.25 0.50 0.5 0.7 0.7 1.2 0.50 0.90 0.5 1.0 1.2 1.7 0.75 REF input to FB propagation delay Units M ax. 0.05 (1,2,6) (1,8) Typ. see Table 2 width LO W(11) tSKEW0 tSKEW4 Typ. REF pulse 0pF(1,4) tSKEW3 M in. see Table 2 Zero output matched- pair skew (xQ 0, xQ 1) tSKEW2 M ax. PI6C3Q991 PI6C3Q993 width HIGH(11) tSKEWPR tSKEW1 Typ. PI6C3Q991-5 PI6C3Q993-5 1.25 1.65 0.25 0 0.25 0.5 0 0.5 0.7 0 0.7 1.2 0 1.2 1.2 0 1.2 1.2 0 1.2 tODCV O utput duty cycle varation from 50%(1) tPWH O utput HIGH time deviation from 50%(1,9) 2.0 2.5 3.0 tPWL deviation from 50%(1,10) 2.5 3.0 3.5 tORISE tOFALL tLOCK tJR O utput LO W time O utput rise time O utput fall time PLL lock time (1) (1) 0.15 1.0 1.8 0.15 1.0 1.8 0.15 1.5 2.5 0.15 1.0 1.8 0.15 1.0 1.8 0.15 1.5 2.5 (1,7) Cycle- to- cycle output jitter(1) 0.5 0.5 0.5 RMS 25 40 40 Peak- to- peak 200 200 200 ns ms ps Notes: 1. All timing tolerances apply for F NOM ≥ 25MHz. Guaranteed by design and characterization, not subject to 100% production testing. 2. Skew is the time between the earliest and the latest output transition among all outputs for which the same t U delay has been selected when all are loaded with the specified load. 3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0t U. 4. tSKEW0 is the skew between outputs when they are selected for 0tU. 5. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode). 6. t DEV is the output-to-output skew between any two devices operating under the same conditions (V CC , ambient temperature, air flow, etc.) 7. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 8. tPD is measured with REF input rise and fall times (from 0.8V to 2.0V) of 1.0ns. 9. Measured at 2.0V. 10. Measured at 0.8V. 11. Refer to Table12 for more detail. 7 PS8449A 10/09/00 PI6C3Q991, PI6CQ3993 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Table 12. Input Timing Requirements Symbol D e s cription M in. tR, tF Maximum input rise and fall times, 0.8V to 2.0V tPWC Input clock pulse, HIGH or LO W 3 Input duty cycle 10 DH M ax. Units 10 ns/V ns 90 % Notes: 1. Input timing requirements are guaranteed by design but not tested. Where pulse width implied by D H is less than tPWC limit, tPWC limit applies. tREF tRPWH tRPWL REF tPD tODCV tODCV FB tJR Q tSKEWPR tSKEW0, 1 tSKEWPR tSKEW0, 1 Other Q tSKEW2 tSKEW2 Inverted Q tSKEW3,4 tSKEW3,4 tSKEW3,4 REF Divided by 2 tSKEW1,3,4 tSKEW2,4 REF Divided by 4 AC Timing Diagram Notes: VCCQ/PE: The AC timing diagram above applies to VCCQ/PE=VCC. For VCCQ/PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align. Skew: The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with 75Ohm to VCC/2. t SKEWPR : The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0t U. t SKEW0: The skew between outputs when they are selected for 0t U. tDEV: The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.) The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. tODCV: tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. tPWH is measured at 2.0V. tPWL is measured at 0.8V. tORISE and tOFALL are measured between 0.8V and 2.0V. 8 PS8449A 10/09/00 PI6C3Q991, PI6C3Q993 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 32-Pin PLCC Package Diagram 28-Pin QSOP Package Diagram 28 0.150 0.157 3.81 3.99 .015 x 45˚ 1 .007 0.178 .010 0.254 .386 9.804 .394 10.009 0.41 .016 1.27 .050 .033 REF 0.84 .228 .244 5.79 6.19 1.35 .053 1.75 .069 SEATING PLANE .025 BSC 0.635 .008 0.203 .012 0.305 .004 0.101 .010 0.254 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 9 PS8449A 10/09/00 PI6C3Q991, PI6CQ3993 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Ordering Information Orde ring Code Package Code Package Type PI6C3Q991J J32 32- Pin PLCC PI6C3Q991- 2J J32 32- Pin PLCC PI6C3Q991- 5J J32 32- Pin PLCC PI6C3Q991- IJ J32 32- Pin PLCC PI6C3Q991- 5IJ J32 32- Pin PLCC PI6C3Q993Q Q28 28- Pin QSOP PI6C3Q993- 2Q Q28 28- Pin QSOP PI6C3Q993- 5Q Q28 28- Pin QSOP PI6C3Q993- IQ Q28 28- Pin QSOP PI6C3Q993- 5IQ Q28 28- Pin QSOP Ope rating Range Commercial Industrial Commercial Industrial Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 10 PS8449A 10/09/00