LatticeECP3 sysIO Usage Guide

LatticeECP3 sysIO
Usage Guide
August 2013
Technical Note TN1177
Introduction
The LatticeECP3™ sysIO™ buffers give the designer the ability to easily interface with other devices using
advanced system I/O standards. This technical note describes the sysIO standards available and how to implement them using Lattice’s ispLEVER® design software.
sysIO Buffer Overview
The LatticeECP3 sysIO interface contains multiple Programmable I/O Cell (PIC) blocks. Each PIC contains two
Programmable I/Os (PIO), PIOA and PIOB, that are connected to their respective sysIO buffers. Two adjacent PIOs
can be joined to provide a differential I/O pair (labeled as “T” and “C”).
Each PIO includes a sysIO buffer and I/O logic (IOLOGIC). The LatticeECP3 sysIO buffers support a variety of single-ended and differential signaling standards. The sysIO buffer also supports the DQS strobe signal that is
required for interfacing with the DDR memory. One of every 12 PIOs in the LatticeECP3 contains a delay element
to facilitate the generation of DQS signals. The DQS signal from the bus is used to strobe the DDR data from the
memory into input register blocks. For more information on the architecture of the sysIO buffer, refer to the
LatticeECP3 Family Data Sheet.
The IOLOGIC includes input, output and tristate registers that implement both single data rate (SDR) and double
data rate (DDR) applications along with the necessary clock and data selection logic. Programmable delay lines
and dedicated logic within the IOLOGIC are used to provide the required shift to incoming clock and data signals
and the delay required by DQS inputs in DDR memory. The DDR implementation in the IOLOGIC and the DDR
memory interface support are discussed in more detail in TN1180, LatticeECP3 High-Speed I/O Interface.
Supported sysIO Standards
The LatticeECP3 sysIO buffer supports both single-ended and differential standards. Single-ended standards can
be further subdivided into internally ratioed standard such as LVCMOS, LVTTL and PCI; and externally referenced
standards such as HSTL and SSTL. The buffers support the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, bus
maintenance (weak pull-up, weak pull-down, or a bus-keeper latch). Other single-ended standards supported
include SSTL and HSTL. Differential standards supported include LVDS, RSDS, BLVDS, LVPECL, differential
SSTL and differential HSTL. LatticeECP3 also support mini-LVDS, PPLVDS (Point-to-Point LVDS) and TRLVDS
(Transition Reduced LVDS). Table 1 lists the sysIO standards supported in the LatticeECP3 devices.
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9-1
tn1177_02.2
LatticeECP3 sysIO
Usage Guide
Table 9-1. Supported Input Standards
Input Standard
VREF (Nominal)
VCCIO (Nominal)
LVTTL
—
3.3
LVCMOS33
—
3.31
LVCMOS25
—
2.51
LVCMOS18
—
1.8
LVCMOS15
—
1.5
Single Ended Interfaces
LVCMOS12
—
—
PCI33
—
—
HSTL18 Class I, II
0.9
—
HSTL15 Class I
0.75
—
SSTL33 Class I, II
1.5
3.3, 2.5
SSTL25 Class I, II
1.25
3.3, 2.5, 1.8
SSTL18 Class I, II
0.9
—
SSTL15
0.75
—
Differential SSTL33 Class I, II
—
3.3, 2.5
Differential SSTL18 Class I, II
See Note 2
—
Differential SSTL25 Class I, II
—
3.3, 2.5, 1.8
Differential HSTL15 Class I
—
—
Differential HSTL18 Class I, II
—
—
Differential Interfaces
Differential SSTL 15
See Note 2
—
LVDS
—
—
Transition Reduced LVDS
—
3.3
LVPECL
—
3.3
Bus LVDS
—
—
MLVDS
—
—
1. For LVTTL33, LVCMOS33 and LVCMOS25, if PCICLAMP is OFF, they can be used
independently of VCCIO in the top banks.
2. VREF is required when using Differential SSTL to interface to DDR memory.
9-2
LatticeECP3 sysIO
Usage Guide
Table 9-2. Supported Output Standards
Output Standard
Drive
VCCIO (Nominal)
Single Ended Interfaces
LVTTL
4mA, 8mA, 12mA, 16mA, 20mA
3.3
LVCMOS33
4mA, 8mA, 12mA, 16mA, 20mA
3.3
LVCMOS25
4mA, 8mA, 12mA, 16mA, 20mA
2.5
3
LVCMOS18
4mA, 8mA, 12mA, 16mA, 20mA
LVCMOS15
4mA, 8mA, 12mA3, 16mA3, 20mA3
3
3
3
1.8
1.5
3
3
LVCMOS12
2mA, 4mA , 6mA, 8mA , 12mA , 16mA , 20mA
PCI33
N/A
1.2
3.3
HSTL18 Class I
8mA, 12mA
1.8
HSTL18 Class II
N/A
1.8
HSTL15 Class I
4mA, 8mA
1.5
SSTL33 Class I, II
N/A
3.3
SSTL25 Class I
8mA, 12mA
2.5
SSTL25 Class II
16mA, 20mA
2.5
SSTL18 Class I
N/A
1.8
SSTL18 Class II
8mA, 12mA
1.8
SSTL15
10mA
1.5
Differential HSTL18 Class I
8mA, 12mA
1.8
Differential HSTL18 Class II
N/A
1.8
Differential HSTL15 Class I
4mA, 8mA
1.5
Differential SSTL33 Class I, II
N/A
3.3
Differential SSTL25 Class I
8mA, 12mA
2.5
Differential SSTL25 Class II
16mA, 20mA
2.5
Differential Interfaces
Differential SSTL18 Class I
N/A
1.8
Differential SSTL18 Class II
8mA, 12mA
1.8
Differential SSTL15
10mA
1.5
LVDS
N/A
2.5
Point-to-Point LVDS (PPLVDS)
N/A
2.5, 3.3
RSDS, RSDSE2
N/A
2.5
Mini-LVDS
N/A
2.5
MLVDS2
N/A
2.5
2
BLVDS
N/A
2.5
LVPECL2
N/A
3.3
1
1. Multiple Drive supported using DiffDrive and MultDrive.
2. Emulated with LVCMOS drivers and external resistors.
3. This drive strength is only available when the output is configured as open-drain.
sysIO Banking Scheme
LatticeECP3 devices have six general-purpose programmable sysIO banks and a seventh configuration bank.
Each of the six general-purpose sysIO banks has a VCCIO supply voltage and two reference voltages, VREF1 and
VREF2. Figure 9-1 shows the six general-purpose banks and the configuration bank with associated supplies.
Bank 8 is a bank dedicated to configuration logic and has seven dedicated configuration I/Os and 14 multiplexed
configuration I/Os. Bank 8 has the power supply pads (VCCIO and VCCAUX) but does not have VREF pads.
9-3
LatticeECP3 sysIO
Usage Guide
On the top and bottom banks, the sysIO buffer pair consists of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). The left and right sysIO buffer pair consists of two singleended output drivers and two sets of single-ended input buffers (both ratioed and referenced). The referenced input
buffer can also be configured as a differential input. In 50% of the pairs, there is also one differential output driver.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive side
of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer.
Figure 9-1. sysIO Banking
TOP
JTAG
BANK7
BANK6
BANK3
GND
SERDES
Wrap from Left
VCCIO8
GND
VCCIO2
VREF1(2)
VREF2(2)
GND
RIGHT
BANK2
LEFT
BANK8
BANK1
GND
VREF2(1)
VREF2(6)
VCCIO1
VCCIO6
VREF1(6)
VREF1(1)
VCCIO7
VREF1(7)
VREF2(7)
GND
GND
VREF2(0)
VREF1(0)
VCCIO0
BANK0
VCCJ
VCCIO3
VREF1(3)
VREF2(3)
GND
Wrap from Right
BOTTOM
VCCIO (1.2V/1.5V/1.8V/2.5V/3.3V)
There are a total of six VCCIO supplies, VCCIO0 - VCCIO8. Each bank has a separate VCCIO supply that powers the
single-ended output drivers and the ratioed input buffers such as LVTTL, LVCMOS, and PCI. LVTTL, LVCMOS3.3,
LVCMOS2.5 and LVCMOS1.2 inputs also have fixed threshold options allowing them to be placed in any bank.
Tables 9-4 and 9-6 list the allowed mixed-voltage support in a given bank. The VCCIO voltage applied to the bank
determines the ratioed input standards that can be supported in that bank. It is also used to power the differential
output drivers. In addition, VCCIO8 is used to supply power to the sysCONFIG™ signals.
9-4
LatticeECP3 sysIO
Usage Guide
VCCAUX (3.3V)
In addition to the bank VCCIO supplies, LatticeECP3 devices have a VCC core logic power supply, and a VCCAUX
auxiliary supply that powers the differential and referenced input buffers. VCCAUX is used to supply I/O reference
voltage requiring 3.3V to satisfy the common-mode range of the drivers and input buffers.
VCCJ (1.2V/1.5V/1.8V/2.5V/3.3V)
The JTAG pins have a separate VCCJ power supply that is independent of the bank VCCIO supplies. VCCJ determines the electrical characteristics of the LVCMOS JTAG pins, both the output high level and the input threshold.
Table 9-3 contains a summary of the required power supplies.
Table 9-3. Power Supplies
Power Supply
Value1
Description
VCC
Core power supply
1.2V
VCCIO
Power supply for the I/O and configuration banks
1.2V/1.5V/1.8V/2.5V/3.3V
VCCAUX
Auxiliary power supply
3.3V
VCCJ
Power supply for JTAG pins
1.2V/1.5V/1.8V/2.5V/3.3V
1. Refer to the LatticeECP3 Family Data Sheet for recommended min. and max. values.
Input Reference Voltage (VREF1, VREF2)
Each bank can support up to two separate VREF input voltages, VREF1 and VREF2, that are used to set the threshold for the referenced input buffers. The location of these VREF pins is pre-determined within the bank. These pins
can be used as regular I/Os if the bank does not require a VREF voltage.
VREF1 for DDR Memory Interface
When interfacing to DDR memory, the VREF1 input must be used as the reference voltage for the DQS and DQ
input from the memory. A voltage divider between VREF1 and GND is used to generate an on-chip reference voltage that is used by the DQS transition detector circuit. This voltage divider is only present on VREF1 it is not available on VREF2. For further information on the DQS transition detect logic and its implementation, refer to TN1180,
LatticeECP3 High-Speed I/O Interface. When not used as VREF, these predefined voltage reference pins are available as user I/O pins.
For DDR1 memory interfaces, the VREF1 should be connected to 1.25V since only SSTL25 signaling is allowed.
For DDR2 memory interfaces, VREF1 should be connected to 0.9V since only SSTL18 signaling is allowed. For
DDR3 memory interfaces, VREF1 should be connected to 0.75V since only SSTL15 signaling is allowed.
VTT Termination Voltage
The VTT termination voltage on LatticeECP3 device is used for the referenced standard termination and common
mode differential termination. These termination voltage pins are available on the left and right of the device only.
Use of VTT is optional, these pins should be left floating if termination to VTT is not required. The allowable range
for VTT is from 0.5V to 1.25V, independent of the value of VCCIO. The user decides the best termination voltage to
apply to VTT. Many applications will choose VTT to be nominally equal to the switching threshold of the interface
standard being used, with a tolerance of +/- 5% (and this is usually equal to half of the driver supply voltage). VTT
Termination can be dynamic for bidirectional pins (enabled when output buffer is put in tristate) or static (always
on).
Hot Socketing Support
The I/Os located on the top and bottom sides of the device are fully hot socketable. The top side of the device
simultaneously supports hot-socketing, mixed voltage support within a bank and programmable clamp diodes for
supporting PCI. The I/Os located on the left and right sides of the device do not support hot socketing. See the
LatticeECP3 Family Data Sheet for hot socketing (IDK) requirements.
9-5
LatticeECP3 sysIO
Usage Guide
Mixed Voltage Support in a Bank
The LatticeECP3 sysIO buffer is connected to three parallel ratioed input buffers. These three parallel buffers are
connected to VCCIO, VCCAUX and to VCC, giving support for thresholds that track with VCCIO as well as fixed thresholds for 3.3V (VCCAUX) and 1.2V (VCC) inputs. This allows the input threshold for ratioed buffers to be assigned on
a pin-by-pin basis, rather than have it track with VCCIO. This option is available for all 1.2V, 2.5V and 3.3V ratioed
inputs and is independent of the bank VCCIO voltage on the top banks when PCICLAMP is OFF. In the left and right
banks, the PCICLAMP is always enabled to clamp any currents when VINPUT is higher than VCCIO. Hence, only 1.2
inputs and 2.5 inputs are allowed independent of VCCIO as long as the VINPUT is less than VCCIO. For example, if
the bank VCCIO is 1.8V and PCICLAMP is OFF, it is possible to have 1.2V and 3.3V ratioed input buffers with fixed
thresholds, as well as 2.5V ratioed inputs with tracking thresholds on the top bank. On the left and right banks,
when VCCIO is 1.8V, it is possible to have only 1.2V with fixed thresholds. But if the VCCIO on the left and right sides
is 3.3V, it is possible to have a 1.2V input with fixed thresholds as well as 2.5V with tracking thresholds.
Prior to device configuration, the ratioed input thresholds track the bank VCCIO. This option only takes effect after
configuration. Output standards within a bank are always set by VCCIO but can drive a lower output standard into a
device that is tolerant up to that VCCIO. Tables 9-4 and 9-5 shows the sysIO standards that can be mixed in the
same bank.
Table 9-4. Mixed Voltage Support in Top Banks
Input sysIO Standards1, 2, 3, 4, 5
VCCIO
1.2V
1.2V
Yes
1.5V
Yes
1.8V
Yes
2.5V
3.3V
1.5V
1.8V
Yes
Output sysIO Standards6
2.5V
3.3V
1.2V
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1.5V
1.8V
2.5V
3.3V
Yes
Yes
Yes
Yes
1. Mixed voltage input support is available on the top banks only when PCICLAMP is OFF
2. All differential input buffers except LVPECL33 and TRLVDS can be supported in banks independent of VCCIO. LVPECL33 can be placed on
top side independent of VCCIO when PCICLAMP is OFF.
3. 1.5V and 1.8V HSTL and SSTL reference inputs can be supported on banks with any VCCIO.
4. 2.5V SSTL reference inputs can be supported on banks with VCCIO set to 1.8V, 2.5V or 3.3V.
5. 3.3V SSTL reference inputs can be supported on banks with VCCIO set to 2.5V or 3.3V.
6. When output is configured as open drain it can be placed in bank independent of VCCIO.
Table 9-5. Mixed Voltage Support in Left and Right Banks
Input sysIO Standards1, 2, 3, 4
VCCIO
1.2V
1.5V
1.8V
2.5V
1.2V
Yes
1.5V
Yes
1.8V
Yes
2.5V
Yes
Yes
3.3V
Yes
Yes
Output sysIO Standards5
3.3V
1.2V
1.5V
1.8V
2.5V
3.3V
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1. All differential input buffers except LVPECL33 and TRLVDS can be supported on banks with VCCIO set to 2.5V or 3.3V. LVPECL and
TRLVDS require VCCIO of 3.3V. If the VCCIO is set to 1.8V or 1.5V, this reduces the VCM (max) and VIN (max) to approximately 1.7V as the
PCICLAMP is always enabled on this side when the VINPUT > VCCIO of the bank.
2. 1.5V and 1.8V HSTL and SSTL reference inputs can be supported on banks with any VCCIO.
3. 2.5V SSTL reference inputs can be supported on banks with VCCIO set to 1.8V, 2.5V or 3.3V.
4. 3.3V SSTL reference inputs can be supported on banks with VCCIO set to 2.5V or 3.3V.
5. When output is configured as open drain it can be placed in bank independent of VCCIO.
9-6
LatticeECP3 sysIO
Usage Guide
sysIO Standards Supported Per Bank
Table 9-6. I/O Standards Supported per Bank
Description
Top Side
Right Side
Bottom Side
Left Side
Types of I/O Buffers
Single-ended
Single-ended and
Differential
Single-ended
Single-ended and
Differential
Single-Ended Standards Outputs
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL15
SSTL18 Class I, II
SSTL25 Class I, II
SSTL33 Class I, II
HSTL15 Class I
HSTL18_I, II
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL15
SSTL18 Class I, II
SSTL25 Class I, II
SSTL33 Class I, II
HSTL15 Class I
HSTL18 Class I, II
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL15
SSTL18 Class I, II
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I
HSTL18 Class I, II
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL15
SSTL18 Class I, II
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I
HSTL18 Class I, II
Differential Standards
Outputs
LVCMOS33D
LVCMOS33D
LVCMOS33D
LVCMOS33D
SSTL15D
SSTL18D Class I, II
SSTL25D Class I, II
SSTL33D Class I, II
HSTL15D Class I
HSTL18D Class I, II
SSTL15D
SSTL18D Class I, II
SSTL25D Class I, II
SSTL33D Class I, II
HSTL15D Class I
HSTL18D Class I, II
SSTL15D
SSTL18D Class I, II
SSTL25D Class I, II,
SSTL33D Class I, II
HSTL15D Class I
HSTL18D Class I, II
SSTL15D
SSTL18D Class I, II
SSTL25D Class I, II,
SSTL33D_I, II
HSTL15D Class I
HSTL18D Class I, II
LVDS25E1
LVPECL1
BLVDS1
RSDSE1
LVDS2, 3
RSDS2
Mini-LVDS2
PPLVDS2 (point-to-point)
LVDS25E1
LVPECL1
BLVDS1
RSDSE1
LVDS25E1
LVPECL1
BLVDS1
RSDSE1
LVDS2
RSDS2
Mini-LVDS2
PPLVDS2 (point-to-point)
LVDS25E1
LVPECL1
BLVDS1
RSDSE1
Inputs
All Single-ended and
Differential TRLVDS
(Transition Reduced
LVDS)
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
Clock Inputs
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
Hot Socketing
Yes
No
Yes
No
Equalization on Inputs No4
Yes4
No
Yes
ISI Correction
For DDR3 memory
For DDR3 memory
For DDR3 memory
On Chip Termination
No
On-Chip Parallel Termina- No
tion
On-Chip Parallel Termination
On-Chip Differential 
Termination
On-Chip Differential 
Termination
PCI Support
1.
2.
3.
4.
5.
PCI33 with or without
clamp5
PCI33 with clamp
PCI33 with clamp
For DDR3 memory
PCI33 with clamp
These differential standards are implemented by using a complementary LVCMOS driver with the external resistor pack.
Available on 50% of the I/Os in the bank.
I/Os in Bank 8 are shared with sysCONFIG pins and do not support true LVDS and DDR registers.
I/Os in Bank 8 do not support equalization.
I/Os in Bank 8 do not have a programmable clamp setting. PCI clamp is always on in Bank 8.
9-7
LatticeECP3 sysIO
Usage Guide
sysIO Buffer Configurations
This section describes the various sysIO features available on the LatticeECP3 FPGAs.
Bus Maintenance Circuit
Each of the LVCMOS, LVTTL and PCI types of inputs has a weak pull-up, weak pull-down and weak bus keeper
capability. The pull-up and pull-down settings offer a fixed characteristic which is useful in creating wired logic such
as wired ORs. However, current can be slightly higher than other options depending on the signal state. The bus
keeper option latches the signal in the last driven state, holding it at a valid level with minimal power dissipation.
You can also choose to turn off the bus maintenance circuitry, minimizing power dissipation and input leakage.
Note that in this case it is important to ensure that inputs are driven to a known state to avoid unnecessary power
dissipation in the input buffer.
On the outputs, the weak pull-ups are on at all times. Users have the option to turn off the pull-up setting in the software.
Programmable Drive
Each LVCMOS or LVTTL, as well as some of the referenced (SSTL and HSTL) output buffers, has a programmable
drive strength option. This option can be set for each I/O independently. The drive strength settings available are
2mA, 4mA, 6mA, 8mA, 12mA, 16mA and 20mA. Actual options available vary by I/O voltage. The user must consider the maximum allowable current per bank and the package thermal limit current when selecting the drive
strength. Table 9-7 shows the available drive settings for each of the output standards.
Table 9-7. Programmable Drive Values for Single-Ended Buffers
Single-Ended I/O Standard
Programmable Drive (mA)
HSTL15_I/ HSTL15D_I
4, 8
HSTL18_I/ HSTL18D_I
8, 12
SSTL25_I/ SSTL25D_I
8, 12
SSTL25_II/ SSTL25D_II
16, 20
SSTL18_II/SSTL18D_II
8, 12
LVCMOS12 (with PCI Clamp OFF)
4, 8, 12, 16, 20
LVCMOS12 (with PCI Clamp ON)
2, 6
LVCMOS15 (with PCI Clamp OFF)
4, 8, 12, 16, 20
LVCMOS15 (with PCI Clamp ON)
4, 8
LVCMOS18 (with PCI Clamp OFF)
4, 8, 12, 16, 20
LVCMOS18 (with PCI Clamp ON)
4, 8, 12, 16
LVCMOS25
4, 8, 12, 16, 20
LVCMOS33
4, 8, 12, 16, 20
LVTTL
4, 8, 12, 16, 20
Programmable Slew Rate
Each LVCMOS or LVTTL output buffer pin also has a programmable output slew rate control that can be configured
for either low noise or high-speed performance. Each I/O pin has an individual slew rate control. This allows
designers to specify slew rate control on a pin-by-pin basis. This slew rate control affects both the rising edge and
the falling edges.
Open Drain Control
All LVCMOS and LVTTL output buffers can be configured to function as open drain outputs. The user can implement an open drain output by turning on the OPENDRAIN attribute in the software.
9-8
LatticeECP3 sysIO
Usage Guide
Differential SSTL and HSTL Support
The single-ended driver associated with the complementary “C” pad can optionally be driven by the complement of
the data that drives the single-ended driver associated with the true pad. This allows a pair of single-ended drivers
to be used to drive complementary outputs with the lowest possible skew between the signals. This is used for driving complementary SSTL and HSTL signals (as required by the differential SSTL and HSTL clock inputs on synchronous DRAM and synchronous SRAM devices, respectively). This capability is also used in conjunction with offchip resistors to emulate LVPECL, and BLVDS output drivers.
PCI Support with Programmable PCICLAMP
Each sysIO buffer can be configured to support PCI33. The buffers on the top of the device have an optional PCI
clamp diode that may optionally be specified in the ispLEVER design tools. The programmable PCICLAMP can be
turned ON or OFF. This option is available on each I/O independently only on the top side banks.
For the other three sides of the device, the PCICLAMP is always ON.
Differential I/O Support
50% of the sysIO buffer pairs on the left and right edges contain a differential output driver that can optionally drive
the pads in the pair. The standards support on these differential output pairs is as follows:
• LVDS
• Point to Point LVDS (PPLVDS)
• Mini-LVDS
• RSDS
All the other pins on all the sides of the device can support Emulated Differential standards using complementary
LVCMOS drivers with external resistors. The standards supported using differential output pairs is as follows:
• BLVDS
• LVDS25E
• RSDSE
• LVPECL
The LatticeECP3 Family Data Sheet lists the LVCMOS drivers and external resistor requirements to implement
these emulated standards. The data sheet also lists the electrical specifications supported for all differential standards.
Differential SSTL and HSTL
All single-ended sysIO buffers pairs support differential SSTL and HSTL. Refer to the LatticeECP3 Family Data
Sheet for a detailed description of the Differential HSTL and SSTL implementations.
Differential LVCMOS33
All single-ended sysIO buffer pairs also support the LVCMOS33D (Differential) standard with configurable drive
strength and slew settings. This generic 3.3V differential buffer allows the user to implement any type of 3.3V differential buffer by configuring the drive strength and calculating the external resistor values as per the application
requirements.
GTL+ Input Support
GTL+ inputs can be supported using either the SSTL15 or HSTL15_I input standard with VREF set to 1.0V and
external VTT termination to 1.5V. GTL+ inputs implemented using this method can support the maximum speed
listed for the SSTL and HSTL standards in the LatticeECP3 Family Data Sheet. GTL+ outputs are not supported in
the LatticeECP3 device.
9-9
LatticeECP3 sysIO
Usage Guide
Figure 9-2. GTL+ Input Buffer Emulation Using HSTL15 Input
VTT = 1.5V
z0
+
VREF = 1.0V
HSTL15
On-Chip Termination
LatticeECP3 devices support on-chip Parallel Termination to VTT as well Common mode differential termination
using the VTT pin. On-chip termination is available on the left and right sides of the device. The VTT pin should be
left to float when using common mode differential termination. Termination can be set to be dynamic for bidirectional buffers where the termination is active only when the output buffer is disabled through the tristate control.
External termination to VTT should be used when implementing the DDR2 and DDR3 memory interfaces.
Equalization Setting
Equalization filtering is available for single-ended inputs on both true and complementary I/Os, and for differential
inputs on the true I/Os. Equalization is required to compensate for the difficulty of sampling alternating logic transitions with a relatively slow slew rate. It is useful for the input DDR modes used in DDR3 memory and fast SPI4.2
mode signaling. It is available on the left and right sides.
Equalization acts as a tunable filter, with settings determining the level of correction. There are four settings available: Zero (none), One, Two and Three. The equalization logic resides in the I/O buffers. Each I/O can have a
unique equalization setting within a DQS-12 group for DDR3 memory.
Software sysIO Attributes
sysIO attributes can be specified in the HDL, using the Preference Editor GUI or in the ASCII Preference file (.prf)
directly. The appendices of this document provide examples of how these can be assigned using each of the methods described above. This section describes each of these attributes in detail.
IO_TYPE
This attribute is used to set the sysIO standard for an I/O. The VCCIO required to set these I/O standards are
embedded in the attribute name itself. There is no separate attribute to set the VCCIO requirements. Table 9-8 lists
the available I/O types.
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LatticeECP3 sysIO
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Table 9-8. IO_TYPE Attribute Values
sysIO Signaling Standard
IO_TYPE
DEFAULT
LVCMOS25
LVDS 2.5V
LVDS252
Point to Point LVDS
PPLVDS2
Mini-LVDS
MINILVDS2
RSDS
RSDS2
Transition Reduced LVDS
TRLVDS3
Emulated LVDS 2.5V
LVDS25E1
Bus LVDS 2.5V
BLVDS251
LVPECL 3.3V
LVPECL331
Emulated RSDS
RSDSE1
MLVDS
MLVDS
HSTL18 Class I and II
HSTL18_I, HTSL18_II
Differential HSTL 18 Class I and II
HSTL18D_I HSTL18D_II
HSTL 15 Class I
HSTL15_I
Differential HSTL 15 Class I
HSTL15D_I
SSTL 33 Class I and II
SSTL33_I, SSTL33_II
Differential SSTL 33 Class I and II
SSTL33D_I SSTL3D_II
SSTL 25 Class I and II
SSTL25_I SSTL25_II
Differential SSTL 25 Class I and II
SSTL25D_I SSTL25D_II
SSTL 18 Class I and II
SSTL18_I SSTL18_II
Differential SSTL 18 Class I and II
SSTL18D_I SSTL18D_II
SSTL 15
SSTL15
LVTTL
LVTTL33
3.3V LVCMOS
LVCMOS33
3.3V LVCMOS Differential
LVCMOS33D
2.5V LVCMOS
LVCMOS25
1.8V LVCMOS
LVCMOS18
1.5V LVCMOS
LVCMOS15
1.2V LVCMOS
LVCMOS12
3.3V PCI
PCI33
1. These differential standards are implemented by using the complementary LVCMOS
driver and external resistor pack.
2. Supported on 50% of the pairs on the left and right sides of the device.
3. Only inputs supported. Available only on the top side of the device.
OPENDRAIN
LVCMOS and LVTTL IO standards can be set to Open Drain configuration by using the OPENDRAIN attribute.
When configuring I/Os on the left and right banks to be Open Drain, it is required that the external pull-up be less
than the bank VCCIO.
Table 9-9. Open Drain Attribute Values
Attribute
Values
Default
OPENDRAIN
ON, OFF
OFF
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LatticeECP3 sysIO
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DRIVE
The DRIVE attribute will set the programmable drive strength for the output standards that have programmable
drive capability
Table 9-10. DRIVE Settings
Output Standard
DRIVE (mA)
Default (mA)
HSTL15_I/ HSTL15D_I
4, 8
8
HSTL18_I/ HSTL18D_I
8, 12
12
SSTL25_I/ SSTL25D_I
8, 12
8
SSTL25_II/ SSTL25D_II
16, 20
16
SSTL18_II/SSTL18D_II
8, 12
12
LVCMOS12 (without OPENDRAIN)
2, 6
6
LVCMOS12 (with OPENDRAIN)
4, 8, 12, 16, 20
12
LVCMOS15 (without OPENDRAIN)
4, 8
8
LVCMOS15 (with OPENDRAIN)
4, 8, 12, 16, 20
12
LVCMOS18 (without OPENDRAIN)
4, 8, 12, 16
12
LVCMOS18 (with OPENDRAIN)
4, 8, 12, 16, 20
12
LVCMOS25
4, 8, 12, 16, 20
12
LVCMOS33
4, 8, 12, 16, 20
12
LVTTL
4, 8, 12, 16, 20
12
DIFFDRIVE
The DIFFDRIVE setting is used to set the differential drive setting for the Mini-LVDS driver when the driver setting
needs to be adjusted to support variation in external termination. An I/O bank can have differential outputs with the
same DIFFDRIVE setting. Differential outputs with different DIFFDRIVE settings cannot be placed in the same I/O
bank.
Table 9-11. DIFFDRIVE Values
I/O Standard
MINILVDS
MULTDRIVE Values
Default
1.6, 1.65, 1.7, 1.75,1.81, 1.87, 1.93, 2.0
1.6
LVDS
1.75
1.75
RSDS
2.0
2.0
PPLVDS
2.0
2.0
MULTDRIVE
DIFFDRIVE only partially supports variation of Mini-LVDS driver current. Therefore, in addition to DIFFDRIVE,
MULTDRIVE settings must be used to adjust the output drive strength of Mini-LVDS.
Table 9-12. MULTDRIVE Values
I/O Standard
MULTDRIVE Values
Default
MINILVDS
1x, 2x, 3x, 4x
1x
LVDS
2x
2x
RSDS
1x
1x
PPLVDS
1x
1x
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LatticeECP3 sysIO
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TERMINATEVTT
This attribute is used to set the on-chip parallel termination to VTT for reference buffer inputs. VTT pins in corresponding banks should be connected externally to the correct level. VTT of the bank should be left floating if this
termination is not used.
Table 9-13. TERMINATEVTT Values
Attribute
Values
TERMINATEVTT
Default
OFF, 40, 50, 60
OFF
DIFFRESISTOR
This attribute is used to set the on-chip differential termination using common mode termination to VTT. This onchip termination is optimized to work primarily for the LVDS I/O type. When the DIFFRESISTOR attribute is set, the
VTT pin should be left floating.
Table 9-14. DIFFRESISTOR Values
Attribute
Values
DIFFRESISTOR
Default
OFF, 80, 100, 120
OFF
EQ_CAL
This attribute is used to set the Equalization setting available on the input pins on the left and right sides of the
device. EQ_CAL is not available in Bank 8.
Table 9-15. EQ_CAL Values
Attribute
Values
EQ_CAL
Default
0, 1, 2, 3, 4
0
PULLMODE
The PULLMODE attribute is available for all the LVTLL and LVCMOS inputs and outputs. This attribute can be
enabled for each I/O independently.
Table 9-16. PULLMODE Values
PULL Options
PULLMODE Value
Pull up (Default)
UP
Pull Down
DOWN
Bus Keeper
KEEPER
Pull Off
NONE
Table 9-17. PULLMODE Settings
Buffer
Values
Default
Input
UP, DOWN, KEEPER, NONE
UP
Output
UP, DOWN, KEEPER, NONE
UP
PCICLAMP
PCICLAMP is available on all the pads of the device. On the top of the device the PCICLAMP setting can be optionally turned OFF. The rest of the banks only support the PCICLAMP value ON.
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LatticeECP3 sysIO
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Table 9-18. PCICLAMP Values
Attribute
PCI33
Values
ON, OFF
Default
ON
SLEWRATE
The SLEWRATE attribute is available for all LVTTL and LVCMOS output drivers. Each I/O pin has an individual
slew rate control. This allows designers to specify slew rate control on a pin-by-pin basis.
Table 9-19. Slew Rate Values
Attribute
SLEWRATE
Values
FAST, SLOW
Default
SLOW
INBUF
By default, all the unused input buffers are disabled. The INBUF attribute is used to enable the unused input buffers
when performing a boundary scan test. This is a global attribute and can be globally set to ON and OFF.
• Values: ON, OFF
• Default: OFF
FIXEDDELAY
This attribute can be used in HDL to enable the input Fixed Delay on the input of an SDR Input register. When set
to TRUE, you can achieve a zero hold time on the input register.
• Value: TRUE, FALSE
• Default: FALSE
DIN/DOUT
This attribute can be used when an I/O register needs to be assigned. Using DIN asserts an input register and
using DOUT asserts an output register in the design. By default, the software will attempt to assign the I/O registers if applicable. Users can turn this OFF by using a synthesis attribute or the ispLEVER Preference Editor. These
attributes can only be applied on registers.
LOC
This attribute can be used to make pin assignments to the I/O ports in the design. This attribute is only used when
the pin assignments are made in HDL source. Pins can also be assigned directly using the GUI in the Preference
Editor of the software. See the appendices for further information.
Design Considerations and Usage
This section discusses some of design rules and considerations that need to be taken into account when designing
with the LatticeECP3 sysIO buffer
Banking Rules
• If VCCIO or VCCJ for any bank is set to 3.3V, it is recommended that it be connected to the same power supply as
VCCAUX, thus minimizing leakage.
• If VCCIO or VCCJ for any bank is set to 1.2V, it is recommended that it be connected to the same power supply as
VCC, thus minimizing leakage.
• When implementing DDR memory interfaces, the VREF1 of the bank is used to provide reference to the interface
pins and cannot be used to power any other referenced inputs.
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LatticeECP3 sysIO
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• Only the top bank supports programmable PCI clamps.
• On the top banks, all legal input buffers should be independent of bank VCCIO except for 1.8V and 1.5V buffers,
which require a bank VCCIO of 1.8V and 1.5V. On the left and right banks, 1.2V input buffers can be assigned to
a bank independent of VCCIO. 2.5V input buffers can be assigned to banks with VCCIO 2.5V and 3.3V. All other
input buffers depend on the VCCIO to the bank.
• When DIFFRESITOR is used, the VTT pin for that bank should be left floating.
• When TERMINATEVTT is used, VTT should be connected to the correct voltage depending on the IO_TYPE set.
For example, for SSTL18 standards, VTT should be connected to 0.9V.
• Both TERMINATEVTT and DIFFRESISTOR use the VTT pin, hence these are mutually exclusive in a bank.
• Equalization is only available on the left and right banks.
• PCICLAMP is programmable on the top-side banks 0 and 1. For all other banks, PCICLAMP is always ON.
Differential I/O Rules
• All banks can support LVDS input buffers. Only the banks on the right and left sides (Banks 2, 3, 6 and 7) will
support True Differential output buffers. The banks on the top and bottom will support the LVDS input buffers but
will not support True LVDS outputs. The user can use emulated LVDS output buffers on these banks.
• All banks support emulated differential buffers using the external resistor pack and complementary LVCMOS
drivers.
• Only 50% of the I/Os on the left and right sides can provide LVDS, mini-LVDS, PPLVDS and RSDS output buffer
capability. See the LatticeECP3 Family Data Sheet for the pin listing for all the true differential pairs.
• The IO_TYPE attribute for a differential buffer can only be assigned to the TRUE pad. The ispLEVER design tool
will automatically assign the other I/O of the differential pair to the complementary pad.
• TRLVDS inputs are only supported on the top banks.
• LVDS, MINILVDS, RSDS, PPDS cannot co-exist in one bank.
• An I/O bank can only have differential outputs with the same DIFFDRIVE setting. Differential outputs with different DIFFDRIVE settings cannot be placed in the same I/O bank.
• DIFFRESISTOR termination is only available on the left and right sides. If enabled, the VTT of the bank should
be left floating. Referenced inputs cannot be used in this bank when DIFFRESISTOR is enabled.
Technical Support Assistance
e-mail:
[email protected]
Internet: www.latticesemi.com
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LatticeECP3 sysIO
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Revision History
Date
Version
February 2009
01.0
May 2009
01.1
Change Summary
Initial release.
Updated Mixed Voltage Support in Top Banks table.
Updated Mixed Voltage Support in Left and Right Banks table.
Added FIXEDDELAY attribute support for SDR registers.
August 2009
01.2
Updated On-Chip Termination text section.
Updated DIFFRESISTOR text section.
Updated Banking Rules bullets.
April 2010
01.3
Removed support for programmable PCICLAMP, equalization and
VREF pins in Bank 8.
June 2010
01.4
Added Appendix C - sysIO Attributes Using the Diamond Spreadsheet
View User Interface.
November 2010
01.5
Updated Supported Input Standards table.
Updated Hot Socketing Support text section.
Updated Hot Socketing row of the I/O Standards Supported per Bank
table.
Updated first footnote in the Mixed Voltage Support in Left and Right
Banks table.
March 2011
01.6
Added support for GTL+ input standard using HSTL input buffer.
April 2011
01.7
Updated to clarify PCICLAMP programmability and DRIVE settings
availably with and without OPENDRAIN.
February 2012
01.8
Updated document with new corporate logo.
March 2012
01.9
Verilog Synplicity Attribute Syntax table – Corrected information in the
Syntax column.
June 2012
02.0
Supported Input Standards table – Updated VCCIO column and
removed GTL+ row.
Supported Output Standards table – Updated VCCIO information for
Point-to-Point LVDS.
Mixed Voltage Support in Top Banks table – Updated footnote 2.
Mixed Voltage Support in Left and Right Banks table – Updated footnote
1.
March 2013
02.1
August 2013
02.2
Mixed Voltage Support in Top Banks table – Updated footnote 2.
Updated DRIVE Settings table.
Updated Technical Support Assistance information.
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LatticeECP3 sysIO
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Appendix A. HDL Attributes
Using HDL attributes, you can assign the sysIO attributes directly in your source code. You will need to use the
attribute definition and syntax for the synthesis vendor you are planning to use. Below is a list of the sysIO attributes, syntax and examples for the Synplify Pro® synthesis tool. This section only lists the sysIO buffer attributes for
these devices. You can refer to the Synplify Pro user manual for a complete list of synthesis attributes. You can
access these manuals through the ispLEVER software Help.
VHDL Synplify Pro
This section lists syntax and examples for all the sysIO attributes in VHDL when using Synplify Pro synthesis tools.
Syntax
Table 9-20. VHDL Attribute Syntax for Synplify Pro
Attribute
Syntax
IO_TYPE
attribute IO_TYPE: string;
attribute IO_TYPE of Pinname: signal is “IO_TYPE Value”;
OPENDRAIN
attribute OPENDRAIN: string;
attribute OPENDRAIN of Pinname: signal is “OpenDrain Value”;
DRIVE
attribute DRIVE: string;
attribute DRIVE of Pinname: signal is “Drive Value”;
DIFFDRIVE
attribute DIFFDRIVE: string;
attribute DIFFDRIVE of Pinname: signal is “Diffdrive Value”;
MULTIDRIVE
attribute MULTIDRIVE: string;
attribute MULTIDRIVE of Pinname: signal is “MULTIDRIVE Value”;
EQ_CAL
attribute EQ_CAL: string;
attribute EQ_CAL of Pinname: signal is “EQ_CAL Value”;
TERMINATEVTT
attribute TERMINATEVTT: string;
attribute TERMINATEVTT of Pinname: signal is “TERMINATEVTT Value”;
DIFFRESISTOR
attribute DIFFRESISTOR: string;
attribute DIFFRESISTOR of Pinname: signal is “DIFFRESISTOR Value”;
PULLMODE
attribute PULLMODE: string;
attribute PULLMODE of Pinname: signal is “Pullmode Value”;
PCICLAMP
attribute PCICLAMP: string;
attribute PCICLAMP of Pinname: signal is “PCIClamp Value”;
SLEWRATE
attribute PULLMODE: string;
attribute PULLMODE of Pinname: signal is “Slewrate Value”;
DIN
attribute DIN: string;
attribute DIN of Pinname: signal is “ “;
DOUT
attribute DOUT: string;
attribute DOUT of Pinname: signal is “ “;
LOC
attribute LOC: string;
attribute LOC of Pinname: signal is “pin_locations”;
FIXEDDELAY
attribute FIXEDDELAY:string;
attribute FIXEDELAY of Pinname: signal is "FIXEDDELAY Value";
Examples
IO_TYPE
--***Attribute Declaration***
ATTRIBUTE IO_TYPE: string;
--***IO_TYPE assignment for I/O Pin***
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LatticeECP3 sysIO
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ATTRIBUTE IO_TYPE OF portA:
ATTRIBUTE IO_TYPE OF portB:
ATTRIBUTE IO_TYPE OF portC:
SIGNAL IS “PCI33”;
SIGNAL IS “LVCMOS33”;
SIGNAL IS “LVDS25”;
OPENDRAIN
--***Attribute Declaration***
ATTRIBUTE OPENDRAIN: string;
--***Open Drain assignment for I/O Pin***
ATTRIBUTE OPENDRAIN OF portB: SIGNAL IS “ON”;
DRIVE
--***Attribute Declaration***
ATTRIBUTE DRIVE: string;
--***DRIVE assignment for I/O Pin***
ATTRIBUTE DRIVE OF portB: SIGNAL IS “20”;
DIFFDRIVE
--***Attribute Declaration***
ATTRIBUTE DIFFDRIVE: string;
--*** DIFFDRIVE assignment for I/O Pin***
ATTRIBUTE DIFFDRIVE OF portB: SIGNAL IS “2.0”;
MULTDRIVE
--***Attribute Declaration***
ATTRIBUTE MULTDRIVE: string;
--*** MULTDRIVE assignment for I/O Pin***
ATTRIBUTE MULTDRIVE OF portB: SIGNAL IS “2X”;
EQ_CAL
--***Attribute Declaration***
ATTRIBUTE EQ_CAL: string;
--*** EQ_CAL assignment for I/O Pin***
ATTRIBUTE EQ_CAL OF portB: SIGNAL IS “1”;
TERMINATEVTT
--***Attribute Declaration***
ATTRIBUTE TERMINATEVTT: string;
--*** TERMINATEVTT assignment for I/O Pin***
ATTRIBUTE TERMINATEVTT OF portB: SIGNAL IS “40”;
DIFFERESISTOR
--***Attribute Declaration***
ATTRIBUTE DIFFRESISTOR: string;
--*** DIFFRESISTOR assignment for I/O Pin***
ATTRIBUTE DIFFRESISTOR OF portB: SIGNAL IS “80”;
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PULLMODE
--***Attribute Declaration***
ATTRIBUTE PULLMODE : string;
--***PULLMODE assignment for I/O Pin***
ATTRIBUTE PULLMODE OF portA: SIGNAL IS “DOWN”;
ATTRIBUTE PULLMODE OF portB: SIGNAL IS “UP”;
PCICLAMP
--***Attribute Declaration***
ATTRIBUTE PCICLAMP: string;
--***PULLMODE assignment for I/O Pin***
ATTRIBUTE PCICLAMP OF portA: SIGNAL IS “OFF”;
SLEWRATE
--***Attribute Declaration***
ATTRIBUTE SLEWRATE : string;
--*** SLEWRATE assignment for I/O Pin***
ATTRIBUTE SLEWRATE OF portB: SIGNAL IS “FAST”;
DIN/DOUT
--***Attribute Declaration***
ATTRIBUTE din : string;
ATTRIBUTE dout : string;
--*** din/dout assignment for I/O Pin***
ATTRIBUTE din OF input_vector: SIGNAL IS “ “;
ATTRIBUTE dout OF output_vector: SIGNAL IS “ “;
LOC
--***Attribute Declaration***
ATTRIBUTE LOC : string;
--*** LOC assignment for I/O Pin***
ATTRIBUTE LOC OF input_vector: SIGNAL IS “E3,B3,C3 “;
FIXEDDELAY
--***Attribute Declaration***
ATTRIBUTE FIXEDDELAY : string;
--*** FIXEDDELAY assignment for I/O Pin***
ATTRIBUTE FIXEDDELAY OF portA: SIGNAL IS “True”;
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Verilog Synplicity
This section lists syntax and examples for all the sysIO Attributes in Verilog using Synplicity® synthesis tool.
Syntax
Table 9-21. Verilog Synplicity Attribute Syntax
Attribute
Syntax
IO_TYPE
PinType PinName /* synthesis IO_TYPE=“IO_Type Value”*/;
OPENDRAIN
PinType PinName /* synthesis OPENDRAIN =“OpenDrain Value”*/;
DRIVE
PinType PinName /* synthesis DRIVE=“Drive Value”*/;
DIFFDRIVE
PinType PinName /* synthesis DIFFDRIVE =“DIFFDRIVE Value”*/;
MULTDRIVE
PinType PinName /* synthesis MULTDRIVE =“MULTDRIVE Value”*/;
EQ_CAL
PinType PinName /* synthesis EQ_CAL =“EQ_CAL Value”*/;
TERMINATEVTT
PinType PinName /* synthesis TERMINATEVTT =“TERMINATEVTT Value”*/;
DIFFRESISTOR
PinType PinName /* synthesis DIFFRESISTOR =“DIFFRESISTOR Value”*/;
PULLMODE
PinType PinName /* synthesis PULLMODE=“Pullmode Value”*/;
PCICLAMP
PinType PinName /* synthesis PCICLAMP =“PCIClamp Value”*/;
SLEWRATE
PinType PinName /* synthesis SLEWRATE=“Slewrate Value”*/;
DIN
PinType PinName /* synthesis DIN=“ ”*/;
DOUT
PinType PinName /* synthesis DOUT=“ ”*/;
LOC
PinType PinName /* synthesis LOC=“pin_locations”*/;
FIXEDDELAY
PinType PinName/*synthesis FIXEDDELAY = “FIXEDDELAY value”*/;
Examples
//IO_TYPE, PULLMODE, SLEWRATE and DRIVE assignment
output portB /*synthesis IO_TYPE=”LVCMOS33” PULLMODE =”UP” SLEWRATE =”FAST”
DRIVE =”20”*/;
output portC /*synthesis IO_TYPE=”LVDS25” */;
//DIFFRESISTOR
input portB /*synthesis IO_TYPE=”LVDS” DIFFRESITOR=”80” */;
//DIFFDRIVE, MULTDRIVE
output portB /*synthesis IO_TYPE=”MINILVDS” DIFFDRIVE=”2.0” MULTDRIVE=”2X”*/;
//TERMINATEVTT, EQ_CAL
input portB /*synthesis IO_TYPE=”SSTL15” TERMINATEVTT=”60” EQ_CAL=”2”*/;
//OPENDRAIN
output portA /*synthesis OPENDRAIN =”ON”*/;
//PCICLAMP
output portA /*synthesis IO_TYPE=”PCI33” PCICLAMP =”OFF”*/;
//FIXEDDELAY
input portB /*synthesis FIXEDDELAY = "true" */;
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LatticeECP3 sysIO
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// Place the flip-flops near the load input
input load /* synthesis din=”” */;
// Place the flip-flops near the outload output
output outload /* synthesis dout=”” */;
//I/O pin location
input [3:0] DATA0 /* synthesis loc=”E3,B1,F3”*/;
//Register pin location
reg data_in_ch1_buf_reg3 /* synthesis loc=”R40C47” */;
//Vectored internal bus
reg [3:0] data_in_ch1_reg /*synthesis loc =”R40C47,R40C46,R40C45,R40C44” */;
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Appendix B. sysIO Attributes Using the ispLEVER Design Planner User
Interface
sysIO buffer attributes can be assigned using the Design Planner Spreadsheet View available in the ispLEVER
design tool. If you are using Lattice Diamond™ design software, see Appendix C. The Pin Attribute Sheet lists all
the ports in a design and all the available sysIO attributes as preferences. Click on each of these cells for a list of all
the valid I/O preferences for that port. Each column takes precedence over the next. Therefore, when you choose a
particular IO_TYPE, the columns for the DRIVE, PULLMODE, SLEW-RATE and other attributes will only list the
valid combinations for that IO_TYPE. Pin locations can be locked using the pin location column of the Pin Attribute
sheet. Right-click on a cell to list all the available pin locations. The Design Planner will also run a DRC check to
check for any incorrect pin assignments.
You can enter the DIN/ DOUT preferences using the Cell Attributes Sheet of the Design Planner. All the preferences assigned using the Design Planner are written into the logical preference file (.lpf).
Figures 9-3 and 9-4 show the Port Attribute Sheet and the Cell Attribute Sheet views of the Design Planner. For further information on how to use the Design Planner, refer to the ispLEVER Help documentation, available in the
Help menu option of the software.
Figure 9-3. Port Attributes Tab of Design Planner SpreadSheet View
Figure 9-4. Cell Attributes Tab
Users can assign VREF for a bank using the VREF Setting option in the Design Planner. See the software online
help for a more detailed description of this setting.
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Figure 9-5. VREF Assignment in Design Planner
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LatticeECP3 sysIO
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Appendix C. sysIO Attributes Using the Diamond Spreadsheet View User
Interface
sysIO buffer attributes can be assigned using the Spreadsheet view in the Lattice Diamond design software. The
Port Assignments Sheet lists all the ports in a design and all the available sysIO attributes in multiple columns.
Click on each of these cells for a list of all the valid I/O preferences for that port. Each column takes precedence
over the next. Therefore, when you choose a particular IO_TYPE, the columns for the DRIVE, PULLMODE, SLEWRATE and other attributes will only list the valid entries for that IO_TYPE.
Pin locations can be locked using the Pin column of the Port Assignments sheet or using the Pin Assignments
sheet. You can right-click on a cell and go to Assign Pins to see a list of available pins.
The Spreadsheet View also has an option to run a DRC check to check for any incorrect pin assignments. You can
enter the DIN/ DOUT preferences using the Cell Mapping tab. All the preferences assigned using the Spreadsheet
view are written into the logical preference file (.lpf).
Figure 9-5 shows the Port Assignments Sheet of the Spreadsheet view. For further information on how to use the
Spreadsheet view, refer to the Diamond Help documentation, available in the Help menu option of the software.
Figure 9-6. Port Attributes Tab of SpreadSheet View
Users can create a VREF pin using the Spreadsheet view as shown in Figure 9-7 and then assign VREF for a bank
using the VREF Column in the Ports Assignment Tab of the Spreadsheet View as show in Figure 9-8. See the Diamond online help for a more detailed description of this setting.
Figure 9-7. Creating a VREF in Spreadsheet View
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LatticeECP3 sysIO
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Figure 9-8. Assigning a VREF for an Input Port in Spreadsheet View
9-25