bq32000 www.ti.com................................................................................................................................................... SLUS900B – DECEMBER 2008 – REVISED JUNE 2009 REAL-TIME CLOCK (RTC) FEATURES APPLICATIONS • • • 1 • • • • Automatic Switchover to Backup Supply I2C Interface Supports Serial Clock up to 400 kHz Uses 32.768-kHz Crystal With –63-ppm to +126-ppm Adjustment Integrated Oscillator-Fail Detection 8-Pin SOIC Package –40°C to 85°C Ambient Operating Temperature General consumer electronics DESCRIPTION The bq32000 device is a compatible replacement for industry standard real-time clocks. The bq32000 features an automatic backup supply with integrated trickle charger. The backup supply can be implemented using a capacitor or non-rechargeable battery. The bq32000 has a programmable calibration adjustment from –63 ppm to +126 ppm. The bq32000 registers include an OF (oscillator fail) flag indicating the status of the RTC oscillator, as well as a STOP bit that allows the host processor to disable the oscillator. The time registers are normally updated once per second, and all the registers are updated at the same time to prevent a timekeeping glitch. The bq32000 includes automatic leap-year compensation. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 85°C (1) (2) (3) SOIC – D Reel of 2500 ORDERABLE PART NUMBER BQ32000DR TOP-SIDE MARKING bq32000 xx y zzzz (3) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. xx = date code, y = assembly site, zzzz = lot code 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2009, Texas Instruments Incorporated bq32000 SLUS900B – DECEMBER 2008 – REVISED JUNE 2009................................................................................................................................................... www.ti.com D PACKAGE (TOP VIEW) OSCI 1 8 VCC OSCO 2 7 IRQ VBACK 3 6 SCL GND 4 5 SDA TERMINAL FUNCTIONS NAME NO. TYPE DESCRIPTION Power and Ground VCC 8 - Main device power GND 4 - Ground VBACK 3 - Backup device power SCL 6 I I2C serial interface clock SDA 5 I/O I2C serial data 7 O Configurable interrupt output. Open-drain output. OSCI 1 - Oscillator input OSCO 2 - Oscillator output Serial Interface Interrupt IRQ Oscillator 2 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq32000 bq32000 www.ti.com................................................................................................................................................... SLUS900B – DECEMBER 2008 – REVISED JUNE 2009 FUNCTIONAL BLOCK DIAGRAM AND APPLICATION CIRCUIT VCC Place supply-decoupling capacitor near supply pin 1 µF VCC VCC Trickle Charge Automatic Backup Switch VBACK Use only super-capacitor or battery, not both 4.7 kW VCORE 0.22 F Interrupt Generator OSCI OSCO 32-kHz Oscillator I2C Register Interface With Undervoltage Lockout 4.7 kW 4.7 kW IRQ SCL SDA Registers GND NOTE: All pullup resistors should be connected to VCC such that no pullup is applied during backup supply operation. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq32000 3 bq32000 SLUS900B – DECEMBER 2008 – REVISED JUNE 2009................................................................................................................................................... www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) LIMIT UNIT –0.3 to 4 V –0.3 to VCC + 0.3 V VCC to GND VIN Input voltage TJ Operating junction temperature –40 to 150 °C TSTG Storage temperature range after reflow –60 to 150 °C (1) All other pins to GND Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN VCC Supply voltage, VCC to GND TA Operating free-air temperature fo Crystal resonant frequency RS Crystal series resistance CL Crystal load capacitance TYP MAX UNIT 3 3.6 V –40 85 °C 32.768 kHz 40 12 kΩ pF ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT Power Supply ICC VCC supply current VBACK Backup supply voltage IBACK Backup supply current µA 100 Operating 1.4 VCC Switchover 2.0 VCC VCC = 0 V, VBAT = 3V, Oscillator on, TA = 25°C 1.2 V 1.5 µA 0.3 VCC V 1 µA Logic Level Inputs VIL Input low voltage VIH Input high voltage IIN Input current 0.7 VCC 0 V ≤ VIN ≤ VCC V -1 Logic Level Outputs VOL Output low voltage IL Leakage current IOL = 3 mA -1 0.4 V 1 µA Real-Time Clock Characteristics Pre-calibration accuracy (1) 4 VCC = 3.3 V, VBAT = 3 V, Oscillator on, TA = 25°C ±35 (1) ppm Typical accuracy is measured using reference board design and KDS DMX-26S surface-mount 32.768-kHz crystal. Variation in board design and crystal section results in different typical accuracy. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq32000 bq32000 www.ti.com................................................................................................................................................... SLUS900B – DECEMBER 2008 – REVISED JUNE 2009 DEVICE INFORMATION IRQ Function The IRQ pin of the bq32000 functions as a general-purpose output or a frequency test output. The function of IRQ is configurable in the device register space by setting the FT, FTF, and OUT bits. On initial power cycles, the OUT bit is set to one, and the FTF and FT bits are set to zero. On subsequent power-ups, with backup supply present, the OUT bit remains unchanged, and the FTF and FT bits are set to zero. When operating on backup supply, the IRQ pin function is unused. IRQ pullup resistor should be tied to VCC to prevent IRQ operation when operating on backup supply. The effect of the calibration logic is not normally observable when IRQ is configured to output 1 Hz. The calibration logic functions by periodically adjusting the width of the 1-Hz clock. The calibration effect is observable only every eight or sixteen minutes, depending on the sign of the calibration. Figure 1. IRQ Pin Functional Diagram Table 1. IRQ Function FT OUT FTF IRQ STATE 1 X 1 1 Hz 1 X 0 512 Hz 0 1 X 1 0 0 X 0 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq32000 5 bq32000 SLUS900B – DECEMBER 2008 – REVISED JUNE 2009................................................................................................................................................... www.ti.com VBACK Switchover The bq32000 has an internal switchover circuit that causes the device to switch from main power supply to backup power supply when the voltage of the main supply pin VCC drops below a minimum threshold. The VBACK switchover circuit uses an internal reference voltage VREF derived from the on-chip bandgap reference; VREF is approximately 2.8 V. The device switches to the VBACK supply when VCC is less than the lesser of VBACK or VREF. Similarly, the device switches to the VCC supply when VCC is greater than either VBACK or VREF. V BACK > VREF V BACK > VREF 3.3V VB AC K VR E F VC C Voltage Voltage VC C –5 V/ms (max) 3.3V VB AC K VR E F T ime On VC C Time On V BAC K On V BAC K V REF > V BACK V REF > V BACK 3.3V 3.3V VR E F VR E F Voltage VB AC K VC C Voltage VB AC K VC C –5 V/ms (max) T ime On VC C On V C C Time On V BAC K On V BAC K On V C C Figure 2. Switchover Diagram 6 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq32000 bq32000 www.ti.com................................................................................................................................................... SLUS900B – DECEMBER 2008 – REVISED JUNE 2009 Trickle Charge The bq32000 includes a trickle charge circuit to maintain the charge of the backup supply when a super capacitor is used. The trickle charge circuit is implemented as a series of three switches that are independently controlled by setting the TCHE[3:0], TCH2, and TCFE bits in the register space. TCHE[3:0] must be written as 0x5h and TCH2 as 1 to close the trickle charge switches and enable charging of the backup supply from VCC. Additionally, TCFE can be set to 1 to bypass the internal diode and boost the charge voltage of the backup supply. All trickle charge switches are opened when the device is initially powered on and each time the device switches from the main supply to the backup supply. The trickle charge circuit is intended for use with super capacitors; however, it can be used with a rechargeable battery under certain conditions. Care must be taken not to overcharge a rechargeable battery when enabling trickle charge. Follow all charging guidelines specific to the rechargeable battery or super capacitor when enabling trickle charge. 20 kW VBACK 180 W 940 W Figure 3. Trickle Charge Switch Functional Diagram I2C Serial Interface The I2C interface allows control and monitoring of the RTC by a microcontroller. I2C is a two-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with off-chip pullup resistors. When the bus is idle, both SDA and SCL lines are pulled high. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. This device operates only as a slave device. I2C communication is initiated by a master sending a start condition, a high-to-low transition on the SDA I/O while SCL is held high. After the start condition, the device address byte is sent, most-significant bit (MSB) first, including the data direction bit (R/W). After receiving a valid address byte, this device responds with an acknowledge, a low on the SDA I/O during the high of the acknowledge-related clock pulse. This device responds to the I2C slave address 11010000b for write commands and slave address 11010001b for read commands. This device does not respond to the general call address. A data byte follows the address acknowledge. If the R/W bit is low, the data is written from the master. If the R/W bit is high, the data from this device are the values read from the register previously selected by a write to the subaddress register. The data byte is followed by an acknowledge sent from this device. Data is output only if complete bytes are received and acknowledged. A stop condition, which is a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the master to terminate the transfer. A master device must wait at least 60 µs after the RTC exits backup mode to generate a START condition. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq32000 7 bq32000 SLUS900B – DECEMBER 2008 – REVISED JUNE 2009................................................................................................................................................... www.ti.com ticf SDA ticr tsdh tvd 0.7 VCC 0.3 VCC Start Condition ticf ticr tsds tsch SCL 0.7 VCC 1 0.3 VCC 2 3 4 tscl tsth 1/fscl Stop Condition tvd SDA 0.7 VCC 0.3 VCC tbuf D7/A Start Condition tsds SCL 0.7 VCC 0.3 VCC 8 9 tsps Figure 4. I2C Timing Diagram Table 2. I2C Timing PARAMETER STANDARD MODE MIN TYP FAST MODE MAX MIN fscl I2C clock frequency 0 tsch I2C clock high time 4 0.6 tscl I2C clock low time 4.7 1.3 tsp I2C spike time 2 tsds I C serial data setup time tsdh I2C serial data hold time ticr I2C input rise time 0 100 0 50 0 250 100 0 0 2 TYP MAX 400 UNIT kHz µs µs 50 ns ns ns 1000 20 + 0.1Cb (1) 300 (1) 300 ns 300 µs ticf I C input fall time 300 20 + 0.1Cb tocf I2C output fall time 300 20 + 0.1Cb (1) tbuf I2C bus free time ns 4.7 1.3 µs tsts I C Start setup time 4.7 0.6 µs tsth I2C Start hold time 4 0.6 µs tsps I2C Stop setup time 4 0.6 tvd (data) Valid data time (SCL low to SDA valid) 1 1 µs tvd (ack) Valid data time of ACK (ACK signal from SCL low to SDA low) 1 1 µs (1) 8 2 µs Cb = total capacitance of one bus line in pF Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq32000 bq32000 www.ti.com................................................................................................................................................... SLUS900B – DECEMBER 2008 – REVISED JUNE 2009 Figure 5. I2C Read Mode Figure 6. I2C Write Mode Register Maps Table 3. Normal Registers REGISTER ADDRESS (HEX) REGISTER NAME DESCRIPTION 0 0x00 SECONDS Clock seconds and STOP bit 1 0x01 MINUTES Clock minutes 2 0x02 CENT_HOURS 3 0x03 DAY Clock day 4 0x04 DATE Clock date 5 0x05 MONTH Clock month 6 0x06 YEARS Clock years 7 0x07 CAL_CFG1 8 0x08 TCH2 Trickle charge enable 9 0x09 CFG2 Configuration 2 Clock hours, century, and CENT_EN bit Calibration and configuration Table 4. Special Function Registers REGISTER ADDRESS (HEX) REGISTER NAME DESCRIPTION 20 0x14 SF KEY 1 Special function key 1 21 0x15 SF KEY 2 Special function key 2 22 0x16 SFR Special function register Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq32000 9 bq32000 SLUS900B – DECEMBER 2008 – REVISED JUNE 2009................................................................................................................................................... www.ti.com Normal Register Descriptions SECONDS Register Address Name Initial Value Description D7 STOP r/w 0 UC STOP 10_SECOND 1_SECOND 0x00 SECONDS 0XXXXXXb Clock seconds and STOP bit D6 X UC D5 10_SECOND r/w X UC D4 D3 D2 D1 D0 X UC X UC 1_SECOND r/w X UC X UC X UC BIT(S) Name Read/Write Initial Cycle Oscillator stop. The STOP bit is used to force the oscillator to stop oscillating. STOP is set to 0 on initial application of power, on all subsequent power cycles STOP remains unchanged. On initial power application STOP can be written to 1 and then written to 0 to force start the oscillator. 0 Normal 1 Stop BCD of tens of seconds. The 10_SECOND bits are the BCD representation of the number of tens of seconds on the clock. Valid values are 0 to 5. If invalid data is written to 10_SECOND, the clock will update with invalid data in 10_SECOND until the counter rolls over; thereafter, the data in 10_SECOND is valid. BCD of seconds. The 1_SECOND bits are the BCD representation of the number of seconds on the clock. Valid values are 0 to 9. If invalid data is written to 1_SECOND, the clock will update with invalid data in 1_SECOND until the counter rolls over; thereafter, the data in 1_SECOND is valid. MINUTES Register Address Name Initial Value Description D7 OF r/w 1 0 D6 X UC OF 10_MINUTE 1_MINUTE 10 0x01 MINUTES 1XXXXXXb Clock minutes D5 10_MINUTE r/w X UC D4 D3 D2 D1 D0 X UC X UC 1_MINUTE r/w X UC X UC X UC BIT(S) Name Read/Write Initial Cycle Oscillator fail flag. The OF bit is a latched flag indicating when the 32.768-kHz oscillator has dropped at least four consecutive pulses. The OF flag is always set on initial power-up, and it can be cleared through the serial interface. When OF is 0, no oscillator failure has been detected. When OF is 1, the oscillator fail detect circuit has detected at least four consecutive dropped pulses. 0 No failure detected 1 Failure detected BCD of tens of minutes. The 10_MINUTE bits are the BCD representation of the number of tens of minutes on the clock. Valid values are 0 to 5. If invalid data is written to 10_MINUTE, the clock will update with invalid data in 10_MINUTE until the counter rolls over; thereafter, the data in 10_MINUTE is valid. BCD of minutes. The 1_MINUTE bits are the BCD representation of the number of minutes on the clock. Valid values are 0 to 9. If invalid data is written to 1_MINUTE, the clock will update with invalid data in 1_MINUTE until the counter rolls over; thereafter, the data in 1_MINUTE is valid. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq32000 bq32000 www.ti.com................................................................................................................................................... SLUS900B – DECEMBER 2008 – REVISED JUNE 2009 CENT_HOURS Register Address Name Initial Value Description D7 CENT_EN r/w X UC CENT_EN CENT 10_HOUR 1_HOUR 0x02 CENT_HOURS XXXXXXXXb Clock hours, century, and CENT_EN bit D6 CENT r/w X UC D5 D4 D3 D2 10_HOUR r/w X UC D1 D0 X UC X UC 1_HOUR r/w X UC X UC X UC BIT(S) Name Read/Write Initial Cycle Century enable. The CENT_EN bit enables the century timekeeping feature. If CENT_EN is set to 1, then the clock tracks the century using the CENT bit. If CENT_EN is set to 0, the clock ignores the CENT bit. 0 Century disabled 1 Century enabled Century. The CENT bit tracks the century when century timekeeping is enabled. The clock toggles the CENT bit when the year count rolls from 99 to 00. Because the clock compliments the CENT bit, the user can define the meaning of CENT (1 for current century and 0 for next century, or 0 for current century and 1 for next century). BCD of tens of hours (24-hour format). The 10_HOUR bits are the BCD representation of the number of tens of hours on the clock, in 24-hour format. Valid values are 0 to 2. If invalid data is written to 10_HOUR, the clock will update with invalid data in 10_HOUR until the counter rolls over; thereafter, the data in 10_HOUR is valid. BCD of hours (24-hour format). The 1_HOUR bits are the BCD representation of the number of hours on the clock, in 24-hour format. Valid values are 0 to 9. If invalid data is written to 1_HOUR, the clock will update with invalid data in 1_HOUR until the counter rolls over; thereafter, the data in 1_HOUR is valid. DAY Register Address Name Initial Value Description 0x03 DAY 00000XXXb Clock day D7 D6 0 0 0 0 RSVD DAY D5 RSVD r/w 0 0 D4 D3 D2 0 0 0 0 X UC D1 DAY r/w X UC D0 X UC BIT(S) Name Read/Write Initial Cycle Reserved. The RSVD bits should always be written as 0. BCD of the day of the week. The DAY bits are the BCD representation of the day of the week. Valid values are 1 to 7 and represent the days from Sunday to Saturday. DAY updates if set to 0 until the counter rolls over; thereafter, the data in DAY is valid. 1 Sunday 2 Monday 3 Tuesday 4 Wednesday 5 Thursday 6 Friday 7 Saturday Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq32000 11 bq32000 SLUS900B – DECEMBER 2008 – REVISED JUNE 2009................................................................................................................................................... www.ti.com DATE Register Address Name Initial Value Description D7 0x04 DATE 00XXXXXXb Clock date D6 D5 RSVD r/w 0 0 0 0 RSVD 10_DATE 1_DATE (1) D4 D3 D2 10_DATE r/w X UC D1 D0 X UC X UC 1_DATE r/w X UC X UC X UC BIT(S) Name Read/Write Initial Cycle Reserved. The RSVD bits should always be written as 0. BCD of tens of date. The 10_DATE bits are the BCD representation of the tens of date on the clock. Valid values are 0 to 3 (1). If invalid data is written to 10_DATE, the clock will update with invalid data in 10_DATE until the counter rolls over; thereafter, the data in 10_DATE is valid. BCD of date. The 1_DATE bits are the BCD representation of the date on the clock. Valid values are 0 to 9 (1). If invalid data is written to 1_DATE, the clock will update with invalid data in 1_DATE until the counter rolls over; thereafter, the data in 1_DATE is valid. 10_DATE and 1_DATE must form a valid date, 01 to 31, dependent on month and year. MONTH Register Address Name Initial Value Description D7 D6 RSVD r/w 0 0 0 0 RSVD 10_MONTH 1_MONTH (1) 0x05 MONTH 000XXXXXb Clock month D5 0 0 D4 10_MONTH r/w X UC D3 D2 D1 D0 X UC X UC 1_MONTH r/w X UC X UC BIT(S) Name Read/Write Initial Cycle Reserved. The RSVD bits should always be written as 0. BCD of tens of month. The 10_MONTH bits are the BCD representation of the tens of month on the clock. Valid values are 0 to 1 (1). If invalid data is written to 10_MONTH, the clock will update with invalid data in 10_MONTH until the counter rolls over; thereafter, the data in 10_MONTH is valid. BCD of month. The 1_MONTH bits are the BCD representation of the month on the clock. Valid values are 0 to 9 (1). If invalid data is written to 1_MONTH, the clock will update with invalid data in 1_MONTH until the counter rolls over; thereafter, the data in 1_MONTH is valid. 10_MONTH and 1_MONTH must form a valid date, 01 to 12. YEARS Register Address Name Initial Value Description D7 0x06 YEARS XXXXXXXXb Clock year D6 D5 D4 D3 D2 10_YEAR r/w X UC X UC 10_YEAR 1_YEAR 12 D1 D0 X UC X UC 1_YEAR r/w X UC X UC X UC X UC BIT(S) Name Read/Write Initial Cycle BCD of tens of years. The 10_YEAR bits are the BCD representation of the tens of years on the clock. Valid values are 0 to 9. If invalid data is written to 10_YEAR, the clock will update with invalid data in 10_YEAR until the counter rolls over; thereafter, the data in 10_YEAR is valid. BCD of year. The 1_YEAR bits are the BCD representation of the years on the clock. Valid values are 0 to 9. If invalid data is written to 1_YEAR, the clock will update with invalid data in 1_YEAR until the counter rolls over; thereafter, the data in 1_YEAR is valid. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq32000 bq32000 www.ti.com................................................................................................................................................... SLUS900B – DECEMBER 2008 – REVISED JUNE 2009 CAL_CFG1 Register Address Name Initial Value Description D7 OUT r/w 1 UC 0x07 CAL_CFG1 10000000b Calibration and control D6 FT r/w 0 UC OUT D5 S r/w 0 UC D4 D3 0 UC 0 UC D2 CAL r/w 0 UC D1 D0 0 UC 0 UC BIT(S) Name Read/Write Initial Cycle Logic output, when FT = 0. When FT is zero, the logic output of IRQ pin reflects the value of OUT. 0 IRQ is logic 0 1 IRQ is logic 1 Frequency test. The FT bit is used to enable the frequency test signal on the IRQ pin. When FT is 1, a square wave is produced on the IRQ pin. The FTF bit in the SFR register determines the frequency of the test signal. 0 Disable 1 Enable Calibration sign. The S bit determines the polarity of the calibration applied to the oscillator. If S is 0, then the calibration slows the RTC. If S is 1, then the calibration speeds the RTC. 0 Slowing (+) 1 Speeding (–) Calibration. The CAL bits along with S determine the calibration amount as shown in Table 5. FT S CAL Table 5. Calibration CAL (DEC) S=0 S=1 0 +0 ppm –0 ppm 1 +2 ppm –4 ppm N +N / 491520 (per minute) –N / 245760 (per minute) 30 +61 ppm –122 ppm 31 +63 ppm –126 ppm TCH2 Register Address Name Initial Value Description D7 0x08 TCH2 10010000b Trickle charge TCH2 control D6 RSVD r/w 1 UC RSVD TCH2 0 0 D5 TCH2 r/w 0 0 D4 D3 1 1 0 UC D2 RSVD r/w 0 UC D1 D0 0 UC 0 UC BIT(S) Name Read/Write Initial Cycle Reserved. The RSVD bits should always be written as 0. Trickle charge switch two. The TCH2 bit determines if the internal trickle charge switch is closed or open. All the trickle charge switches must be closed in order for trickle charging to occur. If TCH2 is 0, then the TCH2 switch is open. If TCH2 is 1, then the TCH2 switch is closed. 0 Open 1 Closed Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq32000 13 bq32000 SLUS900B – DECEMBER 2008 – REVISED JUNE 2009................................................................................................................................................... www.ti.com CFG2 Register Address Name Initial Value Description D7 RSVD r/w 1 1 RSVD TCFE TCHE 14 0x09 CFG2 10101010b Configuration 2 D6 TCFE r/w 0 0 D5 D4 D3 D2 RSVD r/w 1 UC D1 D0 1 1 0 0 TCHE r/w 0 UC 1 1 0 0 BIT(S) Name Read/Write Initial Cycle Reserved. The RSVD bits should always be written as 0. Trickle charge FET bypass. The TCFE bit is used to enable the trickle charge FET. When TCFE is 0, the FET is off. When TCFE is 1, the FET is on. 0 Open 1 Closed Trickle charge enable. The TCHE bits determine if the trickle charger is active. If TCHE is 0x5, then the trickle charger is active, otherwise, the trickle charger is inactive. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq32000 bq32000 www.ti.com................................................................................................................................................... SLUS900B – DECEMBER 2008 – REVISED JUNE 2009 Special Function Registers SF KEY 1 Register Address Name Initial Value Description D7 0x20 SF KEY 1 00000000b Special function key 1 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 SF KEY B1 r/w 0 0 SF KEY B1 0 0 0 0 0 0 BIT(S) Name Read/Write Initial Cycle Special function access key byte 1. Reads as 0x00, and key is 0x5E. The SF KEY 1 and SF KEY 2 registers are used to enable access to the main special function register (SFR). Access to SFR is granted only after the special function keys are written sequentially to SF KEY 1 and SF KEY 2. Each write to the SFR must be preceded by writing the SF keys to the SF key registers, in order, SF KEY 1 then SF KEY 2. SF KEY 2 Register Address Name Initial Value Description D7 0x21 SF KEY 2 00000000b Special function key 2 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 SF KEY 2 r/w 0 0 SF KEY 2 0 0 0 0 0 0 BIT(S) Name Read/Write Initial Cycle Special function access key byte 2. Reads as 0x00, and key is 0xC7. The SF KEY 1 and SF KEY 2 registers are used to enable access to the main special function register (SFR). Access to SFR is granted only after the special function keys are written sequentially to SF KEY 1 and SF KEY 2. Each write to the SFR must be preceded by writing the SF keys to the SF key registers, in order, SF KEY 1 then SF KEY 2. SFR Register Address Name Initial Value Description 0x22 SFR 00000000b Special function register 1 D7 D6 D5 0 0 0 0 0 0 RSVD FTF D4 RSVD r/w 0 0 D3 D2 D1 0 0 0 0 0 0 D0 FTF r/w 0 0 BIT(S) Name Read/Write Initial Cycle Reserved. The RSVD bits should always be written as 0. Force calibration to 1 Hz. FTF allows the frequency of the calibration output to be changed from 512 Hz to 1 Hz. By default, FTF is cleared, and the RTC outputs a 512-Hz calibration signal. Setting FTF forces the calibration signal to 1 Hz, and the calibration tracks the internal ppm adjustment. Note: The default 512-Hz calibration signal does not include the effect of the ppm adjustment. 0 Normal 512-Hz calibration 1 1-Hz calibration Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq32000 15 PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty BQ32000D ACTIVE SOIC D 8 BQ32000DR ACTIVE SOIC D 8 75 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jun-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device BQ32000DR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 6.4 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jun-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ32000DR SOIC D 8 2500 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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