LINEAR TECHNOLOGY NOVEMBER 1998 IN THIS ISSUE… COVER ARTICLE World’s Smallest 24-Bit ADC Packs High Accuracy, Ease of Use, into SO-8 ..................................................... 1 Michael K. Mayes Issue Highlights ............................ 2 VOLUME VIII NUMBER 4 World’s Smallest 24-Bit ADC Packs High Accuracy, Ease of Use, into SO-8 LTC® in the News ........................... 2 DESIGN FEATURES Wide Input Range, High Efficiency Step-Down Switching Regulators .................... 5 Jeff Schenkel A 4.5ns, 4mA, Single-Supply, Dual Comparator Optimized for 3V/5V Operation .......................... 10 Joseph G. Petrofsky 250MHz RGB Video Multiplexer in Space-Saving Package Drives Cables, Switches Pixels at 100MHz ......... 16 John Wright and Frank Cox LT ®1468: An Operational Amplifier for Fast, 16-Bit Systems .............. 18 George Feliz LTC1622: Low Input Voltage, Current Mode PWM Buck Converter .......... 21 San-Hwa Chee LTC1531 Isolated Comparator .... 24 Wayne Shumaker DESIGN IDEAS PolyPhase™ Switching Regulators Offer High Efficiency in Low Voltage, High Current Applications .......... 27 Craig Varga Level Shift Allows CFA Video Amplifier to Swing to Ground on a Single Supply ...................... 30 Frank Cox DESIGN INFORMATION Component and Measurement Advances Ensure 16-Bit DAC Settling Time (Part Two) ........................... 31 Jim Williams Net1 and Net2 Serial Interface Chip Set Supports Test Mode ............... 34 David Soo New Device Cameos ..................... 37 Design Tools ................................ 39 Sales Offices ............................... 40 by Michael K. Mayes Introduction Overview Linear Technology enters the deltasigma1, 2 analog-to-digital converter market with a tiny, high performance, 24-bit ADC, the LTC2400. The device’s superiority to existing deltasigma ADC’s results from the combination of an accurate analog modulator with an innovative new digital architecture. Typically, fineline, digitally optimized processes are required for a delta-sigma ADC’s on-chip digital filter. The resulting ICs have high pin counts, large packages and complex interfaces. The LTC2400’s breakthrough in digital filtering allows the use of an analogoptimized process. The result is the smallest (SO-8 package), lowest pin count (8) simplest to use delta-sigma converter on the market. A highly accurate on-chip oscillator, using Linear’s high performance CMOS process, sets the digital filter’s notch frequency, eliminating the need for an external crystal. Additionally, the part offers exceptional INL, DNL, noise and 50Hz/60Hz rejection. The innovation does not end here; this article will show how performance, ease of use and functionality make this part the new state of the art in high resolution delta-sigma ADCs. The analog modulator is critical to the performance of a delta-sigma ADC. For high DC accuracy, 1st or 2nd order modulators provide insufficient differential nonlinearity (DNL). The LTC2400 achieves optimum DC performance from a 3rd order delta-sigma modulator (see Figure 1). Feedforward compensation and analog processing within the modulator eliminate instability issues associated with high order modulators. The 1-bit ADC and DAC within the modulator guarantee monotonicity and exceptional INL performance of 4ppm. The output of the delta-sigma modulator is applied to a decimating filter. The sinc4 filter removes the quantization noise from the modulator output. Additionally, this filter rejects the fundamental frequency and its harmonics. This notch frequency is set by an on-chip oscillator, typically at line frequency for DC applications. The combination of a 4th order sinc filter with a precision thin-film, factory-trimmed oscillator guarantees at least 120dB rejection of line frequency ±2%. Several converters on the market use sinc3 or sinc1 filters. Since line frequencies can vary up to 2% over a 24-hour period, converters using these lower order filters cannot achieve 120dB Authors can be contacted at (408) 432-1900 continued on page 3 , LTC and LT are registered trademarks of Linear Technology Corporation. Adaptive Power, Burst Mode, C-Load, FilterCAD, Hot Swap, LinearView, Micropower SwitcherCAD, No R SENSE, PolyPhase, SwitcherCAD and UltraFast are trademarks of Linear Technology Corporation. Other product names may be trademarks of the companies that manufacture the products. DESIGN FEATURES VCC GND VIN INTERNAL OSCILLATOR AUTOCALIBRATION AND CONTROL ∫ ∫ fO (INT/EXT) ∫ Σ DOUT SERIAL INTERFACE ADC SCLK CS VREF DECIMATING FIR FILTER DAC Figure 1. LTC2400 block diagram rejection, even with exact external oscillators (refer to Figure 6a). A simple, SPI-compatible 3-wire interface outputs data with singlecycle settling. This simplifies the user interface by eliminating latency and redundant data normally associated with delta-sigma ADCs. As a black box, the converter resembles traditional, easy-to-use converters. Performance 5 5 4 4 3 2 VCC = 5V VREF = 2.5V TA = 25°C fO = GND 1 0 –1 –2 3 OFFSET ERROR (ppm) INTEGRAL NONLINEARITY (ppm) Designed on a 2µ , single-metal, analog CMOS process, the LTC2400 is implemented with a die size under 10kmil2. The key to Linear attaining the nearly impossible is the highly efficient sinc4 filter. Once the tiny digital circuitry was completed, the analog circuitry was optimized for ultrahigh performance. The result is 24-bit DNL with no missing codes guaranteed. As shown in Figure 2, the integral nonlinearity is a mere ±2ppm or 0.0002%. This compares favorably with other 24-bit devices’ INL performance of 15ppm– 30ppm. Transparent to the user, the converter continuously executes selfcalibration algorithms automatically adjusting the offset and full-scale. With an initial accuracy of 1ppm, the offset drifts less than 0.01ppm/°C and the full scale drifts less than 0.02ppm/°C (see Figures 3 and 4). Combining these DC parameters with RMS noise performance of 0.3ppm (see Figure 5), the LTC2400 resembles a 6-digit digital voltmeter on a chip. The modulator consists of operational amplifiers and switched capacitor circuits. Previous deltasigma converters place limitations on these circuits. Since the LTC2400 was designed on an analog process, these limitations are removed. This 2 –2 –4 Linear Technology Magazine • November 1998 3 –1 –4 Figure 2. LTC2400 integral nonlinearity error 4 VCC = 5V VREF = 5V fO = GND 0 –3 –5 0.00E+00 4.19E+06 8.39E+06 1.26E+07 1.68E+07 OUTPUT CODE (DECIMAL) 5 1 –3 –5 –40 allows a power supply range of 2.7V to 5.5V and a reference range of from below 10mV to 90% of VCC. At V CC = 3V, the power consumption is 750µ W; it falls to 45µ W in power-down mode. In many applications, the input signal may exceed VREF or fall below ground. Conventional delta-sigma converters are unable to provide the user with any indication of these overrange conditions. The LTC2400 has on-chip overrange circuitry. It continues to output 24-bit valid data over an effective input range of –12.5% × VREF to 112.5% × VREF. One of the main advantages of delta-sigma converters over SAR or flash-type architectures is the inherent rejection of line frequency. In order to achieve good rejection, past deltasigma converters required an accurate external oscillator or crystal with a precise, uncommon value. The LTC2400 incorporates an on-chip oscillator eliminating the need for FULL-SCALE ERROR (ppm) LTC2400, continued from page 1 2 1 0 –1 –2 VCC = 5V VREF = 5V fO = GND –3 –4 –15 10 35 60 TEMPERATURE (°C) Figure 3. Offset drift 85 –5 –40 –15 10 35 60 TEMPERATURE (°C) 85 Figure 4. Full-scale drift 3 DESIGN FEATURES 0 1200 RMS NOISE = 0.3ppm =1.5µV PEAK-TO-PEAK NOISE = 1.8ppm = 9µV OFFSET ERROR = 0.28ppm –20 800 600 VDD = 5V VREF = 5V TA = 25°C fO = GND SINC2 –60 –80 400 –100 200 –120 0 –1.2 SINC –40 1000 REJECTION (dB) NUMBER OF OCCURRENCES AT VIN = OV 1400 SINC3 SINC4 (LTC2400) –140 –1 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 OUTPUT CODE (ppm OF VREF) 0.6 0.8 1.0 0 1.2 50 100 150 200 FREQUENCY (Hz) 250 300 Figure 6a. Filter response vs filter order Figure 5. Noise histogram 0 Ease of Use At a glance, the LTC2400 looks more like an op amp than a delta-sigma converter. With only eight pins, it’s about as easy to use as a common op amp (see Figure 8). Superior noise rejection and internal analog circuitry enable the use of one supply pin, one ground pin and a single-ended input. The internal oscillator eliminates external crystals/capacitors and added device pins. The remaining pins form a standard 3-wire interface, consisting of a three-statable serial data output (DOUT) under the control of a chip select pin (CS) and a serial data output clock (SCLK). Applications currently using traditional ADCs can easily migrate to the LTC2400. Single-cycle settling yields a one-to-one correspondence between the start of a conversion and the output word. This allows the user to place a multiplexer in front of the ADC without worrying about latency or data statistically dependent on previous conversion results. –20 –40 REJECTION (dB) external components. The internal oscillator is so precise that the ADC rejects line frequency over a ±2% range, independent of supply or operating temperature (see Figure 6a, where sinc1, sinc2 and sinc3 filters are shown for comparison). Line frequencies of 50Hz or 60Hz are selectable by simply tying the fO pin to VCC or ground. Other rejection frequencies can be obtained by driving the fO pin with an external clock. The converter is so robust that the noise performance and line rejection are insensitive to layout. As shown in Figure 7, large noise errors applied to VCC, VREF or VIN (1.25VP-P, 60Hz, ±2%) have no effect on the ADC’s noise and linearity performance. –60 –80 –100 –120 –140 –5.8% –3.3% 60 +3.3% +5.8% FREQUENCY (Hz) Figure 6b. Filter response at line frequency Functionality Despite its small size and low pin count, the LTC2400 provides many flexible modes of operation. For example, tying CS low forces a continuous conversion mode. With CS tied high, the device enters a 45µ W power-down mode. For applications requiring ultralow power, a capacitor can be tied to CS. Under this continued on page 36 CODE OUT (ppm) 20 ONE-SHOT OUTPUT CODE (NO AVERAGING) 10 0 –10 –20 INJECTED NOISE VIN 1VRMS VCC VREF 60Hz TIME Figure 7. Noise injection 4 Linear Technology Magazine • November 1998 CONTINUATIONS Level Shift, continued from page 30 Fortunately, there is always synchronization information associated with video. A simple circuit can be used to DC restore voltage offsets produced by resistor mismatch, op amp offset or DC errors in the input video. Figure 2 shows the additional circuitry needed to perform this function. The LTC201A analog switch and C1 store the offset error during blanking. The clamp pulse should be 3µ s or wider and should occur during blanking. It can conveniently be made by delaying the sync pulse with one shots. If the sync tip is clamped, the clamp pulse must start after and end before the sync pulse or offset errors will be introduced. The integrator made with the LT1632 adjusts the voltage at point B (see Figure 1) to correct the offset. 12V 5V 13 R1 10k C2 6800pF FILM 1/2 LTC201A 3, 14 R3 10k 2, 15 C1 10µF FILM R2 10k 12V TO FIGURE 1, POINT A C3 0.1µF + 1, 16 4, 5 – R4 1.40k VIDEO R7 10k 1/2 LT1632 5V TO FIGURE 1, POINT B R5 50k HOLD 5V C4 0.1µF DC RESTORE LEVEL (ADJUST FOR DESIRED BLANKING LEVEL) 0V SAMPLE R6 20k CLAMP PULSE Figure 2. DC restore subcircuit LTC2400, continued from page 4 configuration, the part performs one conversion, then automatically enters the power-down mode. The duration of the power-down mode is proportional to the capacitor value. While CS is held high, the serial data out pin is high impedance. Once CS is pulled low, the part begins outputting data under the control of the SCLK pin. This device can operate with either an internal or external serial clock. If the SCLK pin is left floating, the LTC2400 automatically detects this state and switches to internal clock mode. If the user drives the SCLK pin with his own clock, the part is automatically switched to external clock mode. Many delta-sigma ADC’s on the market include a PGA. These PGAs require that the designer deal with more device pins, status registers and timing sequences. Additionally, they limit the circuit’s input range. For example, if the PGA’s gain is 256 and the reference is 2.5V the resulting input range is 0mV to 10mV. 36 2.7V–5.5V 60Hz REJECTION 1µF LTC2400 VCC 2.5V –300mV TO 2.8V SCLK VIN DOUT GND Conclusion fO VREF CS reduce the board area required by existing designs. } 3-WIRE SPI INTERFACE Figure 8. LTC2400 typical application The LTC2400 provides better noise and TUE (total unadjusted error) performance than previous delta-sigma ADCs; moreover, the user is no longer confined to a 10mV input range. The input can still range between –12.5% × VREF and 112.5% × VREF. The eight MSBs determine the coarse input range. For example, if the eight MSBs = 00h, the input (VIN ) is in the range: 0 < VIN < 10mV, whereas 01h corresponds to 10mV < VIN < 20mV, and so on. This enables the LTC2400 to directly digitize a variety of low level sensors with large offsets. The LTC2400 package is the smallest on the market (SO-8). This tiny chip combined with no external components enables the user to greatly The LTC2400 is the first of a family of delta-sigma converters from LTC. It offers a combination of the best characteristics of delta-sigma converters and conventional converters. Its attributes include latency-free operation and high precision INL, DNL and offset. It frees the user from adding external components and is easy to use. The on-chip sinc4 filter reduces line frequency noise and its harmonics by 120dB, making it ideal for use in noisy environments. With only eight pins, an on-chip oscillator, 24-bit DNL, 4ppm INL and 10ppm TUE, the LTC2400 is the new state of the art in analog-to-digital conversion. Notes: 1.Candy, J.C and G.C. Temes. “Oversampling Methods for A/D and D/A Conversion,” in Oversampling Delta-Sigma Data Converters. IEEE Press, 1992. 2. Hauser, Max W. “Principles of Oversampling and A/D Conversion.” Journal of the Audio Engineering Society, Vol. 39, No. 1/2 (January/February 1991) pp. 3–26. Linear Technology Magazine • November 1998