LT3782 2-Phase Step-Up DC/DC Controller U FEATURES DESCRIPTIO ■ The LT®3782 is a current mode two phase step-up DC/DC converter controller. Its high switching frequency (up to 500kHz) and 2-phase operation reduce system filtering capacitance and inductance requirements. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2-Phase Operation Reduces Required Input and Output Capacitance Programmable Switching Frequency: 150kHz to 500kHz 6V to 40V Input Range 10V Gate Drive with VCC ≥13V High Current Gate Drive (4A) Programmable Soft-Start and Current Limit Programmable Slope Compensation for High Noise Immunity MOSFET Gate Signals with Programmable Falling Edge Delay for External Synchronous Drivers Programmable Undervoltage Lockout Programmable Duty Cycle Clamp (50% or Higher) Thermally Enhanced 28-Lead SSOP Package With 10V gate drive (VCC ≥13V) and 4A peak drive current, the LT3782 can drive most industrial grade high power MOSFETs with high efficiency. For synchronous applications, the LT3782 provides synchronous gate signals with programmable falling edge delay to avoid cross conduction when using external MOSFET drivers. Other features include programmable undervoltage lockout, soft-start, current limit, duty cycle clamp (50% or higher) and slope compensation. The LT3782 is available in a thermally enhanced 28-lead SSOP package. U APPLICATIO S ■ ■ Industrial Equipment Telecom Infrastructure Interleaved Isolated Power Supply U ■ , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6144194. TYPICAL APPLICATIO 50V 4A Boost Converter L1 R6 825k CIN 10µF 50V 2x 1µF GBIAS2 + GBIAS RUN C3 L2 2µF M1 Si7852dp 2x BGATE1 R8 274k COUT1 10µF 50V 2x D1 30BQ060 GBIAS1 VCC + D2 30BQ060 VOUT 50V, 4A M2 Si7852dp 2x BGATE2 DELAY RFREQ 80k RS2 0.004Ω DCL RSET SS 0.1µF VC 13k 100pF 6.8nF 15 VIN = 12V L1, L2: PB2020.223 CIN, COUT1: X7R, TDK 93 12 VIN = 12V 91 9 VIN = 24V 89 6 POWER LOSS (W) SLOPE 18 VIN = 24V EFFICIENCY 95 VEE1 RSLOPE 59k 97 COUT2 220µF RS1 0.004Ω LT3782 Efficiency and Power Loss vs Load Current EFFICIENCY (%) VIN 10V TO 36V POWER LOSS 87 3 VEE2 10Ω 10Ω 85 SENSE1+ SENSE1– SENSE2+ SENSE2– FB GND 10nF 10nF 1 2 3 IOUT (A) 4 5 0 3782 TA01b RF1 475k 3782 TA01 0 RF2 24.9k 3782fa 1 LT3782 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) TOP VIEW VCC Supply Voltage .................................................. 40V GBIAS, GBIAS1, GBIAS2 Pin (Externally Forced) ............................................................................ 14V SYNC, RUN Pin ........................................................ 30V Operating Junction Temperature Range (Notes 2, 3) .......................................................... –40°C to 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C SS ................................................................– 0.3V to 6V SENSE1+, SENSE2+, SENSE1–, SENSE2– ................................................................– 0.3V to 2V SGATE2 1 28 GBIAS SGATE1 2 27 VCC NC 3 26 NC GND 4 25 NC SYNC 5 24 VEE1 DELAY 6 23 BGATE1 DCL 7 SENSE1+ 8 21 GBIAS2 SENSE1– 9 20 BGATE2 29 SLOPE 10 RSET 11 ORDER PART NUMBER LT3782EFE 22 GBIAS1 19 VEE2 18 NC SENSE2– 12 17 RUN SENSE2+ 13 16 FB SS 14 15 VC FE PART MARKING LT3782EFE FE PACKAGE 28-LEAD PLASTIC SSOP EXPOSED PAD (PIN 29) IS GND MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 38°C/ W Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 13V, RSET = 80k, operating maximum VCC = 24V, no load on any outputs, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Overall ● Supply Voltage (VCC) Supply Current (IVCC) 6 VC ≤ 0.5V (Switching Off), VCC ≤ 40V 40 V 11 16 mA 2.45 2.6 V 0.4 40 0.65 90 mA µA –0.5 –2 µA V V Shutdown ● RUN Threshold 2.3 RUN Threshold Hysteresis 80 Supply Current in Shutdown 1V ≤ RUN ≤ VREF, VCC ≤ 30V RUN ≤ 0.3V, VCC ≤ 30V RUN Pin Input Current VRUN = 2.3V ● mV Voltage Amplifier gm Reference Voltage (VREF) 2.42 2.4 2.44 ● 2.464 2.488 200 260 370 µmho 0.2 0.6 µA Transconductance VVC = 1V, ∆IVC = ±2µA ● Input Current IFB VFB = VREF ● VC High IVC = 0 1.5 V VC Low IVC = 0 0.35 0.4 V Source Current IVC VVC = 0.7V – 1V, VFB = VREF – 100mV 8 11 14 µA Sink Current IVC VVC = 0.7V – 1V, VFB = VREF + 100mV 13 20 28 µA 10 15 µA ● VC Threshold for Switching Off (BGATE1, BGATE2 Low) Soft-Start Current ISS VSS = 0.1V – 2.8V 0.3 6 V 3782fa 2 LT3782 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 13V, RSET = 80k, operating maximum VCC = 24V, no load on any outputs, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Current Amplifier CA1, CA2 Voltage Gain ∆VC/∆VSENSE Current Limit (VSENSE1+ – VSENSE1–) (VSENSE2+ – VSENSE2–) Input Current (ISENSE1+, ISENSE1–, ISENSE2+, ISENSE2–) 4 50 ∆VSENSE = 0V 62 80 mV µA 60 Oscillator Switching Frequency ● ● ● RSET = 130k RSET = 80k RSET = 40k 130 212 386 154 250 465 1.2 Synchronization Pulse Threshold on SYNC Pin Rising Edge VSYNC 0.8 Synchronization Frequency Range (Note: Operation Switching Frequency Equals Half of the Synchronization Frequency) RSET = 130k RSET = 80k RSET = 40k 180 290 550 VRSET RSET = 80k Maximum Duty Cycle VFB = VREF – 25mV, RSET > 80K RSET = 40K Duty Cycle Limit RSET = 80k , VDCL ≤ 0.3V VDCL = 1.2V VDCL = VRSET DCL Pin Input Current VDCL = 0.3V ● VGBIAS IGBIAS < 70mA ● BGATE1, BGATE2 High Voltage 13V ≤ VCC ≤ 24V, IBGATE = –100mA VCC = 8V, IBGATE = –100mA ● ● BGATE1, BGATE2 Source Current (Peak) Capacitive Load >22µF Capacitive Load >50µF ● ● 90 83 177 288 533 2 240 392 715 kHz kHz kHz V kHz kHz kHz 2.3 V 94 90 % % 50 75 Max Duty Cycle % % –0.1 –0.3 µA 10.2 11 11.7 V 7.8 3.8 9.2 5 10.5 V V Gate Driver 3 4 A A BGATE1, BGATE2 Low Voltage 8V ≤ VCC ≤ 24V, IBGATE = 100mA BGATE1, BGATE2 Sink Current (Peak) Capacitive Load >22µF Capacitive Load >50µF SGATE1, SGATE2 High Voltage 8V ≤ VCC ≤ 24V, ISGATE = –20mA 5.5 6.7 V SGATE1, SGATE2 Low Voltage 8V ≤ VCC ≤ 24V, ISGATE = 20mA 0.5 0.7 V SGATE1, SGATE2 Peak Current 500pF Load 100 mA Delay of BGATE High DELAY Pin and RSET Pin Shorted VDELAY = 1V VDELAY = 0.5V VDELAY = 0.25V 100 150 250 500 ns ns ns ns Delay Pin Input Current VDELAY = 0.25V Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT3782 is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 125°C operating temperature range are assured by design, characterization and correlation with statistical process controls. ● 0.5 0.7 3 4 ● ● 4.5 –0.1 V A A –0.3 µA Note 3: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 3782fa 3 LT3782 U W TYPICAL PERFOR A CE CHARACTERISTICS 10.9 18 10.8 16 10.7 14 10.6 12 10.5 10.4 10 8 10.3 6 10.2 4 10.1 2 50 0 0 100 –2 –3 0 –4 –2 –4 12 15 18 21 24 VGBIAS (V) REFERENCE VOLTAGE (V) 2.440 2.438 800 700 VGBIAS 10 600 8 500 6 400 4 300 IGBIAS 2.436 2.434 0 25 75 100 125 50 JUNCTION TEMPERATURE (°C) 150 2 200 0 100 –2 250µ 0 500µ TIME (s) 750µ 0 1m 3782 G06 3782 G05 Switching Frequency vs Duty Cycle 1000 30 VGBIAS vs IGBIAS at Start-Up (Charging 2µF) 2.442 20 40 60 80 100 120 140 160 180 200 RFREQ (kΩ) 27 3782 G03 12 SGATE (Low) to BGATE (High) Delay vs VDELAY (RSET = 80k) Maximum Duty Cycle Limit vs VDCL (RSET = 80k) 105 120 900 110 DUTY CYCLE (%) 700 600 500 400 MAXIMUM DUTY CYCLE (%) 100 800 DELAY (ns) 9 14 3782 G04 95 90 300 200 85 100 90 80 70 60 50 100 0 2 ∆Frequency IGBIAS (mA) FREQUENCY (kHz) 4 VCC (V) 2.444 0 6 –1 6 2.446 600 100 8 ∆VREF 0 Reference Voltage vs Temperature 200 10 3782 G02 Switching Frequency vs RFREQ 300 2 –5 3782 G01 400 12 8 10 12 14 16 18 20 22 24 26 28 30 VCC (V) 6 IGBIAS (mA) 500 3 1 ∆VREF (mV) 20 ICC (mA) 11.0 10.0 ∆VREF vs VCC, ∆Frequency vs VCC (RSET = 80k) ICC vs VCC ∆FREQUENCY (kHz) VGBIAS (V) VGBIAS vs IGBIAS TA = 25°C unless otherwise noted. 0 0.5 1.5 1.0 VDELAY (V) 2.0 2.5 3782 G07 80 100 40 200 400 500 300 SWITCHING FREQUENCY (kHz) 600 3782 G08 0 0.3 0.6 0.9 1.2 1.5 VDCL (V) 1.8 2.1 2.4 3782 G09 3782fa 4 LT3782 U U U PI FU CTIO S SGATE2 (Pin 1): Second Phase Synchronous Drive Signal. An external driver buffer is needed to drive the top synchronous power FET. SGATE1 (Pin 2): First Phase Synchronous Drive Signal. An external driver buffer is needed to drive the top synchronous power FET. NC (Pin 3): Not Connected. Can be connected to GND. GND (Pin 4): Chip Ground. SYNC (Pin 5): Synchronization Input. The pulse width can range from 10% to 70%. Note that the operating frequency is half of the sync frequency. DELAY (Pin 6): When synchronous drivers are used, the programmable delay that delays BGATE turns on after SGATE turns off. DCL (Pin 7): This pin programs the limit of the maximum duty cycle. When connected to VRSET, it operates at natural maximum duty cycle, approximately 90%. SENSE1+ (Pin 8): First Phase Current Sense Amplifier Positive Input. An RC filter is required across the current sense resistor. Current limit threshold is set at 60mV. SENSE1– (Pin 9): First Phase Current Sense Amplifier Negative Input. An RC filter is required across the current sense resistor. SLOPE (Pin 10): A resistor from SLOPE to GND increases the internal current mode PWM slope compensation. RSET (Pin 11): A resistor from RSET to GND sets the oscillator charging current and the operating frequency. SENSE2– (Pin 12): Second Phase Current Sense Amplifier Negative Input. An RC filter is required across the current sense resistor. SENSE2+ (Pin 13): Second Phase Current Sense Amplifier Positive Input. An RC filter is required across the current sense resistor. Current limit threshold is set at 60mV. SS (Pin 14): Soft-Start. A capacitor on this pin sets the output ramp up rate. The typical time for SS to reach the programmed level is (C • 2.44V)/10µA. VC (Pin 15): The output of the gm error amplifier and the control signal of the current loop of the current-mode PWM. Switching starts at 0.7V, and higher VC voltages corresponds to higher inductor current. FB (Pin 16): Error Amplifier Inverting Input. A resistor divider to this pin sets the output voltage. RUN (Pin 17): LT3782 goes into shutdown mode when VRUN is below 2.2V and goes to low bias current shutdown mode when VRUN is below 0.3V. NC (Pin 18): Not Connected. Can be connected to GND. VEE2 (Pin 19): Gate Driver BGATE2 Ground. This pin should be connected to the ground side of the second current sense resistor. BGATE2 (Pin 20): Second Phase MOSFET Driver. GBIAS2 (Pin 21): Bias for Gate Driver BGATE2. Should be connected to GBIAS or an external power supply between 12V to 14V. A bypass low ESR capacitor of 2µF or larger is needed and should be connected directly to the pin to minimize parasitic impedance. GBIAS1 (Pin 22): Bias for Gate Driver BGATE1. Should be connected to GBIAS2. BGATE1 (Pin 23): First Phase MOSFET Driver. VEE1 (Pin 24): Gate Driver BGATE1 Ground. This pin should be connected to the ground side of the second current sense resistor. NC (Pin 25): Not Connected. Can be connected to GND. NC (Pin 26): Not Connected. Can be connected to GND. VCC (Pin 27): Chip Power Supply. Good supply bypassing is required. GBIAS (Pin 28): Internal 11V regulator output for biasing internal circuitry. Should be connected to GBIAS1 AND GBIAS2. EXPOSED PAD (Pin 29): The exposed package pad is fused to internal ground and is for heat sinking. Solder the bottom metal plate onto expanded ground plane for optimum thermal performance. 3782fa 5 LT3782 W BLOCK DIAGRA VIN VCC CIN 20µF 27 VGBIAS = VCC – 1V AND CLAMPED AT 11V REGULATOR GBIAS1 + + LOW POWER SHUTDOWN R6 + A5 RUN 17 R8 A11 – + VOUT L1 15µ A8 D2 + COUT 100µF C3 2µF 21 – + 7V 0.5V L2 15µ GBIAS2 – + 22 D1 GBIAS 28 A6 VCC – 2.5V RF1 + RF2 A7 – + A20 2.44V SGATE1 A4 2 A1 DELAY + + 6 ONE SHOT RSET A12 2.5V BGATE1 GBIAS1 – BGATE1 A13 A14 R1 50k SLOPE COMP CH1 SENSE1+ R7 10Ω RS1 8 + PWM1 M1 22 A9 BLANKING SENSE1– R3 C2 2nF 9 – VEE1 24 A3 + BGATE1 SGATE1 CL1 – + DELAY 60mV SGATE2 SET A15 1 A17 + + A16 2.5V DELAY – BGATE2 ONE SHOT GBIAS2 BGATE2 A18 A19 R2 50k SLOPE COMP CH2 SET SLOPE SLOPE COMP 10 CH1 CH2 S S R PWM2 SYNC BLANKING SENSE2– R4 R9 10Ω RS2 C4 2nF 12 – 5 SENSE2+ 13 + R M2 20 A2 VEE2 19 A10 RSET 11 RFREQ C5 20pF OSC CK Q + D Q D6 + LOGIC CL2 – DCL D7 + 60mV 7 16 GM GND 4 FB – VC VREF I1 10µA D4 SS 15 R5 2k 3782 BD NOTE: PACKAGE BOTTOM METAL PLATE (PIN 29) IS FUSED TO CHIP DIE AGND 4V 14 C7 10nF C1 2000pF 3782fa 6 LT3782 U W U U APPLICATIO S I FOR ATIO Operation Soft-Start and Shutdown The LT3782 is a two phase constant frequency current mode boost controller. Switching frequency can be programmed up to 500kHz. During normal switching cycles, the two channels are controlled by internal flip-flop and are 180 degrees out of phase. During soft-start, the voltage on the SS pin (VSS) controls the output voltage. The output voltage thus ramps up following VSS. The effective range of VSS is from 0V to 2.44V. The typical time for the output to reach the programmed level is Referring to the Block Diagram, the LT3782 basic functions include a transconductance amplifer (gm) to regulate the output voltage and to control the current mode PWM current loop. It also includes the necessary logic and flip-flop to control the PWM switching cycles, two high speed gate drivers to drive high power N-Channel MOSFETs, and 2-phase control signals to drive external gate drivers for optional synchronous operation. C is the capacitor connected from the SS pin to Gnd. In normal operation, each switching cycle starts with a switch turn-on. The inductor current of each channel is sampled through the current sense resistor and amplified then compared to the error amplifier output VC to turn the switch off. The phase delay of the second channel is controlled by the divide-by-two D flip-flop and is exactly 180 degrees out of phase of the first channel. With a resistor divider connected to the FB pin, the output voltage is programmed to the desired value. The 10V gate drivers are sufficient to drive most high power N-Channel MOSFET in many industrial applications. Oscillation Frequency Setting and Synchronization Additional important features include shutdown, current limit, soft-start, synchronization and programmable maximum duty cycle. Additional slope compensation can be added also. Output Voltage Programming With a 2.44V feedback reference voltage VREF, the output VOUT is programmed by a resistor divider as shown in the Block Diagram. ⎛ R ⎞ VOUT = 2 . 44 ⎜ 1+ F1 ⎟ ⎝ RF2 ⎠ t= C • 2.44V 10µA Undervoltage Lockout and Shutdown Only when VRUN is higher than 2.45V VGBIAS will be active and the switching enabled. The LT3782 goes into low current shutdown when VRUN is below 0.3V. A resistor divider can be used on RUN pin to set the desired VCC undervoltage lockout voltage. A 120mV hysteresis is built in on RUN pin thresholds. The switching frequency of LT3782 can be set up to 500kHz by a resistor RFREQ from pin RSET to ground. For fSET = 250kHz, RFREQ = 80k Once the switching frequency fSET is chosen, RFREQ can be found from the Switching Frequency vs RFREQ graph found under the Typical Electrical Characteristics section. Note that because of the 2-phase operation, the internal oscillator is running at twice the switching frequency. To synchronize the LT3782 to the system frequency fSYSTEM, the synchronizing frequency fSYNC should be two times fSYSTEM, and the LT3782 switching frequency fSET should be set below 80% of fSYSTEM. fSYNC = 2fSYSTEM and fSET < (fSYSTEM • 0.8) For example, to synchronize the LT3782 to 200kHz system frequency fSYSTEM, fSYNC needs to be set at 400kHz and fSET needs to be set at 160kHz. From the Switching Frequency vs RFREQ graph found under the Typical Electrical Characteristics section, RFREQ = 130k. 3782fa 7 LT3782 U U W U APPLICATIO S I FOR ATIO With a 200ns one-shot timer on chip, the LT3782 provides flexibility on the external sync pulse width. The sync pulse threshold is about 1.2V (Figure 1). 5V TO 20V 5k LT3782 SYNC to compensate for the propagation delay of external gate driver, a resistor divider can be used from RSET to ground to program VDELAY for the longer delay needed. For example, for a switching frequency of 250kHz and delay of 150ns, then RFREQ1 + RFREQ2 should be 80k and VDELAY should be 1V, with VRSET = 2.3V then RFREQ1 = 47.5k and RFREQ2 = 32.5k (see Figure 3). VN2222 DELAY PULSE WIDTH > 200ns 3782 F01 LT3782 Figure 1. Synchronizing with External Clock RSET RFREQ1 47.5k Current Limit Current limit is set by the 60mV threshold across SEN1P, SEN1N for channel one and SEN2P, SEN2N for channel two. By connecting an external resistor RS (see Block Diagram), the current limit is set for 60mV/RS. RS should be placed very close to the power switch with very short traces. A low pass RC filter is needed across RS to filter out the switching spikes. Good Kelvin sensing is required for accurate current limit. The input bypass capacitor ground should be at the same ground point of the current sense resistor to minimize the ground current path. Synchronous Rectifier Switches For high output voltage applications, the power loss of the catch diodes are relatively small because of high duty cycle. If diodes power loss or heat is a concern, the LT3782 provides PWM signals through SGATE1 and SGATE2 pins to drive external MOSFET drivers for synchronous rectifier operation. Note that SGATE drives the top switch and BGATE drives the bottom switch. To avoid cross conduction between top and bottom switches, the BGATE turn-on is delayed 100ns (when DELAY pin is tied to RSET pin) from SGATE turn-off (see Figure 2). If a longer delay is needed BGATE1 SGATE1 DELAY SET 3782 F03 RFREQ2 32.5k Figure 3. Increase Delay Time Duty Cycle Limit When DCL pin is shorted to RSET pin and switching frequency is less than 250kHz (RFREQ > 80k), the maximum duty cycle of LT3782 will be at least 90%. The maximum duty cycle can be clamped to 50% by grounding the DCL pin or to 75% by forcing the VDCL voltage to 1.2V with a resistor divider from RSET pin to ground. The typical DCL pin input current is 0.2µA. Slope Compensation The LT3782 is designed for high voltage and/or high current applications, and very often these applications generate noise spikes that can be picked up by the current sensing amplifier and cause switching jitter. To avoid switching jitter, careful layout is absolutely necessary to minimize the current sensing noise pickup. Sometimes increasing slope compensation to overcome the noise can help to reduce jitter. The built-in slope compensation can be increased by adding a resistor RSLOPE from SLOPE pin to ground. Note that smaller RSLOPE increases slope compensation and the minimum RSLOPE allowed is RFREQ/2. 3782 F02 Figure 2. Delay Timing 3782fa 8 LT3782 U W U U APPLICATIO S I FOR ATIO Layout Considerations Power Inductor Selection To prevent EMI, the power MOSFETs and input bypass capacitor leads should be kept as short as possible. A ground plane should be used under the switching circuitry to prevent interplane coupling and to act as a thermal spreading path. Note that the bottom pad of the package is the heat sink, as well as the IC signal ground, and must be soldered to the ground plane. In a boost circuit, a power inductor should be designed to carry the maximum input DC current. The inductance should be small enough to generate enough ripple current to provide adequate signal to noise ratio to the LT3782. An empirical starting of the inductor ripple current (per phase) is about 40% of maximum DC current, which is half of the input DC current in a 2-phase circuit: In a boost converter, the conversion gain (assuming 100% efficiency) is calculated as (ignoring the forward voltage drop of the boost diode): ∆IL ≅ 40%• VOUT 1 = VIN 1− D where D is the duty ratio of the main switch. D can then be estimated from the input and output voltages: D = 1− V VIN ; DMAX = 1 − IN(MIN) VOUT VOUT The Peak and Average Input Currents The control circuit in the LT3782 measures the input current by using a sense resistor in each MOSFET source, so the output current needs to be reflected back to the input in order to dimension the power MOSFET properly. Based on the fact that, ideally, the output power is equal to the input power, the maximum average input current is: IIN(MAX) = IO(MAX) 1 – DMAX The peak current is: I IIN(PEAK) = 1.2 • O(MAX) 1 – DMAX The maximum duty cycle, DMAX, should be calculated at minimum VIN. IOUT (MAX) • VOUT I •V = 20%• OUT (MAX) OUT 2VIN VIN where VIN, VOUT and IOUT are the DC input voltage, output voltage and output current, respectively. And the inductance is estimated to be: L= VIN • D fs • ∆IL where fs is the switching frequency per phase. The saturation current level of inductor is estimated to be: ISAT ≥ •V I ∆IL IIN + ≅ 70%• OUT (MAX) OUT 2 2 VIN(MIN) Sense Resistor Selection During the switch on-time, the control circuit limits the maximum voltage drop across the sense resistor to about 60mV. The peak inductor current is therefore limited to 60mV/R. The relationship between the maximum load current, duty cycle and the sense resistor RSENSE is: R ≤ VSENSE(MAX) • 1 – DMAX I 1.2 • O(MAX) 2 3782fa 9 LT3782 U W U U APPLICATIO S I FOR ATIO Important parameters for the power MOSFET include the drain-to-source breakdown voltage (BVDSS), the threshold voltage (VGS(TH)), the on-resistance (RDS(ON)) versus gate-to-source voltage, the gate-to-source and gate-todrain charges (QGS and QGD, respectively), the maximum drain current (ID(MAX)) and the MOSFET’s thermal resistances (RTH(JC) and RTH(JA)). The gate drive voltage is set by the 10V GBIAS regulator. Consequently, 10V rated MOSFETs are required in most high voltage LT3782 applications. Pay close attention to the BVDSS specifications for the MOSFETs relative to the maximum actual switch voltage in the application. The switch node can ring during the turnoff of the MOSFET due to layout parasitics. Check the switching waveforms of the MOSFET directly across the drain and source terminals using the actual PC board layout (not just on a lab breadboard!) for excessive ringing. Calculating Power MOSFET Switching and Conduction Losses and Junction Temperatures In order to calculate the junction temperature of the power MOSFET, the power dissipated by the device must be known. This power dissipation is a function of the duty cycle, the load current and the junction temperature itself (due to the positive temperature coefficient of its RDS(ON)). As a result, some iterative calculation is normally required to determine a reasonably accurate value. Care should be taken to ensure that the converter is capable of delivering the required load current over all operating conditions (line voltage and temperature), and for the worst-case specifications for VSENSE(MAX) and the RDS(ON) of the MOSFET listed in the manufacturer’s data sheet. The power dissipated by the MOSFET in a 2-phase boost converter is: 2 PFET ⎛ IO(MAX) ⎞ ⎜ ⎟ ⎝ 2 ⎠ = • RDS(ON) • D • ρT (1– D) ⎛ IO(MAX) ⎞ ⎜ ⎟ 2 ⎠ 2 ⎝ + k • VO • •C •f (1– D) RSS The first term in the equation above represents the I2R losses in the device, and the second term, the switching losses. The constant, k = 1.7, is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. The ρT term accounts for the temperature coefficient of the RDS(ON) of the MOSFET, which is typically 0.4%/°C. Figure 4 illustrates the variation of normalized RDS(ON) over temperature for a typical power MOSFET. 2.0 ρT NORMALIZED ON RESISTANCE Power MOSFET Selection 1.5 1.0 0.5 0 – 50 50 100 0 JUNCTION TEMPERATURE (°C) 150 3782 F06 Figure 4. Normalized RDS(ON) vs Temperature 3782fa 10 LT3782 U W U U APPLICATIO S I FOR ATIO From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following formula: TJ = TA + PFET • RTH(JA) The RTH(JA) to be used in this equation normally includes the RTH(JC) for the device plus the thermal resistance from the case to the ambient temperature (RTH(CA)). This value of TJ can then be compared to the original, assumed value used in the iterative calculation process. Input Capacitor Choice The input capacitor must have high enough voltage and ripple current ratings to handle the maximum input voltage and RMS ripple current rating. The input ripple current in a boost circuit is very small because the input current is continuous. With 2-phase operation, the ripple cancellaNormalized Peak-to-Peak Input Ripple Current 1.00 tion will further reduce the input capacitor ripple current rating. The ripple current is plotted in Figure 5. Please note that the ripple current is normalized against Inorm = VIN L • fs Output Capacitor Selection The voltage rating of the output capacitor must be greater than the maximum output voltage with sufficient derating. Because the ripple current in output capacitor is a pulsating square wave in a boost circuit, it is important that the ripple current rating of the output capacitor be high enough to deal with this large ripple current. Figure 6 shows the output ripple current in the 1- and 2-phase designs. As we can see, the output ripple current of a 2-phase boost circuit reaches almost zero when the duty cycle equals 50% or the output voltage is twice as much as the input voltage. Thus the 2-phase technique significantly reduces the output capacitor size. 0.90 Normalized Output RMS Ripple Currents 0.80 ∆IIN/INORM 0.70 0.60 1-PHASE 0.50 0.40 IORIPPLE/IOUT 2-PHASE 0.30 0.20 0.10 0 0 0.2 0.6 0.4 DUTY CYCLE 0.8 1.0 3782 F04 Figure 5. Normalized Input Peak-to-Peak Ripple Current: Inorm = VIN L • fs The RMS Ripple Current is About 29% of the Peak-to-Peak Ripple Current. 3.25 3.00 2.75 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 0.1 1-PHASE 2-PHASE 0.2 0.3 0.4 0.5 0.6 0.7 0.8 DUTY CYCLE OR (1-VIN/VOUT) 0.9 3782 F05 Figure 6. Normalized Output Ripple Currents in Boost Converter: 1-Phase and 2-Phase. IOUT Is the DC Output Current. 3782fa 11 LT3782 U U W U APPLICATIO S I FOR ATIO For a given VIN and VOUT, we can calculate the duty cycle D and then derive the output RMS ripple current from Figure 6. After choosing output capacitors with sufficient RMS ripple current rating, we also need to consider the ESR requirement if Electrolytic caps, Tantulum caps, POSCAPs or SP CAPs are selected. Given the required output ripple voltage spec ∆VOUT (in RMS value) and the calculated RMS ripple current ∆IOUT, one can estimate the ESR value of the output capacitor to be ESR ≤ ∆VOUT ∆IOUT External Regulator to Bias Gate Drivers If VIN is higher than 24V and the applications require the LT3782 to drive large MOSFETs the IC temperature may get too high. To reduce heat, an external regulator between 12V to 14V should be used to override the internal VGBIAS regulator to supply the current needed for BGATE1 and BGATE2 (see Figure 7). LT3782 GBIAS + 12V GBIAS1 GBIAS2 3782 F07 2µF Figure 7 Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power (¥100%). Percent efficiency can be expressed as: % Efficiency = 100% – (L1 + L2 + L3 + …), where L1, L2, etc. are the individual loss components as a percentage of the input power. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources usually account for the majority of the losses in LT3782 application circuits: 1. The supply current into VIN. The VIN current is the sum of the DC supply current IQ (given in the Electrical Characteristics) and the MOSFET driver and control currents. The DC supply current into the VIN pin is typically about 7mA and represents a small power loss (much less than 1%) that increases with VIN. The driver current results from switching the gate capacitance of the power MOSFET; this current is typically much larger than the DC current. Each time the MOSFET is switched on and then off, a packet of gate charge QG is transferred from GBIAS to ground. The resulting dQ/dt is a current that must be supplied to the GBIAS capacitor through the VIN pin by an external supply. In normal operation: IQ(TOT) ≈ IQ = f • QG PIC = VIN • (IQ + f • QG) 2. Power MOSFET switching and conduction losses: 2 ⎛ IO(MAX) ⎞ ⎜ 2 ⎟ •R PFET = ⎜ DS(ON) • DMAX • ρ T 1 – DMAX ⎟ ⎟ ⎜ ⎠ ⎝ IO(MAX) 2 + k • VO2 • • C RSS • f 1 – DMAX 3. The I2R losses in the sense resistor can be calculated almost by inspection. 2 PR(SENSE) ⎛ IO(MAX) ⎞ ⎜ 2 ⎟ •R •D =⎜ MAX 1 – DMAX ⎟ ⎟ ⎜ ⎠ ⎝ 4. The losses in the inductor are simply the DC input current squared times the winding resistance. Expressing this loss as a function of the output current yields: 2 PR(WINDING) ⎛ IO(MAX) ⎞ ⎜ 2 ⎟ •R =⎜ W 1 – DMAX ⎟ ⎟ ⎜ ⎠ ⎝ 3782fa 12 LT3782 U W U U APPLICATIO S I FOR ATIO 5. Losses in the boost diode. The power dissipation in the boost diode is: PDIODE = IO(MAX) • VD 2 The boost diode can be a major source of power loss in a boost converter. For 13.2V input, 42V output at 3A, a Schottky diode with a 0.4V forward voltage would dissipate 600mW, which represents about 1% of the input power. Diode losses can become significant at low output voltages where the forward voltage is a significant percentage of the output voltage. 6. Other losses, including CIN and CO ESR dissipation and inductor core losses, generally account for less than 2% of the total losses. PCB Layout Considerations To achieve best performance from an LT3782 circuit, the PC board layout must be carefully done. For lower power applications, a two-layer PC board is sufficient. However, at higher power levels, a multiplayer PC board is recommended. Using a solid ground plane under the circuit is the easiest way to ensure that switching noise does not affect the operation. In order to help dissipate the power from MOSFETs and diodes, keep the ground plane on the layers closest to the layers where power components are mounted. Use power planes for MOSFETs and diodes in order to improve the spreading of the heat from these components into the PCB. For best electrical performance, the LT3782 circuit should be laid out as follows: Place all power components in a tight area. This will minimize the size of high current loops. Orient the input and output capacitors and current sense resistors in a way that minimizes the distance between the pads connected to ground plane. Place the LT3782 and associated components tightly together and next to the section with power components. Use a local via to ground plane for all pads that connect to ground. Use multiple vias for power components. Connect the current sense inputs of LT3782 directly to the current sense resistor pads. Connect the current sense traces on the opposite sides of pads from the traces carrying the MOSFETs source currents to ground. This technique is referred to as Kelvin sensing. 3782fa 13 LT3782 U TYPICAL APPLICATIO S 10V to 24V Input to 24V, 8A Output Boost Converter 10V TO 24V INPUT 1 3 4 5 7 10Ω 8 CS1 SGATE2 VCC NC NC GND NC SYNC VEE1 DELAY BGATE1 DCL GBIAS1 SENSE1+ LT3782 GBIAS2 28 2R2 27 Q1 PH3330 1µF 25 24 CS1 23 22 21 CIN 22µF 25V 2.2µF 9 59k 10 82k 11 BGATE2 VEE2 SLOPE RSET NC 12 SENSE2– RUN 13 SENSE2+ FB 14 VC SS 20 COUT1 22µF, 25V, 4x OUTPUT 24V 8A 0.004Ω 19 CS2 18 825k 17 274k 16 24.9k 15 221k Q2 PH3330 • 10nF CS2 SENSE1– D1 UPS840 COUT2 330µF, 35V, 2x 0.004Ω 10nF 10Ω L1 PB2020-103 26 + 6 GBIAS • 2 SGATE1 L2 PB2020-103 D2 UPS840 3782 TA02 4.7nF L1, L2: PULSE PB2020-103 ALL CERAMIC CAPACITORS ARE X7R, TDK CC1 RC1 CC2 6.8nF 13.3k 100pF *OUTPUT CURRENT WITH BOTH INPUTS PRESENT Efficiency 100 98 15VIN EFFICIENCY (%) 96 12VIN 94 92 90 88 86 0 1 2 3 4 5 IOUT (A) 6 7 8 3782 TA02b 3782fa 14 LT3782 U PACKAGE DESCRIPTIO FE Package 28-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation EB 9.60 – 9.80* (.378 – .386) 4.75 (.187) 4.75 (.187) 28 2726 25 24 23 22 21 20 19 18 1716 15 6.60 ±0.10 2.74 (.108) 4.50 ±0.10 SEE NOTE 4 0.45 ±0.05 EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE 6.40 2.74 (.252) (.108) BSC 1.05 ±0.10 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.50 – 0.75 (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN MILLIMETERS (INCHES) 3. DRAWING NOT TO SCALE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.25 REF 1.20 (.047) MAX 0° – 8° 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE28 (EB) TSSOP 0204 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3782fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT3782 U TYPICAL APPLICATIO S 28V Output Base Station Power Converter with Redundant Input 1 3 4 5 CS1 VCC NC NC GND NC SYNC VEE1 DELAY BGATE1 DCL GBIAS1 8 SENSE1+ LT3782 GBIAS2 9 SENSE1– BGATE2 7 10Ω GBIAS SGATE2 BAS516 26 25 L1 10µH Q1 PH4840S 1µF CINA 22µF 24 CS1 23 COUT2 330µF, 35V, 2x 0.004Ω 21 COUT1 10µF, 50V, 4x 2.2µF 59k 10 82k 11 RSET NC 12 SENSE2– RUN 13 SENSE2+ FB 14 SS VC 20 OUTPUT 28V 4A (8A**) 0.004Ω 19 18 825k 17 274k 16 24.9k 15 261k CINB 22µF CS2 Q2 PH4840S • 10nF CS2 VEE2 SLOPE D1 UPS840 22 10nF 10Ω 2R2 27 + 6 SGATE1 • 2 VINA 0V TO 28V* 28 BAS516 L2 10µH D2 UPS840 3782 TA03 4.7nF RC1 CC2 15k 100pF CC1 4.7nF NOTE: VINB 0V TO 28V* *INPUT VOLTAGE RANGE FOR VINA AND VINB IS 0V TO 28V. AT LEAST ONE OF THE INPUTS MUST BE 12V OR HIGHER. L1, L2: PULSE PB2020-103 ALL CERAMIC CAPACITORS ARE X7R, TDK **OUTPUT CURRENT WITH BOTH INPUTS 12V OR HIGHER RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT®1619 Current Mode PWM Controller 300kHz Fixed Frequency, Boost, SEPIC, Flyback Topology LTC1624 Current Mode DC/DC Controller SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC Design; VIN Up to 36V LTC1696 Overvoltage Protection Controller 0.8V ≤ VIN ≤ 24V, ±2% Overvoltage Threshold Accuracy, ThinSOT Package LTC1700 No RSENSE™ Synchronous Step-Up Controller Up to 95% Efficiency, Operation as Low as 0.9V Input LTC1871/LTC1871-7 Wide Input Range Controller No RSENSE, 7V Gate Drive, Current Mode Control LT1930 1.2MHz, SOT-23 Boost Converter Up to 34V Output, 2.6V ≤ VIN ≤ 16V, Miniature Design LT1952 Single Switch Synchronous Forward Controller High Efficiency, 25W to 500W, Wide Input Range, Adaptive Duty Cycle Clamp LTC3425 5A, 8MHz 4-Phase Monolithic Step-Up DC/DC Converter 0.5V ≤ VIN ≤ 4.5V, 2.4V ≤ VOUT ≤ 5.25V, Very Low Output Ripple LTC3703/LTC3703-5 100V and 60V, Step-Down and Step-Up DC/DC Synchronous Controller High Efficiency Synchronous Operation, High Voltage Operation, No Transformer Required LTC3728 Dual, 550kHz, 2-Phase Synchronous Step-Down Controller Dual 180° Phased Controllers, VIN: 3.5V to 35V, 99% Duty Cycle, 5x5QFN, SSOP-28 Packages LTC3729 20A to 200A, 550kHz PolyPhase™ Synchronous Controller Expandable from 2-Phase to 12-Phase, Uses all Surface Mount Components, VIN up to 36V LTC3731 3- to 12-Phase Step-Down Synchronous Controller 60A to 240A Output Current, 0.6V ≤ VOUT ≤ 6V, 4.5V ≤ VIN ≤ 32V LTC3803 SOT-23 Flyback Controller Adjustable Slope Compensation, Internal Soft-Start, Current Mode 200kHz Operation LTC3806 Synchronous Flyback Controller High Efficiency, Improves Cross Regulation in Multiple Output Designs, Current Mode, 3mm × 4mm 12 Pin DFN Package No RSENSE and PolyPhase are trademarks of Linear Technology Corporation. 3782fa 16 Linear Technology Corporation LT/LT 0705 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004