DESIGN FEATURES Tiny 12-Bit ADC Delivers 2.2Msps Through 3-Wire Serial Interface by Joe Sousa Introduction Serial interfaces occupy little routing space, but usually limit the speed of an ADC. The LTC1402 has a full conversion speed of 2.2Msps and a very compact 3-wire interface for connecting to DSPs and microprocessors without glue logic. It comes in a 16-pin narrow SSOP package. This minuscule package (200mil × 230mil footprint) and compact serial interface are easy to fit close to sensors to best preserve analog signal integrity. Other serial 12-bit ADCs have sample rates limited to hundreds of kilosamples-per-second, which limits their utility in high speed data acquisition systems. This slow sample rate, combined with poor distortion characteristics, makes them unsuitable for tracking high frequency signals. The LTC1402 will capture, in less than 60ns, the fast steps from an external analog input multiplexer for high speed data acquisition and it will digitize high frequency signals very accurately, with a 72dB S/(N+D) (sig- 5V OVDD CONV LTC1402 SCK DOUT OGND 11 VDD TMS320C54X BFSR 16 15 BCLKR 10 BDR 9 GND CONV CLK 3-WIRE SERIAL INTERFACE LINK Figure 1a. DSP serial interface to the TMS320C54X nal-to-noise plus distortion ratio) at 1.1MHz, for communications or signal processing systems. 3-Wire Serial Interface for DSPs, Cables and Optocouplers Figure 1a shows an example of interfacing the LTC1402 to the TMS320C54x DSP. No glue logic is needed to interface the LTC1402 to DSPs. The buffered serial port of the TMS320C54x talks directly to a dedicated 2kB segment of internal buffer memory. The ADC’s serial data is collected in the 2k buffer, in two alternating 1kB segments, in real time, at the full 2.2Msps conversion rate of the LTC1402. Consult the LTC1402 data sheet for the TMS320C54x assembly code for this application. 5V 10µF LTC1402 12 DVDD 3 OVDD AIN+ CONV SCK SIGNAL 4 AIN– DOUT OGND 5V 11 16 16 2 1 3 6 7 5 10 8 CLK 35.2MHz 11 BDR 100Ω 9 11 BFSR BCLKR 7 10 100Ω VDD TMS320C54X 5 100Ω 9 4 15 12 3 1 6 9 CONV 2.2Msps 16 100Ω 100Ω 15 10 2 8 GND 14 CATEGORY FIVE SHIELDED CABLE UP TO 100 FEET 14 4 13 13 LTC1688 PIN 4 = ENA QUAD DRIVER PIN 12 = ENB 15 LTC1520 QUAD RECEIVER Figure 1b. The LTC1402 3-wire serial port sends data over 100 feet of category 5 twisted pair with the LTC1688/LTC1519 quad driver/receiver pairs Linear Technology Magazine • February 2000 15 DESIGN FEATURES 5V 5V HCPL-2430 10µF LTC1402 11 DVDD 3 OVDD AIN+ CONV SCK SIGNAL 4 AIN– DOUT OGND 1N4148 7 12 560Ω 16 VDD TMS320C54X 8 1 BFSR 2 3 15 560Ω 10 9 BCLKR 6 4 1N4148 5 BDR HCPL-2430 GND 8 1 1N4148 7 2 560Ω CONV 2Msps 3 6 CLK 32MHz 5 4 Figure 1c. The LTC1402 is easily isolated with high speed optocouplers The minuscule 16-pin narrow SSOP package of the LTC1402 saves space in compact systems or systems that require a large number of ADCs. It can be located near the signal conditioning circuitry and send serial output data over a PC board trace of up to one foot in length to the DSP, as shown in Figure 1a. Figure 1b shows the LTC1688/ LTC1520 quad cable driver/receiver interfacing the LTC1402 to the DSP port to send the serial data over longer distances. The category-5 quad twisted pair shielded cable can extend up to 100 feet without data corruption. Because the SCK, CONV and DOUT signals originate at the LTC1402, they arrive at the serial port with similar delays and remain synchronized. When the data is received at the serial port of a DSP or other processor, the port must be programmed to respond to the appropriate SCK and CONV edges. It is also necessary to check where the 12-bit output DATA sits in the 16-bit data frame. The TMS320C54x serial port READ instructions can shift the 12-bit data to the preferred position within the 16-bit data frame. The serial interface lends itself to galvanic isolation with external optocouplers. Figure 1c shows how to isolate the LTC1402 with the HPCL16 version start input at the CONV pin (16) do not inject noise into the internal analog signal path of the ADC. As a result, the analog accuracy of the LTC1402 is insensitive to the phase, duty cycle or amplitude (3V or 5V) of the external digital inputs. The DOUT pin (10) swings from the voltage at the OGND pin (9) to the voltage at the OVDD pin (11) to allow direct interfacing to 5V or 3V DSPs and microprocessors. The LTC1402 is ideal in multiple-ground systems, where the differential input is connected to one ground, the supplies and grounds of the LTC1402 connect to a second, local ground and the output ground connects to a third, digital ground. 2430 dual optocoupler. The 40ns propagation delays through the dual optocouplers cancel to maintain a good timing match between the DOUT, SCK and CONV signals. The LTC1402, running at a 2Msps conversion rate, sends 16-bit data frames through the HPCL-2430 optocouplers at 32MB/s. 3V or 5V Serial Interface without Spurious Noise Figure 2 shows the block diagram of the LTC1402. The internal architecture has been optimized to send out data serially during conversion, without degradation of conversion accuracy due to digital noise. The 35MHz clock input at the SCK pin (15) and the external 2.2Msps con- 5V 1 AVDD 10µF 12 DVDD 11 OVDD LTC1402 AIN+ 3 AIN– 4 SAMPLEAND-HOLD 10µF OUTPUT BUFFER 12-BIT ADC DOUT 64k – GAIN 10 4.096V 5 VREF 3V OR 5V 7 64k + LTC1402 14 VSS 8 2.048 REFERENCE 2 AGND1 6 AGND2 16 15 TIMING LOGIC 13 DGND BIP/UNI CONV SCK 9 OGND 10µF –5V OR 0V Figure 2. LTC1402 block diagram Linear Technology Magazine • February 2000 DESIGN FEATURES 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 1.11 Figure 3. Sine wave spectrum plot (bipolar ±2V) with ±5V supplies A proprietary sampling front end circuit achieves exceptional dynamic performance at the 1.1MHz Nyquist frequency: –89dB THD with ±5V supplies and –82dB THD with a single 5V supply. Figures 3 and 4 show the spectra from a 1.1MHz Nyquist frequency sine wave with ±5V supplies and a single 5V supply, respectively. With this very clean spectrum, the LTC1402 minimizes crosstalk and interference in communications applications where the spectrum is divided into many frequency slots. The LTC1402 maintains 72dB S/(N+D) with a 1.1MHz input sine wave, with either a single 5V or ±5V supplies. Positive signals can be applied with single or dual supplies and bipolar signals are easily accommodated with dual-supply operation. The full power bandwidth of the LTC1402 is 80MHz; the full linear bandwidths (SINAD > 68dB) of 5MHz with ±5V supplies and 3.5MHz with a single 5V supply round out the exceptional dynamic performance of the LTC1402. The wideband signal conversion purity shown in Figures 5a and 5b makes the LTC1402 well suited for digitizing sine wave signals well above the 1.1MHz Nyquist frequency. Figures 6 and 7 show that transfer function purity, represented by the differential and integral linearity plots, is maintained at the full 2.2Msps conversion rate. Linear Technology Magazine • February 2000 0.55 FREQUENCY (MHz) EFFECTIVE NUMBER OF BITS 68 10 62 1.11 Figure 4. Sine wave spectrum plot (unipolar 0V–4V) with single 5V supply True Differential Inputs Cancel Wideband Common Mode Noise The front-end sampling circuit acquires the input signal differentially from the AIN+ and AIN– analog inputs. Except for the sign inversion, these two inputs are identical. The wide common mode rejection bandwidth of the LTC1402 (–60dB at 10MHz input) affords excellent ground noise rejection in complex, noisy systems. Figure 8a shows the CMRR performance vs input frequency. The differential inputs are very easy to interface to a wide range of signal sources. Grounding the AIN– input near the signal source reduces common mode ground noise. Setting the BIP/UNI pin (8) to a logic high selects the bipolar ±2.048V range; setting it to a logic low selects the unipolar 0V to 4.096V range. The 0V to 4.096V unipolar range is ideal for single 5V supply applications where the AIN– input is grounded and the signal is applied to the AIN+ input. The ±2.048V bipolar range centered around midsupply can also be used in single 5V supply applications, with the AIN– input tied to a 2.5VDC source. Alternately, the full ±2.048V bipolar range can be driven with a pair of complementary ±1.024V signals into AIN+ and AIN–. This limits the swing of external single 5V supply amplifiers to their most linear region, from 1.5V to 3.5V. Figure 8b shows half of the LT1813 dual op amp driving the LTC1402 in this fully differential configuration with a single 5V supply. 74 11 9 56 8 50 7 44 6 38 5 32 4 26 3 20 2 14 1 fSAMPLE = 2.22MHz 0 4 105 106 10 INPUT FREQUENCY (Hz) 2 8 107 Figure 5a. ENOBs and SINAD vs input frequency (bipolar ±2V) with ±5V supplies 12 74 11 68 10 62 9 56 8 50 7 44 6 38 5 32 4 26 3 20 2 14 1 f SAMPLE = 2.22MHz 0 4 10 105 106 INPUT FREQUENCY (Hz) 2 8 SIGNAL-TO-NOISE + DISTORTION (dB) Very High SFDR in Single 5V Supply Applications 0 3RD 5TH EFFECTIVE NUMBER OF BITS 0.55 FREQUENCY (MHz) 2ND 4TH 6TH 107 Figure 5b. ENOBs and SINAD vs input frequency (unipolar 0V–4V) with single 5V supply 1.00 fSAMPLE = 2.2MHz 0.75 0.50 DNL (LSB) 0 3RD 5TH 0.25 0 –0.25 –0.50 –0.75 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 CODE Figure 6. Differential nonlinearity vs output code (unipolar 0V–4V) 1.00 fSAMPLE = 2.2MHz 0.75 0.50 INL (LSB) 2ND 4TH 6TH 12 fSAMPLE = 2222222.22Hz fSINE = 1131727.43Hz 2048 SAMPLES AMPLITUDE (dB) AMPLITUDE (dB) fSAMPLE = 2222222.22Hz fSINE = 1131727.43Hz 2048 SAMPLES SIGNAL-TO-NOISE + DISTORTION (dB) 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0.25 0 –0.25 –0.50 –0.75 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 CODE Figure 7. Integral nonlinearity vs output code (unipolar 0V–4V) 17 DESIGN FEATURES COMMON MODE REJECTION RATIO (dB) 0 10µF 5V 5V 10µF –10 1 12 11 AVDD DVDD OVDD – 20 51Ω – 30 2VP-P 5pF 3 AIN+ 68pF BIP/UNI – 40 1k VIN = VCM ±1V – 50 1k 5V – 60 68pF 4 0.1µF 5 10µF R –70 0.1 1 10 100 FREQUENCY (MHz) 2 1000 – 8 7 3 Figure 8a. CMRR vs input frequency 5V LTC1402 AIN– VREF GAIN 51Ω 1 1/2 LT1813 8 + VSS AGND2 AGND1 2 14 6 2VP-P 4 1 f (MIN) ≈ IN 2πRC 100 C Internal or External Reference The internal 2.048V reference (multiplied by 2 at the VREF output) sets the bipolar and unipolar ranges to ±2.048V and 0V to 4.096V, respectively. Tying the Gain pin (7) to the VREF pin (5) cuts the reference voltage at the VREF pin and analog input spans in half, to 2.048V. The internal reference can also be disabled by tying the Gain pin to VCC and tying an external reference with an output between 2V and 5V directly to VREF. The single-ended unipolar input range of Figure 9a’s circuit depends on the DAC’s output voltage, which acts as an infinite sample-and-hold for signals such as a CCD sensor dark Figure 8b. True differential inputs accept 4VP-P bipolar differential signal with 2VP-P swings on each input and an effective gain of 2 from the LT1813 inputs. SINAD = 70.7dB with a 1MHz input. current or similar applications, as determined by software procedures. The LTC1446 12-bit serial DAC applies a voltage to the GAIN and AIN– pins of the ADC, in this case subtracting the AIN– voltage from the VREF voltage, thus maintaining a positive full scale of 4.096V while varying zero scale over the range of 0V to 2V. This adjustment of the low end of the scale preserves the full 12-bit dynamic range of the ADC to digitize the input video signal between the dark-current value and 4.096V. The dark-current value must be a slow-moving DC value – – 3 LT1813 SCANNER VIDEO so that the DAC and the reference buffer amplifier can drive their respective 10µF capacitors. The LTC1446 DAC is stable with a 10µF load; care must be taken when substituting capacitors. Figure 9b shows alternative connections to emulate the functional range of a flash converter in an image scanner application. The top and bottom of the conversion ranges are set independently by the LTC1446 DAC, just like the top and bottom voltages of the internal resistor ladder in a flash converter. The bottom of the + 4 + AIN LTC1402 3 LT1813 SCANNER VIDEO AIN– + 4 5 VREF AIN+ LTC1402 AIN– DISABLED IN HIGH IMPEDANCE WITH PIN 7 HIGH 5 VREF 10µF 10µF 1/2 LTC1446 6 AGND2 6 AGND2 64k 64k + – + – 1/2 LTC1446 1/2 LTC1446 64k 7 GAIN 2.048V BANDGAP REFERENCE 10µF Figure 9a. The use of a DAC allows software adjustment of the lower end of the ADC range for applications such as dark-current cancellation. 18 64k 5V 7 GAIN 2.048V BANDGAP REFERENCE 10µF Figure 9b. A dual DAC allows software adjustment of both the fullscale and zero-scale voltages of the ADC, emulating the behavior of a flash converter. Linear Technology Magazine • February 2000 DESIGN FEATURES 100 SUPPLY CURRENT (mA) 10 VDD CURRENT DUAL ± 5V not be necessary if the image sensor has a low input impedance (<100Ω). VDD CURRENT SINGLE 5V Reducing Power at Low Sample Rates VDD CURRENT NAP MODE 1 VDD CURRENT SLEEP MODE (WITH EXTERNAL REFERENCE) 0.1 The LTC1402 consumes 90mW in normal operation, on either single 5V or ±5V supplies. NAP and SLEEP modes cut back power drain to 15mW and 10mW, respectively. NAP mode leaves the reference on and takes only 300ns to wake up, making it ideal for saving power between conversions in lower -sample-rate applications. SLEEP mode also shuts down the reference and takes 10ms to wake up. The REFREADY bit in the output data stream indicates when the reference has settled to full accuracy. NAP and SLEEP modes are easily set with two or four pulses at the CONV pin (16) input, respectively. One or more pulses at the SCK pin (15) input wakes up the LTC1402 for conversion. VSS CURRENT DUAL ± 5V VSS CURRENT SINGLE 5V 0.01 0.001 0.01 10 0.1 1 SAMPLE RATE (MHz) Figure 10. Current consumption vs sample rates for various operating modes and supply configurations conversion range starts at the darkcurrent value and the top of the range is set externally to match the maximum possible output from the image scanner. The voltage at AGND (pin 6) may vary from 0V to 1V; that at VREF (pin 5) may vary from 2V to 5V. The LT1813 input buffer amplifiers may Figure 10 shows the reduced power consumption while the sample rate is reduced and the NAP or SLEEP modes is used between conversions. For example, an undersampling application with NAP mode between conversions at a 455ksps sample rate draws only 40mW. Conclusion The LTC1402 has all the speed and AC and DC performance of fast 12-bit ADCs with parallel data interfaces, but it offers a much smaller, glueless serial interface that saves space in the 16-pin narrow SSOP package. The tiny LTC1402 can be placed right at the sensor for optimum analog signal capture and the compact 3wire serial interface can be routed through a system board, through a cable or through an isolation barrier, to serial ports on DSPs and other processors. LTC2401/LTC2402, continued from page 4 5V RP2 IEXCITATION = 200µA + VRTD LTC2402 FSSET R1 CH0 RTD – VCC IEXCITATION = 200µA CH1 IDC = 0 RP1 SCK SDO 3-WIRE SPI CS ZSSET R2 GND FO Figure 8. RTD remote temperature measurement RTD Temperature Digitizer RTDs used in remote temperature measurements often have long leads between the ADC and RTD sensor. These long leads result in parasitic voltage drops due to excitation current in the interconnect to the RTD. This voltage drop can be measured and digitally removed using the LTC2402, as illustrated in Figure 8. The excitation current (typically 200µA) flows from the ADC reference through a long lead to the remote temperature sensor (RTD). This current is applied to the RTD, whose resistance changes as a function of temperature (100Ω–400Ω for 0°C to Linear Technology Magazine • February 2000 800°C). The same excitation current flows back to the ADC ground and generates another voltage drop across the return leads. In order to get an accurate measurement of the temperature, these voltage drops must be measured and removed from the conversion result. Assuming that the resistance is approximately the same for the forward and return paths (R1 = R2), the second channel (CH1) on the LTC2402 can measure this drop. These errors are then removed with simple digital correction. The result of the first conversion on CH0 corresponds to an input volt- age of VRTD + R1 • IEXCITATION. The result of the second conversion (CH1) is –R1 • IEXCITATION. Note that the LTC2402’s input range is not limited to the supply rails; it has underrange as well as overrange capabilities. The device’s input range is –300mV to FSSET + 300mV (DOUT includes a sign bit indicating a negative input). Adding the two conversion results, the voltage drop across the RTD’s leads is cancelled and the final result is VRTD. Conclusion Linear Technology has introduced two new converters to its 24-bit No Latency ∆Σ™ converter family. The family consists of the LTC2400 (1-channel, 8-pin SO), LTC2408 (8-channel, 24-bit ADC) and the LTC2401/LTC2402 shown here. Each device features excellent absolute accuracy, ease-of-use and near zero drift. The LTC2401/ LTC2402 also include full-scale set (FSSET) and zero-scale set (ZSSET) inputs for removing errors due to systematic voltage drops. The performance, features and ease-of-use of these devices warrant that designers reconsider the accuracy capabilities of their future system designs. 19