® SP6644/6645 Single/Dual Alkaline Cell, High Efficiency Boost DC-DC Regulator ■ 90mA Output Current at 1.3V Input ■ 190mA Output Current at 2.6V Input ■ +2V to +5.5V Output Range ■ 0.88V Guaranteed Start-Up ■ 92% High Efficiency ■ 1.6µA Quiescent Supply Current at VBATT ■ Reverse Battery Protection ■ Internal Synchronous Rectifier ■ 5nA Logic Controlled Shutdown Current From VBATT ■ Low-Battery Detection Active LOW Output ■ Small 8 Pin MSOP Package ■ Flexibility to Optimize Inductor Type with Programmable Peak Current Control ■ No External FETs V B AT 1 B AT T L 0 2 RLIM 3 SP6644 SP6645 8 Pin MSOP SHDN 4 8 V OUT 7 LX 6 GND 4 FB DESCRIPTION The SP6644/6645 devices are high-efficiency, low-power step-up DC-DC converters ideal for single or dual alkaline cell applications such as pagers, remote controls, pointing devices, medical monitors, and other low-power portable end products. Designers can control the SP6644 device with an active LOW shutdown input. The SP6644 device features an active low output for batteries below +1.0V. The SP6645 device features an active low output for batteries below +2.0V. Both devices contain a 0.8Ω synchronous rectifier, a 0.5Ω N-channel MOSFET power switch, an internal voltage reference, circuitry for pulsefrequency-modulation, and an under voltage comparator. The output voltage for the SP6644/6645 devices is preset to +3.3V + 4% or can be adjusted from +2V to +5.5V by manipulating two external resistors TYPICAL APPLICATION CIRCUIT 22µH 0.7A 0.88V to 3.3V Input VBATT 47µF LX VOUT RLIM +3.3VOUT SP6644 SP6645 47µF BATTLO SHDN FB GND Rev:B Date 4/13/04 SP6644/6645 High Efficiency Boost Regulator 1 © Copyright 2004 Sipex Corporation ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VBATT to GND.............................................-0.3 to 6.0V VOUT to GND..............................................-0.3 to 6.0V LX, SHDN, FB, BATTLO, to GND.............-0.3 to 6.0V Reverse battery Current, TAMB=+25˚C.............220mA (NOTE 1) VBATT forward current............................................0.5A VOUT, LX current......................................................1A Storage Temperature Range............-65˚C to +165˚C Lead Temperature (soldering 10s)..................+300˚C Operating Temperature.......................-40˚C to +85˚C Power Dissipation Per Package 8-pin µSOIC (derate 4.85mW/OC above +70OC)..........390mW ELECTRICAL CHARACTERISTICS o VBATT = VSHDN = 1.3V, ILOAD = 0mA, FB = GND, TAMB = -40 C to +85 C, and typical values are at TAMB = +25oC unless otherwise noted. PARAMETER MIN. o TYP. Maximum Operating Input Voltage, VBATT(MAX) Start-Up Input Voltage, VBATT 0.82 Start-Up Input Voltage, VBATT Temperature Coefficient -1 SHDN Input Voltage VIL VIH MAX. UNITS ♦ 3.3 V ♦ 1.1 V ♦ CONDITIONS RL = 3kΩ, mVºC 15 % % of VBATT % of VBATT 80 SHDN Input Current 1 100 nA ♦ FB Input Current 1 10 0 nA ♦ VFB =1.3V, FB Set Voltage, VFB 1.215 1.262 1.309 V ♦ external feedback BATTLO Falling Trip Voltage 0.94 1.88 1.00 2.00 1.06 2.12 V ♦ SP6644, VOUT = 3.3V SP6645, VOUT = 3.3V Output Voltage, VOUT 3.16 3.30 3.44 V ♦ VFB<0.1V Output Voltage Range 2. 0 5.5 V ♦ external feedback 1.0 Ω VOUT = 3.3V 1.6 Ω VOUT = 3.3V N-Channel On-Resistance P-Channel On-Resistance Rev:B Date 4/13/04 0.5 0.8 SP6644/6645 High Efficiency Boost Regulator 2 © Copyright 2004 Sipex Corporation ELECTRICAL CHARACTERISTICS VBATT = VSHDN = 1.3V, ILOAD = 0mA, FB = GND, TAMB = -40oC to +85oC, and typical values are at TAMB = +25oC unless otherwise noted. PARAMETER MIN. TYP. MAX. UNITS Quiescent Current into VOUT, IQOUT 50 80 µA ♦ VOUT = 3.5V Quiescent Current into VBATT, IQBATT 1.6 3.0 µA ♦ VBATT = 1.0V Shutdown Current into VOUT, ISHDNOUT 0.001 0.5 µA ♦ VOUT = 3.5V, VSHDN - 0V Shutdown Current into VBATT, ISHDNBATT 0.005 0.1 µA ♦ VBATT = 1.0V, VSHDN - 0V 0.4 V ♦ VBATT = 0.9V,VOUT = +3.3V,ISINK =1mA 1 µA ♦ VBATT = 2.6V,VBATTLO = 3.5V % ♦ ILOAD = 150mA,VBATT = 2.6V mA ♦ RLIM = 5kΩ, NOTE 3 V ♦ Low Output Voltage for BATTLO, VOL Leakage Current for BATTLO Efficiency Inductor Peak Current, IPEAK Under Voltage Lock-out (UVLO) 89 275 350 0.500 0.720 400 CONDITIONS NOTE 1: The reverse battery current is measured from the Typical Operating Circuit's input terminal to GND when the battery is connected backward. A reverse current of 220mA will not exceed package dissipation limits but, if left for an extended time (more than 10 minutes), may degrade performance. NOTE 2: Specifications to -40oC are guaranteed by design, not production tested. NOTE 3: Inductor Peak Current where . IPEAK Rev:B Date 4/13/04 = 1400 RLIM SP6644/6645 High Efficiency Boost Regulator 3 © Copyright 2004 Sipex Corporation PERFORMANCE CHARACTERISTICS Refer to the circuit in Figure 28, TAMB = +25oC unless otherwise noted. 100 90 90 80 Efficiency (%) Efficiency (%) 100 Vb=1.0V Vb=1.3V Vb=2.0V Vb=2.6V Vb=3.2V 70 60 50 80 Vb=1.0V Vb=1.3V Vb=2.0V Vb=2.6V Vb=3.2V 70 60 50 40 40 0.1 1.0 10.0 100.0 1000.0 0.1 1.0 Iload (mA) Figure 1. Efficiency vs. Output Current (Vout=3.3V), Rlim=2.5k, Li=22uH Sumida CD43 Efficiency (%) 90 Efficiency (%) 100 90 80 Vb=1.0V Vb=1.3V Vb=2.0V Vb=2.6V Vb=3.2V 70 60 50 1.0 10.0 Iload (mA) 100.0 Vb=1.0V Vb=1.3V Vb=2.0V Vb=2.6V Vb=3.2V 70 60 50 40 0.1 1.0 10.0 Iload (mA) 100.0 1000.0 Figure 4. Efficiency vs. Output Current (Vout=3.3V), Rlim=5k, Li=100µH Sumida CD54 100 100 90 90 80 Efficiency (%) Efficiency (%) 1000.0 80 1000.0 Figure 3. Efficiency vs. Output Current (Vout=3.3V), Rlim=2.5k, Li=22uH Sumida CDRH5D18 Low Profile Vb=1.0V Vb=1.3V 70 Vb=2.0V Vb=2.6V Vb=3.2V 60 50 0.1 1.0 10.0 Iload (mA) 100.0 80 Vb=1.0V Vb=1.3V Vb=2.0V Vb=2.6V Vb=3.2V 70 60 50 40 0.1 40 1000.0 Figure 5. Efficiency vs. Output Current (Vout=5V), Rlim=2.5k, Li=22uH Sumida CD43, Refer to Figure 29, R1=499k, R2=169k 1.0 10.0 Iload (mA) 100.0 1000.0 Figure 6. Efficiency vs. Output Current (Vout=5V), Rlim=5k, Li=22uH Sumida CD43, Refer to Figure 29, R1=499k, R2=169k 3.33 3.33 3.32 3.32 3.31 3.31 Vb=1.3V Vb=2.6V 3.30 VOUT (V) VOUT (V) 100.0 Figure 2. Efficiency vs. Output Current (VOUT=3.3V), Rlim=5k, Li=22µH Sumida CD43 100 40 0.1 10.0 Iload (mA) 3.29 Vb=1.3V Vb=2.6V 3.30 3.29 3.28 3.28 3.27 3.27 0 20 40 0 60 80 100 120 140 160 180 200 10 90 100 Figure 8. Line/Load Rejection vs. Output Current (Vout=3.3V), Rlim=5k, Li=22uH Sumida CD43 Figure 7. Line/Load Rejection vs. Output Current (Vout=3.3V), Rlim=2.5k, Li=22uH Sumida CD43 Rev:B Date 4/13/04 20 30 40 50 60 70 80 Iload (mA) Iload (mA) SP6644/6645 High Efficiency Boost Regulator 4 © Copyright 2004 Sipex Corporation PERFORMANCE CHARACTERISTICS 5.08 5.07 5.08 5.06 5.05 5.06 5.07 5.04 5.03 VOUT (V) VOUT (V) Refer to the circuit in Figure 28, TAMB = +25oC unless otherwise noted. Vb=1.3V Vb=2.6V 5.02 5.01 5.05 Vb=1.3V Vb=2.6V 5.04 5.03 5.02 5.01 5.00 0 10 20 30 40 50 60 70 5.00 80 90 100 0 10 20 Iload (mA) Rlim=2.5K Rlim=5K 1.0 40 50 Figure 10. Line/Load vs. Output Current (Vout=5V), Rlim=5k, Li=22uH Sumida CD43, Refer to figure 29, R1=499k, R2=169k 2.0 3.0 Max IO (mA) Max IO (mA) Figure 9. Line/Load vs. Output Current (Vout=5V), Rlim=2.5k, Li=22uH Sumida CD43, Refer to figure 29, R1=499k, R2=169k 240 220 200 180 160 140 120 100 80 60 40 20 0 0.0 30 Iload (mA) 4.0 240 220 200 180 160 140 120 100 80 60 40 20 0 0.0 Rlim=2.5K Rlim=5K 1.0 2.0 3.0 4.0 Vbatt (V) Vbatt (V) Figure 11. Maximum Load Current vs. Vbatt (Vout=3.3V), Li=22uH Sumida CD43 Figure 12. Maximum Load Current vs. Vbatt (Vout=5V), Li=22uH Sumida CD43, Refer to Figure 29, R1=499k, R2=169k 3.33 10000 3.31 Rlim=2.5k Rlim=5k VOUT (V) Battery Current (µA) 3.32 1000 100 3.30 3.29 3.28 10 3.27 0.0 1.0 2.0 3.0 4.0 -40 -20 0 Vbatt (V) 40 60 80 100 Figure 14. Output Voltage vs. Temperature, Rlim=2.5k, Rload=3k, (Vout=3.3V),Li=22uH Sumida CD43 Figure 13. No Load Battery Current vs. Vbatt (Vout=3.3V), Li=22uH Sumida CD43 60 3.0 55 2.5 50 2.0 IBQ (µA) IOQ (µA) 20 Temperature (degC) 45 40 35 1.5 1.0 0.5 30 0.0 -40 -20 0 20 40 60 80 100 -40 -20 Temperature (degC) 20 40 60 80 100 Temperature (degC) Figure 15. Io Pin Quiescent Current vs. Temperature, (Vout=3.3V) Rev:B Date 4/13/04 0 Figure 16. Ibatt Pin Quiescent Current vs. Temperature, (Vout=3.3V), Vbatt=1.0V SP6644/6645 High Efficiency Boost Regulator 5 © Copyright 2004 Sipex Corporation PERFORMANCE CHARACTERISTICS Refer to the circuit in Figure 28, TAMB = +25oC unless otherwise noted. 100 3.037 90 70 60 VOUT (V) Efficiency (%) 3.036 Vb=1.0V Vb=1.3V Vb=2.0V Vb=2.6V Vb=3.2V 80 50 3.035 Vb=1.3V Vb=2.6V 3.034 3.033 40 3.032 30 0.1 1.0 10.0 Iload (mA) 100.0 0 1000.0 60 80 100 120 140 160 180 200 Iload (mA) Figure 18. SP6644/6201 LDO Line/Load Rejection vs. Output Current (Vout=3.3V), Rlim=2.5k, Li=22µH Sumida CD-43, Refer to Figure 30 Figure 17. SP6644/6201 DC/DC LDO Combination Efficiency vs. Output Current (Vout=3.3V), Rlim=2.5k, Li=22µH Sumida CD-43, Refer to Figure 30 240 220 200 180 160 140 120 100 80 60 40 20 0 10000 Battery Current (µA) Max IO (mA) 20 40 0.0 1.0 2.0 3.0 1000 100 10 4.0 0.0 Vbatt (V) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Vbatt (V) Figure 20. SP6644/6201 DC/DC LDO No-Load Ibatt vs. Vbatt (Vout=3.3V), Rlim=2.5k, Li=22µH Sumida CD43, Refer to Figure 30 Figure 19. SP6644/6201 DC/DC LDO Maximum Load Current vs. Vbatt (Vout=3.3V), Rlim=2.5k, Li=22µH Sumida CD-43, Refer to Figure 30 Li 0.5A/div SP6201 Out 10mV/div VOUT 50mV/div SP6644 Out 20mV/div VBATT 50mV/div Figure 21. SP6644/6201 DC/DC LDO Output Ripple Voltage (Vout=3.3V), Rlim=2.5k, Li=22µH Sumida CD43, Refer to Figure 30 Figure 22. Load Transient Response, Vbatt=1.3V, (Vout=3.3V), Rlim=2.5k, Li=22µH Sumida CD-43 VOUT 50mV/div Li 0.2A/div VBATT 1V/div VOUT, VLX,VBATT 1V/div Figure 23. Line Transient Response, (Vout=3.3V), Rlim=2.5k, Iload=22µH Sumida CD-43 Rev:B Date 4/13/04 Figure 24. Switching Waveforms, (Vout=3.3V), Vbatt=1.3V, Rlim=2.5k, Iload=10mA, Li=22µH Sumida CD-43 SP6644/6645 High Efficiency Boost Regulator 6 © Copyright 2004 Sipex Corporation PERFORMANCE CHARACTERISTICS Refer to the circuit in Figure 28, TAMB = +25oC, unless otherwise noted. SDN 2V/div Li 0.5A/div VBATT 1 VOUT, VBATT 1V/div Figure 25. Shutdown Response and Inductor Current, Vout=3.3V, Vbatt=1.3V, Rlim=2.5k, Rload=550 Ohms, Li=22uH Sumida CD43 SP6644 SP6645 8 VOUT 7 LX BATTLO 2 RLIM 3 6 GND SHDN 4 5 FB Figure 26. Pinout for the SP6644/6645 PIN DESCRIPTION NAME FUNCTION PIN NO. Battery Supply. This pin ties to the sensor input of the BATTLO comparator. 1 BATTLO Open-Drain Battery Low Output. When the voltage drops below 1V for the SP6644 or 2V for the SP6645, BATTLO sinks current. 2 RLIM Resistor Programmable Inductor Peak Current. Connecting a resistor from this pin to 1400 ground programs the inductor peak current where IPEAK = RLIM 3 Active-LOW Shutdown Input. Connect to VBATT for normal operation. 4 Feedback Input. Input for adjustable-output operation. Connect this input pin to an external resistor voltage divider between VOUT and GND. Connect to GND for fixedoutput operation. 5 Connect to the lowest circuit potential, typically ground. 6 LX Coil. An inductor is connected from VBATT to the N-Channel MOSFET switch drain and the P-Channel synchronous-rectifier drain through this pin. 7 VOUT Power Output. Feedback input for fixed 3.3V operation and IC power input. Connect filter capacitor close to VOUT. 8 VBATT SHDN FB GND Table 1. SP6644/6645 Pin Descriptions Rev:B Date 4/13/04 SP6644/6645 High Efficiency Boost Regulator 7 © Copyright 2004 Sipex Corporation DESCRIPTION peak inductor current is satisfied. This is indicated by the falling edge of the I-Charge comparator output. The approximate inductor charging time is defined by: The SP6644/6645 devices are high-efficiency, low-power step-up DC-DC converters ideal for single or dual alkaline cell applications such as pagers, remote controls, and other low-power portable end products. tCHARGE ≅ L x IPEAK / VBATT where tCHARGE [s] is the approximate inductor charging time, L [H] is the inductance, IPEAK [A] is the peak inductor current, and VBATT [V] is the input voltage to the device. The SP6644/6645 devices feature a 5nA logiccontrolled shutdown mode and a dedicated low-battery detector circuitry. Both devices contain a 0.8Ω synchronous rectifier, a 0.5Ω N-channel MOSFET power switch, an internal voltage reference, circuitry for pulse-frequencymodulation, and an under voltage comparator. The output voltage for the SP6644/6645 devices can be adjusted from +2V to +5.5V by manipulating two external resistors. The output voltage is preset to +3.3V. The peak inductor current, IPEAK, is programmed externally by putting a resistor between the RLIM pin and ground. This is defined by: IPEAK = 1400 RLIM where IPEAK [A] is the peak inductor current and RLIM [Ω] is the value of the resistor connected from pin RLIM to ground. THEORY OF OPERATION The SP6644/6645 devices are ideal for end products that function with a single or dual alkaline cell, such as remote controls, pagers, and other portable consumer products. Designers can implement the SP6644/6645 devices into applications with the following power management operating states: 1. where the primary battery is good and the load is active, and 2. where the primary battery is good and the load is sleeping. When the charging N MOSFET turns off, the discharging P MOSFET turns on and the inductor current flows into the output capacitor and the load recharging the output. When the current through the discharging P MOSFET approaches zero, the I-Discharge comparator indicates to the logic to turn off the P MOSFET. The approximate time for discharging the inductor current can be determined by: tDCHG ≅ In the first operating state where the primary supply is good and the load is active, the SP6644/6645 devices typically offer 88% efficiency, drawing tens of milliamps. L x IPEAK VOUT - VBATT where tDCHG [s] is the time to discharge the inductor, L [H] is the inductance, IPEAK [A] is the peak inductor current, VOUT [V] is the output voltage, and VBATT [V] is the input voltage to the device. Applications will predominantly operate in the second state where the primary supply is good and the load is sleeping. The SP6644/6645 devices draw a very low quiescent current while the load in its disabled state will draw typically hundreds of microamps. The output filter capacitor stores charge while current from the inductor is high and holds the output voltage high until the discharge phase of the next switching cycle, smoothing power flow to the load. Between switching cycles, the inductor damping switch is closed suppressing the ringing caused by the inductor and the parasitic capacitance on the LX node. The pulse-frequency-modulation (PFM) circuitry provides higher efficiencies at low to moderate output loads than traditional PWM converters are capable of delivering. In a state where the error comparator detects that the output voltage at VOUT is too low, the internal N-channel MOSFET switch is turned on until the Rev:B Date 4/13/04 SP6644/6645 High Efficiency Boost Regulator 8 © Copyright 2004 Sipex Corporation BLOCK DIAGRAM VBATT VOUT LOGIC DRV-P PDISCHARGE FB I-Discharge DRV-N +1.25V VREF LX Inductor Damping Switch REFREADY +1.0V (SP6644) +2.0V (SP6645) START UP OSC I-Charge N VLPK RLIM NCHARGE SP6644 SP6645 SHDN RLIM BATTLO N +1.0V (SP6644) +2.0V (SP6645) GND Figure 27. Internal Block Diagram of the SP6644/6645 Rev:B Date 4/13/04 SP6644/6645 High Efficiency Boost Regulator 9 © Copyright 2004 Sipex Corporation Internal Bootstrap Circuitry The internal bootstrap circuitry contains a low-voltage start-up oscillator that pumps up the output voltage to approximately 1.9V so the main DC-DC converter can function. At lower battery supply voltages, the circuitry can start up with low-load conditions. Designers can reduce the load as needed to allow start-up with input voltages below 1V. Refer to Figures 10 to 13. Once started, the output voltage can maintain the load as the battery voltage decreases below the initial start-up voltage. The start-up oscillator is powered by VBATT driving a charge pump and NMOS switch. During start-up, the P-channel synchronous rectifier remains off and either its body diode or an external diode is used as an output rectifier. Since the FB leakage current is 10nA maximum, designers should select the feedback resistor R2 in the 100kΩ to 1MΩ range. R1 can be determined with the following equation: R1 = R2 x VOUT -1 VREF where R1 [Ω] and R2 [Ω] are the feedback resistors in Figure 29, VOUT [V] is the output voltage, and VREF [V] is 1.25V. Battery Reversal Protection The SP6644/6645 devices will tolerate singlecell battery reversal up to the package powerdissipation limits noted in the ABSOLUTE MAXIMUM RATINGS section. An internal diode in series with an internal 5Ω resistor limits any reverse current to less than 220mA preventing damage to the devices. Prolonged operation above 220mA reverse-battery current can degrade performance of the devices. BATTLO Circuitry The SP6644 device has an internal comparator for low-battery detection. If VBATT drops below 1V, BATTLO will sink current. BATTLO is an open-drain output. The SP6645 operates in the same manner with a threshold voltage of 2V. The Inductor The programmable peak inductor current feature of the SP6644/6645 devices affords a great deal of flexibility in choosing an inductor. The most important point to consider when choosing an inductor is to insure that the peak inductor current is programmed below the saturation rating of the inductor. If the inductor goes into saturation, the internal switches and the inductor will be stressed due to current peaking, potentially leading to reliability problems with the application circuit. Shutdown for the SP6644 A logic LOW at SHDN will drive the SP6644 into a shutdown mode where BATTLO goes into a high-impedance state, the internal switching MOSFET turns off, and the synchronous rectifier turns off to prevent reverse current from flowing from the output back to the input. Designers should note that in shutdown, the output can drift to one diode drop below VBATT because there is still a forward current path through the synchronous-rectifier body diode from the input to the output. To disable the shutdown feature, designers can connect SHDN to VBATT. The peak inductor current is programmed by putting a resistor between the RLIM pin and ground. The usable current range is between 150mA and 560mA. This is defined by: Adjustable Output Voltage Driving FB to ground (logic LOW) will drive the output voltage to the fixed-voltage operation of +3.3V + 4%. Connecting FB to a voltage divider between VOUT and ground will select an adjustable output voltage between +2V and +5.5V. Refer to Figure 28. FB regulates to +1.25V. Rev:B Date 4/13/04 IPEAK = 1400 RLIM where IPEAK [A] is the peak inductor current, and RLIM [Ω] is the value of the resistor connected from pin RLIM to ground. SP6644/6645 High Efficiency Boost Regulator 10 © Copyright 2004 Sipex Corporation 22µH 0.7A 0.88V to 3.3V Input 22µF VBATT 0.1µF LX RLIM VOUT VOUT= 2V to 5.2V SP6644 SP6645 47µF 100pF* BATTLO SHDN R1 *optional compensation FB R2 GND Figure 28. Adjustable Output Voltage Circuitry APPLICATION NOTES With an external resistor tolerance of +1%, the peak current tolerance will be +6%. To make sure that the SP6644/6645 internal circuitry adequately controls the inductor current, it is recommended that values equal to or greater than 22µH (+10%) be used. Printed circuit board layout is a critical part of design. Poor designs can result in excessive EMI on the voltage gradients and feedback paths on the ground planes with applications involving high switching frequencies and large peak currents. Excessive EMI can result in instability or regulation errors. The SP6644/6645 devices control algorithm delivers an average maximum load current in regulation as defined by: E x IPEAK x VBATT 2 x VOUT where ILOAD-MAX [A] is the maximum load current, E is the efficiency factor (generally between 0.8 and 0.9), IPEAK [A] is the programmed peak inductor current, VBATT [V] is the input voltage to the device, and VOUT [V] is the output voltage. All power components should be placed on the PC board as closely as possible with the traces kept short, direct, and wide (>50mils or 1.25mm). Extra copper on the PC board should be integrated into ground as a pseudo-ground plane. On a multilayer PC board, route the star ground using component-side copper fill, then connect it to the internal ground plane using vias. Given the minimum input voltage, output voltage, and maximum average load current, the value of IPEAK can be solved for and an appropriate inductor can be chosen. It is good design practice to use the lowest peak current possible to reduce possible EMI and output ripple voltage. A closed-core inductor, such as a toroid or shielded bobbin, will minimize any fringe magnetic fields or EMI. For the SP6644/6645 devices, the inductor and input and output filter capacitors should be soldered with their ground pins as close together as possible in a star-ground configuration. The VOUT pin must be bypassed directly to ground as close to the SP6644/6645 devices as possible (within 0.2in or 5mm). The DC-DC converter and any digital circuitry should be placed on the opposite corner of the PC board as far away from sensitive RF and analog input stages. The external voltage-feedback network should be placed very close to the FB pin as well as the RLIM resistor (within 0.2in or 5mm). Any ILOAD-MAX = Rev:B Date 4/13/04 SP6644/6645 High Efficiency Boost Regulator 11 © Copyright 2004 Sipex Corporation noisy traces, such as from the LX pin, should be kept away from the voltage-feedback network and separated from it using grounded copper to minimize EMI. Designers should add LC pi filters, linear post-regulators, or shielding in applications necessary to address excessive noise, voltage ripple, or EMI concerns. The LC pi filter's cutoff frequency should be at least a decade or two below the DC-DC converters's switching frequency for the specified load and input voltage. Capacitor equivalent series resistance is a major contributor to output ripple, usually greater than 60%. Low ESR capacitors are recommended. Ceramic capacitors have the lowest ESR. Low-ESR tantalum capacitors may be a more acceptable solution having both a low ESR and lower cost than ceramic capacitors. Designers should select input and output capacitors with a rating exceeding the peak inductor current. Do not allow tantalum capacitors to exceed their ripple-current ratings. A 22µF, 6V, low-ESR, surface-mount tantalum output filter capacitor typically provides 60mV output ripple when stepping up from 1.3V to 3.3V at 20mA. An input filter capacitor can reduce peak currents drawn from the battery and improve efficiency. Low-ESR aluminum electrolytic capacitors are acceptable in some applications but standard aluminum electrolytic capacitors are not recommended. A small SOT23-5pin 200mA Low Drop Out linear regulator can be used at the SP6644/6645 output to reduce output noise and ripple. The schematic in figure 29 illustrates this circuit with the SP6644 3.3V output followed by the Sipex SP6201 3.0V output Low Drop Out linear regulator. Compare in Figure 21 the SP6644 ripple of 40-50mVpp with the SP6201 ripple of about 3mVpp and you can see the amount of noise reduction obtained. Additional performance characteristics for the SP6644/6201 combination can be seen in figures 17 to 20. Inductor Specification Inductance (uH) 22 47 100 Manufacturer/Part No. Resistance (ohms) 0.38 (max) 0.28 (max) 0.32 (typ) 0.84 (max) 0.56 (typ) 0.7 (max) 1.1(typ) Sumida CD43-220 Sumida CDRH5D18-220 Coilcraft DO1608C-223 Sumida CD43-470 Coilcraft DO1608C-473 Sumida CD54-101 Coilcraft DO1608C-104 Isat (mA) 680 760 700 440 500 520 310 Table 1. Surface-Mount Inductor Information Rev:B Date 4/13/04 SP6644/6645 High Efficiency Boost Regulator 12 © Copyright 2004 Sipex Corporation SCHEMATIC WITH LDO COMBINATION 0.88V to 3.3V Input VBATT + GND C1 47µF LX L1 22µH J1 1 2 3 1 BATTLO 2 4 VOUT VBATT BATTLO 3 SHDN +3.3V VOUT R4 1M RLIM SHDN SP6644 U1 LX GND FB 8 R1 Open 7 6 + C2 47µF GND 1 VIN 2 GND VOUT 5 SP6201 3 ENABLE RESET_N 4 +3.0V VOUT C3 1µF 5 R2 100k R3 2.5k Probe access points for external connection by the user Figure 29. Schematic SP6644/6201 DC/DC LDO Combination Rev:B Date 4/13/04 SP6644/6645 High Efficiency Boost Regulator 13 © Copyright 2004 Sipex Corporation PACKAGE: 8 PIN MSOP D e1 Ø1 E/2 R1 R E1 E Gauge Plane L2 Ø1 Seating Plane Ø L L1 1 2 e Pin #1 indentifier must be indicated within this shaded area (D/2 * E1/2) Dimensions in (mm) 8-PIN MSOP JEDEC MO-187 (AA) Variation MIN NOM MAX A - - A1 0 - 0.15 A2 0.75 0.85 0.95 b 0.22 - 0.38 c 0.08 - 0.23 D 3.00 BSC E 4.90 BSC E1 3.00 BSC e 0.65 BSC e1 1.95 BSC L 0.40 L1 0.60 1.10 D A2 A b A1 (b) WITH PLATING 0.80 0.95 REF 0.25 BSC L2 - N 8 c - R 0.07 - - R1 0.07 - - - 15º Ø 0º Ø1 0º 1 Rev:B Date 4/13/04 BASE METAL 8º PACKAGE: 8-PIN MSOP SP6644/6645 High Efficiency Boost Regulator 14 © Copyright 2004 Sipex Corporation ORDERING INFORMATION Model Temperature Range Package Type SP6644EU ............................................. -40OC to +85OC ......................................... 8-Pin MSOP SP6645EU ............................................. -40OC to +85OC ......................................... 8-Pin MSOP Please consult the factory for pricing and availability on a Tape-On-Reel option. Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation Headquarters and Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: [email protected] Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Rev:B Date 4/13/04 SP6644/6645 High Efficiency Boost Regulator 15 © Copyright 2004 Sipex Corporation