DESIGN IDEAS Active Voltage Positioning Saves Output Capacitors in Portable by John Seago and Ajmal Godil Computer Applications Introduction pp. 16–20) can take advantage of active voltage positioning. Active voltage positioning is a technique that can be used to save cost and space by reducing the number of output capacitors required to meet a microprocessor’s power supply requirements. Total system cost and required PCB space are important aspects of today’s portable equipment designs, so decreasing the number of large, expensive output capacitors is worth some effort. Both the LTC1735/ LTC1736 current mode switching regulator controllers (Linear Technology IX:1, February 1999, pp. 1, 3–5, 35) and the LTC1702/LTC1703 voltage mode controllers (Linear Technology IX:3, September 1999, Microprocessor Load Steps Microprocessors frequently change their load current requirement from almost no load to maximum load current and back again very quickly. The rising and trailing edges of these load current steps exceed the bandwidth of the switching regulator control loop. Currently, a typical load step is either 0.2A to 12A in 100ns or 12A to 0.2A in 100ns. The core voltage of the microprocessor must be held to about ±0.1V of nominal in spite of these load steps. Since the switching regulator control loop cannot respond in 100ns, the output capacitors must temporarily supply the load current when the output current increases rapidly. Also, the output capacitors must absorb the energy stored in the inductor when the output current decreases rapidly. Capacitor ESR and ESL primarily determine the amount of droop and overshoot in the output voltage caused by a load current step. Normally, several capacitors in parallel are required to meet the microprocessor load transient requirements. R1 100k POWER GOOD R2 680k R4 68k R3 160k 6 C2 0.1µF R5 100k C4 C3 2 100pF 3 1 100pF C1 4 39pF 5 C5 47pF C6 330pF PGOOD VIN RUN/SS TG ITH COSC VIN 7.5V–24V C8 0.1µF BOOST SW FCB INTVCC SGND EXTVCC LTC1736 7 C7 SENSE– VIDVCC 1000pF 8 SENSE+ BG 9 PGND VFB 10 VID4 VOSENSE 11 VID3 VID0 12 VID2 VID1 C12–C14 10µF, 35V Y5V ×3 21 Q1 FDS6680A 24 23 22 20 17 16 19 C9 0.22µF D1 MBR0530 C11 C10 1µF + 4.7µF 10V L1 1.0µH R6 0.003Ω VOUT 0.9V–2.0V 14A + D2 MBRS340 C15–C17 180µF, 4V ×3 18 15 14 Q2–Q3 FDS6680A ×2 13 VID0 VID1 VID2 VID3 VID4 C12–C14: TAIYO YUDEN GMK325F106 (408) 573-4150 C15–C17: PANASONIC EEFUE0G181R (201) 348-7522 L1: PANASONIC ETQP6F1R0SA Q1–Q3: FAIRCHILD FDS6680A (207) 775-4502 R6: IRC LRF2512-01-R003-J (512) 992-7900 Figure 1. LTC1736-based core-voltage regulator with active voltage positioning Linear Technology Magazine • February 2000 23 DESIGN IDEAS LTC1736 Circuit with Active Voltage Positioning 1.72V 1.60V 1.48V 100µs/DIV Figure 2. Transient response for a 12A load-current step How Active Voltage Positioning Works output voltage variation is allowed on the output capacitors. The implementation of active voltage positioning depends on the type of OPTI-LOOP error amplifier used in the switching regulator. With the LTC1736, connecting two resistors to the ITH pin adjusts the output voltage in inverse proportion to the amount of load current. This technique will only work with a current mode control regulator. Different techniques are available for the LTC1703; these can also be used on the LTC1736 and will be discussed later. Active voltage positioning is a form of deregulation. It sets the output voltage high for light loads and low for heavy loads. In the low-current-tohigh-current transition, the output voltage starts at a voltage higher than nominal so the output voltage can sag more and still meet the minimum output voltage specification. By setting the output voltage lower than nominal for heavy load conditions, more output voltage variation is possible when the load current suddenly decreases to almost zero. Less output capacitance is required because more D1 MBR0520L C12 1µF + 18 C6 0.1µF 4 Q2 L2 1µH 5 3 Q3 C13 150µF ×4 R9 30k 6 12 Q1 11 C23 1200pF 9 8 R19 1.8k C19 0.1µF R20 390k C18 10 13 14 C17 43pF 8.2pF C1 22µF C22 10µF 2 R18 0.0025Ω VOUT CPU 0.9V–2.0V 14A R17 10Ω Q1–Q3: IRF7811 (310) 322-3331 Q4: SILICONIX Si4966 (800) 544-5665 C1, C2: TAIYO YUDEN LMK432BJ226MM (408) 573-4150 C3: AVX TPSV3307010R0060 (207) 282-5111 C10: SANYO POSCAP 6TPA47M (619) 661-6835 C13: SANYO POSCAP 4TPC150M L1: COILTRONICS 2P2B-2R2 (561) 241-7876 L2: SUMIDA CEP125 (847) 956-0666 R18: 2 × 5mΩ IN PARALLEL Reducing output capacitance with active voltage positioning requires connecting two resistors to the ITH pin and readjusting the loop compensation component values. Figure 1 shows a core voltage regulator circuit designed to operate from a 7.5V to 24V input and provide ±7.5% accuracy to VID controlled output voltages from 0.9V to 2.0V with load current steps from 0.2A to 12A. Although 7.5% output voltage accuracy does not sound very impressive, 7.5% of 1.4V is only 105mV, including setpoint accuracy and load and line regulation, as well as margin for transient response to the 12A load step. The circuit in Figure 1 is a current mode, synchronous buck regulator with a switching frequency of 300kHz. The nominal output voltage is selected by the standard Intel mobile VID code. The actual output voltage varies as a function of the load current. The no-load output voltage from this circuit is higher than nominal because the current sourced by R3 creates a positive offset at the input of the transconductance error amplifier. The error amplifier current sourced into 15 VCC BOOST1 TG1 LTC1703 PVCC BOOST2 TG2 SW1 SW2 BG1 BG2 IMAX1 FB2 SENS IMAX2 FB1 COMP1 RUN/SS1 SGND COMP2 RUN/SS2 FAULT FCB B0 PGND B1 B4 B2 B3 1 C2 22µF D2 MBR0520L VIN 5V C7 0.1µF 27 Q4-A 25 L1 2.2µH 24 26 Q4-B 19 28 C3 330µF R10 43k VOUT I/O 1.5V/3A R7 2.7k 820 pF R11 9.76k C10 47µF R13 10.7k 20 C14 1µF 21 22 7 C16 0.1µF C20 18pF C21 62pF 23 R16 180k 17 16 R15 330k VID0 VID1 VID2 VID3 VID4 Figure 3. LTC1703-based regulator with active voltage positioning implemented with a sense resistor 24 Linear Technology Magazine • February 2000 DESIGN IDEAS C12 1µF + 18 C6 0.1µF 2 4 Q2 5 3 Q3 C13 150µF ×4 C23 1200pF R9 30k 6 12 Q1 11 9 8 R19 1.8k C19 0.1µF C18 R21 390k 10 13 14 C17 43pF 8.2pF C1 22µF C23 10µF D1 MBR0520L L2 1µH VOUT CPU 0.9V–2.0V 14A R17 10Ω Q1–Q3: IRF7811 (310) 322-3331 Q4: SILICONIX Si4966 (800) 544-5665 C1, C2: TAIYO YUDEN LMK432BJ226MM (408) 573-4150 C3: AVX TPSV3307010R0060 (207) 282-5111 C10: SANYO POSCAP 6TPA47M (619) 661-6835 C13: SANYO POSCAP 4TPC150M L1: COILTRONICS 2P2B-2R2 (561) 241-7876 L2: SUMIDA CEP125 (847) 956-0666 R20 C22 150Ω 1µF 15 LTC1703 VCC BOOST1 PVCC BOOST2 TG1 TG2 SW1 SW2 BG1 BG2 IMAX1 FB2 SENS IMAX2 COMP2 FB1 RUN/SS2 COMP1 FAULT RUN/SS1 FCB SGND B0 PGND B1 B4 B2 B3 1 27 C2 22µF C3 330µF VIN 5V D2 MBR0520L C7 0.1µF Q4-A 25 L1 2.2µH 24 Q4-B 820 R11 pF 9.76k 19 28 VOUT I/O 1.5V/3A R7 2.7k 26 R10 43k C10 47µF R13 10.7k 20 C14 1µF 21 22 7 C16 0.1µF 23 C20 18pF C21 62pF R16 180k 17 16 R15 330k VID0 VID1 VID2 VID3 VID4 Figure 4. LTC1703-based regulator with active voltage positioning implemented using the DC resistance of the inductor R4 develops a negative input offset voltage. This negative offset causes the output voltage to be less than nominal under full load conditions. Forced offsets at the input of the error amplifier should be limited to ±30mV. If a lower output voltage is required at full load, the voltage drop across the current sense resistor can be subtracted from the regulated output voltage by connecting the VOSENSE pin to the inductor side of the sense resistor, as shown in Figure 1. Figure 2 shows a transient waveform of 50mV and –100mV from a 12V input and 1.6V output of Figure 1’s circuit. The output voltage tolerance of 7.5% allows a ±120mV variation. R20, is added between the FB1 pin and ground. The DC value by which the output voltage increases over nominal can be calculated by the following formula: VHIGHER = (0.8/390k) • 10k ≈ 20mV In Figure 4, the voltage deregulation is set by the DC resistance of the power inductor, which is approximately 2.5mΩ. The SENSE pin on the LTC1703 is connected between R20 (150Ω) and C24 (1µF). R20 and C24, which are connected across the inductor L2, act as a lowpass filter Linear Technology Magazine • February 2000 Conclusion Active voltage positioning allows more output voltage change during a load transient so fewer output capacitors are required. Fewer capacitors result i n a s m a l l e r, l e s s e x p e n s i v e regulator. LOAD STEP = 0A–14A VIN = 5V VOUT = 1.6V COUT = 4 × 150µF POSCAPS LTC1703 Circuit with Active Voltage Positioning Figures 3 and 4 show two methods of implementing active voltage positioning on an LTC1703 circuit. In Figure 3, the voltage deregulation is set by adding a 2.5mΩ resistor (R18) in the power path. At full load, the output voltage will be less than nominal by IFULL LOAD • 0.0025. In order to program the output voltage higher than nominal at zero load, a 390k resistor, with a time constant of 150µs. Likewise, a 390k resistor, R21, is added between the FB1 pin and ground. Figure 5 shows the transient response of the LTC1703 circuit in Figures 3 and 4 for a 0A–14A transient load step with four 150µF Poscap capacitors. 1.72V VHIGHER 1.60V 1.48V 50µs/DIV Figure 5. LTC1703 VOUT CPU transient response with active voltage positioning 25