TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 D features D D D D D D D D D High-Efficiency Synchronous Step-Down Converter With Greater Than 95% Efficiency 2 V to 5.5 V Operating Input Voltage Range Adjustable Output Voltage Range From 0.8 V to VI Fixed Output Voltage Options Available in 0.9 V, 1 V, 1.2 V, 1.5 V, 1.8 V, 1.9 V, 2.5 V, and 3.3 V Synchronizable to External Clock Signal up to 1 MHz Up to 600 mA Output Current Pin-Programmable Current Limit High Efficiency Over a Wide Load Current Range in Power Save Mode 100% Maximum Duty Cycle for Lowest Dropout D D D D Low-Noise Operation Antiringing Switch and PFM/PWM Operation Mode Internal Softstart 50-µA Quiescent Current (TYP) Available in the 10-Pin Microsmall Outline Package (MSOP) Evaluation Module Available applications D D D D D D Low-Power CPUs and DSPs Cellular Phones Organizers, PDAs, and Handheld PCs MP-3 Portable Audio Players Digital Cameras USB-Based DSL Modems and Other Network Interface Cards description The TPS6200x devices are a family of low-noise synchronous step-down dc-dc converters that are ideally suited for systems powered from a 1-cell Li-ion battery or from a 2- to 3-cell NiCd, NiMH, or alkaline battery. The TPS6200x operates typically down to an input voltage of 1.8 V, with a specified minimum input voltage of 2 V. EFFICIENCY vs LOAD CURRENT 100 VI = 2 V to 5.5 V 90 1 VIN L EN FB 9 10 µH VO = 0.8 V to VI 80 10 µF Efficiency – % 70 8 SYNC = Low 10 µF TPS6200x 60 6 SYNC = High 50 7 ILIM 40 SYNC GND 30 3 PGND PG FC † 10 4 PG 2 0.1 µF 20 VI = 3.6 V, VO = 2.5 V 10 0 5 0.1 1 10 100 IO – Load Current – mA † With VO ≥1.8 V; Co = 10 µF, VO <1.8 V; Co = 47 µF 1000 Figure 1 Figure 2. Typical Application Circuit for Fixed Output Voltage Option Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 description (continued) The TPS6200x is a synchronous current-mode PWM converter with integrated N- and P-channel power MOSFET switches. Synchronous rectification is used to increase efficiency and to reduce external component count. To achieve the highest efficiency over a wide load current range, the converter enters a power-saving pulse-frequency modulation (PFM) mode at light load currents. Operating frequency is typically 750 kHz, allowing the use of small inductor and capacitor values. The device can be synchronized to an external clock signal in the range of 500 kHz to 1 MHz. For low-noise operation, the converter can be operated in the PWM mode and the internal antiringing switch reduces noise and EMI. In the shutdown mode, the current consumption is reduced to less than 1 µA. The TPS6200x is available in the 10-pin (DGS) microsmall outline package (MSOP) and operates over a free-air temperature range of –40°C to 85°C. MSOP (DGS) PACKAGE (TOP VIEW) VIN FC GND PG FB 1 10 2 9 3 8 4 7 5 6 PGND L EN SYNC ILIM AVAILABLE OPTIONS TA – 40°C to 85°C VOLTAGE OPTIONS PACKAGE MICROSMALL OUTLINE (DGS)† MARKING DGS Adjustable TPS62000DGS AIH 0.9 V TPS62001DGS AII 1V TPS62002DGS AIJ 1.2 V TPS62003DGS AIK 1.5 V TPS62004DGS AIL 1.8 V TPS62005DGS AIM 1.9 V TPS62008DGS AJI 2.5 V TPS62006DGS AIN 3.3 V TPS62007DGS AIO † The DGS package is available taped and reeled. Add R suffix to device type (e.g. TPS62000DGSR) to order quantities of 2500 devices per reel. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 functional block diagram PG FC (See Note B) VIN 10 Ω Undervoltage Lockout Bias Supply EN + _ R1 PFM/PWM Comparator _ + Soft Start + PFM/PWM Control Logic Current Limit Logic Driver Shoot-Through Logic N-Channel Power MOSFET EN + _ L Compensation R2 R1 + R2 ≈ 1 MΩ P-Channel Power MOSFET PFM/PWM Mode Select Error Amplifier _ FB (See Note A) Current Sense Slope Compensation Power Good Vref = 0.45 V Sync + Oscillator Load Comparator + _ Current Sense + Offset PGND Antiringing FB GND SYNC ILIM NOTES: A. The adjustable output voltage version does not use the internal feedback resistor divider. The FB pin is directly connected to the error amplifier. B. Do not connect the FC pin to an external power source POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION EN 8 I Enable. A logic high enables the converter, logic low forces the device into shutdown mode reducing the supply current to less than 1 µA. FB 5 I Feedback pin for the fixed output voltage option. For the adjustable version an external resistive divider is connected to this pin. The internal voltage divider is disabled for the adjustable version. FC 2 Supply bypass pin. A 0.1 µF coupling capacitor should be connected as close as possible to this pin for good high frequency input voltage supply filtering. GND 3 Ground ILIM 6 I Switch current limit. Connect ILIM to GND to set the switch current limit to typically 600 mA, or connect this pin to VIN to set the current limit to typically 1200 mA. L 9 I/O Connect the inductor to this pin. This pin is the switch pin connected to the drain of the internal power MOSFETS. PG 4 O Power good comparator output. This is an open-drain output. A pullup resistor should be connected between PG and VO. The output goes active high when the output voltage is greater than 94.5% of the nominal value. PGND 10 SYNC 7 I Input for synchronization to external clock signal. Synchronizes the converter switching frequency to an external clock signal with CMOS level: SYNC = HIGH: Low-noise mode enabled, fixed frequency PWM operation is forced SYNC = LOW (GND): Power save mode enabled, PFM/PWM mode enabled. VIN 1 I Supply voltage input Power ground. Connect all power grounds to this pin. detailed description operation The TPS6200x is a step down converter operating in a current mode PFM/PWM scheme with a typical switching frequency of 750 kHz. At moderate to heavy loads, the converter operates in the pulse width modulation (PWM) and at light loads the converter enters a power save mode (pulse frequency modulation) to keep the efficiency high. In the PWM mode operation, the part operates at a fixed frequency of 750 kHz. At the beginning of each clock cycle, the high side P-channel MOSFET is turned on. The current in the inductor ramps up and is sensed via an internal circuit. The high side switch is turned off when the sensed current causes the PFM/PWM comparator to trip when the output voltage is in regulation or when the inductor current reaches the current limit (set by ILIM). After a minimum dead time preventing shoot through current, the low side N-channel MOSFET is turned on and the current ramps down again. As the clock cycle is completed, the low side switch is turned off and the next clock cycle starts. In discontinuous conduction mode (DCM), the inductor current ramps to zero before the end of each clock cycle. In order to increase the efficiency the load comparator turns off the low side MOSFET before the inductor current becomes negative. This prevents reverse current flowing from the output capacitor through the inductor and low side MOSFET to ground that would cause additional losses. As the load current decreases and the peak inductor current does not reach the power save mode threshold of typically 120 mA for more than 15 clock cycles, the converter enters a pulse frequency modulation (PFM) mode. In the PFM mode, the converter operates with: D D D 4 Variable frequency Constant peak current that reduces switching losses Quiescent current at a minimum POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 operation (continued) Thus maintaining the highest efficiency at light load currents. In this mode, the output voltage is monitored with the error amplifier. As soon as the output voltage falls below the nominal value, the high side switch is turned on and the inductor current ramps up. When the inductor current reaches the peak current of typical: 150 mA + 50 mA/V x (VI – VO), the high side switch turns off and the low side switch turns on. As the inductor current ramps down, the low side switch is turned off before the inductor current becomes negative which completes the cycle. When the output voltage falls below the nominal voltage again, the next cycle is started. The converter enters the PWM mode again as soon as the output voltage can not be maintained with the typical peak inductor current in the PFM mode. The control loop is internally compensated reducing the amount of external components. The switch current is internally sensed and the maximum current limit can be set to typical 600 mA by connecting ILIM to ground or to typically 1.2 A connecting ILIM to VIN. 100% duty cycle operation As the input voltage approaches the output voltage and the duty cycle exceeds typical 95%, the converter turns the P-channel high side switch continuously on. In this mode, the output voltage is equal to the input voltage minus the voltage drop across the P-channel MOSFET. synchronization, power save mode and forced PWM mode If no clock signal is applied, the converter operates with a typical switching frequency of 750 kHz. It is possible to synchronize the converter to an external clock within a frequency range from 500 kHz to 1000 kHz. The device automatically detects the rising edge of the first clock and is synchronizes immediately to the external clock. If the clock signal is stopped, the converter automatically switches back to the internal clock and continues operation without interruption. The switch over is initiated if no rising edge on the SYNC pin is detected for a duration of four clock cycles. Therefore, the maximum delay time can be 8 µs in case the internal clock has a minimum frequency of 500 kHz. In case the device is synchronized to an external clock, the power save mode is disabled and the device stays in forced PWM mode. Connecting the SYNC pin to the GND pin enables the power save mode. The converter operates in the PWM mode at moderate to heavy loads and in the PFM mode during light loads maintaining high efficiency over a wide load current range. Connecting the SYNC pin to the VIN pin forces the converter to operate permanently in the PWM mode even at light or no load currents. The advantage is the converter operates with a fixed switching frequency that allows simple filtering of the switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power save mode during light loads (see Figure 1). It is possible to switch from forced PWM mode to the power save mode during operation. The flexible configuration of the SYNC pin during operation of the device allows efficient power management by adjusting the operation of the TPS6200x to the specific system requirements. low noise antiringing switch An antiringing switch is implemented in order to reduce the EMI radiated from the converter during discontinuous conduction mode (DCM). In DCM, the inductor current ramps to zero before the end of each switching period. The internal load comparator turns off the low side switch at that instant thus preventing the current flowing backward through the inductance which increases the efficiency. An antiringing switch across the inductor prevents parasitic oscillation caused by the residual energy stored in the inductance (see Figure 12). NOTE: The antiringing switch is only activated in the fixed output voltage versions. It is not enabled for the adjustable output voltage version TPS62000. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 detailed description (continued) soft start As the enable pin (EN) goes high, the soft-start function generates an internal voltage ramp. This causes the start-up current to slowly rise preventing output voltage overshoot and high inrush currents. The soft-start duration is typical 1 ms (see Figure 13). When the soft-start function is completed, the error amplifier is connected directly to the internal voltage reference. enable Logic low on EN forces the TPS6200x into shutdown. In shutdown, the power switch, drivers, voltage reference, oscillator, and all other functions are turned off. The supply current is reduced to less than 1 µA in the shutdown mode. undervoltage lockout An undervoltage lockout circuit provides the save operation of the device. It prevents the converter from turning on when the voltage on VIN is less than typically 1.6 V power good comparator The power good (PG) comparator has an open drain output capable of sinking typically 10 µA. The PG is only active when the device is enabled (EN = high). When the device is disabled (EN = low), the PG pin is high impedance. The PG output is only valid after a 100 µs delay after the device is enabled and the supply voltage is greater than 1.2 V. This is only important in cases where the pullup resistor of the PG pin is connected to an external voltage source which might cause an initial spike (false high signal) within the first 100 µs after the input voltage exceeds 1.2 V. This initial spike can be filtered with a small R-C filter to avoid false power good signals during start-up. If the PG pin is connected to the output of the TPS62000 with a pullup resistor, no initial spike (false high signal) occurs and no precautions have to be taken during start-up. The PG pin becomes active high when the output voltage exceeds typically 94.5% of its nominal value. Leave the PG pin unconnected when not used. no load operation In case the converter operates in the forced PWM mode and there is no load connected to the output, the converter will regulate the output voltage by allowing the inductor current to reverse for a short period of time. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltages on pin VIN and FC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V Voltages on pins EN, ILIM, SYNC, PG, FB, L (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VIN + 0.3 V Peak switch current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 A Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature (soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network ground terminal. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING 10 pin MSOP 555 mW 5.56 mW/°C 305 mW 221 mW NOTE: The thermal resistance junction to ambient of the 10-pin MSOP is 180°C/W. The device does not run into thermal limitations provided it is operated within the specified range. recommended operating conditions MIN Supply voltage, VI TYP MAX UNIT 2 5.5 V 0.8 V Output current for 3-cell operation, IO (VI ≥ 2.5 V; L = 10 µH, f = 750 kHz) VI 600 mA Output current for 2-cell operation, IO (VI ≥ 2 V; L = 10 µH, f = 750 kHz) 200 mA Output voltage range for adjustable output voltage version, VO Inductor, L (see Note 2) µH 10 Input capacitor, Ci (see Note 2) 10 µF Output capacitor, Co (see Note 2) VO ≥ 1.8 V) 10 µF Output capacitor, Co (see Note 2) VO < 1.8 V) µF 47 Operating ambient temperature, TA Operating junction temperature, TJ NOTE 2: Refer to application section for further information. -40 85 °C -40 125 °C electrical characteristics over recommended operating free-air temperature range, VI = 3.6 V, VO = 2.5 V, IO = 300 mA, EN = VIN, ILIM = VIN, TA = –40°C to 85°C (unless otherwise noted) supply current PARAMETER VI I(Q) I(SD) Input voltage range TEST CONDITIONS IO = 0 mA to 600 mA IO = 0 mA to 200 mA Operating quiescent current Shutdown current MIN TYP MAX 2.5 5.5 2 5.5 IO = 0 mA, SYNC = GND (PFM-mode enabled) EN = GND UNIT V 50 75 µA 0.1 1 µA TYP MAX enable PARAMETER VIH VIL EN high-level input voltage Ilkg V(UVLO) EN input leakage current TEST CONDITIONS MIN 1.3 V EN low level input voltage EN = GND or VIN Undervoltage lockout threshold 1.2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT 0.4 V 0.01 0.1 µA 1.6 1.95 V 7 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 electrical characteristics over recommended operating free-air temperature range, VI = 3.6 V, VO = 2.5 V, IO = 300 mA, EN = VIN, ILIM = VIN, TA = –40°C to 85°C (unless otherwise noted) (continued) power switch and current limit PARAMETER TEST CONDITIONS VI = VGS = 3.6 V, VI = VGS = 2 V, P channel MOSFET on-resistance P-channel on resistance P-channel leakage current rDS(on) DS( ) VDS = 5.5 V VI = VGS = 3.6 V, N channel MOSFET on-resistance N-channel on resistance VI = VGS = 2 V, VDS = 5.5 V N-channel leakage current I(LIM) P channel current limit P-channel VIH VIL ILIM high-level input voltage Ilkg ILIM input leakage current I = 200 mA MIN TYP MAX 200 280 410 I = 200 mA 480 1 IO = 200 mA IO = 200 mA 200 280 410 500 1 2.5 V ≤ VI ≤ 5.5 V, ILIM = VIN 800 1200 1600 2 V ≤ VI ≤ 5.5 V, ILIM = GND 390 600 900 1.3 UNIT mΩ µA mΩ µA mA V ILIM low-level input voltage 0.4 V 0.01 0.1 µA MIN TYP MAX UNIT 88% VO 92% VO 94% VO V ILIM = GND or VIN power good output (see Note 3) PARAMETER V(PG) TEST CONDITIONS Power good threshold Feedback voltage falling Power good hysteresis VOL Ilkg 2.5% VO V(FB) = 0.8 × VO nominal, I(sink) = 10 µA V(FB) = VO nominal PG output low voltage PG output leakage current Minimum supply voltage for valid power good signal V 0.3 0.01 V 1 1.2 µA V NOTE 3: Power good is not valid for the first 100 µs after EN goes high. Please refer to the application section for more information. oscillator PARAMETER fs f(SYNC) Oscillator frequency VIH VIL SYNC high level input voltage Synchronization range CMOS-logic clock signal on SYNC pin MIN TYP MAX UNIT 500 750 1000 kHz 1000 kHz 500 1.3 V SYNC low level input voltage Ilkg SYNC input leakage current Duty cycle of external clock signal 8 TEST CONDITIONS SYNC = GND or VIN 0.01 20% POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0.4 V 0.1 µA 60% TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 electrical characteristics over recommended operating free-air temperature range, VI = 3.6 V, VO = 2.5 V, IO = 300 mA, EN = VIN, ILIM = VIN, TA = –40°C to 85°C (unless otherwise noted) (continued) output PARAMETER VO Vref VO Adjustable output voltage range TPS62000 Reference voltage TPS6200x Fixed output voltage (see Note 4) Line regulation Load regulation η TEST CONDITIONS Efficiency Start-up time MIN TYP 0.8 MAX 5.5 0.45 TPS62000 adjustable –3% 4% –3% 3% TPS62001 0.9 V VI = 2.5 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA 10 mA < IO ≤ 600 mA –3% 4% –3% 3% TPS62002 1V VI = 2.5 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA 10 mA < IO ≤ 600 mA –3% 4% –3% 3% TPS62003 1.2 V VI = 2.5 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA 10 mA < IO ≤ 600 mA –3% 4% –3% 3% TPS62004 1.5 V VI = 2.5 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA 10 mA < IO ≤ 600 mA –3% 4% –3% 3% TPS62005 1.8 V VI = 2.5 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA 10 mA < IO ≤ 600 mA –3% 4% –3% 3% TPS62008 1.9 V VI = 2.5 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA 10 mA < IO ≤ 600 mA –3% 4% –3% 3% TPS62006 2.5 V VI = 2.7 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA 10 mA < IO ≤ 600 mA –3% 4% –3% 3% TPS62007 3.3 V VI = 3.6 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA 10 mA < IO ≤ 600 mA –3% 4% –3% 3% 0.05 VI = 5.5 V; IO = 10 mA to 600 mA VI = 5 V; VO = 3.3 V; IO = 300 mA VI = 3.6 V; VO = 2.5 V; IO = 200 mA IO = 0 mA, time from active EN to VO V V VI = 2.5 V to 5.5 V; 0 mA ≤ IO ≤ 600 mA 10 mA < IO ≤ 600 mA VI = VO + 0.5 V (min. 2 V) to 5.5 V, IO = 10 mA UNIT V %/V 0.6% 95% 0.4 2 ms NOTE 4: The output voltage accuracy includes line and load regulation over the full temperature range, TA = –40°C to 85°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 TYPICAL CHARACTERISTICS Table of Graphs FIGURE η Efficiency vs Load current 3, 4, 5 V(drop) Dropout voltage vs Load current 6 vs Input voltage (power save mode) 7 vs Input voltage (forced PWM) 8 IQ Operating quiescent current fosc Oscillator frequency vs Free-air temperature 9 Load transient response VO 10 Line transient response 11 Power save mode operation 12 Start-up vs Time 13 Output voltage vs Load current 14 EFFICIENCY vs LOAD CURRENT 100 EFFICIENCY vs LOAD CURRENT 100 VO = 3.3 V 90 VO = 2.5 V 90 70 Efficiency – % Efficiency – % VI = 3.6 V 80 VI = 5 V 80 70 VI = 5 V 60 60 50 50 40 0.1 1 10 100 IO – Load Current – mA 1000 40 0.1 Figure 3 10 VI = 3.6 V 1 10 100 IO – Load Current – mA Figure 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1000 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 TYPICAL CHARACTERISTICS EFFICIENCY vs LOAD CURRENT DROPOUT VOLTAGE vs LOAD CURRENT 300 100 VO = 1.8 V 250 Dropout Voltage – mV Efficiency – % 90 80 VI = 3.6 V 70 VI = 5 V 60 50 200 VO = 2.5 V 150 VO = 3.3 V 100 50 40 0.1 0 1 10 100 IO – Load Current – mA 1000 0 100 200 300 400 IO – Load Current – mA Figure 5 OPERATING QUIESCENT CURRENT vs INPUT VOLTAGE (FORCED PWM) 4000 Power-Save Mode, SYNC = Low I (Q)– Operating Quescent Current – µ A I (Q)– Operating Quescent Current – µ A 60 55 TA = 80°C TA = 20°C 45 TA =–40°C 40 35 30 2 2.5 3 3.5 600 Figure 6 OPERATING QUIESCENT CURRENT vs INPUT VOLTAGE (POWER SAVE MODE) 50 500 4 4.5 5 5.5 VI – Input Voltage (Power Save Mode) – V Forced PWM, SYNC = High 3500 TA = 80°C TA = 20°C 3000 2500 TA =–40°C 2000 1500 1000 2 2.5 3 3.5 4 4.5 5 VI – Input Voltage (Forced PWM) – V Figure 7 5.5 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY vs FREE-AIR TEMPERATURE LOAD TRANSIENT RESPONSE I(Load) = 60 mA to 540 mA, VI = 3.6 V, VO = 2.5 V f – Oscillator Frequency – kHz 790 770 750 VO 25 mV/div VI = 5 V VI = 3.6 V 730 710 VI = 2 V 690 IO 500 mA/div 670 650 –40 –20 0 20 40 60 TA – Free-Air Temperature – °C 80 200 µs/div Figure 9 Figure 10 LINE TRANSIENT RESPONSE POWER SAVE MODE OPERATION VL 2 V/div VI 3.6 V to 4.6 V VO 100 mV/div IL 200 mA/div 400 µs/div 10 µs/div Figure 11 12 Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 TYPICAL CHARACTERISTICS START-UP vs TIME EN 2 V/div VO 1 V/div Power Good 1 V/div II 200 mA/div 250 µs/div Figure 13 OUTPUT VOLTAGE vs LOAD CURRENT 2.55 2.54 VO – Output Voltage – V 2.53 2.52 2.51 2.50 2.49 2.48 2.47 2.46 2.45 0 100 200 300 400 500 600 IO – Load Current – mA Figure 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 APPLICATION INFORMATION adjustable output voltage version When the adjustable output voltage version (TPS62000DGS) is used, the output voltage is set by the external resistor divider (see Figure 15). ǒ) Ǔ The output voltage is calculated as: V O + 0.45 V 1 R1 R2 With R1 + R2 ≤ 1 MΩ R1 + R2 should not be greater than 1 MΩ because of stability reasons. For stability reasons, a small bypass capacitor (Cff) is required in parallel to the upper feedback resistor, refer to Figure 15. The bypass capacitor value can be calculated as: 1 + 2π x 30000 for C o t 47 µF x R1 1 C (ff) + for C o ≥ 47 µF 2π x 5000 x R1 C (ff) R1 is the upper resistor of the voltage divider. For C(ff), choose a value which comes closest to the computed result. VI = 2.7 V to 5.5 V 1 VIN L 9 L1 = 10 µH VO = 2.5 V/600 mA R3 = 320 kΩ + Ci = 10 µF 8 EN FB 5 R1 = 820 kΩ TPS62000 6 C(ff) = 6.8 pF 4 ILIM PG + PG Co = 10 µF 7 SYNC GND 3 10 R2 = 180 kΩ PGND FC 2 C3 = 0.1 µF Figure 15. Typical Application Circuit for Adjustable Output Voltage Option inductor selection A 10 µH minimum output inductor is used with the TPS6200x. Values larger than 22 µH or smaller than 10 µH may cause stability problems because of the internal compensation of the regulator. For output voltages greater than 1.8 V, a 22 µH inductance might be used in order to improve the efficiency of the converter. After choosing the inductor value of typically 10 µH, two additional inductor parameters should be considered: first the current rating of the inductor and second the dc resistance. The dc resistance of the inductance influences directly the efficiency of the converter. Therefore, an inductor with lowest dc resistance should be selected for highest efficiency. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 APPLICATION INFORMATION inductor selection (continued) In order to avoid saturation of the inductor, the inductor should be rated at least for the maximum output current plus the inductor ripple current which is calculated as: DIL + VO Where: V 1– O V I L ƒ I L(max) + IO(max) ) D2IL ƒ = Switching frequency (750 kHz typical) L = Inductor value ∆IL = Peak-to-peak inductor ripple current IL(max) = Maximum inductor current The highest inductor current occurs at maximum VI. A more conservative approach is to select the inductor current rating just for the maximum switch current of the TPS6200x which is 1.6 A with ILIM = VIN and 900 mA with ILIM = GND. See table 1 for recommended inductors. Table 1. Recommended Inductors OUTPUT CURRENT INDUCTOR VALUE 10 µH 0 mA to 600 mA 10 µH 0 mA to 300 mA COMPONENT SUPPLIER COMMENTS Coilcraft DO3316P-103 Coilcraft DT3316P-103 Sumida CDR63B-100 Sumida CDRH5D28-100 High efficiency Coilcraft DO1608C-100 Sumida CDRH4D28-100 Smallest solution Coilcraft DS1608C-103 High efficiency muRata LQH4C100K04 Smallest solution output capacitor selection For best performance, a low ESR output capacitor is needed. At output voltages greater than 1.8 V, ceramic output capacitors can be used to show the best performance. Output voltages below 1.8 V require a larger output capacitor and ESR value to improve the performance and stability of the converter. Capacitor Selection OUTPUT VOLTAGE RANGE OUTPUT CAPACITOR OUTPUT CAPACITOR ESR 1.8 V ≤ VI ≤ 5.5 V Co ≥ 10 µF ESR ≤ 120 mΩ 0.8 V ≤ VI < 1.8 V Co ≥ 47 µF ESR > 50 mΩ See Table 2 for recommended capacitors. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 APPLICATION INFORMATION output capacitor selection (continued) If an output capacitor is selected with an ESR value ≤ 120 mΩ, its RMS ripple current rating always meets the application requirements. Just for completeness, the RMS ripple current is calculated as: I RMS(C ) o V 1– O V I L ƒ + VO 1 2 Ǹ3 The overall output ripple voltage is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charge and discharging the output capacitor: DVO + VO V 1– O V I L ƒ ǒ 8 1 Co ƒ Ǔ ) ESR Where the highest output voltage ripple occurs at the highest input voltage VI. Table 2. Recommended Capacitors CAPACITOR VALUE ESR/mΩ 10 µF 50 Taiyo Yuden JMK316BJ106KL COMPONENT SUPPLIER Ceramic COMMENTS 47 µF 100 Sanyo 6TPA47M POSCAP 68 µF 100 Spraque 594D686X0010C2T Tantalum input capacitor selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. The input capacitor should have a minimum value of 10 µF and can be increased without any limit for better input voltage filtering. ǸǒǓ The input capacitor should be rated for the maximum input ripple current calculated as: I RMS + I O(max) V O V I V 1– O V I The worst case RMS ripple current occurs at D = 0.5 and is calculated as: I RMS + I2O . Ceramic capacitor show a good performance because of their low ESR value, and they are less sensitive against voltage transients compared to tantalum capacitors. Place the input capacitor as close as possible to the input pin of the IC for best performance. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 APPLICATION INFORMATION layout considerations As for all switching power supplies, the layout is an important step in the design especially at high peak currents and switching frequencies. If the layout is not carefully done, the regulator might show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current paths as indicted in bold in Figure 16. The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor. Place the bypass capacitor, C3, as close as possible to the FC pin. The analog ground, GND, and the power ground, PGND, need to be separated. Use a common ground node as shown in Figure 16 to minimize the effects of ground noise. 1 VI VIN L EN FB L1 9 VO + 8 Ci R3 5 R1 TPS62000 6 C(ff) 4 ILIM + PG PG Co 7 R2 10 SYNC GND PGND FC 3 C3 2 Figure 16. Layout Diagram typical application VI = 5 V C1 10 µF 1 8 VIN L EN FB 9 7 ILIM SYNC GND 3 VO = 3.3 V/600 mA 5 TPS62007DGS 6 L1 22 µH 680 kΩ PGND PG FC C2 10 µF 10 4 Power Good 2 L1: Sumdia CDRH5D28-220 C1, C2: 10 µF Ceramic Taiyo Yuden JMK316BJ106KL C3: 0.1 µF Ceramic C3 0.1 µF Figure 17. Standard 5 V to 3.3 V/600 mA Conversion; High Efficiency POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 APPLICATION INFORMATION typical application (continued) 1 VI = 2.7 V to 4.2 V C1 10 µF 8 VIN L EN FB 9 7 ILIM 470 kΩ PGND SYNC GND 3 VO = 2.5 V/600 mA 5 TPS62006DGS 6 L1 10 µH PG FC C2 10 µF 10 4 Power Good L1: C1,C2: 2 C3 0.1 µF C3: Sumdia CDRH5D28-100 10 µF Ceramic Taiyo Yuden JMK316BJ106KL 0.1 µF Ceramic Figure 18. Single Li-on to 2.5 V/600 mA Using Ceramic Capacitors Only VI = 2.5 V to 4.2 V C1 10 µF 1 8 VIN L EN FB 9 7 ILIM PGND SYNC GND 3 PG FC VO = 1.8 V/300 mA 5 C2 10 µF TPS62005DGS 6 L1 10 µH 10 4 L1: C1,C2: 2 C3 0.1 µF C3: Murata LQH4C100K04 10 µF Ceramic Taiyo Yuden JMK316BJ106KL 0.1 µF Ceramic NOTE: For low noise operation connect SYNC to VIN Figure 19. Single Li-on to 1.8 V/300 mA; Smallest Solution Size 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 APPLICATION INFORMATION typical application (continued) 1 VI = 2 V to 3.8 V C1 10 µF 8 VIN L EN FB L1 10 µH 9 VO = 1.2 V/200 mA 5 C2 47 µF TPS62003 6 7 ILIM 10 PGND SYNC GND 4 PG FC 3 + L1: C1: 2 C3 0.1 µF C2: C3: Murata LQH4C100K04 10 µF Ceramic Taiyo Yuden JMK316BJ106KL Sanyo 6TPA47M 0.1 µF Ceramic Figure 20. Dual Cell NiMH or NiCd to 1.2 V/200 mA; Smallest Solution Size VI = 2.5 V to 5.5 V C1 10 µF 1 8 VIN L EN FB 9 L1 10 µH R4 5 820 kΩ VO = 1.1 V or 1.5 V/600 mA R1 470 kΩ TPS62000 6 7 ILIM SYNC GND 3 PG PGND FC 4 PG† C(ff)ĕ 150 pF C2 47 µF + 10 R2 326 kΩ R3 524 kΩ 2 C3 0.1 µF L1: C1: Sumida CDRH5D28-100 Q1 10 µF Ceramic Taiyo Yuden BSS138 JMK316BJ106KL C2: Sanyo 6TPA47M C3: 0.1 µF Ceramic † Use a small R-C filter to filter wrong reset signals during output voltage transitions. ‡ A large value is used for C(ff) to compensate for the parasitic capacitance introduced into the regulation loop by Q1. Logic Input Hi VO = 1.5 V Low VO = 1.1 V Figure 21. Dynamic Output Voltage Programming As Used in Low Power DSP Applications POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TPS62000, TPS62001, TPS62002, TPS62003 TPS62004, TPS62005, TPS62006, TPS62007, TPS62008 HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER SLVS294B – SEPTEMBER 2000 – REVISED JUNE 2002 MECHANICAL DATA DGS (S-PDSO-G10) PLASTIC SMALL-OUTLINE PACKAGE 0,27 0,17 0,50 10 0,25 M 6 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°– 6° 5 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073272/A 03/98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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