Feb 1999 Generating Low Cost, Low Noise, Dual-Voltage Supplies

DESIGN IDEAS
Generating Low Cost, Low Noise,
Dual-Voltage Supplies
by Ajmal Godil
Some sensitive electronic applications, such as telecommunication and
data acquisition, require both 5V and
–5V low noise supplies, which may
have to be generated from a single
high voltage positive supply. The circuit in Figure 1 shows a cost-effective
way to generate 5V and –5V from a
single 10V–28V supply by using the
low noise LT1777 and a few off-theshelf components.
The LT1777 is a step-down regulator specially designed for low noise
applications. In order to achieve low
VIN
10V–28V
4
10
3
SHDN
14
100pF
VCC
VSW
VIN
VD
SHDN
VC
FB
LT1777
GND
GND
12
R3
22k
7
SYNC
SGND
GND
GND
6
continued on page 29
L1B
200µH
LSENSE
0.47µH
+VOUT
5V*
5
1
8
D1
MBRS1100
12
C2**
4.7µF
+
–VOUT
–5V*
C8
1µF
10V
Table 1. Allowable load current on the –5V
supply vs input voltage and 5V load current
5V ILOAD (mA)
Maximum allowed
current on the
–5V supply (mA)
VIN = 10V
50
40
100
70
200
110
300
130
350
140
VIN = 18V
50
90
100
150
200
200
300
230
350
200
VIN = 28V
D2 MBRS1100
L1A
200µH
L1A/B: COILTRONICS CTX200-4
(561) 241-7876
LSENSE: GOWANDA SML32-470K
(716) 532-2234
C3, C7: AVX TPSD107M010R0065
(803) 946-0362
C6: 63CV1D0BS
C2: AVX 1206YG475
R1
36.5k
1%
R2
12.1k
1%
9
C4
100pF
C5
2200pF
C1
1µF
10V
C3
100µF
10V
13
+
C6
100µF
63V
noise, the LT1777 is equipped with
dI/dt limiting circuitry, which is programmed via a small external inductor
in the power path. It also contains
internal circuitry to limit the dV/dt
turn-on and turn-off ramp rates. Figure 2 shows the VSW node voltage and
the VSW node current for the low noise
LT1777. Figure 3 shows the VSW node
voltage and VSW node current for the
high voltage LT1676 buck regulator
under the same test conditions. It can
be seen from Figures 2 and 3 that the
C7
100µF
10V
* SEE TABLE 1 FOR RELATIONSHIP BETWEEN LOAD
ON +VOUT AND MAXIMUM CURRENT ON –VOUT.
** THIS IS A CERAMIC CAP, BUT A
TANTALUM CAP COULD ALSO BE USED
50
130
100
180
200
260
300
270
350
230
Figure 1. This cost-effective supply generates ±5V from a 10V–28V input.
VSW NODE
VOLTAGE
VSW NODE
VOLTAGE
10V/DIV
10V/DIV
VSW NODE
CURRENT
VSW NODE
CURRENT
200mA/DIV
200mA/DIV
500ns/DIV
Figure 2. VSW node voltage and node current for the
LT1777
Linear Technology Magazine • February 1999
500ns/DIV
Figure 3. VSW node voltage and node current for the
LT1676
27
DESIGN IDEAS
VIN
11V–15V
VIN
12V
8
+
10µF
+
C1*
10µF
2
GND
CAP+
8
6.8µF
V+
3
VOUT
5V/200mA
6
VREF
LT1054CS8
1
CAP–
4
FB/SHDN
R1
39.2k
R3*
200k
VOUT
5
+
2
C1
33µF
V+
CAP+
VREF
U1 LT1054CS8
10µF
D2
D1
330pF
C2
33µF
4
Figure 3. This switched capacitor regulator doubles the current
between the input and the output, increasing efficiency and
eliminating the need for a heat sink.
1
3
86.6k
C3
33µF
CAP–
VOUT
5
C1, C2, C3: AVX TAJB336M010R
C4: AVX TAJB685M025R
D1, D2, D3: MOTOROLA MBR0520LT1
Q1: IR IRLML2402
*FOR 3.3V/200mA, SET R4 = 147k, PUT 6.2Ω IN SERIES
WITH C1 AND PRELOAD WITH R4 = 2.2k
100mA. (Unfortunately, there is too
much voltage loss to regulate to –5V
from a 12V source.) Note that many
negative supplies will power loads
that can pull the output above ground
(op amp circuits in particular); Q1
prevents such a load from pulling
U1’s VOUT pin above its ground pin.
20.0k
FB/SHDN
D3
GND
R4*
33k
6
VOUT
–4V/100mA
Q1
Figure 5. This circuit converts 12V to –4V. Only 63mA of input current
is required for 100mA of output current.
Because most of U1’s operating
current flows out of its ground pin,
the input current to this circuit is a
bit more than one-half of the output
current. While delivering 100mA, the
input from 12V was measured at
64mA, resulting in 53% efficiency.
One alternative, a switched capacitor
inverter followed by a linear regulator, would be 33% efficient at best and
power dissipation would be 0.8W. This
circuit dissipates only 0.35W, allowing this all–surface mount circuit to
run cool.
VIN
VIN
1
1
3
3
2
2
4
4
VOUT
VOUT
CURRENT FLOW
Figure 4. Adding three diodes to a switched capacitor inverter doubles the current between the input and the output.
LT1777, continued from page 27
switch node voltage and current waveforms for the LT1777 are more
controlled and rise and fall more slowly
than those of the LT1676 regulator.
By slowing down the sharp edges
during turn-on and turn-off for the
power switch, conducted and radiated EMI are reduced.
The circuit in Figure 1 shows three
inductors: L1A, L1B and LSENSE. L1A
Linear Technology Magazine • February 1999
and L1B are two windings on a single
core to generate ±5V. C2 has been
added to minimize coupling mismatches between the two windings
(L1A and L1B); this forces the winding potentials to be equal and improves
cross-regulation. This creates the dual
SEPIC (single-ended primary inductance converter) topology. LSENSE is a
user-selectable sense inductor to pro-
gram the dI/dt ramp rate (see the
LT1777 Data Sheet for more information). Table 1 summarizes the
allowable load current on the –5V
supply as a function of input supply
voltage and the load current on the
5V supply. Note that 5V and –5V
supplies are allowed to droop by 0.25V,
which corresponds to 5% load
regulation.
29