ICS97U870 Integrated Circuit Systems, Inc. Advance Information 1.8V Wide Range Frequency Clock Driver Recommended Application: Custom On-Board Memory / Zero Delay Board Fan Out Pin Configuration 1 2 3 4 5 6 A Product Description/Features: • ICS Universal Input: Supports multiple switching standards • Low skew, low jitter PLL clock driver • 1 to 10 differential clock distribution (SSTL_18 outputs) • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs B C D E F G H J K Switching Characteristics: • Period jitter: 40ps • Half-period jitter: 60ps • CYCLE - CYCLE jitter 40ps • OUTPUT - OUTPUT skew: 40ps 52-Ball BGA A B C D E F G H J K 1 CLKT1 CLKC1 CLKC2 CLKT2 CLK_INT CLK_INC AGND AVDD CLKT3 CLKC3 2 CLKT0 GND GND VDDQ VDDQ VDDQ VDDQ GND GND CLKC4 3 CLKC0 GND NB VDDQ NB NB VDDQ NB GND CLKT4 4 CLKC5 GND NB VDDQ NB NB VDDQ NB GND CLKT9 5 CLKT5 GND GND OS VDDQ OE VDDQ GND GND CLKC9 6 CLKT6 CLKC6 CLKC7 CLKT7 FB_INT FB_INC FB_OUTC FB_OUTT CLKT8 CLKC8 Block Diagram Powerdown Control and Test Logic OS AVDD LD* or OE CLKC0 LD*, OS or OE CLKT1 CLKC1 CLKT1 CLKT0 CLKC0 VDDQ CLKC5 CLKT5 CLKT6 CLKC6 VDDQ CLKT0 OE CLKC1 40 31 CLKT2 PLL bypass CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5 CLK_INT CLKT6 CLK_INC CLKC6 10K-100k PLL GND FB_INT FB_INC * The Logic Detect (LD) powers down the device when a logic low is applied to both CLK_INT and CLK_INC. CLKT7 VDDQ CLKC2 CLKT2 CLK_INT CLK_INC VDDQ AGND AVDD VDDQ GND 30 1 ICS97U870 10 21 CLKC7 CLKT7 VDDQ FB_INT FB_INC FB_OUTC FB_OUTT VDDQ OE OS CLKC7 11 CLKT8 CLKC8 CLKT9 20 CLKT3 CLKC3 CLKC4 CLKT4 VDDQ CLKT9 CLKC9 CLKC8 CLKT8 VDDQ LD* CLKC9 FB_OUTT 40-Pin MLF FB_OUTC 0817—07/07/03 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. ICS97U870 Advance Information Pin Descriptions Te r m i n a l Name Electrical Characteristics Description AGND Analog Ground Ground AVDD A n a l o g p ow e r 1.8 V nominal CLK_INT C l o ck i n p u t w i t h a ( 1 0 K - 1 0 0 K O h m ) p u l l d o w n r e s i s t o r Differential input CLK_INC Complentar y clock input with a (10K-100K Ohm) pulldown resistor Differential input FB_INT Feedback clock input Differential input FB_INC Complementary feedback clock input Differential input FB_OUTT Feedback clock output Differential output FB_OUTC Complementary feedback clock output Differential output OE Output Enable (Asynchronous) LVCMOS input OS Output Select (tied to GND or VDDQ) LVCMOS input GND Ground Ground VDDQ Logic and output power 1.8V nominal CLKT[0:9] Clock outputs Differential outputs CLKC[0:9] Complementary clock outputs Differential outputs NB No ball The PLL clock buffer, ICS97U870, is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and differential data input and output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF. ICS97U870 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB_OUTT/ FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or VDDQ. When OS is high, OE will function as described above. When OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC). When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC) within the specified stabilization time tSTAB. The PLL in ICS97U870 clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]). ICS97U870 is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. ICS97U870 is characterized for operation from 0°C to 70°C. 0817—07/07/03 2 ICS97U870 Advance Information Function Table Inputs Outputs PLL AVDD OE OS CLK_INT CLK_INT CLKT CLKC FB_OUTT FB_OUTC GND H X L H L H L H Bypassed/Off GND H X H L H L H L Bypassed/Off GND L H L H *L(Z) *L(Z) L H Bypassed/Off GND L L H L *L(Z), CLKT7 active *L(Z), CLKC7 active H L Bypassed/Off 1.8V(nom) L H L H *L(Z) *L(Z) L H On 1.8V(nom) L L H L *L(Z), CLKT7 active *L(Z), CLKC7 active H L On 1.8V(nom) H X L H L H L H On 1.8V(nom) H X H L H L H L On 1.8V(nom) X X L L *L(Z) *L(Z) *L(Z) *L(Z) Off 1.8V(nom) X X H H Reser ved *L(Z) means the outputs are disabled to a low stated meeting the IODL limit. 0817—07/07/03 3 ICS97U870 Advance Information Absolute Maximum Ratings Supply Voltage (VDDQ & AVDD) . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 2.5V GND - 0.5V to VDDQ + 0.5V 0°C to +70°C -65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP Input High Current VI = VDDQ or GND IIH (CLK_INT, CLK_INC) Input Low Current (OE, VI = VDDQ or GND IIL OS, FB_INT, FB_INC) Output Disabled Low IODL OE = L, VODL = 100mV 100 Current IDD1.8 CL = 0pf @ 270MHz Operating Supply Current CL = 0pf I DDLD Input Clamp Voltage V IK VDDQ = 1.7V Iin = -18mA V DDQ - 0.2 High-level output IOH = -100 µA V OH voltage IOH = -9 mA 1.1 1.45 IOL=100 µA 0.25 Low-level output voltage V OL IOL=9 mA CIN VI = GND or V DDQ 2 Input Capacitance1 1 COUT VOUT = GND or V DDQ 2 Output Capacitance 1 Guaranteed by design, not 100% tested in production. 0817—07/07/03 4 MAX UNITS ±250 µA ±10 µA µA 300 500 -1.2 0.10 0.6 3 3 mA µA V V V V V pF pF ICS97U870 Advance Information Recommended Operating Condition (see note1) TA = 0 - 70°C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER Supply Voltage Low level input voltage SYMBOL V DDQ, AVDD V IL Low level universal input voltage V IL High level input voltage V IH High level universal input voltage DC input signal voltage (note 2) Differential input signal voltage (note 3) Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) High level output current Low level output current Operating free-air temperature V IH CONDITIONS CLK_INT, CLK_INC, FB_INC, FB_INT OE, OS CLK_INT, CLK_INC universal input mode CLK_INT, CLK_INC, FB_INC, FB_INT OE, OS CLK_INT, CLK_INC universal input mode V IN V ID DC - CLK_INT, CLK_INC, FB_INC, FB_INT AC - CLK_INT, CLK_INC, FB_INC, FB_INT V OX V IX Universal input mode MIN 1.7 0.4 0.35 x VDDQ V 0.35 x VDDQ V VDDQ - 0.4 V 0.65 x VDDQ V 0.8 VDDQ + 0.3 V -0.3 VDDQ + 0.3 V 0.3 VDDQ + 0.4 V 0.6 VDDQ + 0.4 V V DDQ/2 - 0.10 V DDQ/2 + 0.10 V 0.45 (VIH - V IL) VDD/2 0.55 (VIH - V IL) V Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signal must be crossing. 5 UNITS V V 0 0817—07/07/03 MAX 1.9 0.65 x VDDQ IOH IOL TA TYP 1.8 -9 9 mA mA 70 °C ICS97U870 Advance Information Timing Requirements TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN MAX UNITS Max clock frequency freqop 1.8V+0.1V @ 25°C 95 370 MHz Application Frequency Range freqApp 1.8V+0.1V @ 25°C 160 350 MHz Input clock duty cycle dtin 40 60 % 15 µs CLK stabilization TSTAB Switching Characteristics1 TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER Output enable time Output disable time Period jitter Half-period jitter Input slew rate Output clock slew rate Cycle-to-cycle period jitter Dynamic Phase Offset Static Phase Offset Output to Output Skew SSC modulation frequency SSC clock input frequency deviation PLL Loop bandwidth (-3 dB from unity gain) SYMBOL t en t dis t jit (per) t jit(hper) SLr1(i) CONDITION OE to any output OE to any output Input Clock Output Enable (OE), (OS) SLr1(o) t jit(cc+) t jit(cc-) t ( )dyn t SPO2 tskew MIN 30.00 3 40 -40 20 50 40 33 UNITS ns ns ps ps v/ns v/ns v/ns ps ps ps ps ps kHz 0.00 -0.50 % -30 -60 1 0.5 1.5 0 0 -20 -50 2.0 Notes: 1. Switching characteristics guaranteed for application frequency range. 2. Static phase offset shifted by design. 0817—07/07/03 6 TYP 4.73 5.82 2.5 2.5 0 MAX 8 8 30 60 4 MHz ICS97U870 Advance Information Parameter Measurement Information VDD V(CLKC) V(CLKC) ICS97U870 GND Figure 1. IBIS Model Output Load VDD/2 C = 10 pF - GND ICS97U870 R = 10Ω Z = 60Ω SCOPE Z = 50Ω Z = 2.97" Z = 120Ω R = 10Ω Z = 60Ω V(TT) R = 1MΩ C = 1 pF Z = 50Ω Z = 2.97" R = 1MΩ V(TT) C = 1 pF C = 10 pF Note: VTT = GND GND -VDD/2 Figure 2. Output Load Test Circuit YX, FB_OUTC YX, FB_OUTT tc(n) tc(n+1) tjit(cc) = tc(n) ± tc(n+1) Figure 3. Cycle-to-Cycle Jitter 0817—07/07/03 7 ICS97U870 Advance Information Parameter Measurement Information CLK_INC CLK_INT FB_INC FB_INT t( ) n n=N t( ) n 1 t( )= N (N is a large number of samples) Figure 4. Static Phase Offset YX# YX YX, FB_OUTC YX, FB_OUTT t(skew) Figure 5. Output Skew YX, FB_OUTC YX, FB_OUTT tC(n) YX, FB_OUTC YX, FB_OUTT 1 fO t(jit_per) = tc(n) - 1 fO Figure 6. Period Jitter 0817—07/07/03 8 t ( ) n+1 ICS97U870 Advance Information Parameter Measurement Information YX, FB_OUTC YX, FB_OUTT t jit(hper_n+1) t jit(hper_n) 1 fo tjit(hper) = t jit(hper_n) - 1 2xfO Figure 7. Half-Period Jitter 80% 80% VID, VOD Clock Inputs and Outputs 20% 20% tslr tslf Figure 8. Input and Output Slew Rates 0817—07/07/03 9 ICS97U870 Advance Information CK CK FBIN FBIN t( t( ) SSC OFF SSC ON t( ) SSC OFF SSC ON t( )dyn t( )dyn t( )dyn Figure 9. Dynamic Phase Offset 50% VDDQ OE t en Y 50% VDDQ Y Y/ Y OE 50% VDDQ t dis Y 50 % VDDQ Y Figure 10. Time delay between OE and Clock Output (Y, Y) 0817—07/07/03 10 )dyn ICS97U870 Advance Information Figure 11. AVDD Filtering - Place the 2200pF capacitor close to the PLL. - Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one GND via (farthest from PLL). - Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz). 0817—07/07/03 11 ICS97U870 Advance Information 0.40 DIA. ± 0.15 TYP. SYMBOL A A1 A2 D E I J M aaa bbb ccc b e Seating Plane A1 3 2 1 A B C D E F G H I J E TOP VIEW D 0.15 MIN. 1.00 MAX. MIN. 0.86 0.15 0.71 4.40 6.90 0.35 NOM. 0.93 0.18 0.75 4.50 7.00 0.625 REF. 0.575 REF. 6X10 0.40 0.65 TYP. Ordering Information ICS97U870yHT Example: ICS XXXX y H - T Designation for tape and reel packaging Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0817—07/07/03 12 MAX. 1.00 0.21 0.79 4.60 7.10 0.10 0.10 0.10 0.45 ICS97U870 Advance Information Symbol 40-Pin MLF Common Dimensions A - 0.85 A1 0.00 0.01 0.05 A2 - 0.65 0.80 A3 0.20 REF D 6.00 BSC D1 5.75 BSC E 6.00 BSC E1 5.75 BSC Q 0.90 12 P 0.24 0.42 0.60 R 0.13 0.17 0.23 Pitch Varation D e 0.50 BSC N 40 Nd 10 Ne Ordering Information ICS97U870yKT Example: 10 L 0.30 0.40 0.50 b 0.18 0.23 0.30 Q 0.00 0.20 0.45 D2 2.75 2.90 3.05 E2 2.75 2.90 3.05 ICS XXXX y K - T Designation for tape and reel packaging Package Type K = MLF Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0817—07/07/03 13