DATASHEET ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER Description Features The PLL clock buffer, ICS98UAE877A, is designed for a VDDQ of 1.5V, an AVDD of 1.5V and differential data input and output levels. • • • • • • ICS98UAE877A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or VDDQ. When OS is high, OE will function as described above. When OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC). When AVDD is grounded, the PLL is turned off and bypassed for test purposes. Low skew, low jitter PLL clock driver 1 to 10 differential clock distribution Feedback pins for input to output synchronization Spread Spectrum tolerant inputs Auto PD when input signal is at a certain logic state Available in 52-ball VFBGA and a 40-pin MLF Applications • DDR2 Memory Modules / Zero Delay Board Fan Out • Provides complete DDR DIMM solution with IDT74SSTUAE32xxx family Switching Characteristics When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC) within the specified stabilization time tSTAB. • Period jitter: 40ps (DDR2-400/533) 30ps (DDR2-667) • Half-period jitter: 60ps (DDR2-400/533) 50ps (DDR2-667) • Output-Output Skew 40ps (DDR2-400/533) 30ps (DDR2-667) • Cycle-Cycle Jitter 40ps The PLL in ICS98UAE877A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]). ICS98UAE877A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. ICS98UAE877A is available in Commercial Temperature Range (0°C to 70°C) and Industrial Temperature Range (-40°C to +85°C). See Ordering Information for details 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER 1 ICS98UAE877A 7181/2 ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER COMMERCIAL TEMPERATURE GRADE Block Diagram LD or OE OE OS AVDD (1) POWER DOWN AND LD, OS, or OE TEST MODE PLL BYPASS LOGIC LD CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLK_INT CLKT5 CLK_INC CLKC5 10KΩ - 100KΩ PLL CLKT6 CLKC6 FBIN_INT CLKT7 FBIN_INC CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 NOTE: 1. The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK_INT and CLK_INC. 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER 2 FBOUTT FBOUTC ICS98UAE877A 7181/2 ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER COMMERCIAL TEMPERATURE GRADE CLKT5 CLKT6 CLKC6 VDDQ 34 33 32 31 VDDQ CLKC5 35 CLKT0 37 36 6 CLKC0 5 38 4 CLKC1 3 CLKT1 2 39 1 40 Pin Configurations A 23 VDDQ 9 22 OE GND 10 21 OS 20 8 VDDQ 19 AVDD VDDQ FBOUTT CLKT8 AGND 24 17 FBOUTC 7 18 25 CLKC9 6 CLKC8 FB_INC VDDQ 16 26 CLKT9 FB_INT 5 15 27 CLK_INC VDDQ 28 4 CLKT4 3 13 H CLKT2 CLK_INT 14 G CLKT7 VDDQ CLKC4 F 29 11 E 30 2 12 D 1 CLKT3 C CLKC7 VDDQ CLKC2 CLKC3 B J K A B C D E F G H J K 1 CLKT1 CLKC1 CLKC2 CLKT2 CLK_INT CLK_INC AGND AVDD CLKT3 CLKC3 2 CLKT0 GND GND VDDQ VDDQ VDDQ VDDQ GND GND CLKC4 3 CLKC0 GND NB VDDQ NB NB VDDQ NB GND CLKT4 4 CLKC5 GND NB VDDQ NB NB VDDQ NB GND CLKT9 5 CLKT5 GND GND OS VDDQ OE VDDQ GND GND CLKC9 40-PIN MLF TOP VIEW 6 CLKT6 CLKC6 CLKC7 CLKT7 FB_INT FB_INC FB_OUTC FB_OUTT CLKT8 CLKC8 176 BALL BGA TOP VIEW 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER 3 ICS98UAE877A 7181/2 ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER COMMERCIAL TEMPERATURE GRADE Pin Descriptions Terminal Name Description Electrical Characteristics AGND Analog Ground Ground AVDD Analog Power 1.5V Nominal CLK_INT Clock Input with a 10K-100K Ω pulldown resistor Differential Input CLK_INC Complementary Clock Input with a 10K-100K Ω pulldown resistor Differential Input FB_INT Feedback Clock Input Differential Input FB_INC Complementary Feedback clock input Differential Input FB_OUTT Feedback Clock Output Differential Output FB_OUTC Complementary Feedback clock Output Differential Output OE Output Enable (Asynchronous) LVCMOS Input OS Output Select (tied to GND or VDDQ) LVCMOS Input GND Ground VDDQ Logic and Output Power Ground 1.5V Nominal CLKT[0:9] Clock Outputs Differential Outputs CLKC[0:9] Complementary Clock Outputs Differential Outputs NB No Ball 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER 4 ICS98UAE877A 7181/2 ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER COMMERCIAL TEMPERATURE GRADE Function Table Inputs Outputs AVDD OE OS CLK_ INT CLK_ INC CLKT CLKC FB_ OUTT FB_ OUTC PLL GND H X L H L H L H Bypassed/Off GND H X H L H L H L Bypassed/Off GND L H L H L(Z)1 L(Z)1 GND L L H L L(Z), CLKT7 active1 L(Z), CLKC7 active1 H L Bypassed/Off 1.5V (nom) L H L H L(Z)1 L(Z)1 L H On 1.5V (nom) L L H L L(Z), CLKT7 active1 L(Z), CLKC7 active1 H L On 1.5V (nom) H X L H L H L H On 1.5V (nom) H X H L H 1.5V (nom) X X L L 1.5V (nom) X X H H 1 L(Z) Bypassed/Off L 1 H 1 L(Z) L 1 L(Z) L(Z) On 1 Off Reserved Outputs are disabled to a LOW state meeting the IODL limit. Absolute Maximum Ratings Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Item Rating Supply Voltage, (AVDD and VDDQ) -0.5V to 2.5V Logic Inputs GND - 0.5V to VDDQ + 0.5V Ambient Operating Temperature -40°C to +85°C Storage Temperature -65 to +150°C 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER 5 ICS98UAE877A 7181/2 ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER COMMERCIAL TEMPERATURE GRADE DC Electrical Characteristics Over Operating Range Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C, Industrial: TA = -40°C to +85°C; Supply Voltage AVDD/VDDQ = 1.5V ± 0.075V. Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage VIK Test Conditions IOH = -100μA Min. Typ. Max. VDDQ - 2 IOH = -6mA 1.1 IOL = 100μA V 1.45 0.25 Units 0.1 V IOL = 6mA 0.6 Input Clamp Voltage IIN = -18mA -1.2 V IIH Input HIGH Current CLK_INT, CLK_INC; VI = VDD or GND μA IIL Input LOW Current OS, FB_INT, FB_INC; VI = VDD or GND ±250 ±10 μA μA Output Disabled LOW Current OE = L, VODL = 100mV CL = 0pF @ 410MHz 300 mA IDDLD Operating Supply Current CL = 0pF 500 μA CIN1 Input Capacitance VI = VDDQ or GND 2 3 Output Capacitance VOUT = VDDQ or GND 2 3 IODL IDD1.5 COUT 1 1 100 pF Guaranteed by design, not 100% tested in production. 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER 6 ICS98UAE877A 7181/2 ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER COMMERCIAL TEMPERATURE GRADE Recommended Operating Conditions Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C, Industrial: TA = -40°C to +85°C; Supply Voltage AVDD/VDDQ = 1.5V ± 0.075V. Symbol AVDD, VDDQ VIL VIH VIN VID Parameter1 Conditions Supply Voltage LOW - Level Input Voltage HIGH -Level Input Voltage Typ. Max. Units 1.425 1.5 1.575 V 0.35 x VDDQ V CLK_INT, CLK_INC, FB_INT, FB_INC OE, OS CLK_INT, CLK_INC, FB_INT, FB_INC 0.65 x VDDQ V OE, OS DC Input Signal Voltage2 Differential Input Signal Voltage3 Min. -0.3 DC - CLK_INT, CLK_INC, FB_INT, FB_INC 0.35 AC - CLK_INT, CLK_INC, FB_INT, FB_INC 0.6 VDDQ + 0.3 V VDDQ + 0.4 V VOX Output Differential Cross-Voltage4 VIX Input Differential Cross-Voltage4 IOH HIGH-Level Output Current -6 IOL LOW-Level Output Current 6 TA Operating Free-Air Temperature VDDQ/2 - 0.1 VDDQ/2 +0.1 VDDQ/2 0.15 VDDQ/2 + 0.15 VDDQ/2 V mA -40 +85 °C 1 Unused inputs must be held HIGH or LOW to prevent them from floating. 2 DC input signal voltage specifies the allowable DC execution of differential input. 3 Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4 Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signal must be crossing. 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER 7 ICS98UAE877A 7181/2 ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER COMMERCIAL TEMPERATURE GRADE Timing Requirements Over Recommended Operating Free-Air Temperature Range Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C, Industrial: TA = -40°C to +85°C; Supply Voltage AVDD/VDDQ = 1.5V ± 0.075V. Symbol freqOP freqAPP dTIN TSTAB Parameter1 Conditions 2 Max Clock Frequency 3 Application Frequency Range Min. Max. Units 1.5V ± 0.075V @ 25°C 95 410 MHz 1.5V ± 0.075V @ 25°C 160 410 MHz 40 60 % 9 μs Input Clock Duty Cycle 4 CLK Stabilization 1 The PLL must be able to handle spread spectrum induced skew. 2 Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.) 3 Application clock frequency indicates a range over which the PLL must meet all timing parameters. 4 Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal, within the value specificied by the Static Phase Offset (t∅), after power-up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CLK and CLK go to a logic low state, enter the power-down mode and later return to active operation. CLK and CLK may be left floating after they have been driven low for one complete clock cycle. 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER 8 ICS98UAE877A 7181/2 ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER COMMERCIAL TEMPERATURE GRADE Switching Characteristics Over Recommended Free Air Operating Range Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C, Industrial: TA = -40°C to +85°C; Supply Voltage AVDD/VDDQ = 1.5V ± 0.075V Symbol Parameter1 Conditions tEN Output Enable Time OE to any output tDIS Output Disable Time OE to any output tJIT(PER) Period Jitter tJIT(HPER) Half-Period Jitter SLr1(i) Input Slew Rate SLr1(o) Output Clock Slew Rate tJIT(CC+) tJIT(CC-) t(∅)DYN ∑(su) ∑t(h) tSKEW Output-to-Output Skew Typ. Max. Units 4.73 8 ns 5.82 8 ns 160 - 270 -40 40 271 - 410 -30 30 160 - 270 -60 60 271 - 410 -50 50 Input Clock 1 Output Enable (OE, OS) 0.5 160 - 410 Dynamic Phase Offset Static Phase Offset Min. 160 - 410 2.5 ps ps 4 v/ns 0.8 2 0 40 0 -40 160 - 270 -50 50 271 - 410 -20 20 271 - 410 -60 Cycle-to-Cycle Period Jitter tSPO2 1 2 (MHz) 0 v/ns ps ps 60 ps tJIT(PER) + t(∅)DYN + tSKEW(O) 80 ps t(∅)DYN + tSKEW(O) 60 ps 160 - 270 60 271 - 410 30 ps SSC Modulation Frequency 30 33 KHz SSC Clock Input Frequency Deviation 0 -0.5 % PLL Loop Bandwidth (-3dB from unity gain) 2 MHz Guaranteed for application frequency range. Static phase offset shifted by design. 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER 9 ICS98UAE877A 7181/2 ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER COMMERCIAL TEMPERATURE GRADE Parameter Measurement Information VDD ICS98UAE877A V(CLK) V(CLK) GND Figure 1: IBIS Model Output Load VDD/2 GND C = 10pF ICS98UAE877A R = 10Ω Z = 60Ω SCOPE Z = 50Ω L = 2.97" R = 1MΩ C = 1pF Z = 120Ω R = 10Ω Z = 60Ω Z = 50Ω VTT C = 10pF L = 2.97" R = 1MΩ C = 1pF VTT GND Note: VTT = GND VDD/2 Figure 2: Output Load Test Circuit Yx, FB_OUTC Yx, FB_OUTT tC(N + 1) tC(N) tJIT(CC) = tC(N) + tC(N + 1) Figure 3: Cycle-to-Cycle Jitter 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER 10 ICS98UAE877A 7181/2 ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER COMMERCIAL TEMPERATURE GRADE CLK_INC CLK_INT CLK_INC CLK_INT t(∅)n+1 t(∅)n n=N t(∅) = t(∅)n 1 N Figure 4: Static Phase Offset Yx Yx Yx, FB_OUTC Yx, FB_OUTT tSKEW Figure 5: Output Skew Yx, FB_OUTC Yx, FB_OUTT tC(n) Yx, FB_OUTC Yx, FB_OUTT 1 fo t(JIT_PER) = tC(n) - 1 fo Figure 6: Period Jitter 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER 11 ICS98UAE877A 7181/2 ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER COMMERCIAL TEMPERATURE GRADE Yx, FB_OUTC Yx, FB_OUTT tJIT(HPER_n+1) tJIT(HPER_n) 1 fo tJIT(HPER) = tJIT(HPER_n) - 1 2xfo Figure 7: Half-Period Jitter 80% 80% VID VOD 20% 20% Clock Inputs and outputs tSLR tSLF Figure 8: Input and Output Slew Rates 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER 12 ICS98UAE877A 7181/2 ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER COMMERCIAL TEMPERATURE GRADE CLK CLK FB_IN FB_IN t(∅) t(∅) SSC OFF SSC OFF SSC ON SSC ON t(∅)dyn t(∅)dyn t(∅)dyn t(∅)dyn Figure 9: Dynamic Phase Offset 50% VDDQ OE Y tEN 50% VDDQ Y, Y Y OE 50% VDDQ tDIS Y 50% VDDQ Y Figure 10: Time Delay Between OE and Clock Output (Y, Y) 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER 13 ICS98UAE877A 7181/2 ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER VIA CARD 1Ω COMMERCIAL TEMPERATURE GRADE BEAD 0603 AVDD VDDQ 4.7uF 1206 0.1uF 0603 2200pF 0603 PLL GND AGND VIA CARD Figure 11. AVDD Filtering *Place the 2200pF capacitors close to the PLL. *Use wide traces for PLL Analog power and GND. Connect PLL and caps to AGND trace and connect trace to one GND via (farthest from PLL). *Recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8Ω DC max., 600Ω at 100MHz). 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER 14 ICS98UAE877A 7181/2 ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER COMMERCIAL TEMPERATURE GRADE Package Outline and Package Dimensions - BGA Package dimensions are kept current with JEDEC Publication No. 95 C SEATING PLANE Numeric Designations for Horizontal Grid A1 b REF T 4 3 2 1 A B C D Alpha Designations for Vertical Grid (Letters I, O, Q, and S not used) D d TYP D1 -e- TYP TOP VIEW E c REF -e- TYP h TYP E1 0.12 C ALL DIMENSIONS IN MILLIMETERS D 7.00 Bsc BALL GRID d T Min/Max e E Horiz Vert Total Min/Max 0.25/0.45 4.50 Bsc 0.86/1.00 0.65 Bsc 6 10 60 h Min/Max 0.15/0.31 D1 5.85 Bsc REF. DIMS E1 b c 3.25 Bsc 0.575 0.625 ** NOTE: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source Ref.: JEDEC Publication 95, MO-205*, MO-255** 10-0055 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER 15 ICS98UAE877A 7181/2 ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER COMMERCIAL TEMPERATURE GRADE Package Outline and Package Dimensions - MLF Package dimensions are kept current with JEDEC Publication No. 95 Seating Plane A1 Index Area (ND - 1) x e (Ref.) L A3 N (Ref.) N D & NE Even (Typ.) If ND & NE are Even e/2 1 1 Anvil Singulation 2 2 or E (NE - 1) x e (Ref.) E2 Sawn Singulation E2/2 Top View b (Ref.) N D & NE Odd A D C 0.08 e D2/2 Thermal Base D2 C Thermally Enhanced, Very Thin, Fine Pitch Quad Flat / No Lead Plastic Package Symbol Min. Max. A 0.80 1.00 A1 0 0.05 A3 b 0.25 Reference 0.18 0.30 e 0.50 BASIC N 40 Nd 10 Ne 10 D x E BASIC 6.00 x 6.00 D2 2.75 3.05 E2 2.75 3.05 L 0.30 0.5 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER 16 ICS98UAE877A 7181/2 ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER COMMERCIAL TEMPERATURE GRADE Ordering Information ICSS98UAE XX XXX Device Type Package X X Shipping Shipping Carrier Carrier 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER T Tape and Reel Blank I 0°C to +70°C (Commercial) -40°C to +85°C (Industrial) HLF KLF Low Profile, Fine Pitch, Ball Grid Array - Lead-Free Very Thin, Fine Pitch Quad Flat Package - Lead-Free 877A 1.5V Low-Power Wide-Range Frequency Clock Driver 17 ICS98UAE877A 7181/2 ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER COMMERCIAL TEMPERATURE GRADE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA