ICS93705 Integrated Circuit Systems, Inc. DDR Phase Lock Loop Zero Delay Clock Buffer Recommended Application: DDR Zero Delay Clock Buffer Pin Configuration Switching Characteristics: • PEAK - PEAK jitter (66MHz): <120ps • PEAK - PEAK jitter (>100MHz): <75ps • CYCLE - CYCLE jitter (66MHz):<120ps • CYCLE - CYCLE jitter (>100MHz):<65ps • OUTPUT - OUTPUT skew: <100ps • Output Rise and Fall Time: 450ps - 950ps • DUTY CYCLE: 49% - 51% Logic INPUTS OUTPUTS FB_OUTT AVDD CLK_INT CLKT CLKC FB_OUTT CLKT0 CLKC0 2.5V (nom) L L H L on 2.5V (nom) H H L H on Z Z Z off CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 FB_INT CLK_INT CLKT5 CLKC5 PLL CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 0418C—08/08/02 GND CLKC5 CLKT5 VDD CLKT6 CLKC6 GND GND CLKC7 CLKT7 VDD SDATA N/C FB_INT VDD FB_OUTT N/C GND CLKC8 CLKT8 VDD CLKT9 CLKC9 GND Functionality CLKT1 CLKC1 SCLK SDATA 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48-Pin SSOP Block Diagram Control 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS93705 GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD SCLK CLK_INT N/C VDD AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND Product Description/Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input 2.5V <20MHz(1) (nom) PLL State GND L L H L Bypassed/off GND H H L H Bypassed/off ICS93705 Pin Descriptions PIN NUMBER PIN NAME TYPE DESCRIPTION 1, 7, 8, 18, 24, 25, GND 31, 41, 42, 48 PWR Ground 26, 30, 40, 43, 47, CLKC(9:0) 23, 19, 9, 6, 2 OUT "Complementary" clocks of differential pair outputs. 27, 29, 39, 44, 46, CLKT(9:0) 22, 20, 10, 5, 3 OUT "Tr ue" Clock of differential pair outputs. 4, 11, 15, 21, 28, 34, 38, 45, VDD PWR Power supply 2.5V 12 SCLK IN Clock input of I2C input, 5V tolerant input 13 CLK_INT IN "True" reference clock input, 3.3V tolerant input 14, 32, 36 N/C - Not connected 16 AVDD PWR Analog power supply, 2.5V 17 AGND PWR A n a l o g gr o u n d . 33 FB_OUTT OUT "True" Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT. 35 FB_INT IN "True" Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error. 37 SDATA I/O Data pin for I2C circuitry 5V tolerant Byte 0: Output Control (1= enable, 0 = disable) BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# - PWD 1 1 1 1 1 1 1 1 Byte 1: Output Control (1= enable, 0 = disable) BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DESCRIPTION Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved 0418C—08/08 /02 2 PIN# - PWD 1 1 1 1 1 1 1 1 DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ICS93705 Byte 2: Reserved (1= enable, 0 = disable) BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# - PWD 1 1 1 1 1 1 1 1 Byte 3: Reserved (1= enable, 0 = disable) DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BIT PIN# PWD Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 1 Byte 4: Reserved (1= enable, 0 = disable) BIT PIN# PWD DESCRIPTION Bit 7 1 Reserved Bit 6 1 Reserved Bit 5 1 Reserved Bit 4 1 Reserved Bit 3 1 Reserved Bit 2 1 Reserved Bit 1 1 Reserved Bit 0 1 Reserved Byte 5: Reserved (1= enable, 0 = disable) BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Byte 6: Reserved (1= enable, 0 = disable) BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PIN# PWD 0 0 0 29, 30 1 39, 40 1 44, 43 1 46, 47 1 1 DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DESCRIPTION Reser ved (Note) Reser ved (Note) Reser ved (Note) CLK8 (T&C) CLK7 (T&C) CLK6 (T&C) CLK5 (T&C) Reser ved Note: Don’t write into these registers (7:5), writing into these registers can cause malfunction. 0418C—08/08 /02 3 PIN# PWD 3,2 1 1 10, 9 1 20, 19 1 22, 23 1 27, 26 1 1 1 DESCRIPTION CLK0 (T&C) CLK2 (T&C) CLK3 (T&C) CLK4 (T&C) CLK9 (T&C) Reser ved Reser ved ICS93705 Absolute Maximum Ratings Supply Voltage (VDD & AVDD) . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 3.6V GND –0.5 V to VDD +0.5 V 0°C to +85°C –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input / Supply / Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 2.5 V +/-0.2V (unless otherwise stated) PARAMETER SYMBOL Input High Current IIH VI = VDD or GND µA Input Low Current IIL VI = VDD or GND µA Operating Supply Current CONDITIONS IDD2.5 CL = 0 pF at 133 MHz IDDPD CL = 0 pF Output High Current I OH VDD = 2.3V, VOUT = 1V Output High Current I OL VDD = 2.3V, VOUT = 1.2V High Impedance Output Current I OZ VDD = 2.7V, VOUT = VDD or GND Input Clamp Voltage VIK Iin = -18 mA; High-level Output Voltage VOH Low-level Output Voltage 1 Input Capacitance 1 Output Capacitance 1 VOL MIN TYP 245 -43 26 MAX UNITS 300 mA 100 µA -18 mA 43 mA 10 µA V VDD = min to max, IOH = -1mA 2.42 V VDD = 2.3V, I OH = -12mA 1.87 V VDD = min to max, IOH = 1mA 0.04 0.1 V VDD = 2.3V, I OH = 12mA 0.35 0.6 V CIN VI = VDD or GND COUT VI = VDD or GND 2.1 pF 3 Guaranteed by design, not 100% tested in production. 0418C—08/08 /02 4 pF ICS93705 Recommended Operating Condition TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Analog/core supply voltage SYMBOL MIN TYP MAX UNITS VDD, A VDD 2.3 2.5 2.7 V VIL VIH IDC VDD/2 + 0.5V 40 VDD/2 - 0.5V 60 500 V V % ps Input voltage level Input duty cycle Input max jitter CONDITIONS ITCYC Timing Requirements TA = 0 - 70C; Supply Voltage AVDD, VDD = 2.5 V +/-0.2V (unless otherwise stated) PARAMETER SYMBOL Operating Clock Frequency Input Clock Duty Cycle Clock Stabilization 1 1 1 CONDITIONS MIN TYP MAX UNITS freq op 66 170 MHz d tin 40 60 % 100 µs MAX UNITS t STAB from VDD = 2.5V to 1% target frequency 1. Guaranteed by design, not 100% tested in production. Switching Characteristics TA = 0 - 70C; Supply Voltage VDD = 2.5 V +/-0.2V (unless otherwise stated) PARAMETER SYMBOL Absolute Jitter1 t jabs Cycle to cycle Jitter1,2 t c-c Phase Error1 t pe with input clock 0-2.5V 0.8ns rise/fall Output to output Skew Tskew with input clock 0-2.5V 0.8ns rise/fall Low-to-high level Propagation Delay Time, Bypass Mode1 t PLH CLK_IN to any output, Load = 120W / 12 pF Pulse Skew1 Tskewp 1 1,3 Duty Cycle (differential) Rise Time, Fall Time 1 CONDITIONS MIN TYP 66 MHz 120 100 / 125 / 133 / 167 MHz 75 ps 66 MHz 50 110 100 / 125 / 133 / 167 MHz 35 65 50 150 ps 40 100 ps 4.5 6 ns 100 ps -150 4 ps DC no loads, 66 MHz to 167 MHz 49 50 51 % t R, t F Single-ended 20 - 80 %; Load = 120Ω / 12 pF 450 550 950 ps 1. Guaranteed by design, not 100% tested in production. 2. Refers to transistion on non-inverting period. 3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = twH / t C, where the cycle time (t C) decreases as the frequency increases. 0418C—08/08 /02 5 ICS93705 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: • • • • • • • • • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 • ICS clock will acknowledge each byte one at a time. • Controller (host) sends a Stop bit How to Read: How to Write: Controller (Host) Start Bit Address D4(H) Controller (host) will send start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit Controller (Host) Start Bit Address D5(H) ICS (Slave/Receiver) ICS (Slave/Receiver) ACK Byte Count ACK Dummy Command Code ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Dummy Byte Count Byte 1 Byte 0 Byte 2 Byte 1 Byte 3 Byte 2 Byte 4 Byte 3 Byte 5 Byte 4 Byte 6 Byte 5 Byte 6 ACK Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 0418C—08/08 /02 6 ICS93705 c N SYMBOL L E1 E INDEX AREA 1 2 α h x 45° D In Millimeters COMMON DIMENSIONS MIN MAX A 2.413 2.794 .095 .110 A1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c D 0.127 0.254 SEE VARIATIONS .005 .010 SEE VARIATIONS E 10.033 10.668 .395 .420 E1 7.391 7.595 .291 .299 e A -Ce 0.635 BASIC h 0.381 L 0.508 1.016 SEE VARIATIONS N A1 In Inches COMMON DIMENSIONS MIN MAX α 0.025 BASIC 0.635 0° .015 .025 .020 .040 SEE VARIATIONS 8° 0° 8° MIN MAX MIN MAX 15.748 16.002 SEATING PLANE b VARIATIONS .10 (.004) C N 300 mil SSOP 48 D mm. D (inch) .620 .630 JEDEC MO- 118 6/ 1/ 00 DOC# 10- 0034 REV B Ordering Information ICS93705yF-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0418C—08/08 /02 7